1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #include <hal_rx.h> 22 23 /** 24 * hal_tx_comp_get_status() - TQM Release reason 25 * @hal_desc: completion ring Tx status 26 * 27 * This function will parse the WBM completion descriptor and populate in 28 * HAL structure 29 * 30 * Return: none 31 */ 32 static inline 33 void hal_tx_comp_get_status_generic(void *desc, 34 void *ts1, 35 struct hal_soc *hal) 36 { 37 uint8_t rate_stats_valid = 0; 38 uint32_t rate_stats = 0; 39 struct hal_tx_completion_status *ts = 40 (struct hal_tx_completion_status *)ts1; 41 42 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 43 TQM_STATUS_NUMBER); 44 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 45 ACK_FRAME_RSSI); 46 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 47 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 48 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 49 MSDU_PART_OF_AMSDU); 50 51 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 52 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 53 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 54 TRANSMIT_COUNT); 55 56 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 57 TX_RATE_STATS); 58 59 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 60 TX_RATE_STATS_INFO_VALID, rate_stats); 61 62 ts->valid = rate_stats_valid; 63 64 if (rate_stats_valid) { 65 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 66 rate_stats); 67 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 68 TRANSMIT_PKT_TYPE, rate_stats); 69 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 70 TRANSMIT_STBC, rate_stats); 71 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 72 rate_stats); 73 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 74 rate_stats); 75 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 76 rate_stats); 77 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 78 rate_stats); 79 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 80 rate_stats); 81 } 82 83 ts->release_src = hal_tx_comp_get_buffer_source(desc); 84 ts->status = hal_tx_comp_get_release_reason( 85 desc, 86 hal_soc_to_hal_soc_handle(hal)); 87 88 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 89 TX_RATE_STATS_INFO_TX_RATE_STATS); 90 } 91 92 /** 93 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 94 * @desc: Handle to Tx Descriptor 95 * @paddr: Physical Address 96 * @pool_id: Return Buffer Manager ID 97 * @desc_id: Descriptor ID 98 * @type: 0 - Address points to a MSDU buffer 99 * 1 - Address points to MSDU extension descriptor 100 * 101 * Return: void 102 */ 103 static inline void hal_tx_desc_set_buf_addr_generic(void *desc, 104 dma_addr_t paddr, uint8_t rbm_id, 105 uint32_t desc_id, uint8_t type) 106 { 107 /* Set buffer_addr_info.buffer_addr_31_0 */ 108 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 109 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 110 111 /* Set buffer_addr_info.buffer_addr_39_32 */ 112 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 113 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 114 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 115 (((uint64_t) paddr) >> 32)); 116 117 /* Set buffer_addr_info.return_buffer_manager = rbm id */ 118 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 119 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 120 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 121 RETURN_BUFFER_MANAGER, rbm_id); 122 123 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 124 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 125 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 126 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 127 128 /* Set Buffer or Ext Descriptor Type */ 129 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 130 BUF_OR_EXT_DESC_TYPE) |= 131 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 132 } 133 134 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 135 /** 136 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 137 * tlv_tag: Taf of the TLVs 138 * rx_tlv: the pointer to the TLVs 139 * @ppdu_info: pointer to ppdu_info 140 * 141 * Return: true if the tlv is handled, false if not 142 */ 143 static inline bool 144 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 145 struct hal_rx_ppdu_info *ppdu_info) 146 { 147 uint32_t value; 148 149 switch (tlv_tag) { 150 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 151 { 152 uint8_t *he_sig_a_mu_ul_info = 153 (uint8_t *)rx_tlv + 154 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 155 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 156 ppdu_info->rx_status.he_flags = 1; 157 158 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 159 FORMAT_INDICATION); 160 if (value == 0) { 161 ppdu_info->rx_status.he_data1 = 162 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 163 } else { 164 ppdu_info->rx_status.he_data1 = 165 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 166 } 167 168 /* data1 */ 169 ppdu_info->rx_status.he_data1 |= 170 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 171 QDF_MON_STATUS_HE_DL_UL_KNOWN | 172 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 173 174 /* data2 */ 175 ppdu_info->rx_status.he_data2 |= 176 QDF_MON_STATUS_TXOP_KNOWN; 177 178 /*data3*/ 179 value = HAL_RX_GET(he_sig_a_mu_ul_info, 180 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 181 ppdu_info->rx_status.he_data3 = value; 182 /* 1 for UL and 0 for DL */ 183 value = 1; 184 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 185 ppdu_info->rx_status.he_data3 |= value; 186 187 /*data4*/ 188 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 189 SPATIAL_REUSE); 190 ppdu_info->rx_status.he_data4 = value; 191 192 /*data5*/ 193 value = HAL_RX_GET(he_sig_a_mu_ul_info, 194 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 195 ppdu_info->rx_status.he_data5 = value; 196 ppdu_info->rx_status.bw = value; 197 198 /*data6*/ 199 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 200 TXOP_DURATION); 201 value = value << QDF_MON_STATUS_TXOP_SHIFT; 202 ppdu_info->rx_status.he_data6 |= value; 203 return true; 204 } 205 default: 206 return false; 207 } 208 } 209 #else 210 static inline bool 211 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 212 struct hal_rx_ppdu_info *ppdu_info) 213 { 214 return false; 215 } 216 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ 217 218 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \ 219 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 220 221 static inline void 222 hal_rx_handle_mu_ul_info( 223 void *rx_tlv, 224 struct mon_rx_user_status *mon_rx_user_status) 225 { 226 mon_rx_user_status->mu_ul_user_v0_word0 = 227 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11, 228 SW_RESPONSE_REFERENCE_PTR); 229 230 mon_rx_user_status->mu_ul_user_v0_word1 = 231 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22, 232 SW_RESPONSE_REFERENCE_PTR_EXT); 233 } 234 235 static inline void 236 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 237 struct mon_rx_user_status *mon_rx_user_status) 238 { 239 uint32_t mpdu_ok_byte_count; 240 uint32_t mpdu_err_byte_count; 241 242 mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, 243 RX_PPDU_END_USER_STATS_17, 244 MPDU_OK_BYTE_COUNT); 245 mpdu_err_byte_count = HAL_RX_GET(rx_tlv, 246 RX_PPDU_END_USER_STATS_19, 247 MPDU_ERR_BYTE_COUNT); 248 249 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 250 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 251 } 252 #else 253 static inline void 254 hal_rx_handle_mu_ul_info(void *rx_tlv, 255 struct mon_rx_user_status *mon_rx_user_status) 256 { 257 } 258 259 static inline void 260 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 261 struct mon_rx_user_status *mon_rx_user_status) 262 { 263 struct hal_rx_ppdu_info *ppdu_info = 264 (struct hal_rx_ppdu_info *)ppduinfo; 265 266 /* HKV1: doesn't support mpdu byte count */ 267 mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; 268 mon_rx_user_status->mpdu_err_byte_count = 0; 269 } 270 #endif 271 272 static inline void 273 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, 274 struct mon_rx_user_status *mon_rx_user_status) 275 { 276 struct hal_rx_ppdu_info *ppdu_info = 277 (struct hal_rx_ppdu_info *)ppduinfo; 278 279 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 280 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 281 mon_rx_user_status->tcp_msdu_count = 282 ppdu_info->rx_status.tcp_msdu_count; 283 mon_rx_user_status->udp_msdu_count = 284 ppdu_info->rx_status.udp_msdu_count; 285 mon_rx_user_status->other_msdu_count = 286 ppdu_info->rx_status.other_msdu_count; 287 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 288 mon_rx_user_status->frame_control_info_valid = 289 ppdu_info->rx_status.frame_control_info_valid; 290 mon_rx_user_status->data_sequence_control_info_valid = 291 ppdu_info->rx_status.data_sequence_control_info_valid; 292 mon_rx_user_status->first_data_seq_ctrl = 293 ppdu_info->rx_status.first_data_seq_ctrl; 294 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 295 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 296 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 297 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 298 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 299 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 300 301 mon_rx_user_status->mpdu_cnt_fcs_ok = 302 ppdu_info->com_info.mpdu_cnt_fcs_ok; 303 mon_rx_user_status->mpdu_cnt_fcs_err = 304 ppdu_info->com_info.mpdu_cnt_fcs_err; 305 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 306 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 307 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 308 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 309 310 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 311 } 312 313 #ifdef WLAN_TX_PKT_CAPTURE_ENH 314 static inline void 315 hal_rx_populate_tx_capture_user_info(void *ppduinfo, 316 uint32_t user_id) 317 { 318 struct hal_rx_ppdu_info *ppdu_info; 319 struct mon_rx_info *mon_rx_info; 320 struct mon_rx_user_info *mon_rx_user_info; 321 322 ppdu_info = (struct hal_rx_ppdu_info *)ppduinfo; 323 mon_rx_info = &ppdu_info->rx_info; 324 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 325 mon_rx_user_info->qos_control_info_valid = 326 mon_rx_info->qos_control_info_valid; 327 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 328 } 329 #else 330 static inline void 331 hal_rx_populate_tx_capture_user_info(void *ppduinfo, 332 uint32_t user_id) 333 { 334 } 335 #endif 336 337 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ 338 ppdu_info, rssi_info_tlv) \ 339 { \ 340 ppdu_info->rx_status.rssi_chain[chain][0] = \ 341 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 342 RSSI_PRI20_CHAIN##chain); \ 343 ppdu_info->rx_status.rssi_chain[chain][1] = \ 344 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 345 RSSI_EXT20_CHAIN##chain); \ 346 ppdu_info->rx_status.rssi_chain[chain][2] = \ 347 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 348 RSSI_EXT40_LOW20_CHAIN##chain); \ 349 ppdu_info->rx_status.rssi_chain[chain][3] = \ 350 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 351 RSSI_EXT40_HIGH20_CHAIN##chain); \ 352 ppdu_info->rx_status.rssi_chain[chain][4] = \ 353 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 354 RSSI_EXT80_LOW20_CHAIN##chain); \ 355 ppdu_info->rx_status.rssi_chain[chain][5] = \ 356 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 357 RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ 358 ppdu_info->rx_status.rssi_chain[chain][6] = \ 359 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 360 RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ 361 ppdu_info->rx_status.rssi_chain[chain][7] = \ 362 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 363 RSSI_EXT80_HIGH20_CHAIN##chain); \ 364 } \ 365 366 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 367 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ 368 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ 369 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ 370 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ 371 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ 372 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ 373 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ 374 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ 375 376 static inline uint32_t 377 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 378 uint8_t *rssi_info_tlv) 379 { 380 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 381 return 0; 382 } 383 384 #ifdef WLAN_TX_PKT_CAPTURE_ENH 385 static inline void 386 hal_get_qos_control(void *rx_tlv, 387 struct hal_rx_ppdu_info *ppdu_info) 388 { 389 ppdu_info->rx_info.qos_control_info_valid = 390 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 391 QOS_CONTROL_INFO_VALID); 392 393 if (ppdu_info->rx_info.qos_control_info_valid) 394 ppdu_info->rx_info.qos_control = 395 HAL_RX_GET(rx_tlv, 396 RX_PPDU_END_USER_STATS_5, 397 QOS_CONTROL_FIELD); 398 } 399 400 static inline void 401 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 402 struct hal_rx_ppdu_info *ppdu_info) 403 { 404 if (ppdu_info->sw_frame_group_id 405 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) { 406 ppdu_info->rx_info.mac_addr1_valid = 407 HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start); 408 409 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 410 HAL_RX_GET(rx_mpdu_start, 411 RX_MPDU_INFO_15, 412 MAC_ADDR_AD1_31_0); 413 } 414 } 415 #else 416 static inline void 417 hal_get_qos_control(void *rx_tlv, 418 struct hal_rx_ppdu_info *ppdu_info) 419 { 420 } 421 422 static inline void 423 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 424 struct hal_rx_ppdu_info *ppdu_info) 425 { 426 } 427 #endif 428 429 /** 430 * hal_get_radiotap_he_gi_ltf() - Convert HE ltf and GI value 431 * from stats enum to radiotap enum 432 * @he_gi: HE GI value used in stats 433 * @he_ltf: HE LTF value used in stats 434 * 435 * Return: void 436 */ 437 static inline void hal_get_radiotap_he_gi_ltf(uint16_t *he_gi, uint16_t *he_ltf) 438 { 439 switch (*he_gi) { 440 case HE_GI_0_8: 441 *he_gi = HE_GI_RADIOTAP_0_8; 442 break; 443 case HE_GI_1_6: 444 *he_gi = HE_GI_RADIOTAP_1_6; 445 break; 446 case HE_GI_3_2: 447 *he_gi = HE_GI_RADIOTAP_3_2; 448 break; 449 default: 450 *he_gi = HE_GI_RADIOTAP_RESERVED; 451 } 452 453 switch (*he_ltf) { 454 case HE_LTF_1_X: 455 *he_ltf = HE_LTF_RADIOTAP_1_X; 456 break; 457 case HE_LTF_2_X: 458 *he_ltf = HE_LTF_RADIOTAP_2_X; 459 break; 460 case HE_LTF_4_X: 461 *he_ltf = HE_LTF_RADIOTAP_4_X; 462 break; 463 default: 464 *he_ltf = HE_LTF_RADIOTAP_UNKNOWN; 465 } 466 } 467 468 /* channel number to freq conversion */ 469 #define CHANNEL_NUM_14 14 470 #define CHANNEL_NUM_15 15 471 #define CHANNEL_NUM_27 27 472 #define CHANNEL_NUM_35 35 473 #define CHANNEL_NUM_182 182 474 #define CHANNEL_NUM_197 197 475 #define CHANNEL_FREQ_2484 2484 476 #define CHANNEL_FREQ_2407 2407 477 #define CHANNEL_FREQ_2512 2512 478 #define CHANNEL_FREQ_5000 5000 479 #define CHANNEL_FREQ_5940 5940 480 #define CHANNEL_FREQ_4000 4000 481 #define CHANNEL_FREQ_5150 5150 482 #define FREQ_MULTIPLIER_CONST_5MHZ 5 483 #define FREQ_MULTIPLIER_CONST_20MHZ 20 484 /** 485 * hal_rx_radiotap_num_to_freq() - Get frequency from chan number 486 * @chan_num - Input channel number 487 * @center_freq - Input Channel Center frequency 488 * 489 * Return - Channel frequency in Mhz 490 */ 491 static uint16_t 492 hal_rx_radiotap_num_to_freq(uint16_t chan_num, qdf_freq_t center_freq) 493 { 494 if (center_freq < CHANNEL_FREQ_5940) { 495 if (chan_num == CHANNEL_NUM_14) 496 return CHANNEL_FREQ_2484; 497 if (chan_num < CHANNEL_NUM_14) 498 return CHANNEL_FREQ_2407 + 499 (chan_num * FREQ_MULTIPLIER_CONST_5MHZ); 500 501 if (chan_num < CHANNEL_NUM_27) 502 return CHANNEL_FREQ_2512 + 503 ((chan_num - CHANNEL_NUM_15) * 504 FREQ_MULTIPLIER_CONST_20MHZ); 505 506 if (chan_num > CHANNEL_NUM_182 && 507 chan_num < CHANNEL_NUM_197) 508 return ((chan_num * FREQ_MULTIPLIER_CONST_5MHZ) + 509 CHANNEL_FREQ_4000); 510 511 return CHANNEL_FREQ_5000 + 512 (chan_num * FREQ_MULTIPLIER_CONST_5MHZ); 513 } else { 514 return CHANNEL_FREQ_5940 + 515 (chan_num * FREQ_MULTIPLIER_CONST_5MHZ); 516 } 517 } 518 519 /** 520 * hal_rx_status_get_tlv_info() - process receive info TLV 521 * @rx_tlv_hdr: pointer to TLV header 522 * @ppdu_info: pointer to ppdu_info 523 * 524 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 525 */ 526 static inline uint32_t 527 hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, 528 hal_soc_handle_t hal_soc_hdl, 529 qdf_nbuf_t nbuf) 530 { 531 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 532 uint32_t tlv_tag, user_id, tlv_len, value; 533 uint8_t group_id = 0; 534 uint8_t he_dcm = 0; 535 uint8_t he_stbc = 0; 536 uint16_t he_gi = 0; 537 uint16_t he_ltf = 0; 538 void *rx_tlv; 539 bool unhandled = false; 540 struct mon_rx_user_status *mon_rx_user_status; 541 struct hal_rx_ppdu_info *ppdu_info = 542 (struct hal_rx_ppdu_info *)ppduinfo; 543 544 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 545 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 546 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 547 548 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 549 550 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 551 rx_tlv, tlv_len); 552 553 switch (tlv_tag) { 554 555 case WIFIRX_PPDU_START_E: 556 { 557 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 558 559 ppdu_info->com_info.ppdu_id = 560 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 561 PHY_PPDU_ID); 562 /* channel number is set in PHY meta data */ 563 ppdu_info->rx_status.chan_num = 564 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 565 SW_PHY_META_DATA) & 0x0000FFFF); 566 ppdu_info->rx_status.chan_freq = 567 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 568 SW_PHY_META_DATA) & 0xFFFF0000)>>16; 569 if (ppdu_info->rx_status.chan_num && 570 ppdu_info->rx_status.chan_freq) { 571 ppdu_info->rx_status.chan_freq = 572 hal_rx_radiotap_num_to_freq( 573 ppdu_info->rx_status.chan_num, 574 ppdu_info->rx_status.chan_freq); 575 } 576 ppdu_info->com_info.ppdu_timestamp = 577 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 578 PPDU_START_TIMESTAMP); 579 ppdu_info->rx_status.ppdu_timestamp = 580 ppdu_info->com_info.ppdu_timestamp; 581 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 582 583 /* If last ppdu_id doesn't match new ppdu_id, 584 * 1. reset mpdu_cnt 585 * 2. update last_ppdu_id with new 586 * 3. reset mpdu fcs bitmap 587 */ 588 if (com_info->ppdu_id != com_info->last_ppdu_id) { 589 com_info->mpdu_cnt = 0; 590 com_info->last_ppdu_id = 591 com_info->ppdu_id; 592 com_info->num_users = 0; 593 qdf_mem_zero(&com_info->mpdu_fcs_ok_bitmap, 594 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 595 sizeof(com_info->mpdu_fcs_ok_bitmap[0])); 596 } 597 break; 598 } 599 600 case WIFIRX_PPDU_START_USER_INFO_E: 601 break; 602 603 case WIFIRX_PPDU_END_E: 604 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 605 "[%s][%d] ppdu_end_e len=%d", 606 __func__, __LINE__, tlv_len); 607 /* This is followed by sub-TLVs of PPDU_END */ 608 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 609 break; 610 611 case WIFIPHYRX_PKT_END_E: 612 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 613 break; 614 615 case WIFIRXPCU_PPDU_END_INFO_E: 616 ppdu_info->rx_status.rx_antenna = 617 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA); 618 ppdu_info->rx_status.tsft = 619 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 620 WB_TIMESTAMP_UPPER_32); 621 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 622 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 623 WB_TIMESTAMP_LOWER_32); 624 ppdu_info->rx_status.duration = 625 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 626 RX_PPDU_DURATION); 627 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 628 break; 629 630 /* 631 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 632 * for MU, based on num users we see this tlv that many times. 633 */ 634 case WIFIRX_PPDU_END_USER_STATS_E: 635 { 636 unsigned long tid = 0; 637 uint16_t seq = 0; 638 639 ppdu_info->rx_status.ast_index = 640 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 641 AST_INDEX); 642 643 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 644 RECEIVED_QOS_DATA_TID_BITMAP); 645 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 646 647 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 648 ppdu_info->rx_status.tid = HAL_TID_INVALID; 649 650 ppdu_info->rx_status.tcp_msdu_count = 651 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 652 TCP_MSDU_COUNT) + 653 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 654 TCP_ACK_MSDU_COUNT); 655 ppdu_info->rx_status.udp_msdu_count = 656 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 657 UDP_MSDU_COUNT); 658 ppdu_info->rx_status.other_msdu_count = 659 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 660 OTHER_MSDU_COUNT); 661 662 if (ppdu_info->sw_frame_group_id 663 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 664 ppdu_info->rx_status.frame_control_info_valid = 665 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 666 FRAME_CONTROL_INFO_VALID); 667 668 if (ppdu_info->rx_status.frame_control_info_valid) 669 ppdu_info->rx_status.frame_control = 670 HAL_RX_GET(rx_tlv, 671 RX_PPDU_END_USER_STATS_4, 672 FRAME_CONTROL_FIELD); 673 674 hal_get_qos_control(rx_tlv, ppdu_info); 675 } 676 677 ppdu_info->rx_status.data_sequence_control_info_valid = 678 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 679 DATA_SEQUENCE_CONTROL_INFO_VALID); 680 681 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 682 FIRST_DATA_SEQ_CTRL); 683 if (ppdu_info->rx_status.data_sequence_control_info_valid) 684 ppdu_info->rx_status.first_data_seq_ctrl = seq; 685 686 ppdu_info->rx_status.preamble_type = 687 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 688 HT_CONTROL_FIELD_PKT_TYPE); 689 switch (ppdu_info->rx_status.preamble_type) { 690 case HAL_RX_PKT_TYPE_11N: 691 ppdu_info->rx_status.ht_flags = 1; 692 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 693 break; 694 case HAL_RX_PKT_TYPE_11AC: 695 ppdu_info->rx_status.vht_flags = 1; 696 break; 697 case HAL_RX_PKT_TYPE_11AX: 698 ppdu_info->rx_status.he_flags = 1; 699 break; 700 default: 701 break; 702 } 703 704 ppdu_info->com_info.mpdu_cnt_fcs_ok = 705 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 706 MPDU_CNT_FCS_OK); 707 ppdu_info->com_info.mpdu_cnt_fcs_err = 708 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 709 MPDU_CNT_FCS_ERR); 710 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 711 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 712 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 713 else 714 ppdu_info->rx_status.rs_flags &= 715 (~IEEE80211_AMPDU_FLAG); 716 717 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 718 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7, 719 FCS_OK_BITMAP_31_0); 720 721 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 722 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8, 723 FCS_OK_BITMAP_63_32); 724 725 if (user_id < HAL_MAX_UL_MU_USERS) { 726 mon_rx_user_status = 727 &ppdu_info->rx_user_status[user_id]; 728 729 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 730 731 ppdu_info->com_info.num_users++; 732 733 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 734 mon_rx_user_status); 735 736 hal_rx_populate_tx_capture_user_info(ppdu_info, 737 user_id); 738 739 } 740 break; 741 } 742 743 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 744 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 745 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1, 746 FCS_OK_BITMAP_95_64); 747 748 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 749 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2, 750 FCS_OK_BITMAP_127_96); 751 752 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 753 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3, 754 FCS_OK_BITMAP_159_128); 755 756 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 757 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4, 758 FCS_OK_BITMAP_191_160); 759 760 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 761 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5, 762 FCS_OK_BITMAP_223_192); 763 764 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 765 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6, 766 FCS_OK_BITMAP_255_224); 767 break; 768 769 case WIFIRX_PPDU_END_STATUS_DONE_E: 770 return HAL_TLV_STATUS_PPDU_DONE; 771 772 case WIFIDUMMY_E: 773 return HAL_TLV_STATUS_BUF_DONE; 774 775 case WIFIPHYRX_HT_SIG_E: 776 { 777 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 778 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 779 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 780 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 781 FEC_CODING); 782 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 783 1 : 0; 784 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 785 HT_SIG_INFO_0, MCS); 786 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 787 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 788 HT_SIG_INFO_0, CBW); 789 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 790 HT_SIG_INFO_1, SHORT_GI); 791 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 792 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 793 HT_SIG_SU_NSS_SHIFT) + 1; 794 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 795 break; 796 } 797 798 case WIFIPHYRX_L_SIG_B_E: 799 { 800 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 801 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 802 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 803 804 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 805 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 806 switch (value) { 807 case 1: 808 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 809 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 810 break; 811 case 2: 812 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 813 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 814 break; 815 case 3: 816 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 817 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 818 break; 819 case 4: 820 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 821 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 822 break; 823 case 5: 824 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 825 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 826 break; 827 case 6: 828 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 829 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 830 break; 831 case 7: 832 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 833 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 834 break; 835 default: 836 break; 837 } 838 ppdu_info->rx_status.cck_flag = 1; 839 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 840 break; 841 } 842 843 case WIFIPHYRX_L_SIG_A_E: 844 { 845 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 846 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 847 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 848 849 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 850 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 851 switch (value) { 852 case 8: 853 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 854 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 855 break; 856 case 9: 857 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 858 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 859 break; 860 case 10: 861 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 862 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 863 break; 864 case 11: 865 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 866 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 867 break; 868 case 12: 869 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 870 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 871 break; 872 case 13: 873 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 874 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 875 break; 876 case 14: 877 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 878 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 879 break; 880 case 15: 881 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 882 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 883 break; 884 default: 885 break; 886 } 887 ppdu_info->rx_status.ofdm_flag = 1; 888 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 889 break; 890 } 891 892 case WIFIPHYRX_VHT_SIG_A_E: 893 { 894 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 895 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 896 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 897 898 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 899 SU_MU_CODING); 900 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 901 1 : 0; 902 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 903 ppdu_info->rx_status.vht_flag_values5 = group_id; 904 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 905 VHT_SIG_A_INFO_1, MCS); 906 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 907 VHT_SIG_A_INFO_1, GI_SETTING); 908 909 switch (hal->target_type) { 910 case TARGET_TYPE_QCA8074: 911 case TARGET_TYPE_QCA8074V2: 912 case TARGET_TYPE_QCA6018: 913 case TARGET_TYPE_QCA5018: 914 case TARGET_TYPE_QCN9000: 915 #ifdef QCA_WIFI_QCA6390 916 case TARGET_TYPE_QCA6390: 917 #endif 918 ppdu_info->rx_status.is_stbc = 919 HAL_RX_GET(vht_sig_a_info, 920 VHT_SIG_A_INFO_0, STBC); 921 value = HAL_RX_GET(vht_sig_a_info, 922 VHT_SIG_A_INFO_0, N_STS); 923 value = value & VHT_SIG_SU_NSS_MASK; 924 if (ppdu_info->rx_status.is_stbc && (value > 0)) 925 value = ((value + 1) >> 1) - 1; 926 ppdu_info->rx_status.nss = 927 ((value & VHT_SIG_SU_NSS_MASK) + 1); 928 929 break; 930 case TARGET_TYPE_QCA6290: 931 #if !defined(QCA_WIFI_QCA6290_11AX) 932 ppdu_info->rx_status.is_stbc = 933 HAL_RX_GET(vht_sig_a_info, 934 VHT_SIG_A_INFO_0, STBC); 935 value = HAL_RX_GET(vht_sig_a_info, 936 VHT_SIG_A_INFO_0, N_STS); 937 value = value & VHT_SIG_SU_NSS_MASK; 938 if (ppdu_info->rx_status.is_stbc && (value > 0)) 939 value = ((value + 1) >> 1) - 1; 940 ppdu_info->rx_status.nss = 941 ((value & VHT_SIG_SU_NSS_MASK) + 1); 942 #else 943 ppdu_info->rx_status.nss = 0; 944 #endif 945 break; 946 case TARGET_TYPE_QCA6490: 947 case TARGET_TYPE_QCA6750: 948 ppdu_info->rx_status.nss = 0; 949 break; 950 default: 951 break; 952 } 953 ppdu_info->rx_status.vht_flag_values3[0] = 954 (((ppdu_info->rx_status.mcs) << 4) 955 | ppdu_info->rx_status.nss); 956 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 957 VHT_SIG_A_INFO_0, BANDWIDTH); 958 ppdu_info->rx_status.vht_flag_values2 = 959 ppdu_info->rx_status.bw; 960 ppdu_info->rx_status.vht_flag_values4 = 961 HAL_RX_GET(vht_sig_a_info, 962 VHT_SIG_A_INFO_1, SU_MU_CODING); 963 964 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 965 VHT_SIG_A_INFO_1, BEAMFORMED); 966 if (group_id == 0 || group_id == 63) 967 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 968 else 969 ppdu_info->rx_status.reception_type = 970 HAL_RX_TYPE_MU_MIMO; 971 972 break; 973 } 974 case WIFIPHYRX_HE_SIG_A_SU_E: 975 { 976 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 977 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 978 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 979 ppdu_info->rx_status.he_flags = 1; 980 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 981 FORMAT_INDICATION); 982 if (value == 0) { 983 ppdu_info->rx_status.he_data1 = 984 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 985 } else { 986 ppdu_info->rx_status.he_data1 = 987 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 988 } 989 990 /* data1 */ 991 ppdu_info->rx_status.he_data1 |= 992 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 993 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 994 QDF_MON_STATUS_HE_DL_UL_KNOWN | 995 QDF_MON_STATUS_HE_MCS_KNOWN | 996 QDF_MON_STATUS_HE_DCM_KNOWN | 997 QDF_MON_STATUS_HE_CODING_KNOWN | 998 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 999 QDF_MON_STATUS_HE_STBC_KNOWN | 1000 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1001 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1002 1003 /* data2 */ 1004 ppdu_info->rx_status.he_data2 = 1005 QDF_MON_STATUS_HE_GI_KNOWN; 1006 ppdu_info->rx_status.he_data2 |= 1007 QDF_MON_STATUS_TXBF_KNOWN | 1008 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1009 QDF_MON_STATUS_TXOP_KNOWN | 1010 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1011 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1012 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1013 1014 /* data3 */ 1015 value = HAL_RX_GET(he_sig_a_su_info, 1016 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 1017 ppdu_info->rx_status.he_data3 = value; 1018 value = HAL_RX_GET(he_sig_a_su_info, 1019 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 1020 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 1021 ppdu_info->rx_status.he_data3 |= value; 1022 value = HAL_RX_GET(he_sig_a_su_info, 1023 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 1024 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1025 ppdu_info->rx_status.he_data3 |= value; 1026 1027 value = HAL_RX_GET(he_sig_a_su_info, 1028 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 1029 ppdu_info->rx_status.mcs = value; 1030 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1031 ppdu_info->rx_status.he_data3 |= value; 1032 1033 value = HAL_RX_GET(he_sig_a_su_info, 1034 HE_SIG_A_SU_INFO_0, DCM); 1035 he_dcm = value; 1036 value = value << QDF_MON_STATUS_DCM_SHIFT; 1037 ppdu_info->rx_status.he_data3 |= value; 1038 value = HAL_RX_GET(he_sig_a_su_info, 1039 HE_SIG_A_SU_INFO_1, CODING); 1040 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 1041 1 : 0; 1042 value = value << QDF_MON_STATUS_CODING_SHIFT; 1043 ppdu_info->rx_status.he_data3 |= value; 1044 value = HAL_RX_GET(he_sig_a_su_info, 1045 HE_SIG_A_SU_INFO_1, 1046 LDPC_EXTRA_SYMBOL); 1047 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1048 ppdu_info->rx_status.he_data3 |= value; 1049 value = HAL_RX_GET(he_sig_a_su_info, 1050 HE_SIG_A_SU_INFO_1, STBC); 1051 he_stbc = value; 1052 value = value << QDF_MON_STATUS_STBC_SHIFT; 1053 ppdu_info->rx_status.he_data3 |= value; 1054 1055 /* data4 */ 1056 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 1057 SPATIAL_REUSE); 1058 ppdu_info->rx_status.he_data4 = value; 1059 1060 /* data5 */ 1061 value = HAL_RX_GET(he_sig_a_su_info, 1062 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 1063 ppdu_info->rx_status.he_data5 = value; 1064 ppdu_info->rx_status.bw = value; 1065 value = HAL_RX_GET(he_sig_a_su_info, 1066 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 1067 switch (value) { 1068 case 0: 1069 he_gi = HE_GI_0_8; 1070 he_ltf = HE_LTF_1_X; 1071 break; 1072 case 1: 1073 he_gi = HE_GI_0_8; 1074 he_ltf = HE_LTF_2_X; 1075 break; 1076 case 2: 1077 he_gi = HE_GI_1_6; 1078 he_ltf = HE_LTF_2_X; 1079 break; 1080 case 3: 1081 if (he_dcm && he_stbc) { 1082 he_gi = HE_GI_0_8; 1083 he_ltf = HE_LTF_4_X; 1084 } else { 1085 he_gi = HE_GI_3_2; 1086 he_ltf = HE_LTF_4_X; 1087 } 1088 break; 1089 } 1090 ppdu_info->rx_status.sgi = he_gi; 1091 ppdu_info->rx_status.ltf_size = he_ltf; 1092 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1093 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1094 ppdu_info->rx_status.he_data5 |= value; 1095 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1096 ppdu_info->rx_status.he_data5 |= value; 1097 1098 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1099 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1100 ppdu_info->rx_status.he_data5 |= value; 1101 1102 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1103 PACKET_EXTENSION_A_FACTOR); 1104 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1105 ppdu_info->rx_status.he_data5 |= value; 1106 1107 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 1108 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1109 ppdu_info->rx_status.he_data5 |= value; 1110 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1111 PACKET_EXTENSION_PE_DISAMBIGUITY); 1112 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1113 ppdu_info->rx_status.he_data5 |= value; 1114 1115 /* data6 */ 1116 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1117 value++; 1118 ppdu_info->rx_status.nss = value; 1119 ppdu_info->rx_status.he_data6 = value; 1120 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1121 DOPPLER_INDICATION); 1122 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1123 ppdu_info->rx_status.he_data6 |= value; 1124 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1125 TXOP_DURATION); 1126 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1127 ppdu_info->rx_status.he_data6 |= value; 1128 1129 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 1130 HE_SIG_A_SU_INFO_1, TXBF); 1131 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1132 break; 1133 } 1134 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 1135 { 1136 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 1137 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 1138 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 1139 1140 ppdu_info->rx_status.he_mu_flags = 1; 1141 1142 /* HE Flags */ 1143 /*data1*/ 1144 ppdu_info->rx_status.he_data1 = 1145 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1146 ppdu_info->rx_status.he_data1 |= 1147 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1148 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1149 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1150 QDF_MON_STATUS_HE_STBC_KNOWN | 1151 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1152 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1153 1154 /* data2 */ 1155 ppdu_info->rx_status.he_data2 = 1156 QDF_MON_STATUS_HE_GI_KNOWN; 1157 ppdu_info->rx_status.he_data2 |= 1158 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1159 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1160 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1161 QDF_MON_STATUS_TXOP_KNOWN | 1162 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1163 1164 /*data3*/ 1165 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1166 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 1167 ppdu_info->rx_status.he_data3 = value; 1168 1169 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1170 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 1171 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1172 ppdu_info->rx_status.he_data3 |= value; 1173 1174 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1175 HE_SIG_A_MU_DL_INFO_1, 1176 LDPC_EXTRA_SYMBOL); 1177 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1178 ppdu_info->rx_status.he_data3 |= value; 1179 1180 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1181 HE_SIG_A_MU_DL_INFO_1, STBC); 1182 he_stbc = value; 1183 value = value << QDF_MON_STATUS_STBC_SHIFT; 1184 ppdu_info->rx_status.he_data3 |= value; 1185 1186 /*data4*/ 1187 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1188 SPATIAL_REUSE); 1189 ppdu_info->rx_status.he_data4 = value; 1190 1191 /*data5*/ 1192 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1193 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1194 ppdu_info->rx_status.he_data5 = value; 1195 ppdu_info->rx_status.bw = value; 1196 1197 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1198 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 1199 switch (value) { 1200 case 0: 1201 he_gi = HE_GI_0_8; 1202 he_ltf = HE_LTF_4_X; 1203 break; 1204 case 1: 1205 he_gi = HE_GI_0_8; 1206 he_ltf = HE_LTF_2_X; 1207 break; 1208 case 2: 1209 he_gi = HE_GI_1_6; 1210 he_ltf = HE_LTF_2_X; 1211 break; 1212 case 3: 1213 he_gi = HE_GI_3_2; 1214 he_ltf = HE_LTF_4_X; 1215 break; 1216 } 1217 ppdu_info->rx_status.sgi = he_gi; 1218 ppdu_info->rx_status.ltf_size = he_ltf; 1219 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1220 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1221 ppdu_info->rx_status.he_data5 |= value; 1222 1223 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1224 ppdu_info->rx_status.he_data5 |= value; 1225 1226 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1227 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 1228 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1229 ppdu_info->rx_status.he_data5 |= value; 1230 1231 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1232 PACKET_EXTENSION_A_FACTOR); 1233 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1234 ppdu_info->rx_status.he_data5 |= value; 1235 1236 1237 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1238 PACKET_EXTENSION_PE_DISAMBIGUITY); 1239 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1240 ppdu_info->rx_status.he_data5 |= value; 1241 1242 /*data6*/ 1243 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1244 DOPPLER_INDICATION); 1245 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1246 ppdu_info->rx_status.he_data6 |= value; 1247 1248 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1249 TXOP_DURATION); 1250 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1251 ppdu_info->rx_status.he_data6 |= value; 1252 1253 /* HE-MU Flags */ 1254 /* HE-MU-flags1 */ 1255 ppdu_info->rx_status.he_flags1 = 1256 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1257 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1258 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1259 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1260 QDF_MON_STATUS_RU_0_KNOWN; 1261 1262 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1263 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 1264 ppdu_info->rx_status.he_flags1 |= value; 1265 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1266 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 1267 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 1268 ppdu_info->rx_status.he_flags1 |= value; 1269 1270 /* HE-MU-flags2 */ 1271 ppdu_info->rx_status.he_flags2 = 1272 QDF_MON_STATUS_BW_KNOWN; 1273 1274 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1275 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1276 ppdu_info->rx_status.he_flags2 |= value; 1277 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1278 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 1279 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1280 ppdu_info->rx_status.he_flags2 |= value; 1281 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1282 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 1283 value = value - 1; 1284 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1285 ppdu_info->rx_status.he_flags2 |= value; 1286 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1287 break; 1288 } 1289 case WIFIPHYRX_HE_SIG_B1_MU_E: 1290 { 1291 1292 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 1293 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 1294 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 1295 1296 ppdu_info->rx_status.he_sig_b_common_known |= 1297 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 1298 /* TODO: Check on the availability of other fields in 1299 * sig_b_common 1300 */ 1301 1302 value = HAL_RX_GET(he_sig_b1_mu_info, 1303 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 1304 ppdu_info->rx_status.he_RU[0] = value; 1305 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1306 break; 1307 } 1308 case WIFIPHYRX_HE_SIG_B2_MU_E: 1309 { 1310 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 1311 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 1312 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 1313 /* 1314 * Not all "HE" fields can be updated from 1315 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1316 * to populate rest of the "HE" fields for MU scenarios. 1317 */ 1318 1319 /* HE-data1 */ 1320 ppdu_info->rx_status.he_data1 |= 1321 QDF_MON_STATUS_HE_MCS_KNOWN | 1322 QDF_MON_STATUS_HE_CODING_KNOWN; 1323 1324 /* HE-data2 */ 1325 1326 /* HE-data3 */ 1327 value = HAL_RX_GET(he_sig_b2_mu_info, 1328 HE_SIG_B2_MU_INFO_0, STA_MCS); 1329 ppdu_info->rx_status.mcs = value; 1330 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1331 ppdu_info->rx_status.he_data3 |= value; 1332 1333 1334 value = HAL_RX_GET(he_sig_b2_mu_info, 1335 HE_SIG_B2_MU_INFO_0, STA_CODING); 1336 value = value << QDF_MON_STATUS_CODING_SHIFT; 1337 ppdu_info->rx_status.he_data3 |= value; 1338 1339 /* HE-data4 */ 1340 value = HAL_RX_GET(he_sig_b2_mu_info, 1341 HE_SIG_B2_MU_INFO_0, STA_ID); 1342 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1343 ppdu_info->rx_status.he_data4 |= value; 1344 1345 /* HE-data5 */ 1346 1347 /* HE-data6 */ 1348 value = HAL_RX_GET(he_sig_b2_mu_info, 1349 HE_SIG_B2_MU_INFO_0, NSTS); 1350 /* value n indicates n+1 spatial streams */ 1351 value++; 1352 ppdu_info->rx_status.nss = value; 1353 ppdu_info->rx_status.he_data6 |= value; 1354 1355 break; 1356 1357 } 1358 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1359 { 1360 uint8_t *he_sig_b2_ofdma_info = 1361 (uint8_t *)rx_tlv + 1362 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1363 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1364 1365 /* 1366 * Not all "HE" fields can be updated from 1367 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1368 * to populate rest of "HE" fields for MU OFDMA scenarios. 1369 */ 1370 1371 /* HE-data1 */ 1372 ppdu_info->rx_status.he_data1 |= 1373 QDF_MON_STATUS_HE_MCS_KNOWN | 1374 QDF_MON_STATUS_HE_DCM_KNOWN | 1375 QDF_MON_STATUS_HE_CODING_KNOWN; 1376 1377 /* HE-data2 */ 1378 ppdu_info->rx_status.he_data2 |= 1379 QDF_MON_STATUS_TXBF_KNOWN; 1380 1381 /* HE-data3 */ 1382 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1383 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1384 ppdu_info->rx_status.mcs = value; 1385 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1386 ppdu_info->rx_status.he_data3 |= value; 1387 1388 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1389 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1390 he_dcm = value; 1391 value = value << QDF_MON_STATUS_DCM_SHIFT; 1392 ppdu_info->rx_status.he_data3 |= value; 1393 1394 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1395 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1396 value = value << QDF_MON_STATUS_CODING_SHIFT; 1397 ppdu_info->rx_status.he_data3 |= value; 1398 1399 /* HE-data4 */ 1400 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1401 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1402 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1403 ppdu_info->rx_status.he_data4 |= value; 1404 1405 /* HE-data5 */ 1406 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1407 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1408 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1409 ppdu_info->rx_status.he_data5 |= value; 1410 1411 /* HE-data6 */ 1412 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1413 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1414 /* value n indicates n+1 spatial streams */ 1415 value++; 1416 ppdu_info->rx_status.nss = value; 1417 ppdu_info->rx_status.he_data6 |= value; 1418 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1419 break; 1420 } 1421 case WIFIPHYRX_RSSI_LEGACY_E: 1422 { 1423 uint8_t reception_type; 1424 int8_t rssi_value; 1425 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1426 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1427 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1428 1429 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1430 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1431 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1432 ppdu_info->rx_status.he_re = 0; 1433 1434 reception_type = HAL_RX_GET(rx_tlv, 1435 PHYRX_RSSI_LEGACY_0, 1436 RECEPTION_TYPE); 1437 switch (reception_type) { 1438 case QDF_RECEPTION_TYPE_ULOFMDA: 1439 ppdu_info->rx_status.reception_type = 1440 HAL_RX_TYPE_MU_OFDMA; 1441 ppdu_info->rx_status.ulofdma_flag = 1; 1442 ppdu_info->rx_status.he_data1 = 1443 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1444 break; 1445 case QDF_RECEPTION_TYPE_ULMIMO: 1446 ppdu_info->rx_status.reception_type = 1447 HAL_RX_TYPE_MU_MIMO; 1448 ppdu_info->rx_status.he_data1 = 1449 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1450 break; 1451 default: 1452 ppdu_info->rx_status.reception_type = 1453 HAL_RX_TYPE_SU; 1454 break; 1455 } 1456 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 1457 rssi_value = HAL_RX_GET(rssi_info_tlv, 1458 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1459 ppdu_info->rx_status.rssi[0] = rssi_value; 1460 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1461 "RSSI_PRI20_CHAIN0: %d\n", rssi_value); 1462 1463 rssi_value = HAL_RX_GET(rssi_info_tlv, 1464 RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); 1465 ppdu_info->rx_status.rssi[1] = rssi_value; 1466 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1467 "RSSI_PRI20_CHAIN1: %d\n", rssi_value); 1468 1469 rssi_value = HAL_RX_GET(rssi_info_tlv, 1470 RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); 1471 ppdu_info->rx_status.rssi[2] = rssi_value; 1472 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1473 "RSSI_PRI20_CHAIN2: %d\n", rssi_value); 1474 1475 rssi_value = HAL_RX_GET(rssi_info_tlv, 1476 RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); 1477 ppdu_info->rx_status.rssi[3] = rssi_value; 1478 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1479 "RSSI_PRI20_CHAIN3: %d\n", rssi_value); 1480 1481 rssi_value = HAL_RX_GET(rssi_info_tlv, 1482 RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); 1483 ppdu_info->rx_status.rssi[4] = rssi_value; 1484 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1485 "RSSI_PRI20_CHAIN4: %d\n", rssi_value); 1486 1487 rssi_value = HAL_RX_GET(rssi_info_tlv, 1488 RECEIVE_RSSI_INFO_10, 1489 RSSI_PRI20_CHAIN5); 1490 ppdu_info->rx_status.rssi[5] = rssi_value; 1491 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1492 "RSSI_PRI20_CHAIN5: %d\n", rssi_value); 1493 1494 rssi_value = HAL_RX_GET(rssi_info_tlv, 1495 RECEIVE_RSSI_INFO_12, 1496 RSSI_PRI20_CHAIN6); 1497 ppdu_info->rx_status.rssi[6] = rssi_value; 1498 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1499 "RSSI_PRI20_CHAIN6: %d\n", rssi_value); 1500 1501 rssi_value = HAL_RX_GET(rssi_info_tlv, 1502 RECEIVE_RSSI_INFO_14, 1503 RSSI_PRI20_CHAIN7); 1504 ppdu_info->rx_status.rssi[7] = rssi_value; 1505 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1506 "RSSI_PRI20_CHAIN7: %d\n", rssi_value); 1507 break; 1508 } 1509 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1510 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1511 ppdu_info); 1512 break; 1513 case WIFIRX_HEADER_E: 1514 { 1515 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 1516 1517 if (ppdu_info->fcs_ok_cnt >= 1518 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 1519 hal_err("Number of MPDUs(%d) per status buff exceeded", 1520 ppdu_info->fcs_ok_cnt); 1521 break; 1522 } 1523 1524 /* Update first_msdu_payload for every mpdu and increment 1525 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 1526 */ 1527 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 1528 rx_tlv; 1529 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 1530 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1531 ppdu_info->msdu_info.payload_len = tlv_len; 1532 ppdu_info->user_id = user_id; 1533 ppdu_info->hdr_len = tlv_len; 1534 ppdu_info->data = rx_tlv; 1535 ppdu_info->data += 4; 1536 1537 /* for every RX_HEADER TLV increment mpdu_cnt */ 1538 com_info->mpdu_cnt++; 1539 return HAL_TLV_STATUS_HEADER; 1540 } 1541 case WIFIRX_MPDU_START_E: 1542 { 1543 uint8_t *rx_mpdu_start = 1544 (uint8_t *)rx_tlv + HAL_RX_OFFSET(UNIFIED_RX_MPDU_START_0, 1545 RX_MPDU_INFO_RX_MPDU_INFO_DETAILS); 1546 uint32_t ppdu_id = 1547 HAL_RX_GET_PPDU_ID(rx_mpdu_start); 1548 uint8_t filter_category = 0; 1549 1550 ppdu_info->nac_info.fc_valid = 1551 HAL_RX_GET_FC_VALID(rx_mpdu_start); 1552 1553 ppdu_info->nac_info.to_ds_flag = 1554 HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start); 1555 1556 ppdu_info->nac_info.frame_control = 1557 HAL_RX_GET(rx_mpdu_start, 1558 RX_MPDU_INFO_14, 1559 MPDU_FRAME_CONTROL_FIELD); 1560 1561 ppdu_info->sw_frame_group_id = 1562 HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start); 1563 1564 if (ppdu_info->sw_frame_group_id == 1565 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 1566 ppdu_info->rx_status.frame_control_info_valid = 1567 ppdu_info->nac_info.fc_valid; 1568 ppdu_info->rx_status.frame_control = 1569 ppdu_info->nac_info.frame_control; 1570 } 1571 1572 hal_get_mac_addr1(rx_mpdu_start, 1573 ppdu_info); 1574 1575 ppdu_info->nac_info.mac_addr2_valid = 1576 HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start); 1577 1578 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1579 HAL_RX_GET(rx_mpdu_start, 1580 RX_MPDU_INFO_16, 1581 MAC_ADDR_AD2_15_0); 1582 1583 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1584 HAL_RX_GET(rx_mpdu_start, 1585 RX_MPDU_INFO_17, 1586 MAC_ADDR_AD2_47_16); 1587 1588 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1589 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1590 ppdu_info->rx_status.ppdu_len = 1591 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1592 MPDU_LENGTH); 1593 } else { 1594 ppdu_info->rx_status.ppdu_len += 1595 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1596 MPDU_LENGTH); 1597 } 1598 1599 filter_category = 1600 HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start); 1601 1602 if (filter_category == 0) 1603 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1604 else if (filter_category == 1) 1605 ppdu_info->rx_status.monitor_direct_used = 1; 1606 1607 ppdu_info->nac_info.mcast_bcast = 1608 HAL_RX_GET(rx_mpdu_start, 1609 RX_MPDU_INFO_13, 1610 MCAST_BCAST); 1611 break; 1612 } 1613 case WIFIRX_MPDU_END_E: 1614 ppdu_info->user_id = user_id; 1615 ppdu_info->fcs_err = 1616 HAL_RX_GET(rx_tlv, RX_MPDU_END_1, 1617 FCS_ERR); 1618 return HAL_TLV_STATUS_MPDU_END; 1619 case WIFIRX_MSDU_END_E: 1620 if (user_id < HAL_MAX_UL_MU_USERS) { 1621 ppdu_info->rx_msdu_info[user_id].cce_metadata = 1622 HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); 1623 ppdu_info->rx_msdu_info[user_id].fse_metadata = 1624 HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv); 1625 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 1626 HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv); 1627 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 1628 HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv); 1629 ppdu_info->rx_msdu_info[user_id].flow_idx = 1630 HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv); 1631 } 1632 return HAL_TLV_STATUS_MSDU_END; 1633 case 0: 1634 return HAL_TLV_STATUS_PPDU_DONE; 1635 1636 default: 1637 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1638 unhandled = false; 1639 else 1640 unhandled = true; 1641 break; 1642 } 1643 1644 if (!unhandled) 1645 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1646 "%s TLV type: %d, TLV len:%d %s", 1647 __func__, tlv_tag, tlv_len, 1648 unhandled == true ? "unhandled" : ""); 1649 1650 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1651 rx_tlv, tlv_len); 1652 1653 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1654 } 1655 1656 /** 1657 * hal_reo_setup - Initialize HW REO block 1658 * 1659 * @hal_soc: Opaque HAL SOC handle 1660 * @reo_params: parameters needed by HAL for REO config 1661 */ 1662 static void hal_reo_setup_generic(struct hal_soc *soc, 1663 void *reoparams) 1664 { 1665 uint32_t reg_val; 1666 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1667 1668 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1669 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1670 1671 hal_reo_config(soc, reg_val, reo_params); 1672 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1673 1674 /* TODO: Setup destination ring mapping if enabled */ 1675 1676 /* TODO: Error destination ring setting is left to default. 1677 * Default setting is to send all errors to release ring. 1678 */ 1679 1680 HAL_REG_WRITE(soc, 1681 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 1682 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1683 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1684 1685 HAL_REG_WRITE(soc, 1686 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 1687 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1688 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1689 1690 HAL_REG_WRITE(soc, 1691 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 1692 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1693 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1694 1695 HAL_REG_WRITE(soc, 1696 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 1697 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1698 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1699 1700 /* 1701 * When hash based routing is enabled, routing of the rx packet 1702 * is done based on the following value: 1 _ _ _ _ The last 4 1703 * bits are based on hash[3:0]. This means the possible values 1704 * are 0x10 to 0x1f. This value is used to look-up the 1705 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1706 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1707 * registers need to be configured to set-up the 16 entries to 1708 * map the hash values to a ring number. There are 3 bits per 1709 * hash entry – which are mapped as follows: 1710 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1711 * 7: NOT_USED. 1712 */ 1713 if (reo_params->rx_hash_enabled) { 1714 HAL_REG_WRITE(soc, 1715 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1716 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1717 reo_params->remap1); 1718 1719 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1720 HAL_REG_READ(soc, 1721 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1722 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1723 1724 HAL_REG_WRITE(soc, 1725 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1726 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1727 reo_params->remap2); 1728 1729 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1730 HAL_REG_READ(soc, 1731 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1732 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1733 } 1734 1735 /* TODO: Check if the following registers shoould be setup by host: 1736 * AGING_CONTROL 1737 * HIGH_MEMORY_THRESHOLD 1738 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1739 * GLOBAL_LINK_DESC_COUNT_CTRL 1740 */ 1741 } 1742 1743 /** 1744 * hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring 1745 * @hal_soc: Opaque HAL SOC handle 1746 * @hal_ring: Source ring pointer 1747 * @headp: Head Pointer 1748 * @tailp: Tail Pointer 1749 * @ring: Ring type 1750 * 1751 * Return: Update tail pointer and head pointer in arguments. 1752 */ 1753 static inline 1754 void hal_get_hw_hptp_generic(struct hal_soc *hal_soc, 1755 hal_ring_handle_t hal_ring_hdl, 1756 uint32_t *headp, uint32_t *tailp, 1757 uint8_t ring) 1758 { 1759 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1760 struct hal_hw_srng_config *ring_config; 1761 enum hal_ring_type ring_type = (enum hal_ring_type)ring; 1762 1763 if (!hal_soc || !srng) { 1764 QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_ERROR, 1765 "%s: Context is Null", __func__); 1766 return; 1767 } 1768 1769 ring_config = HAL_SRNG_CONFIG(hal_soc, ring_type); 1770 if (!ring_config->lmac_ring) { 1771 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1772 *headp = SRNG_SRC_REG_READ(srng, HP); 1773 *tailp = SRNG_SRC_REG_READ(srng, TP); 1774 } else { 1775 *headp = SRNG_DST_REG_READ(srng, HP); 1776 *tailp = SRNG_DST_REG_READ(srng, TP); 1777 } 1778 } 1779 } 1780 1781 #if defined(WBM_IDLE_LSB_WRITE_CONFIRM_WAR) 1782 /** 1783 * hal_wbm_idle_lsb_write_confirm() - Check and update WBM_IDLE_LINK ring LSB 1784 * @srng: srng handle 1785 * 1786 * Return: None 1787 */ 1788 static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng) 1789 { 1790 if (srng->ring_id == HAL_SRNG_WBM_IDLE_LINK) { 1791 while (SRNG_SRC_REG_READ(srng, BASE_LSB) != 1792 ((unsigned int)srng->ring_base_paddr & 0xffffffff)) 1793 SRNG_SRC_REG_WRITE(srng, BASE_LSB, 1794 srng->ring_base_paddr & 1795 0xffffffff); 1796 } 1797 } 1798 #else 1799 static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng) 1800 { 1801 } 1802 #endif 1803 1804 /** 1805 * hal_srng_src_hw_init - Private function to initialize SRNG 1806 * source ring HW 1807 * @hal_soc: HAL SOC handle 1808 * @srng: SRNG ring pointer 1809 */ 1810 static inline 1811 void hal_srng_src_hw_init_generic(struct hal_soc *hal, 1812 struct hal_srng *srng) 1813 { 1814 uint32_t reg_val = 0; 1815 uint64_t tp_addr = 0; 1816 1817 hal_debug("hw_init srng %d", srng->ring_id); 1818 1819 if (srng->flags & HAL_SRNG_MSI_INTR) { 1820 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 1821 srng->msi_addr & 0xffffffff); 1822 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 1823 (uint64_t)(srng->msi_addr) >> 32) | 1824 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 1825 MSI1_ENABLE), 1); 1826 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1827 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1828 } 1829 1830 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1831 hal_wbm_idle_lsb_write_confirm(srng); 1832 1833 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1834 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1835 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 1836 srng->entry_size * srng->num_entries); 1837 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 1838 1839 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1840 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 1841 1842 /** 1843 * Interrupt setup: 1844 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1845 * if level mode is required 1846 */ 1847 reg_val = 0; 1848 1849 /* 1850 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 1851 * programmed in terms of 1us resolution instead of 8us resolution as 1852 * given in MLD. 1853 */ 1854 if (srng->intr_timer_thres_us) { 1855 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1856 INTERRUPT_TIMER_THRESHOLD), 1857 srng->intr_timer_thres_us); 1858 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 1859 } 1860 1861 if (srng->intr_batch_cntr_thres_entries) { 1862 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1863 BATCH_COUNTER_THRESHOLD), 1864 srng->intr_batch_cntr_thres_entries * 1865 srng->entry_size); 1866 } 1867 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 1868 1869 reg_val = 0; 1870 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 1871 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 1872 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 1873 } 1874 1875 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 1876 1877 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 1878 * remain 0 to avoid some WBM stability issues. Remote head/tail 1879 * pointers are not required since this ring is completely managed 1880 * by WBM HW 1881 */ 1882 reg_val = 0; 1883 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 1884 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1885 ((unsigned long)(srng->u.src_ring.tp_addr) - 1886 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1887 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 1888 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 1889 } else { 1890 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, RING_ID_DISABLE), 1); 1891 } 1892 1893 /* Initilaize head and tail pointers to indicate ring is empty */ 1894 SRNG_SRC_REG_WRITE(srng, HP, 0); 1895 SRNG_SRC_REG_WRITE(srng, TP, 0); 1896 *(srng->u.src_ring.tp_addr) = 0; 1897 1898 reg_val |= ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1899 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1900 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1901 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1902 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1903 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1904 1905 /* Loop count is not used for SRC rings */ 1906 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 1907 1908 /* 1909 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1910 * todo: update fw_api and replace with above line 1911 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1912 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1913 */ 1914 reg_val |= 0x40; 1915 1916 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 1917 } 1918 1919 /** 1920 * hal_srng_dst_hw_init - Private function to initialize SRNG 1921 * destination ring HW 1922 * @hal_soc: HAL SOC handle 1923 * @srng: SRNG ring pointer 1924 */ 1925 static inline 1926 void hal_srng_dst_hw_init_generic(struct hal_soc *hal, 1927 struct hal_srng *srng) 1928 { 1929 uint32_t reg_val = 0; 1930 uint64_t hp_addr = 0; 1931 1932 hal_debug("hw_init srng %d", srng->ring_id); 1933 1934 if (srng->flags & HAL_SRNG_MSI_INTR) { 1935 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 1936 srng->msi_addr & 0xffffffff); 1937 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 1938 (uint64_t)(srng->msi_addr) >> 32) | 1939 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 1940 MSI1_ENABLE), 1); 1941 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1942 SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1943 } 1944 1945 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1946 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1947 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1948 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 1949 srng->entry_size * srng->num_entries); 1950 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 1951 1952 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 1953 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 1954 SRNG_DST_REG_WRITE(srng, ID, reg_val); 1955 1956 1957 /** 1958 * Interrupt setup: 1959 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1960 * if level mode is required 1961 */ 1962 reg_val = 0; 1963 if (srng->intr_timer_thres_us) { 1964 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1965 INTERRUPT_TIMER_THRESHOLD), 1966 srng->intr_timer_thres_us >> 3); 1967 } 1968 1969 if (srng->intr_batch_cntr_thres_entries) { 1970 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1971 BATCH_COUNTER_THRESHOLD), 1972 srng->intr_batch_cntr_thres_entries * 1973 srng->entry_size); 1974 } 1975 1976 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 1977 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1978 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1979 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1980 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 1981 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 1982 1983 /* Initilaize head and tail pointers to indicate ring is empty */ 1984 SRNG_DST_REG_WRITE(srng, HP, 0); 1985 SRNG_DST_REG_WRITE(srng, TP, 0); 1986 *(srng->u.dst_ring.hp_addr) = 0; 1987 1988 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1989 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1990 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1991 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1992 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1993 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1994 1995 /* 1996 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1997 * todo: update fw_api and replace with above line 1998 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1999 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 2000 */ 2001 reg_val |= 0x40; 2002 2003 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 2004 2005 } 2006 2007 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2008 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 2009 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 2010 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 2011 2012 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2013 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 2014 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 2015 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 2016 2017 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2018 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 2019 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 2020 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 2021 2022 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 2023 (((*(((uint32_t *) wbm_desc) + \ 2024 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 2025 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 2026 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 2027 2028 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 2029 (((*(((uint32_t *) wbm_desc) + \ 2030 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 2031 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 2032 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 2033 2034 /** 2035 * hal_rx_wbm_err_info_get_generic(): Retrieves WBM error code and reason and 2036 * save it to hal_wbm_err_desc_info structure passed by caller 2037 * @wbm_desc: wbm ring descriptor 2038 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 2039 * Return: void 2040 */ 2041 static inline void hal_rx_wbm_err_info_get_generic(void *wbm_desc, 2042 void *wbm_er_info1) 2043 { 2044 struct hal_wbm_err_desc_info *wbm_er_info = 2045 (struct hal_wbm_err_desc_info *)wbm_er_info1; 2046 2047 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 2048 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 2049 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 2050 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 2051 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 2052 } 2053 2054 /** 2055 * hal_tx_comp_get_release_reason_generic() - TQM Release reason 2056 * @hal_desc: completion ring descriptor pointer 2057 * 2058 * This function will return the type of pointer - buffer or descriptor 2059 * 2060 * Return: buffer type 2061 */ 2062 static inline uint8_t hal_tx_comp_get_release_reason_generic(void *hal_desc) 2063 { 2064 uint32_t comp_desc = 2065 *(uint32_t *) (((uint8_t *) hal_desc) + 2066 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 2067 2068 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 2069 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 2070 } 2071 2072 /** 2073 * hal_get_wbm_internal_error_generic() - is WBM internal error 2074 * @hal_desc: completion ring descriptor pointer 2075 * 2076 * This function will return 0 or 1 - is it WBM internal error or not 2077 * 2078 * Return: uint8_t 2079 */ 2080 static inline uint8_t hal_get_wbm_internal_error_generic(void *hal_desc) 2081 { 2082 uint32_t comp_desc = 2083 *(uint32_t *)(((uint8_t *)hal_desc) + 2084 WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET); 2085 2086 return (comp_desc & WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK) >> 2087 WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB; 2088 } 2089 2090 /** 2091 * hal_rx_dump_mpdu_start_tlv_generic: dump RX mpdu_start TLV in structured 2092 * human readable format. 2093 * @mpdu_start: pointer the rx_attention TLV in pkt. 2094 * @dbg_level: log level. 2095 * 2096 * Return: void 2097 */ 2098 static inline void hal_rx_dump_mpdu_start_tlv_generic(void *mpdustart, 2099 uint8_t dbg_level) 2100 { 2101 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 2102 struct rx_mpdu_info *mpdu_info = 2103 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 2104 2105 hal_verbose_debug( 2106 "rx_mpdu_start tlv (1/5) - " 2107 "rxpcu_mpdu_filter_in_category: %x " 2108 "sw_frame_group_id: %x " 2109 "ndp_frame: %x " 2110 "phy_err: %x " 2111 "phy_err_during_mpdu_header: %x " 2112 "protocol_version_err: %x " 2113 "ast_based_lookup_valid: %x " 2114 "phy_ppdu_id: %x " 2115 "ast_index: %x " 2116 "sw_peer_id: %x " 2117 "mpdu_frame_control_valid: %x " 2118 "mpdu_duration_valid: %x " 2119 "mac_addr_ad1_valid: %x " 2120 "mac_addr_ad2_valid: %x " 2121 "mac_addr_ad3_valid: %x " 2122 "mac_addr_ad4_valid: %x " 2123 "mpdu_sequence_control_valid: %x " 2124 "mpdu_qos_control_valid: %x " 2125 "mpdu_ht_control_valid: %x " 2126 "frame_encryption_info_valid: %x ", 2127 mpdu_info->rxpcu_mpdu_filter_in_category, 2128 mpdu_info->sw_frame_group_id, 2129 mpdu_info->ndp_frame, 2130 mpdu_info->phy_err, 2131 mpdu_info->phy_err_during_mpdu_header, 2132 mpdu_info->protocol_version_err, 2133 mpdu_info->ast_based_lookup_valid, 2134 mpdu_info->phy_ppdu_id, 2135 mpdu_info->ast_index, 2136 mpdu_info->sw_peer_id, 2137 mpdu_info->mpdu_frame_control_valid, 2138 mpdu_info->mpdu_duration_valid, 2139 mpdu_info->mac_addr_ad1_valid, 2140 mpdu_info->mac_addr_ad2_valid, 2141 mpdu_info->mac_addr_ad3_valid, 2142 mpdu_info->mac_addr_ad4_valid, 2143 mpdu_info->mpdu_sequence_control_valid, 2144 mpdu_info->mpdu_qos_control_valid, 2145 mpdu_info->mpdu_ht_control_valid, 2146 mpdu_info->frame_encryption_info_valid); 2147 2148 hal_verbose_debug( 2149 "rx_mpdu_start tlv (2/5) - " 2150 "fr_ds: %x " 2151 "to_ds: %x " 2152 "encrypted: %x " 2153 "mpdu_retry: %x " 2154 "mpdu_sequence_number: %x " 2155 "epd_en: %x " 2156 "all_frames_shall_be_encrypted: %x " 2157 "encrypt_type: %x " 2158 "mesh_sta: %x " 2159 "bssid_hit: %x " 2160 "bssid_number: %x " 2161 "tid: %x " 2162 "pn_31_0: %x " 2163 "pn_63_32: %x " 2164 "pn_95_64: %x " 2165 "pn_127_96: %x " 2166 "peer_meta_data: %x " 2167 "rxpt_classify_info.reo_destination_indication: %x " 2168 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 2169 "rx_reo_queue_desc_addr_31_0: %x ", 2170 mpdu_info->fr_ds, 2171 mpdu_info->to_ds, 2172 mpdu_info->encrypted, 2173 mpdu_info->mpdu_retry, 2174 mpdu_info->mpdu_sequence_number, 2175 mpdu_info->epd_en, 2176 mpdu_info->all_frames_shall_be_encrypted, 2177 mpdu_info->encrypt_type, 2178 mpdu_info->mesh_sta, 2179 mpdu_info->bssid_hit, 2180 mpdu_info->bssid_number, 2181 mpdu_info->tid, 2182 mpdu_info->pn_31_0, 2183 mpdu_info->pn_63_32, 2184 mpdu_info->pn_95_64, 2185 mpdu_info->pn_127_96, 2186 mpdu_info->peer_meta_data, 2187 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 2188 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 2189 mpdu_info->rx_reo_queue_desc_addr_31_0); 2190 2191 hal_verbose_debug( 2192 "rx_mpdu_start tlv (3/5) - " 2193 "rx_reo_queue_desc_addr_39_32: %x " 2194 "receive_queue_number: %x " 2195 "pre_delim_err_warning: %x " 2196 "first_delim_err: %x " 2197 "key_id_octet: %x " 2198 "new_peer_entry: %x " 2199 "decrypt_needed: %x " 2200 "decap_type: %x " 2201 "rx_insert_vlan_c_tag_padding: %x " 2202 "rx_insert_vlan_s_tag_padding: %x " 2203 "strip_vlan_c_tag_decap: %x " 2204 "strip_vlan_s_tag_decap: %x " 2205 "pre_delim_count: %x " 2206 "ampdu_flag: %x " 2207 "bar_frame: %x " 2208 "mpdu_length: %x " 2209 "first_mpdu: %x " 2210 "mcast_bcast: %x " 2211 "ast_index_not_found: %x " 2212 "ast_index_timeout: %x ", 2213 mpdu_info->rx_reo_queue_desc_addr_39_32, 2214 mpdu_info->receive_queue_number, 2215 mpdu_info->pre_delim_err_warning, 2216 mpdu_info->first_delim_err, 2217 mpdu_info->key_id_octet, 2218 mpdu_info->new_peer_entry, 2219 mpdu_info->decrypt_needed, 2220 mpdu_info->decap_type, 2221 mpdu_info->rx_insert_vlan_c_tag_padding, 2222 mpdu_info->rx_insert_vlan_s_tag_padding, 2223 mpdu_info->strip_vlan_c_tag_decap, 2224 mpdu_info->strip_vlan_s_tag_decap, 2225 mpdu_info->pre_delim_count, 2226 mpdu_info->ampdu_flag, 2227 mpdu_info->bar_frame, 2228 mpdu_info->mpdu_length, 2229 mpdu_info->first_mpdu, 2230 mpdu_info->mcast_bcast, 2231 mpdu_info->ast_index_not_found, 2232 mpdu_info->ast_index_timeout); 2233 2234 hal_verbose_debug( 2235 "rx_mpdu_start tlv (4/5) - " 2236 "power_mgmt: %x " 2237 "non_qos: %x " 2238 "null_data: %x " 2239 "mgmt_type: %x " 2240 "ctrl_type: %x " 2241 "more_data: %x " 2242 "eosp: %x " 2243 "fragment_flag: %x " 2244 "order: %x " 2245 "u_apsd_trigger: %x " 2246 "encrypt_required: %x " 2247 "directed: %x " 2248 "mpdu_frame_control_field: %x " 2249 "mpdu_duration_field: %x " 2250 "mac_addr_ad1_31_0: %x " 2251 "mac_addr_ad1_47_32: %x " 2252 "mac_addr_ad2_15_0: %x " 2253 "mac_addr_ad2_47_16: %x " 2254 "mac_addr_ad3_31_0: %x " 2255 "mac_addr_ad3_47_32: %x ", 2256 mpdu_info->power_mgmt, 2257 mpdu_info->non_qos, 2258 mpdu_info->null_data, 2259 mpdu_info->mgmt_type, 2260 mpdu_info->ctrl_type, 2261 mpdu_info->more_data, 2262 mpdu_info->eosp, 2263 mpdu_info->fragment_flag, 2264 mpdu_info->order, 2265 mpdu_info->u_apsd_trigger, 2266 mpdu_info->encrypt_required, 2267 mpdu_info->directed, 2268 mpdu_info->mpdu_frame_control_field, 2269 mpdu_info->mpdu_duration_field, 2270 mpdu_info->mac_addr_ad1_31_0, 2271 mpdu_info->mac_addr_ad1_47_32, 2272 mpdu_info->mac_addr_ad2_15_0, 2273 mpdu_info->mac_addr_ad2_47_16, 2274 mpdu_info->mac_addr_ad3_31_0, 2275 mpdu_info->mac_addr_ad3_47_32); 2276 2277 hal_verbose_debug( 2278 "rx_mpdu_start tlv (5/5) - " 2279 "mpdu_sequence_control_field: %x " 2280 "mac_addr_ad4_31_0: %x " 2281 "mac_addr_ad4_47_32: %x " 2282 "mpdu_qos_control_field: %x " 2283 "mpdu_ht_control_field: %x ", 2284 mpdu_info->mpdu_sequence_control_field, 2285 mpdu_info->mac_addr_ad4_31_0, 2286 mpdu_info->mac_addr_ad4_47_32, 2287 mpdu_info->mpdu_qos_control_field, 2288 mpdu_info->mpdu_ht_control_field); 2289 } 2290 2291 /** 2292 * hal_tx_desc_set_search_type - Set the search type value 2293 * @desc: Handle to Tx Descriptor 2294 * @search_type: search type 2295 * 0 – Normal search 2296 * 1 – Index based address search 2297 * 2 – Index based flow search 2298 * 2299 * Return: void 2300 */ 2301 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 2302 static void hal_tx_desc_set_search_type_generic(void *desc, 2303 uint8_t search_type) 2304 { 2305 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 2306 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 2307 } 2308 #else 2309 static void hal_tx_desc_set_search_type_generic(void *desc, 2310 uint8_t search_type) 2311 { 2312 } 2313 2314 #endif 2315 2316 /** 2317 * hal_tx_desc_set_search_index - Set the search index value 2318 * @desc: Handle to Tx Descriptor 2319 * @search_index: The index that will be used for index based address or 2320 * flow search. The field is valid when 'search_type' is 2321 * 1 0r 2 2322 * 2323 * Return: void 2324 */ 2325 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 2326 static void hal_tx_desc_set_search_index_generic(void *desc, 2327 uint32_t search_index) 2328 { 2329 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 2330 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 2331 } 2332 #else 2333 static void hal_tx_desc_set_search_index_generic(void *desc, 2334 uint32_t search_index) 2335 { 2336 } 2337 #endif 2338 2339 /** 2340 * hal_tx_desc_set_cache_set_num_generic - Set the cache-set-num value 2341 * @desc: Handle to Tx Descriptor 2342 * @cache_num: Cache set number that should be used to cache the index 2343 * based search results, for address and flow search. 2344 * This value should be equal to LSB four bits of the hash value 2345 * of match data, in case of search index points to an entry 2346 * which may be used in content based search also. The value can 2347 * be anything when the entry pointed by search index will not be 2348 * used for content based search. 2349 * 2350 * Return: void 2351 */ 2352 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 2353 static void hal_tx_desc_set_cache_set_num_generic(void *desc, 2354 uint8_t cache_num) 2355 { 2356 HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |= 2357 HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num); 2358 } 2359 #else 2360 static void hal_tx_desc_set_cache_set_num_generic(void *desc, 2361 uint8_t cache_num) 2362 { 2363 } 2364 #endif 2365 2366 /** 2367 * hal_tx_set_pcp_tid_map_generic() - Configure default PCP to TID map table 2368 * @soc: HAL SoC context 2369 * @map: PCP-TID mapping table 2370 * 2371 * PCP are mapped to 8 TID values using TID values programmed 2372 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 2373 * The mapping register has TID mapping for 8 PCP values 2374 * 2375 * Return: none 2376 */ 2377 static void hal_tx_set_pcp_tid_map_generic(struct hal_soc *soc, uint8_t *map) 2378 { 2379 uint32_t addr, value; 2380 2381 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2382 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2383 2384 value = (map[0] | 2385 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 2386 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 2387 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 2388 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 2389 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 2390 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 2391 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 2392 2393 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2394 } 2395 2396 /** 2397 * hal_tx_update_pcp_tid_generic() - Update the pcp tid map table with 2398 * value received from user-space 2399 * @soc: HAL SoC context 2400 * @pcp: pcp value 2401 * @tid : tid value 2402 * 2403 * Return: void 2404 */ 2405 static 2406 void hal_tx_update_pcp_tid_generic(struct hal_soc *soc, 2407 uint8_t pcp, uint8_t tid) 2408 { 2409 uint32_t addr, value, regval; 2410 2411 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2412 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2413 2414 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 2415 2416 /* Read back previous PCP TID config and update 2417 * with new config. 2418 */ 2419 regval = HAL_REG_READ(soc, addr); 2420 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 2421 regval |= value; 2422 2423 HAL_REG_WRITE(soc, addr, 2424 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2425 } 2426 2427 /** 2428 * hal_tx_update_tidmap_prty_generic() - Update the tid map priority 2429 * @soc: HAL SoC context 2430 * @val: priority value 2431 * 2432 * Return: void 2433 */ 2434 static 2435 void hal_tx_update_tidmap_prty_generic(struct hal_soc *soc, uint8_t value) 2436 { 2437 uint32_t addr; 2438 2439 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 2440 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2441 2442 HAL_REG_WRITE(soc, addr, 2443 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 2444 } 2445 2446 /** 2447 * hal_rx_msdu_packet_metadata_get(): API to get the 2448 * msdu information from rx_msdu_end TLV 2449 * 2450 * @ buf: pointer to the start of RX PKT TLV headers 2451 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 2452 */ 2453 static void 2454 hal_rx_msdu_packet_metadata_get_generic(uint8_t *buf, 2455 void *pkt_msdu_metadata) 2456 { 2457 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2458 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 2459 struct hal_rx_msdu_metadata *msdu_metadata = 2460 (struct hal_rx_msdu_metadata *)pkt_msdu_metadata; 2461 2462 msdu_metadata->l3_hdr_pad = 2463 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 2464 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 2465 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 2466 msdu_metadata->sa_sw_peer_id = 2467 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 2468 } 2469 2470 /** 2471 * hal_rx_msdu_end_offset_get_generic(): API to get the 2472 * msdu_end structure offset rx_pkt_tlv structure 2473 * 2474 * NOTE: API returns offset of msdu_end TLV from structure 2475 * rx_pkt_tlvs 2476 */ 2477 static uint32_t hal_rx_msdu_end_offset_get_generic(void) 2478 { 2479 return RX_PKT_TLV_OFFSET(msdu_end_tlv); 2480 } 2481 2482 /** 2483 * hal_rx_attn_offset_get_generic(): API to get the 2484 * msdu_end structure offset rx_pkt_tlv structure 2485 * 2486 * NOTE: API returns offset of attn TLV from structure 2487 * rx_pkt_tlvs 2488 */ 2489 static uint32_t hal_rx_attn_offset_get_generic(void) 2490 { 2491 return RX_PKT_TLV_OFFSET(attn_tlv); 2492 } 2493 2494 /** 2495 * hal_rx_msdu_start_offset_get_generic(): API to get the 2496 * msdu_start structure offset rx_pkt_tlv structure 2497 * 2498 * NOTE: API returns offset of attn TLV from structure 2499 * rx_pkt_tlvs 2500 */ 2501 static uint32_t hal_rx_msdu_start_offset_get_generic(void) 2502 { 2503 return RX_PKT_TLV_OFFSET(msdu_start_tlv); 2504 } 2505 2506 /** 2507 * hal_rx_mpdu_start_offset_get_generic(): API to get the 2508 * mpdu_start structure offset rx_pkt_tlv structure 2509 * 2510 * NOTE: API returns offset of attn TLV from structure 2511 * rx_pkt_tlvs 2512 */ 2513 static uint32_t hal_rx_mpdu_start_offset_get_generic(void) 2514 { 2515 return RX_PKT_TLV_OFFSET(mpdu_start_tlv); 2516 } 2517 2518 /** 2519 * hal_rx_mpdu_end_offset_get_generic(): API to get the 2520 * mpdu_end structure offset rx_pkt_tlv structure 2521 * 2522 * NOTE: API returns offset of attn TLV from structure 2523 * rx_pkt_tlvs 2524 */ 2525 static uint32_t hal_rx_mpdu_end_offset_get_generic(void) 2526 { 2527 return RX_PKT_TLV_OFFSET(mpdu_end_tlv); 2528 } 2529 #endif /* HAL_GENERIC_API_H_ */ 2530