1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 22 ((struct rx_msdu_desc_info *) \ 23 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 24 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 25 /** 26 * hal_rx_msdu_desc_info_get_ptr_generic() - Get msdu desc info ptr 27 * @msdu_details_ptr - Pointer to msdu_details_ptr 28 * Return - Pointer to rx_msdu_desc_info structure. 29 * 30 */ 31 static void *hal_rx_msdu_desc_info_get_ptr_generic(void *msdu_details_ptr) 32 { 33 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 34 } 35 36 37 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 38 ((struct rx_msdu_details *) \ 39 _OFFSET_TO_BYTE_PTR((link_desc),\ 40 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 41 /** 42 * hal_rx_link_desc_msdu0_ptr_generic - Get pointer to rx_msdu details 43 * @link_desc - Pointer to link desc 44 * Return - Pointer to rx_msdu_details structure 45 * 46 */ 47 48 static void *hal_rx_link_desc_msdu0_ptr_generic(void *link_desc) 49 { 50 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 51 } 52 53 /** 54 * hal_tx_comp_get_status() - TQM Release reason 55 * @hal_desc: completion ring Tx status 56 * 57 * This function will parse the WBM completion descriptor and populate in 58 * HAL structure 59 * 60 * Return: none 61 */ 62 #if defined(WCSS_VERSION) && \ 63 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 64 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 65 static inline void hal_tx_comp_get_status_generic(void *desc, 66 void *ts1, void *hal) 67 { 68 uint8_t rate_stats_valid = 0; 69 uint32_t rate_stats = 0; 70 struct hal_tx_completion_status *ts = 71 (struct hal_tx_completion_status *)ts1; 72 73 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 74 TQM_STATUS_NUMBER); 75 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 76 ACK_FRAME_RSSI); 77 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 78 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 79 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 80 MSDU_PART_OF_AMSDU); 81 82 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 83 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 84 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 85 TRANSMIT_COUNT); 86 87 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 88 TX_RATE_STATS); 89 90 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 91 TX_RATE_STATS_INFO_VALID, rate_stats); 92 93 ts->valid = rate_stats_valid; 94 95 if (rate_stats_valid) { 96 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 97 rate_stats); 98 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 99 TRANSMIT_PKT_TYPE, rate_stats); 100 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 101 TRANSMIT_STBC, rate_stats); 102 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 103 rate_stats); 104 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 105 rate_stats); 106 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 107 rate_stats); 108 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 109 rate_stats); 110 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 111 rate_stats); 112 } 113 114 ts->release_src = hal_tx_comp_get_buffer_source(desc); 115 ts->status = hal_tx_comp_get_release_reason(desc, hal); 116 117 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 118 TX_RATE_STATS_INFO_TX_RATE_STATS); 119 } 120 #else 121 static inline void hal_tx_comp_get_status_generic(void *desc, 122 struct hal_tx_completion_status *ts, void *hal) 123 { 124 125 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 126 TQM_STATUS_NUMBER); 127 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 128 ACK_FRAME_RSSI); 129 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 130 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 131 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 132 MSDU_PART_OF_AMSDU); 133 134 ts->release_src = hal_tx_comp_get_buffer_source(desc); 135 ts->status = hal_tx_comp_get_release_reason(desc, hal); 136 } 137 #endif 138 139 140 /** 141 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 142 * @desc: Handle to Tx Descriptor 143 * @paddr: Physical Address 144 * @pool_id: Return Buffer Manager ID 145 * @desc_id: Descriptor ID 146 * @type: 0 - Address points to a MSDU buffer 147 * 1 - Address points to MSDU extension descriptor 148 * 149 * Return: void 150 */ 151 static inline void hal_tx_desc_set_buf_addr_generic(void *desc, 152 dma_addr_t paddr, uint8_t pool_id, 153 uint32_t desc_id, uint8_t type) 154 { 155 /* Set buffer_addr_info.buffer_addr_31_0 */ 156 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 157 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 158 159 /* Set buffer_addr_info.buffer_addr_39_32 */ 160 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 161 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 162 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 163 (((uint64_t) paddr) >> 32)); 164 165 /* Set buffer_addr_info.return_buffer_manager = pool id */ 166 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 167 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 168 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 169 RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID)); 170 171 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 172 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 173 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 174 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 175 176 /* Set Buffer or Ext Descriptor Type */ 177 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 178 BUF_OR_EXT_DESC_TYPE) |= 179 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 180 } 181 182 #if defined(CONFIG_MCL) && defined(QCA_WIFI_QCA6290_11AX) 183 /** 184 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 185 * tlv_tag: Taf of the TLVs 186 * rx_tlv: the pointer to the TLVs 187 * @ppdu_info: pointer to ppdu_info 188 * 189 * Return: true if the tlv is handled, false if not 190 */ 191 static inline bool 192 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 193 struct hal_rx_ppdu_info *ppdu_info) 194 { 195 uint32_t value; 196 197 switch (tlv_tag) { 198 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 199 { 200 uint8_t *he_sig_a_mu_ul_info = 201 (uint8_t *)rx_tlv + 202 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 203 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 204 ppdu_info->rx_status.he_flags = 1; 205 206 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 207 FORMAT_INDICATION); 208 if (value == 0) { 209 ppdu_info->rx_status.he_data1 = 210 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 211 } else { 212 ppdu_info->rx_status.he_data1 = 213 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 214 } 215 216 /* data1 */ 217 ppdu_info->rx_status.he_data1 |= 218 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 219 QDF_MON_STATUS_HE_DL_UL_KNOWN | 220 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 221 222 /* data2 */ 223 ppdu_info->rx_status.he_data2 |= 224 QDF_MON_STATUS_TXOP_KNOWN; 225 226 /*data3*/ 227 value = HAL_RX_GET(he_sig_a_mu_ul_info, 228 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 229 ppdu_info->rx_status.he_data3 = value; 230 /* 1 for UL and 0 for DL */ 231 value = 1; 232 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 233 ppdu_info->rx_status.he_data3 |= value; 234 235 /*data4*/ 236 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 237 SPATIAL_REUSE); 238 ppdu_info->rx_status.he_data4 = value; 239 240 /*data5*/ 241 value = HAL_RX_GET(he_sig_a_mu_ul_info, 242 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 243 ppdu_info->rx_status.he_data5 = value; 244 ppdu_info->rx_status.bw = value; 245 246 /*data6*/ 247 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 248 TXOP_DURATION); 249 value = value << QDF_MON_STATUS_TXOP_SHIFT; 250 ppdu_info->rx_status.he_data6 |= value; 251 return true; 252 } 253 default: 254 return false; 255 } 256 } 257 #else 258 static inline bool 259 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 260 struct hal_rx_ppdu_info *ppdu_info) 261 { 262 return false; 263 } 264 #endif /* CONFIG_MCL && QCA_WIFI_QCA6290_11AX */ 265 266 /** 267 * hal_rx_status_get_tlv_info() - process receive info TLV 268 * @rx_tlv_hdr: pointer to TLV header 269 * @ppdu_info: pointer to ppdu_info 270 * 271 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 272 */ 273 static inline uint32_t 274 hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, 275 void *halsoc) 276 { 277 struct hal_soc *hal = (struct hal_soc *)halsoc; 278 uint32_t tlv_tag, user_id, tlv_len, value; 279 uint8_t group_id = 0; 280 uint8_t he_dcm = 0; 281 uint8_t he_stbc = 0; 282 uint16_t he_gi = 0; 283 uint16_t he_ltf = 0; 284 void *rx_tlv; 285 bool unhandled = false; 286 struct hal_rx_ppdu_info *ppdu_info = 287 (struct hal_rx_ppdu_info *)ppduinfo; 288 289 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 290 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 291 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 292 293 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 294 switch (tlv_tag) { 295 296 case WIFIRX_PPDU_START_E: 297 ppdu_info->com_info.ppdu_id = 298 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 299 PHY_PPDU_ID); 300 /* channel number is set in PHY meta data */ 301 ppdu_info->rx_status.chan_num = 302 HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 303 SW_PHY_META_DATA); 304 ppdu_info->com_info.ppdu_timestamp = 305 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 306 PPDU_START_TIMESTAMP); 307 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 308 break; 309 310 case WIFIRX_PPDU_START_USER_INFO_E: 311 break; 312 313 case WIFIRX_PPDU_END_E: 314 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 315 "[%s][%d] ppdu_end_e len=%d", 316 __func__, __LINE__, tlv_len); 317 /* This is followed by sub-TLVs of PPDU_END */ 318 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 319 break; 320 321 case WIFIRXPCU_PPDU_END_INFO_E: 322 ppdu_info->rx_status.tsft = 323 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 324 WB_TIMESTAMP_UPPER_32); 325 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 326 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 327 WB_TIMESTAMP_LOWER_32); 328 ppdu_info->rx_status.duration = 329 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 330 RX_PPDU_DURATION); 331 break; 332 333 case WIFIRX_PPDU_END_USER_STATS_E: 334 { 335 unsigned long tid = 0; 336 uint16_t seq = 0; 337 338 ppdu_info->rx_status.ast_index = 339 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 340 AST_INDEX); 341 342 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 343 RECEIVED_QOS_DATA_TID_BITMAP); 344 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 345 346 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 347 ppdu_info->rx_status.tid = HAL_TID_INVALID; 348 349 ppdu_info->rx_status.tcp_msdu_count = 350 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 351 TCP_MSDU_COUNT) + 352 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 353 TCP_ACK_MSDU_COUNT); 354 ppdu_info->rx_status.udp_msdu_count = 355 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 356 UDP_MSDU_COUNT); 357 ppdu_info->rx_status.other_msdu_count = 358 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 359 OTHER_MSDU_COUNT); 360 361 ppdu_info->rx_status.frame_control_info_valid = 362 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 363 FRAME_CONTROL_INFO_VALID); 364 365 if (ppdu_info->rx_status.frame_control_info_valid) 366 ppdu_info->rx_status.frame_control = 367 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 368 FRAME_CONTROL_FIELD); 369 370 ppdu_info->rx_status.data_sequence_control_info_valid = 371 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 372 DATA_SEQUENCE_CONTROL_INFO_VALID); 373 374 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 375 FIRST_DATA_SEQ_CTRL); 376 if (ppdu_info->rx_status.data_sequence_control_info_valid) 377 ppdu_info->rx_status.first_data_seq_ctrl = seq; 378 379 ppdu_info->rx_status.preamble_type = 380 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 381 HT_CONTROL_FIELD_PKT_TYPE); 382 switch (ppdu_info->rx_status.preamble_type) { 383 case HAL_RX_PKT_TYPE_11N: 384 ppdu_info->rx_status.ht_flags = 1; 385 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 386 break; 387 case HAL_RX_PKT_TYPE_11AC: 388 ppdu_info->rx_status.vht_flags = 1; 389 break; 390 case HAL_RX_PKT_TYPE_11AX: 391 ppdu_info->rx_status.he_flags = 1; 392 break; 393 default: 394 break; 395 } 396 397 ppdu_info->com_info.mpdu_cnt_fcs_ok = 398 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 399 MPDU_CNT_FCS_OK); 400 ppdu_info->com_info.mpdu_cnt_fcs_err = 401 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 402 MPDU_CNT_FCS_ERR); 403 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 404 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 405 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 406 else 407 ppdu_info->rx_status.rs_flags &= 408 (~IEEE80211_AMPDU_FLAG); 409 break; 410 } 411 412 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 413 break; 414 415 case WIFIRX_PPDU_END_STATUS_DONE_E: 416 return HAL_TLV_STATUS_PPDU_DONE; 417 418 case WIFIDUMMY_E: 419 return HAL_TLV_STATUS_BUF_DONE; 420 421 case WIFIPHYRX_HT_SIG_E: 422 { 423 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 424 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 425 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 426 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 427 FEC_CODING); 428 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 429 1 : 0; 430 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 431 HT_SIG_INFO_0, MCS); 432 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 433 HT_SIG_INFO_0, CBW); 434 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 435 HT_SIG_INFO_1, SHORT_GI); 436 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 437 break; 438 } 439 440 case WIFIPHYRX_L_SIG_B_E: 441 { 442 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 443 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 444 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 445 446 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 447 switch (value) { 448 case 1: 449 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 450 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 451 break; 452 case 2: 453 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 454 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 455 break; 456 case 3: 457 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 458 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 459 break; 460 case 4: 461 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 462 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 463 break; 464 case 5: 465 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 466 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 467 break; 468 case 6: 469 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 470 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 471 break; 472 case 7: 473 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 474 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 475 break; 476 default: 477 break; 478 } 479 ppdu_info->rx_status.cck_flag = 1; 480 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 481 break; 482 } 483 484 case WIFIPHYRX_L_SIG_A_E: 485 { 486 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 487 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 488 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 489 490 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 491 switch (value) { 492 case 8: 493 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 494 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 495 break; 496 case 9: 497 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 498 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 499 break; 500 case 10: 501 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 502 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 503 break; 504 case 11: 505 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 506 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 507 break; 508 case 12: 509 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 510 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 511 break; 512 case 13: 513 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 514 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 515 break; 516 case 14: 517 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 518 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 519 break; 520 case 15: 521 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 522 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 523 break; 524 default: 525 break; 526 } 527 ppdu_info->rx_status.ofdm_flag = 1; 528 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 529 break; 530 } 531 532 case WIFIPHYRX_VHT_SIG_A_E: 533 { 534 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 535 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 536 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 537 538 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 539 SU_MU_CODING); 540 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 541 1 : 0; 542 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 543 ppdu_info->rx_status.vht_flag_values5 = group_id; 544 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 545 VHT_SIG_A_INFO_1, MCS); 546 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 547 VHT_SIG_A_INFO_1, GI_SETTING); 548 549 switch (hal->target_type) { 550 case TARGET_TYPE_QCA8074: 551 case TARGET_TYPE_QCA8074V2: 552 ppdu_info->rx_status.is_stbc = 553 HAL_RX_GET(vht_sig_a_info, 554 VHT_SIG_A_INFO_0, STBC); 555 value = HAL_RX_GET(vht_sig_a_info, 556 VHT_SIG_A_INFO_0, N_STS); 557 if (ppdu_info->rx_status.is_stbc && (value > 0)) 558 value = ((value + 1) >> 1) - 1; 559 ppdu_info->rx_status.nss = 560 ((value & VHT_SIG_SU_NSS_MASK) + 1); 561 562 break; 563 case TARGET_TYPE_QCA6290: 564 #if !defined(QCA_WIFI_QCA6290_11AX) 565 ppdu_info->rx_status.is_stbc = 566 HAL_RX_GET(vht_sig_a_info, 567 VHT_SIG_A_INFO_0, STBC); 568 value = HAL_RX_GET(vht_sig_a_info, 569 VHT_SIG_A_INFO_0, N_STS); 570 if (ppdu_info->rx_status.is_stbc && (value > 0)) 571 value = ((value + 1) >> 1) - 1; 572 ppdu_info->rx_status.nss = 573 ((value & VHT_SIG_SU_NSS_MASK) + 1); 574 #else 575 ppdu_info->rx_status.nss = 0; 576 #endif 577 break; 578 #ifdef QCA_WIFI_QCA6390 579 case TARGET_TYPE_QCA6390: 580 ppdu_info->rx_status.nss = 0; 581 break; 582 #endif 583 default: 584 break; 585 } 586 ppdu_info->rx_status.vht_flag_values3[0] = 587 (((ppdu_info->rx_status.mcs) << 4) 588 | ppdu_info->rx_status.nss); 589 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 590 VHT_SIG_A_INFO_0, BANDWIDTH); 591 ppdu_info->rx_status.vht_flag_values2 = 592 ppdu_info->rx_status.bw; 593 ppdu_info->rx_status.vht_flag_values4 = 594 HAL_RX_GET(vht_sig_a_info, 595 VHT_SIG_A_INFO_1, SU_MU_CODING); 596 597 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 598 VHT_SIG_A_INFO_1, BEAMFORMED); 599 if (group_id == 0 || group_id == 63) 600 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 601 else 602 ppdu_info->rx_status.reception_type = 603 HAL_RX_TYPE_MU_MIMO; 604 605 break; 606 } 607 case WIFIPHYRX_HE_SIG_A_SU_E: 608 { 609 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 610 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 611 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 612 ppdu_info->rx_status.he_flags = 1; 613 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 614 FORMAT_INDICATION); 615 if (value == 0) { 616 ppdu_info->rx_status.he_data1 = 617 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 618 } else { 619 ppdu_info->rx_status.he_data1 = 620 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 621 } 622 623 /* data1 */ 624 ppdu_info->rx_status.he_data1 |= 625 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 626 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 627 QDF_MON_STATUS_HE_DL_UL_KNOWN | 628 QDF_MON_STATUS_HE_MCS_KNOWN | 629 QDF_MON_STATUS_HE_DCM_KNOWN | 630 QDF_MON_STATUS_HE_CODING_KNOWN | 631 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 632 QDF_MON_STATUS_HE_STBC_KNOWN | 633 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 634 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 635 636 /* data2 */ 637 ppdu_info->rx_status.he_data2 = 638 QDF_MON_STATUS_HE_GI_KNOWN; 639 ppdu_info->rx_status.he_data2 |= 640 QDF_MON_STATUS_TXBF_KNOWN | 641 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 642 QDF_MON_STATUS_TXOP_KNOWN | 643 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 644 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 645 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 646 647 /* data3 */ 648 value = HAL_RX_GET(he_sig_a_su_info, 649 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 650 ppdu_info->rx_status.he_data3 = value; 651 value = HAL_RX_GET(he_sig_a_su_info, 652 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 653 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 654 ppdu_info->rx_status.he_data3 |= value; 655 value = HAL_RX_GET(he_sig_a_su_info, 656 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 657 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 658 ppdu_info->rx_status.he_data3 |= value; 659 660 value = HAL_RX_GET(he_sig_a_su_info, 661 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 662 ppdu_info->rx_status.mcs = value; 663 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 664 ppdu_info->rx_status.he_data3 |= value; 665 666 value = HAL_RX_GET(he_sig_a_su_info, 667 HE_SIG_A_SU_INFO_0, DCM); 668 he_dcm = value; 669 value = value << QDF_MON_STATUS_DCM_SHIFT; 670 ppdu_info->rx_status.he_data3 |= value; 671 value = HAL_RX_GET(he_sig_a_su_info, 672 HE_SIG_A_SU_INFO_1, CODING); 673 value = value << QDF_MON_STATUS_CODING_SHIFT; 674 ppdu_info->rx_status.he_data3 |= value; 675 value = HAL_RX_GET(he_sig_a_su_info, 676 HE_SIG_A_SU_INFO_1, 677 LDPC_EXTRA_SYMBOL); 678 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 679 ppdu_info->rx_status.he_data3 |= value; 680 value = HAL_RX_GET(he_sig_a_su_info, 681 HE_SIG_A_SU_INFO_1, STBC); 682 he_stbc = value; 683 value = value << QDF_MON_STATUS_STBC_SHIFT; 684 ppdu_info->rx_status.he_data3 |= value; 685 686 /* data4 */ 687 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 688 SPATIAL_REUSE); 689 ppdu_info->rx_status.he_data4 = value; 690 691 /* data5 */ 692 value = HAL_RX_GET(he_sig_a_su_info, 693 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 694 ppdu_info->rx_status.he_data5 = value; 695 ppdu_info->rx_status.bw = value; 696 value = HAL_RX_GET(he_sig_a_su_info, 697 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 698 switch (value) { 699 case 0: 700 he_gi = HE_GI_0_8; 701 he_ltf = HE_LTF_1_X; 702 break; 703 case 1: 704 he_gi = HE_GI_0_8; 705 he_ltf = HE_LTF_2_X; 706 break; 707 case 2: 708 he_gi = HE_GI_1_6; 709 he_ltf = HE_LTF_2_X; 710 break; 711 case 3: 712 if (he_dcm && he_stbc) { 713 he_gi = HE_GI_0_8; 714 he_ltf = HE_LTF_4_X; 715 } else { 716 he_gi = HE_GI_3_2; 717 he_ltf = HE_LTF_4_X; 718 } 719 break; 720 } 721 ppdu_info->rx_status.sgi = he_gi; 722 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 723 ppdu_info->rx_status.he_data5 |= value; 724 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 725 ppdu_info->rx_status.he_data5 |= value; 726 727 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 728 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 729 ppdu_info->rx_status.he_data5 |= value; 730 731 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 732 PACKET_EXTENSION_A_FACTOR); 733 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 734 ppdu_info->rx_status.he_data5 |= value; 735 736 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 737 value = value << QDF_MON_STATUS_TXBF_SHIFT; 738 ppdu_info->rx_status.he_data5 |= value; 739 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 740 PACKET_EXTENSION_PE_DISAMBIGUITY); 741 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 742 ppdu_info->rx_status.he_data5 |= value; 743 744 /* data6 */ 745 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 746 value++; 747 ppdu_info->rx_status.nss = value; 748 ppdu_info->rx_status.he_data6 = value; 749 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 750 DOPPLER_INDICATION); 751 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 752 ppdu_info->rx_status.he_data6 |= value; 753 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 754 TXOP_DURATION); 755 value = value << QDF_MON_STATUS_TXOP_SHIFT; 756 ppdu_info->rx_status.he_data6 |= value; 757 758 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 759 HE_SIG_A_SU_INFO_1, TXBF); 760 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 761 break; 762 } 763 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 764 { 765 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 766 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 767 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 768 769 ppdu_info->rx_status.he_mu_flags = 1; 770 771 /* HE Flags */ 772 /*data1*/ 773 ppdu_info->rx_status.he_data1 = 774 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 775 ppdu_info->rx_status.he_data1 |= 776 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 777 QDF_MON_STATUS_HE_DL_UL_KNOWN | 778 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 779 QDF_MON_STATUS_HE_STBC_KNOWN | 780 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 781 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 782 783 /* data2 */ 784 ppdu_info->rx_status.he_data2 = 785 QDF_MON_STATUS_HE_GI_KNOWN; 786 ppdu_info->rx_status.he_data2 |= 787 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 788 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 789 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 790 QDF_MON_STATUS_TXOP_KNOWN | 791 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 792 793 /*data3*/ 794 value = HAL_RX_GET(he_sig_a_mu_dl_info, 795 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 796 ppdu_info->rx_status.he_data3 = value; 797 798 value = HAL_RX_GET(he_sig_a_mu_dl_info, 799 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 800 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 801 ppdu_info->rx_status.he_data3 |= value; 802 803 value = HAL_RX_GET(he_sig_a_mu_dl_info, 804 HE_SIG_A_MU_DL_INFO_1, 805 LDPC_EXTRA_SYMBOL); 806 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 807 ppdu_info->rx_status.he_data3 |= value; 808 809 value = HAL_RX_GET(he_sig_a_mu_dl_info, 810 HE_SIG_A_MU_DL_INFO_1, STBC); 811 he_stbc = value; 812 value = value << QDF_MON_STATUS_STBC_SHIFT; 813 ppdu_info->rx_status.he_data3 |= value; 814 815 /*data4*/ 816 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 817 SPATIAL_REUSE); 818 ppdu_info->rx_status.he_data4 = value; 819 820 /*data5*/ 821 value = HAL_RX_GET(he_sig_a_mu_dl_info, 822 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 823 ppdu_info->rx_status.he_data5 = value; 824 ppdu_info->rx_status.bw = value; 825 826 value = HAL_RX_GET(he_sig_a_mu_dl_info, 827 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 828 switch (value) { 829 case 0: 830 he_gi = HE_GI_0_8; 831 he_ltf = HE_LTF_4_X; 832 break; 833 case 1: 834 he_gi = HE_GI_0_8; 835 he_ltf = HE_LTF_2_X; 836 break; 837 case 2: 838 he_gi = HE_GI_1_6; 839 he_ltf = HE_LTF_2_X; 840 break; 841 case 3: 842 he_gi = HE_GI_3_2; 843 he_ltf = HE_LTF_4_X; 844 break; 845 } 846 ppdu_info->rx_status.sgi = he_gi; 847 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 848 ppdu_info->rx_status.he_data5 |= value; 849 850 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 851 ppdu_info->rx_status.he_data5 |= value; 852 853 value = HAL_RX_GET(he_sig_a_mu_dl_info, 854 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 855 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 856 ppdu_info->rx_status.he_data5 |= value; 857 858 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 859 PACKET_EXTENSION_A_FACTOR); 860 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 861 ppdu_info->rx_status.he_data5 |= value; 862 863 864 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 865 PACKET_EXTENSION_PE_DISAMBIGUITY); 866 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 867 ppdu_info->rx_status.he_data5 |= value; 868 869 /*data6*/ 870 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 871 DOPPLER_INDICATION); 872 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 873 ppdu_info->rx_status.he_data6 |= value; 874 875 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 876 TXOP_DURATION); 877 value = value << QDF_MON_STATUS_TXOP_SHIFT; 878 ppdu_info->rx_status.he_data6 |= value; 879 880 /* HE-MU Flags */ 881 /* HE-MU-flags1 */ 882 ppdu_info->rx_status.he_flags1 = 883 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 884 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 885 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 886 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 887 QDF_MON_STATUS_RU_0_KNOWN; 888 889 value = HAL_RX_GET(he_sig_a_mu_dl_info, 890 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 891 ppdu_info->rx_status.he_flags1 |= value; 892 value = HAL_RX_GET(he_sig_a_mu_dl_info, 893 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 894 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 895 ppdu_info->rx_status.he_flags1 |= value; 896 897 /* HE-MU-flags2 */ 898 ppdu_info->rx_status.he_flags2 = 899 QDF_MON_STATUS_BW_KNOWN; 900 901 value = HAL_RX_GET(he_sig_a_mu_dl_info, 902 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 903 ppdu_info->rx_status.he_flags2 |= value; 904 value = HAL_RX_GET(he_sig_a_mu_dl_info, 905 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 906 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 907 ppdu_info->rx_status.he_flags2 |= value; 908 value = HAL_RX_GET(he_sig_a_mu_dl_info, 909 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 910 value = value - 1; 911 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 912 ppdu_info->rx_status.he_flags2 |= value; 913 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 914 break; 915 } 916 case WIFIPHYRX_HE_SIG_B1_MU_E: 917 { 918 919 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 920 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 921 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 922 923 ppdu_info->rx_status.he_sig_b_common_known |= 924 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 925 /* TODO: Check on the availability of other fields in 926 * sig_b_common 927 */ 928 929 value = HAL_RX_GET(he_sig_b1_mu_info, 930 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 931 ppdu_info->rx_status.he_RU[0] = value; 932 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 933 break; 934 } 935 case WIFIPHYRX_HE_SIG_B2_MU_E: 936 { 937 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 938 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 939 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 940 /* 941 * Not all "HE" fields can be updated from 942 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 943 * to populate rest of the "HE" fields for MU scenarios. 944 */ 945 946 /* HE-data1 */ 947 ppdu_info->rx_status.he_data1 |= 948 QDF_MON_STATUS_HE_MCS_KNOWN | 949 QDF_MON_STATUS_HE_CODING_KNOWN; 950 951 /* HE-data2 */ 952 953 /* HE-data3 */ 954 value = HAL_RX_GET(he_sig_b2_mu_info, 955 HE_SIG_B2_MU_INFO_0, STA_MCS); 956 ppdu_info->rx_status.mcs = value; 957 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 958 ppdu_info->rx_status.he_data3 |= value; 959 960 961 value = HAL_RX_GET(he_sig_b2_mu_info, 962 HE_SIG_B2_MU_INFO_0, STA_CODING); 963 value = value << QDF_MON_STATUS_CODING_SHIFT; 964 ppdu_info->rx_status.he_data3 |= value; 965 966 /* HE-data4 */ 967 value = HAL_RX_GET(he_sig_b2_mu_info, 968 HE_SIG_B2_MU_INFO_0, STA_ID); 969 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 970 ppdu_info->rx_status.he_data4 |= value; 971 972 /* HE-data5 */ 973 974 /* HE-data6 */ 975 value = HAL_RX_GET(he_sig_b2_mu_info, 976 HE_SIG_B2_MU_INFO_0, NSTS); 977 /* value n indicates n+1 spatial streams */ 978 value++; 979 ppdu_info->rx_status.nss = value; 980 ppdu_info->rx_status.he_data6 |= value; 981 982 break; 983 984 } 985 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 986 { 987 uint8_t *he_sig_b2_ofdma_info = 988 (uint8_t *)rx_tlv + 989 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 990 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 991 992 /* 993 * Not all "HE" fields can be updated from 994 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 995 * to populate rest of "HE" fields for MU OFDMA scenarios. 996 */ 997 998 /* HE-data1 */ 999 ppdu_info->rx_status.he_data1 |= 1000 QDF_MON_STATUS_HE_MCS_KNOWN | 1001 QDF_MON_STATUS_HE_DCM_KNOWN | 1002 QDF_MON_STATUS_HE_CODING_KNOWN; 1003 1004 /* HE-data2 */ 1005 ppdu_info->rx_status.he_data2 |= 1006 QDF_MON_STATUS_TXBF_KNOWN; 1007 1008 /* HE-data3 */ 1009 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1010 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1011 ppdu_info->rx_status.mcs = value; 1012 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1013 ppdu_info->rx_status.he_data3 |= value; 1014 1015 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1016 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1017 he_dcm = value; 1018 value = value << QDF_MON_STATUS_DCM_SHIFT; 1019 ppdu_info->rx_status.he_data3 |= value; 1020 1021 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1022 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1023 value = value << QDF_MON_STATUS_CODING_SHIFT; 1024 ppdu_info->rx_status.he_data3 |= value; 1025 1026 /* HE-data4 */ 1027 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1028 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1029 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1030 ppdu_info->rx_status.he_data4 |= value; 1031 1032 /* HE-data5 */ 1033 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1034 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1035 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1036 ppdu_info->rx_status.he_data5 |= value; 1037 1038 /* HE-data6 */ 1039 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1040 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1041 /* value n indicates n+1 spatial streams */ 1042 value++; 1043 ppdu_info->rx_status.nss = value; 1044 ppdu_info->rx_status.he_data6 |= value; 1045 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1046 break; 1047 } 1048 case WIFIPHYRX_RSSI_LEGACY_E: 1049 { 1050 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1051 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_3, 1052 RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS); 1053 1054 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1055 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1056 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1057 ppdu_info->rx_status.he_re = 0; 1058 1059 value = HAL_RX_GET(rssi_info_tlv, 1060 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1061 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1062 "RSSI_PRI20_CHAIN0: %d\n", value); 1063 1064 value = HAL_RX_GET(rssi_info_tlv, 1065 RECEIVE_RSSI_INFO_0, RSSI_EXT20_CHAIN0); 1066 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1067 "RSSI_EXT20_CHAIN0: %d\n", value); 1068 1069 value = HAL_RX_GET(rssi_info_tlv, 1070 RECEIVE_RSSI_INFO_0, RSSI_EXT40_LOW20_CHAIN0); 1071 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1072 "RSSI_EXT40_LOW20_CHAIN0: %d\n", value); 1073 1074 value = HAL_RX_GET(rssi_info_tlv, 1075 RECEIVE_RSSI_INFO_0, RSSI_EXT40_HIGH20_CHAIN0); 1076 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1077 "RSSI_EXT40_HIGH20_CHAIN0: %d\n", value); 1078 1079 value = HAL_RX_GET(rssi_info_tlv, 1080 RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW20_CHAIN0); 1081 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1082 "RSSI_EXT80_LOW20_CHAIN0: %d\n", value); 1083 1084 value = HAL_RX_GET(rssi_info_tlv, 1085 RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW_HIGH20_CHAIN0); 1086 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1087 "RSSI_EXT80_LOW_HIGH20_CHAIN0: %d\n", value); 1088 1089 value = HAL_RX_GET(rssi_info_tlv, 1090 RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH_LOW20_CHAIN0); 1091 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1092 "RSSI_EXT80_HIGH_LOW20_CHAIN0: %d\n", value); 1093 1094 value = HAL_RX_GET(rssi_info_tlv, 1095 RECEIVE_RSSI_INFO_1, 1096 RSSI_EXT80_HIGH20_CHAIN0); 1097 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1098 "RSSI_EXT80_HIGH20_CHAIN0: %d\n", value); 1099 break; 1100 } 1101 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1102 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1103 ppdu_info); 1104 break; 1105 case WIFIRX_HEADER_E: 1106 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1107 ppdu_info->msdu_info.payload_len = tlv_len; 1108 break; 1109 case WIFIRX_MPDU_START_E: 1110 { 1111 uint8_t *rx_mpdu_start = 1112 (uint8_t *)rx_tlv + HAL_RX_OFFSET(UNIFIED_RX_MPDU_START_0, 1113 RX_MPDU_INFO_RX_MPDU_INFO_DETAILS); 1114 uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, 1115 PHY_PPDU_ID); 1116 uint8_t filter_category = 0; 1117 1118 ppdu_info->nac_info.fc_valid = 1119 HAL_RX_GET(rx_mpdu_start, 1120 RX_MPDU_INFO_2, 1121 MPDU_FRAME_CONTROL_VALID); 1122 1123 ppdu_info->nac_info.to_ds_flag = 1124 HAL_RX_GET(rx_mpdu_start, 1125 RX_MPDU_INFO_2, 1126 TO_DS); 1127 1128 ppdu_info->nac_info.mac_addr2_valid = 1129 HAL_RX_GET(rx_mpdu_start, 1130 RX_MPDU_INFO_2, 1131 MAC_ADDR_AD2_VALID); 1132 1133 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1134 HAL_RX_GET(rx_mpdu_start, 1135 RX_MPDU_INFO_16, 1136 MAC_ADDR_AD2_15_0); 1137 1138 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1139 HAL_RX_GET(rx_mpdu_start, 1140 RX_MPDU_INFO_17, 1141 MAC_ADDR_AD2_47_16); 1142 1143 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1144 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1145 ppdu_info->rx_status.ppdu_len = 1146 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1147 MPDU_LENGTH); 1148 } else { 1149 ppdu_info->rx_status.ppdu_len += 1150 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1151 MPDU_LENGTH); 1152 } 1153 1154 filter_category = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, 1155 RXPCU_MPDU_FILTER_IN_CATEGORY); 1156 if (filter_category == 1) 1157 ppdu_info->rx_status.monitor_direct_used = 1; 1158 break; 1159 } 1160 case 0: 1161 return HAL_TLV_STATUS_PPDU_DONE; 1162 1163 default: 1164 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1165 unhandled = false; 1166 else 1167 unhandled = true; 1168 break; 1169 } 1170 1171 if (!unhandled) 1172 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1173 "%s TLV type: %d, TLV len:%d %s", 1174 __func__, tlv_tag, tlv_len, 1175 unhandled == true ? "unhandled" : ""); 1176 1177 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1178 rx_tlv, tlv_len); 1179 1180 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1181 } 1182 /** 1183 * hal_reo_status_get_header_generic - Process reo desc info 1184 * @d - Pointer to reo descriptior 1185 * @b - tlv type info 1186 * @h1 - Pointer to hal_reo_status_header where info to be stored 1187 * 1188 * Return - none. 1189 * 1190 */ 1191 static void hal_reo_status_get_header_generic(uint32_t *d, int b, void *h1) 1192 { 1193 1194 uint32_t val1 = 0; 1195 struct hal_reo_status_header *h = 1196 (struct hal_reo_status_header *)h1; 1197 1198 switch (b) { 1199 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1200 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1201 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1202 break; 1203 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1204 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1205 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1206 break; 1207 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1208 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1209 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1210 break; 1211 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1212 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1213 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1214 break; 1215 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1216 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1217 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1218 break; 1219 case HAL_REO_DESC_THRES_STATUS_TLV: 1220 val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1221 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1222 break; 1223 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1224 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1225 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1226 break; 1227 default: 1228 pr_err("ERROR: Unknown tlv\n"); 1229 break; 1230 } 1231 h->cmd_num = 1232 HAL_GET_FIELD( 1233 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1234 val1); 1235 h->exec_time = 1236 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1237 CMD_EXECUTION_TIME, val1); 1238 h->status = 1239 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1240 REO_CMD_EXECUTION_STATUS, val1); 1241 switch (b) { 1242 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1243 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1244 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1245 break; 1246 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1247 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1248 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1249 break; 1250 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1251 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1252 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1253 break; 1254 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1255 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1256 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1257 break; 1258 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1259 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1260 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1261 break; 1262 case HAL_REO_DESC_THRES_STATUS_TLV: 1263 val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1264 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1265 break; 1266 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1267 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1268 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1269 break; 1270 default: 1271 pr_err("ERROR: Unknown tlv\n"); 1272 break; 1273 } 1274 h->tstamp = 1275 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1276 } 1277 1278 /** 1279 * hal_reo_setup - Initialize HW REO block 1280 * 1281 * @hal_soc: Opaque HAL SOC handle 1282 * @reo_params: parameters needed by HAL for REO config 1283 */ 1284 static void hal_reo_setup_generic(void *hal_soc, 1285 void *reoparams) 1286 { 1287 struct hal_soc *soc = (struct hal_soc *)hal_soc; 1288 uint32_t reg_val; 1289 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1290 1291 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1292 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1293 1294 reg_val &= ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK | 1295 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | 1296 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); 1297 1298 reg_val |= HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, 1299 FRAGMENT_DEST_RING, reo_params->frag_dst_ring) | 1300 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_LIST_ENABLE, 1) | 1301 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_FLUSH_ENABLE, 1); 1302 1303 HAL_REG_WRITE(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1304 SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); 1305 1306 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1307 1308 /* TODO: Setup destination ring mapping if enabled */ 1309 1310 /* TODO: Error destination ring setting is left to default. 1311 * Default setting is to send all errors to release ring. 1312 */ 1313 1314 HAL_REG_WRITE(soc, 1315 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 1316 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1317 HAL_DEFAULT_REO_TIMEOUT_MS * 1000); 1318 1319 HAL_REG_WRITE(soc, 1320 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 1321 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1322 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1323 1324 HAL_REG_WRITE(soc, 1325 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 1326 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1327 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1328 1329 HAL_REG_WRITE(soc, 1330 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 1331 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1332 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1333 1334 /* 1335 * When hash based routing is enabled, routing of the rx packet 1336 * is done based on the following value: 1 _ _ _ _ The last 4 1337 * bits are based on hash[3:0]. This means the possible values 1338 * are 0x10 to 0x1f. This value is used to look-up the 1339 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1340 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1341 * registers need to be configured to set-up the 16 entries to 1342 * map the hash values to a ring number. There are 3 bits per 1343 * hash entry – which are mapped as follows: 1344 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1345 * 7: NOT_USED. 1346 */ 1347 if (reo_params->rx_hash_enabled) { 1348 HAL_REG_WRITE(soc, 1349 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1350 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1351 reo_params->remap1); 1352 1353 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1354 FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x"), 1355 HAL_REG_READ(soc, 1356 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1357 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1358 1359 HAL_REG_WRITE(soc, 1360 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1361 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1362 reo_params->remap2); 1363 1364 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1365 FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x"), 1366 HAL_REG_READ(soc, 1367 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1368 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1369 } 1370 1371 1372 /* TODO: Check if the following registers shoould be setup by host: 1373 * AGING_CONTROL 1374 * HIGH_MEMORY_THRESHOLD 1375 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1376 * GLOBAL_LINK_DESC_COUNT_CTRL 1377 */ 1378 } 1379 1380 /** 1381 * hal_srng_src_hw_init - Private function to initialize SRNG 1382 * source ring HW 1383 * @hal_soc: HAL SOC handle 1384 * @srng: SRNG ring pointer 1385 */ 1386 static inline void hal_srng_src_hw_init_generic(void *halsoc, 1387 struct hal_srng *srng) 1388 { 1389 struct hal_soc *hal = (struct hal_soc *)halsoc; 1390 uint32_t reg_val = 0; 1391 uint64_t tp_addr = 0; 1392 1393 HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); 1394 1395 if (srng->flags & HAL_SRNG_MSI_INTR) { 1396 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 1397 srng->msi_addr & 0xffffffff); 1398 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 1399 (uint64_t)(srng->msi_addr) >> 32) | 1400 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 1401 MSI1_ENABLE), 1); 1402 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1403 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1404 } 1405 1406 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1407 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1408 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1409 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 1410 srng->entry_size * srng->num_entries); 1411 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 1412 1413 #if defined(WCSS_VERSION) && \ 1414 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 1415 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 1416 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1417 #else 1418 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, RING_ID), srng->ring_id) | 1419 SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1420 #endif 1421 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 1422 1423 /** 1424 * Interrupt setup: 1425 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1426 * if level mode is required 1427 */ 1428 reg_val = 0; 1429 1430 /* 1431 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 1432 * programmed in terms of 1us resolution instead of 8us resolution as 1433 * given in MLD. 1434 */ 1435 if (srng->intr_timer_thres_us) { 1436 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1437 INTERRUPT_TIMER_THRESHOLD), 1438 srng->intr_timer_thres_us); 1439 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 1440 } 1441 1442 if (srng->intr_batch_cntr_thres_entries) { 1443 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1444 BATCH_COUNTER_THRESHOLD), 1445 srng->intr_batch_cntr_thres_entries * 1446 srng->entry_size); 1447 } 1448 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 1449 1450 reg_val = 0; 1451 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 1452 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 1453 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 1454 } 1455 1456 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 1457 1458 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 1459 * remain 0 to avoid some WBM stability issues. Remote head/tail 1460 * pointers are not required since this ring is completely managed 1461 * by WBM HW 1462 */ 1463 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 1464 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1465 ((unsigned long)(srng->u.src_ring.tp_addr) - 1466 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1467 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 1468 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 1469 } 1470 1471 /* Initilaize head and tail pointers to indicate ring is empty */ 1472 SRNG_SRC_REG_WRITE(srng, HP, 0); 1473 SRNG_SRC_REG_WRITE(srng, TP, 0); 1474 *(srng->u.src_ring.tp_addr) = 0; 1475 1476 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1477 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1478 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1479 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1480 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1481 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1482 1483 /* Loop count is not used for SRC rings */ 1484 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 1485 1486 /* 1487 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1488 * todo: update fw_api and replace with above line 1489 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1490 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1491 */ 1492 reg_val |= 0x40; 1493 1494 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 1495 1496 } 1497 1498 /** 1499 * hal_srng_dst_hw_init - Private function to initialize SRNG 1500 * destination ring HW 1501 * @hal_soc: HAL SOC handle 1502 * @srng: SRNG ring pointer 1503 */ 1504 static inline void hal_srng_dst_hw_init_generic(void *halsoc, 1505 struct hal_srng *srng) 1506 { 1507 struct hal_soc *hal = (struct hal_soc *)halsoc; 1508 uint32_t reg_val = 0; 1509 uint64_t hp_addr = 0; 1510 1511 HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); 1512 1513 if (srng->flags & HAL_SRNG_MSI_INTR) { 1514 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 1515 srng->msi_addr & 0xffffffff); 1516 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 1517 (uint64_t)(srng->msi_addr) >> 32) | 1518 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 1519 MSI1_ENABLE), 1); 1520 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1521 SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1522 } 1523 1524 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1525 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1526 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1527 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 1528 srng->entry_size * srng->num_entries); 1529 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 1530 1531 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 1532 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 1533 SRNG_DST_REG_WRITE(srng, ID, reg_val); 1534 1535 1536 /** 1537 * Interrupt setup: 1538 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1539 * if level mode is required 1540 */ 1541 reg_val = 0; 1542 if (srng->intr_timer_thres_us) { 1543 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1544 INTERRUPT_TIMER_THRESHOLD), 1545 srng->intr_timer_thres_us >> 3); 1546 } 1547 1548 if (srng->intr_batch_cntr_thres_entries) { 1549 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1550 BATCH_COUNTER_THRESHOLD), 1551 srng->intr_batch_cntr_thres_entries * 1552 srng->entry_size); 1553 } 1554 1555 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 1556 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1557 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1558 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1559 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 1560 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 1561 1562 /* Initilaize head and tail pointers to indicate ring is empty */ 1563 SRNG_DST_REG_WRITE(srng, HP, 0); 1564 SRNG_DST_REG_WRITE(srng, TP, 0); 1565 *(srng->u.dst_ring.hp_addr) = 0; 1566 1567 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1568 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1569 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1570 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1571 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1572 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1573 1574 /* 1575 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1576 * todo: update fw_api and replace with above line 1577 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1578 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1579 */ 1580 reg_val |= 0x40; 1581 1582 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 1583 1584 } 1585 1586 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1587 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 1588 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 1589 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 1590 1591 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1592 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 1593 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 1594 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 1595 1596 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1597 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 1598 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 1599 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 1600 1601 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 1602 (((*(((uint32_t *) wbm_desc) + \ 1603 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 1604 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 1605 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 1606 1607 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 1608 (((*(((uint32_t *) wbm_desc) + \ 1609 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 1610 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 1611 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 1612 1613 /** 1614 * hal_rx_wbm_err_info_get_generic(): Retrieves WBM error code and reason and 1615 * save it to hal_wbm_err_desc_info structure passed by caller 1616 * @wbm_desc: wbm ring descriptor 1617 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 1618 * Return: void 1619 */ 1620 static inline void hal_rx_wbm_err_info_get_generic(void *wbm_desc, 1621 void *wbm_er_info1) 1622 { 1623 struct hal_wbm_err_desc_info *wbm_er_info = 1624 (struct hal_wbm_err_desc_info *)wbm_er_info1; 1625 1626 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 1627 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 1628 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 1629 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 1630 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 1631 } 1632 1633 /** 1634 * hal_tx_comp_get_release_reason_generic() - TQM Release reason 1635 * @hal_desc: completion ring descriptor pointer 1636 * 1637 * This function will return the type of pointer - buffer or descriptor 1638 * 1639 * Return: buffer type 1640 */ 1641 static inline uint8_t hal_tx_comp_get_release_reason_generic(void *hal_desc) 1642 { 1643 uint32_t comp_desc = 1644 *(uint32_t *) (((uint8_t *) hal_desc) + 1645 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1646 1647 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1648 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1649 } 1650 1651 /** 1652 * hal_rx_dump_mpdu_start_tlv_generic: dump RX mpdu_start TLV in structured 1653 * human readable format. 1654 * @mpdu_start: pointer the rx_attention TLV in pkt. 1655 * @dbg_level: log level. 1656 * 1657 * Return: void 1658 */ 1659 static inline void hal_rx_dump_mpdu_start_tlv_generic(void *mpdustart, 1660 uint8_t dbg_level) 1661 { 1662 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1663 struct rx_mpdu_info *mpdu_info = 1664 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1665 1666 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1667 "rx_mpdu_start tlv - " 1668 "rxpcu_mpdu_filter_in_category: %d " 1669 "sw_frame_group_id: %d " 1670 "ndp_frame: %d " 1671 "phy_err: %d " 1672 "phy_err_during_mpdu_header: %d " 1673 "protocol_version_err: %d " 1674 "ast_based_lookup_valid: %d " 1675 "phy_ppdu_id: %d " 1676 "ast_index: %d " 1677 "sw_peer_id: %d " 1678 "mpdu_frame_control_valid: %d " 1679 "mpdu_duration_valid: %d " 1680 "mac_addr_ad1_valid: %d " 1681 "mac_addr_ad2_valid: %d " 1682 "mac_addr_ad3_valid: %d " 1683 "mac_addr_ad4_valid: %d " 1684 "mpdu_sequence_control_valid: %d " 1685 "mpdu_qos_control_valid: %d " 1686 "mpdu_ht_control_valid: %d " 1687 "frame_encryption_info_valid: %d " 1688 "fr_ds: %d " 1689 "to_ds: %d " 1690 "encrypted: %d " 1691 "mpdu_retry: %d " 1692 "mpdu_sequence_number: %d " 1693 "epd_en: %d " 1694 "all_frames_shall_be_encrypted: %d " 1695 "encrypt_type: %d " 1696 "mesh_sta: %d " 1697 "bssid_hit: %d " 1698 "bssid_number: %d " 1699 "tid: %d " 1700 "pn_31_0: %d " 1701 "pn_63_32: %d " 1702 "pn_95_64: %d " 1703 "pn_127_96: %d " 1704 "peer_meta_data: %d " 1705 "rxpt_classify_info.reo_destination_indication: %d " 1706 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %d " 1707 "rx_reo_queue_desc_addr_31_0: %d " 1708 "rx_reo_queue_desc_addr_39_32: %d " 1709 "receive_queue_number: %d " 1710 "pre_delim_err_warning: %d " 1711 "first_delim_err: %d " 1712 "key_id_octet: %d " 1713 "new_peer_entry: %d " 1714 "decrypt_needed: %d " 1715 "decap_type: %d " 1716 "rx_insert_vlan_c_tag_padding: %d " 1717 "rx_insert_vlan_s_tag_padding: %d " 1718 "strip_vlan_c_tag_decap: %d " 1719 "strip_vlan_s_tag_decap: %d " 1720 "pre_delim_count: %d " 1721 "ampdu_flag: %d " 1722 "bar_frame: %d " 1723 "mpdu_length: %d " 1724 "first_mpdu: %d " 1725 "mcast_bcast: %d " 1726 "ast_index_not_found: %d " 1727 "ast_index_timeout: %d " 1728 "power_mgmt: %d " 1729 "non_qos: %d " 1730 "null_data: %d " 1731 "mgmt_type: %d " 1732 "ctrl_type: %d " 1733 "more_data: %d " 1734 "eosp: %d " 1735 "fragment_flag: %d " 1736 "order: %d " 1737 "u_apsd_trigger: %d " 1738 "encrypt_required: %d " 1739 "directed: %d " 1740 "mpdu_frame_control_field: %d " 1741 "mpdu_duration_field: %d " 1742 "mac_addr_ad1_31_0: %d " 1743 "mac_addr_ad1_47_32: %d " 1744 "mac_addr_ad2_15_0: %d " 1745 "mac_addr_ad2_47_16: %d " 1746 "mac_addr_ad3_31_0: %d " 1747 "mac_addr_ad3_47_32: %d " 1748 "mpdu_sequence_control_field: %d " 1749 "mac_addr_ad4_31_0: %d " 1750 "mac_addr_ad4_47_32: %d " 1751 "mpdu_qos_control_field: %d " 1752 "mpdu_ht_control_field: %d ", 1753 mpdu_info->rxpcu_mpdu_filter_in_category, 1754 mpdu_info->sw_frame_group_id, 1755 mpdu_info->ndp_frame, 1756 mpdu_info->phy_err, 1757 mpdu_info->phy_err_during_mpdu_header, 1758 mpdu_info->protocol_version_err, 1759 mpdu_info->ast_based_lookup_valid, 1760 mpdu_info->phy_ppdu_id, 1761 mpdu_info->ast_index, 1762 mpdu_info->sw_peer_id, 1763 mpdu_info->mpdu_frame_control_valid, 1764 mpdu_info->mpdu_duration_valid, 1765 mpdu_info->mac_addr_ad1_valid, 1766 mpdu_info->mac_addr_ad2_valid, 1767 mpdu_info->mac_addr_ad3_valid, 1768 mpdu_info->mac_addr_ad4_valid, 1769 mpdu_info->mpdu_sequence_control_valid, 1770 mpdu_info->mpdu_qos_control_valid, 1771 mpdu_info->mpdu_ht_control_valid, 1772 mpdu_info->frame_encryption_info_valid, 1773 mpdu_info->fr_ds, 1774 mpdu_info->to_ds, 1775 mpdu_info->encrypted, 1776 mpdu_info->mpdu_retry, 1777 mpdu_info->mpdu_sequence_number, 1778 mpdu_info->epd_en, 1779 mpdu_info->all_frames_shall_be_encrypted, 1780 mpdu_info->encrypt_type, 1781 mpdu_info->mesh_sta, 1782 mpdu_info->bssid_hit, 1783 mpdu_info->bssid_number, 1784 mpdu_info->tid, 1785 mpdu_info->pn_31_0, 1786 mpdu_info->pn_63_32, 1787 mpdu_info->pn_95_64, 1788 mpdu_info->pn_127_96, 1789 mpdu_info->peer_meta_data, 1790 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 1791 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 1792 mpdu_info->rx_reo_queue_desc_addr_31_0, 1793 mpdu_info->rx_reo_queue_desc_addr_39_32, 1794 mpdu_info->receive_queue_number, 1795 mpdu_info->pre_delim_err_warning, 1796 mpdu_info->first_delim_err, 1797 mpdu_info->key_id_octet, 1798 mpdu_info->new_peer_entry, 1799 mpdu_info->decrypt_needed, 1800 mpdu_info->decap_type, 1801 mpdu_info->rx_insert_vlan_c_tag_padding, 1802 mpdu_info->rx_insert_vlan_s_tag_padding, 1803 mpdu_info->strip_vlan_c_tag_decap, 1804 mpdu_info->strip_vlan_s_tag_decap, 1805 mpdu_info->pre_delim_count, 1806 mpdu_info->ampdu_flag, 1807 mpdu_info->bar_frame, 1808 mpdu_info->mpdu_length, 1809 mpdu_info->first_mpdu, 1810 mpdu_info->mcast_bcast, 1811 mpdu_info->ast_index_not_found, 1812 mpdu_info->ast_index_timeout, 1813 mpdu_info->power_mgmt, 1814 mpdu_info->non_qos, 1815 mpdu_info->null_data, 1816 mpdu_info->mgmt_type, 1817 mpdu_info->ctrl_type, 1818 mpdu_info->more_data, 1819 mpdu_info->eosp, 1820 mpdu_info->fragment_flag, 1821 mpdu_info->order, 1822 mpdu_info->u_apsd_trigger, 1823 mpdu_info->encrypt_required, 1824 mpdu_info->directed, 1825 mpdu_info->mpdu_frame_control_field, 1826 mpdu_info->mpdu_duration_field, 1827 mpdu_info->mac_addr_ad1_31_0, 1828 mpdu_info->mac_addr_ad1_47_32, 1829 mpdu_info->mac_addr_ad2_15_0, 1830 mpdu_info->mac_addr_ad2_47_16, 1831 mpdu_info->mac_addr_ad3_31_0, 1832 mpdu_info->mac_addr_ad3_47_32, 1833 mpdu_info->mpdu_sequence_control_field, 1834 mpdu_info->mac_addr_ad4_31_0, 1835 mpdu_info->mac_addr_ad4_47_32, 1836 mpdu_info->mpdu_qos_control_field, 1837 mpdu_info->mpdu_ht_control_field); 1838 } 1839 #endif 1840 1841 /** 1842 * hal_tx_desc_set_search_type - Set the search type value 1843 * @desc: Handle to Tx Descriptor 1844 * @search_type: search type 1845 * 0 – Normal search 1846 * 1 – Index based address search 1847 * 2 – Index based flow search 1848 * 1849 * Return: void 1850 */ 1851 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 1852 static void hal_tx_desc_set_search_type_generic(void *desc, 1853 uint8_t search_type) 1854 { 1855 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 1856 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 1857 } 1858 #else 1859 static void hal_tx_desc_set_search_type_generic(void *desc, 1860 uint8_t search_type) 1861 { 1862 } 1863 1864 #endif 1865 1866 /** 1867 * hal_tx_desc_set_search_index - Set the search index value 1868 * @desc: Handle to Tx Descriptor 1869 * @search_index: The index that will be used for index based address or 1870 * flow search. The field is valid when 'search_type' is 1871 * 1 0r 2 1872 * 1873 * Return: void 1874 */ 1875 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 1876 static void hal_tx_desc_set_search_index_generic(void *desc, 1877 uint32_t search_index) 1878 { 1879 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 1880 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 1881 } 1882 #else 1883 static void hal_tx_desc_set_search_index_generic(void *desc, 1884 uint32_t search_index) 1885 { 1886 } 1887 #endif 1888