1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 22 ((struct rx_msdu_desc_info *) \ 23 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 24 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 25 /** 26 * hal_rx_msdu_desc_info_get_ptr_generic() - Get msdu desc info ptr 27 * @msdu_details_ptr - Pointer to msdu_details_ptr 28 * Return - Pointer to rx_msdu_desc_info structure. 29 * 30 */ 31 static void *hal_rx_msdu_desc_info_get_ptr_generic(void *msdu_details_ptr) 32 { 33 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 34 } 35 36 37 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 38 ((struct rx_msdu_details *) \ 39 _OFFSET_TO_BYTE_PTR((link_desc),\ 40 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 41 /** 42 * hal_rx_link_desc_msdu0_ptr_generic - Get pointer to rx_msdu details 43 * @link_desc - Pointer to link desc 44 * Return - Pointer to rx_msdu_details structure 45 * 46 */ 47 48 static void *hal_rx_link_desc_msdu0_ptr_generic(void *link_desc) 49 { 50 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 51 } 52 53 /** 54 * hal_tx_comp_get_status() - TQM Release reason 55 * @hal_desc: completion ring Tx status 56 * 57 * This function will parse the WBM completion descriptor and populate in 58 * HAL structure 59 * 60 * Return: none 61 */ 62 #if defined(WCSS_VERSION) && \ 63 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 64 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 65 static inline void hal_tx_comp_get_status_generic(void *desc, 66 void *ts1, void *hal) 67 { 68 uint8_t rate_stats_valid = 0; 69 uint32_t rate_stats = 0; 70 struct hal_tx_completion_status *ts = 71 (struct hal_tx_completion_status *)ts1; 72 73 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 74 TQM_STATUS_NUMBER); 75 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 76 ACK_FRAME_RSSI); 77 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 78 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 79 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 80 MSDU_PART_OF_AMSDU); 81 82 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 83 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 84 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 85 TRANSMIT_COUNT); 86 87 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 88 TX_RATE_STATS); 89 90 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 91 TX_RATE_STATS_INFO_VALID, rate_stats); 92 93 ts->valid = rate_stats_valid; 94 95 if (rate_stats_valid) { 96 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 97 rate_stats); 98 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 99 TRANSMIT_PKT_TYPE, rate_stats); 100 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 101 TRANSMIT_STBC, rate_stats); 102 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 103 rate_stats); 104 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 105 rate_stats); 106 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 107 rate_stats); 108 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 109 rate_stats); 110 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 111 rate_stats); 112 } 113 114 ts->release_src = hal_tx_comp_get_buffer_source(desc); 115 ts->status = hal_tx_comp_get_release_reason(desc, hal); 116 117 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 118 TX_RATE_STATS_INFO_TX_RATE_STATS); 119 } 120 #else 121 static inline void hal_tx_comp_get_status_generic(void *desc, 122 struct hal_tx_completion_status *ts, void *hal) 123 { 124 125 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 126 TQM_STATUS_NUMBER); 127 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 128 ACK_FRAME_RSSI); 129 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 130 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 131 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 132 MSDU_PART_OF_AMSDU); 133 134 ts->release_src = hal_tx_comp_get_buffer_source(desc); 135 ts->status = hal_tx_comp_get_release_reason(desc, hal); 136 } 137 #endif 138 139 140 /** 141 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 142 * @desc: Handle to Tx Descriptor 143 * @paddr: Physical Address 144 * @pool_id: Return Buffer Manager ID 145 * @desc_id: Descriptor ID 146 * @type: 0 - Address points to a MSDU buffer 147 * 1 - Address points to MSDU extension descriptor 148 * 149 * Return: void 150 */ 151 static inline void hal_tx_desc_set_buf_addr_generic(void *desc, 152 dma_addr_t paddr, uint8_t pool_id, 153 uint32_t desc_id, uint8_t type) 154 { 155 /* Set buffer_addr_info.buffer_addr_31_0 */ 156 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 157 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 158 159 /* Set buffer_addr_info.buffer_addr_39_32 */ 160 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 161 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 162 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 163 (((uint64_t) paddr) >> 32)); 164 165 /* Set buffer_addr_info.return_buffer_manager = pool id */ 166 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 167 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 168 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 169 RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID)); 170 171 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 172 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 173 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 174 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 175 176 /* Set Buffer or Ext Descriptor Type */ 177 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 178 BUF_OR_EXT_DESC_TYPE) |= 179 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 180 } 181 182 #if defined(CONFIG_MCL) && defined(QCA_WIFI_QCA6290_11AX) 183 /** 184 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 185 * tlv_tag: Taf of the TLVs 186 * rx_tlv: the pointer to the TLVs 187 * @ppdu_info: pointer to ppdu_info 188 * 189 * Return: true if the tlv is handled, false if not 190 */ 191 static inline bool 192 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 193 struct hal_rx_ppdu_info *ppdu_info) 194 { 195 uint32_t value; 196 197 switch (tlv_tag) { 198 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 199 { 200 uint8_t *he_sig_a_mu_ul_info = 201 (uint8_t *)rx_tlv + 202 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 203 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 204 ppdu_info->rx_status.he_flags = 1; 205 206 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 207 FORMAT_INDICATION); 208 if (value == 0) { 209 ppdu_info->rx_status.he_data1 = 210 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 211 } else { 212 ppdu_info->rx_status.he_data1 = 213 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 214 } 215 216 /* data1 */ 217 ppdu_info->rx_status.he_data1 |= 218 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 219 QDF_MON_STATUS_HE_DL_UL_KNOWN | 220 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 221 222 /* data2 */ 223 ppdu_info->rx_status.he_data2 |= 224 QDF_MON_STATUS_TXOP_KNOWN; 225 226 /*data3*/ 227 value = HAL_RX_GET(he_sig_a_mu_ul_info, 228 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 229 ppdu_info->rx_status.he_data3 = value; 230 /* 1 for UL and 0 for DL */ 231 value = 1; 232 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 233 ppdu_info->rx_status.he_data3 |= value; 234 235 /*data4*/ 236 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 237 SPATIAL_REUSE); 238 ppdu_info->rx_status.he_data4 = value; 239 240 /*data5*/ 241 value = HAL_RX_GET(he_sig_a_mu_ul_info, 242 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 243 ppdu_info->rx_status.he_data5 = value; 244 ppdu_info->rx_status.bw = value; 245 246 /*data6*/ 247 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 248 TXOP_DURATION); 249 value = value << QDF_MON_STATUS_TXOP_SHIFT; 250 ppdu_info->rx_status.he_data6 |= value; 251 return true; 252 } 253 default: 254 return false; 255 } 256 } 257 #else 258 static inline bool 259 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 260 struct hal_rx_ppdu_info *ppdu_info) 261 { 262 return false; 263 } 264 #endif /* CONFIG_MCL && QCA_WIFI_QCA6290_11AX */ 265 266 /** 267 * hal_rx_status_get_tlv_info() - process receive info TLV 268 * @rx_tlv_hdr: pointer to TLV header 269 * @ppdu_info: pointer to ppdu_info 270 * 271 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 272 */ 273 static inline uint32_t 274 hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, 275 void *halsoc) 276 { 277 struct hal_soc *hal = (struct hal_soc *)halsoc; 278 uint32_t tlv_tag, user_id, tlv_len, value; 279 uint8_t group_id = 0; 280 uint8_t he_dcm = 0; 281 uint8_t he_stbc = 0; 282 uint16_t he_gi = 0; 283 uint16_t he_ltf = 0; 284 void *rx_tlv; 285 bool unhandled = false; 286 struct hal_rx_ppdu_info *ppdu_info = 287 (struct hal_rx_ppdu_info *)ppduinfo; 288 289 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 290 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 291 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 292 293 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 294 switch (tlv_tag) { 295 296 case WIFIRX_PPDU_START_E: 297 ppdu_info->com_info.ppdu_id = 298 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 299 PHY_PPDU_ID); 300 /* channel number is set in PHY meta data */ 301 ppdu_info->rx_status.chan_num = 302 HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 303 SW_PHY_META_DATA); 304 ppdu_info->com_info.ppdu_timestamp = 305 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 306 PPDU_START_TIMESTAMP); 307 ppdu_info->rx_status.ppdu_timestamp = 308 ppdu_info->com_info.ppdu_timestamp; 309 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 310 break; 311 312 case WIFIRX_PPDU_START_USER_INFO_E: 313 break; 314 315 case WIFIRX_PPDU_END_E: 316 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 317 "[%s][%d] ppdu_end_e len=%d", 318 __func__, __LINE__, tlv_len); 319 /* This is followed by sub-TLVs of PPDU_END */ 320 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 321 break; 322 323 case WIFIRXPCU_PPDU_END_INFO_E: 324 ppdu_info->rx_status.tsft = 325 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 326 WB_TIMESTAMP_UPPER_32); 327 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 328 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 329 WB_TIMESTAMP_LOWER_32); 330 ppdu_info->rx_status.duration = 331 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 332 RX_PPDU_DURATION); 333 break; 334 335 case WIFIRX_PPDU_END_USER_STATS_E: 336 { 337 unsigned long tid = 0; 338 uint16_t seq = 0; 339 340 ppdu_info->rx_status.ast_index = 341 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 342 AST_INDEX); 343 344 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 345 RECEIVED_QOS_DATA_TID_BITMAP); 346 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 347 348 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 349 ppdu_info->rx_status.tid = HAL_TID_INVALID; 350 351 ppdu_info->rx_status.tcp_msdu_count = 352 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 353 TCP_MSDU_COUNT) + 354 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 355 TCP_ACK_MSDU_COUNT); 356 ppdu_info->rx_status.udp_msdu_count = 357 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 358 UDP_MSDU_COUNT); 359 ppdu_info->rx_status.other_msdu_count = 360 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 361 OTHER_MSDU_COUNT); 362 363 ppdu_info->rx_status.frame_control_info_valid = 364 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 365 FRAME_CONTROL_INFO_VALID); 366 367 if (ppdu_info->rx_status.frame_control_info_valid) 368 ppdu_info->rx_status.frame_control = 369 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 370 FRAME_CONTROL_FIELD); 371 372 ppdu_info->rx_status.data_sequence_control_info_valid = 373 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 374 DATA_SEQUENCE_CONTROL_INFO_VALID); 375 376 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 377 FIRST_DATA_SEQ_CTRL); 378 if (ppdu_info->rx_status.data_sequence_control_info_valid) 379 ppdu_info->rx_status.first_data_seq_ctrl = seq; 380 381 ppdu_info->rx_status.preamble_type = 382 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 383 HT_CONTROL_FIELD_PKT_TYPE); 384 switch (ppdu_info->rx_status.preamble_type) { 385 case HAL_RX_PKT_TYPE_11N: 386 ppdu_info->rx_status.ht_flags = 1; 387 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 388 break; 389 case HAL_RX_PKT_TYPE_11AC: 390 ppdu_info->rx_status.vht_flags = 1; 391 break; 392 case HAL_RX_PKT_TYPE_11AX: 393 ppdu_info->rx_status.he_flags = 1; 394 break; 395 default: 396 break; 397 } 398 399 ppdu_info->com_info.mpdu_cnt_fcs_ok = 400 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 401 MPDU_CNT_FCS_OK); 402 ppdu_info->com_info.mpdu_cnt_fcs_err = 403 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 404 MPDU_CNT_FCS_ERR); 405 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 406 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 407 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 408 else 409 ppdu_info->rx_status.rs_flags &= 410 (~IEEE80211_AMPDU_FLAG); 411 break; 412 } 413 414 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 415 break; 416 417 case WIFIRX_PPDU_END_STATUS_DONE_E: 418 return HAL_TLV_STATUS_PPDU_DONE; 419 420 case WIFIDUMMY_E: 421 return HAL_TLV_STATUS_BUF_DONE; 422 423 case WIFIPHYRX_HT_SIG_E: 424 { 425 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 426 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 427 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 428 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 429 FEC_CODING); 430 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 431 1 : 0; 432 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 433 HT_SIG_INFO_0, MCS); 434 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 435 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 436 HT_SIG_INFO_0, CBW); 437 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 438 HT_SIG_INFO_1, SHORT_GI); 439 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 440 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 441 HT_SIG_SU_NSS_SHIFT) + 1; 442 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 443 break; 444 } 445 446 case WIFIPHYRX_L_SIG_B_E: 447 { 448 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 449 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 450 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 451 452 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 453 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 454 switch (value) { 455 case 1: 456 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 457 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 458 break; 459 case 2: 460 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 461 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 462 break; 463 case 3: 464 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 465 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 466 break; 467 case 4: 468 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 469 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 470 break; 471 case 5: 472 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 473 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 474 break; 475 case 6: 476 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 477 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 478 break; 479 case 7: 480 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 481 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 482 break; 483 default: 484 break; 485 } 486 ppdu_info->rx_status.cck_flag = 1; 487 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 488 break; 489 } 490 491 case WIFIPHYRX_L_SIG_A_E: 492 { 493 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 494 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 495 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 496 497 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 498 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 499 switch (value) { 500 case 8: 501 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 502 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 503 break; 504 case 9: 505 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 506 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 507 break; 508 case 10: 509 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 510 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 511 break; 512 case 11: 513 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 514 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 515 break; 516 case 12: 517 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 518 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 519 break; 520 case 13: 521 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 522 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 523 break; 524 case 14: 525 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 526 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 527 break; 528 case 15: 529 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 530 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 531 break; 532 default: 533 break; 534 } 535 ppdu_info->rx_status.ofdm_flag = 1; 536 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 537 break; 538 } 539 540 case WIFIPHYRX_VHT_SIG_A_E: 541 { 542 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 543 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 544 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 545 546 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 547 SU_MU_CODING); 548 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 549 1 : 0; 550 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 551 ppdu_info->rx_status.vht_flag_values5 = group_id; 552 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 553 VHT_SIG_A_INFO_1, MCS); 554 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 555 VHT_SIG_A_INFO_1, GI_SETTING); 556 557 switch (hal->target_type) { 558 case TARGET_TYPE_QCA8074: 559 case TARGET_TYPE_QCA8074V2: 560 case TARGET_TYPE_QCA6018: 561 ppdu_info->rx_status.is_stbc = 562 HAL_RX_GET(vht_sig_a_info, 563 VHT_SIG_A_INFO_0, STBC); 564 value = HAL_RX_GET(vht_sig_a_info, 565 VHT_SIG_A_INFO_0, N_STS); 566 if (ppdu_info->rx_status.is_stbc && (value > 0)) 567 value = ((value + 1) >> 1) - 1; 568 ppdu_info->rx_status.nss = 569 ((value & VHT_SIG_SU_NSS_MASK) + 1); 570 571 break; 572 case TARGET_TYPE_QCA6290: 573 #if !defined(QCA_WIFI_QCA6290_11AX) 574 ppdu_info->rx_status.is_stbc = 575 HAL_RX_GET(vht_sig_a_info, 576 VHT_SIG_A_INFO_0, STBC); 577 value = HAL_RX_GET(vht_sig_a_info, 578 VHT_SIG_A_INFO_0, N_STS); 579 if (ppdu_info->rx_status.is_stbc && (value > 0)) 580 value = ((value + 1) >> 1) - 1; 581 ppdu_info->rx_status.nss = 582 ((value & VHT_SIG_SU_NSS_MASK) + 1); 583 #else 584 ppdu_info->rx_status.nss = 0; 585 #endif 586 break; 587 #ifdef QCA_WIFI_QCA6390 588 case TARGET_TYPE_QCA6390: 589 ppdu_info->rx_status.nss = 0; 590 break; 591 #endif 592 default: 593 break; 594 } 595 ppdu_info->rx_status.vht_flag_values3[0] = 596 (((ppdu_info->rx_status.mcs) << 4) 597 | ppdu_info->rx_status.nss); 598 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 599 VHT_SIG_A_INFO_0, BANDWIDTH); 600 ppdu_info->rx_status.vht_flag_values2 = 601 ppdu_info->rx_status.bw; 602 ppdu_info->rx_status.vht_flag_values4 = 603 HAL_RX_GET(vht_sig_a_info, 604 VHT_SIG_A_INFO_1, SU_MU_CODING); 605 606 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 607 VHT_SIG_A_INFO_1, BEAMFORMED); 608 if (group_id == 0 || group_id == 63) 609 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 610 else 611 ppdu_info->rx_status.reception_type = 612 HAL_RX_TYPE_MU_MIMO; 613 614 break; 615 } 616 case WIFIPHYRX_HE_SIG_A_SU_E: 617 { 618 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 619 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 620 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 621 ppdu_info->rx_status.he_flags = 1; 622 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 623 FORMAT_INDICATION); 624 if (value == 0) { 625 ppdu_info->rx_status.he_data1 = 626 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 627 } else { 628 ppdu_info->rx_status.he_data1 = 629 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 630 } 631 632 /* data1 */ 633 ppdu_info->rx_status.he_data1 |= 634 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 635 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 636 QDF_MON_STATUS_HE_DL_UL_KNOWN | 637 QDF_MON_STATUS_HE_MCS_KNOWN | 638 QDF_MON_STATUS_HE_DCM_KNOWN | 639 QDF_MON_STATUS_HE_CODING_KNOWN | 640 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 641 QDF_MON_STATUS_HE_STBC_KNOWN | 642 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 643 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 644 645 /* data2 */ 646 ppdu_info->rx_status.he_data2 = 647 QDF_MON_STATUS_HE_GI_KNOWN; 648 ppdu_info->rx_status.he_data2 |= 649 QDF_MON_STATUS_TXBF_KNOWN | 650 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 651 QDF_MON_STATUS_TXOP_KNOWN | 652 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 653 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 654 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 655 656 /* data3 */ 657 value = HAL_RX_GET(he_sig_a_su_info, 658 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 659 ppdu_info->rx_status.he_data3 = value; 660 value = HAL_RX_GET(he_sig_a_su_info, 661 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 662 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 663 ppdu_info->rx_status.he_data3 |= value; 664 value = HAL_RX_GET(he_sig_a_su_info, 665 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 666 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 667 ppdu_info->rx_status.he_data3 |= value; 668 669 value = HAL_RX_GET(he_sig_a_su_info, 670 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 671 ppdu_info->rx_status.mcs = value; 672 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 673 ppdu_info->rx_status.he_data3 |= value; 674 675 value = HAL_RX_GET(he_sig_a_su_info, 676 HE_SIG_A_SU_INFO_0, DCM); 677 he_dcm = value; 678 value = value << QDF_MON_STATUS_DCM_SHIFT; 679 ppdu_info->rx_status.he_data3 |= value; 680 value = HAL_RX_GET(he_sig_a_su_info, 681 HE_SIG_A_SU_INFO_1, CODING); 682 value = value << QDF_MON_STATUS_CODING_SHIFT; 683 ppdu_info->rx_status.he_data3 |= value; 684 value = HAL_RX_GET(he_sig_a_su_info, 685 HE_SIG_A_SU_INFO_1, 686 LDPC_EXTRA_SYMBOL); 687 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 688 ppdu_info->rx_status.he_data3 |= value; 689 value = HAL_RX_GET(he_sig_a_su_info, 690 HE_SIG_A_SU_INFO_1, STBC); 691 he_stbc = value; 692 value = value << QDF_MON_STATUS_STBC_SHIFT; 693 ppdu_info->rx_status.he_data3 |= value; 694 695 /* data4 */ 696 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 697 SPATIAL_REUSE); 698 ppdu_info->rx_status.he_data4 = value; 699 700 /* data5 */ 701 value = HAL_RX_GET(he_sig_a_su_info, 702 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 703 ppdu_info->rx_status.he_data5 = value; 704 ppdu_info->rx_status.bw = value; 705 value = HAL_RX_GET(he_sig_a_su_info, 706 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 707 switch (value) { 708 case 0: 709 he_gi = HE_GI_0_8; 710 he_ltf = HE_LTF_1_X; 711 break; 712 case 1: 713 he_gi = HE_GI_0_8; 714 he_ltf = HE_LTF_2_X; 715 break; 716 case 2: 717 he_gi = HE_GI_1_6; 718 he_ltf = HE_LTF_2_X; 719 break; 720 case 3: 721 if (he_dcm && he_stbc) { 722 he_gi = HE_GI_0_8; 723 he_ltf = HE_LTF_4_X; 724 } else { 725 he_gi = HE_GI_3_2; 726 he_ltf = HE_LTF_4_X; 727 } 728 break; 729 } 730 ppdu_info->rx_status.sgi = he_gi; 731 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 732 ppdu_info->rx_status.he_data5 |= value; 733 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 734 ppdu_info->rx_status.he_data5 |= value; 735 736 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 737 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 738 ppdu_info->rx_status.he_data5 |= value; 739 740 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 741 PACKET_EXTENSION_A_FACTOR); 742 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 743 ppdu_info->rx_status.he_data5 |= value; 744 745 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 746 value = value << QDF_MON_STATUS_TXBF_SHIFT; 747 ppdu_info->rx_status.he_data5 |= value; 748 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 749 PACKET_EXTENSION_PE_DISAMBIGUITY); 750 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 751 ppdu_info->rx_status.he_data5 |= value; 752 753 /* data6 */ 754 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 755 value++; 756 ppdu_info->rx_status.nss = value; 757 ppdu_info->rx_status.he_data6 = value; 758 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 759 DOPPLER_INDICATION); 760 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 761 ppdu_info->rx_status.he_data6 |= value; 762 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 763 TXOP_DURATION); 764 value = value << QDF_MON_STATUS_TXOP_SHIFT; 765 ppdu_info->rx_status.he_data6 |= value; 766 767 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 768 HE_SIG_A_SU_INFO_1, TXBF); 769 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 770 break; 771 } 772 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 773 { 774 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 775 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 776 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 777 778 ppdu_info->rx_status.he_mu_flags = 1; 779 780 /* HE Flags */ 781 /*data1*/ 782 ppdu_info->rx_status.he_data1 = 783 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 784 ppdu_info->rx_status.he_data1 |= 785 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 786 QDF_MON_STATUS_HE_DL_UL_KNOWN | 787 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 788 QDF_MON_STATUS_HE_STBC_KNOWN | 789 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 790 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 791 792 /* data2 */ 793 ppdu_info->rx_status.he_data2 = 794 QDF_MON_STATUS_HE_GI_KNOWN; 795 ppdu_info->rx_status.he_data2 |= 796 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 797 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 798 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 799 QDF_MON_STATUS_TXOP_KNOWN | 800 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 801 802 /*data3*/ 803 value = HAL_RX_GET(he_sig_a_mu_dl_info, 804 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 805 ppdu_info->rx_status.he_data3 = value; 806 807 value = HAL_RX_GET(he_sig_a_mu_dl_info, 808 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 809 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 810 ppdu_info->rx_status.he_data3 |= value; 811 812 value = HAL_RX_GET(he_sig_a_mu_dl_info, 813 HE_SIG_A_MU_DL_INFO_1, 814 LDPC_EXTRA_SYMBOL); 815 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 816 ppdu_info->rx_status.he_data3 |= value; 817 818 value = HAL_RX_GET(he_sig_a_mu_dl_info, 819 HE_SIG_A_MU_DL_INFO_1, STBC); 820 he_stbc = value; 821 value = value << QDF_MON_STATUS_STBC_SHIFT; 822 ppdu_info->rx_status.he_data3 |= value; 823 824 /*data4*/ 825 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 826 SPATIAL_REUSE); 827 ppdu_info->rx_status.he_data4 = value; 828 829 /*data5*/ 830 value = HAL_RX_GET(he_sig_a_mu_dl_info, 831 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 832 ppdu_info->rx_status.he_data5 = value; 833 ppdu_info->rx_status.bw = value; 834 835 value = HAL_RX_GET(he_sig_a_mu_dl_info, 836 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 837 switch (value) { 838 case 0: 839 he_gi = HE_GI_0_8; 840 he_ltf = HE_LTF_4_X; 841 break; 842 case 1: 843 he_gi = HE_GI_0_8; 844 he_ltf = HE_LTF_2_X; 845 break; 846 case 2: 847 he_gi = HE_GI_1_6; 848 he_ltf = HE_LTF_2_X; 849 break; 850 case 3: 851 he_gi = HE_GI_3_2; 852 he_ltf = HE_LTF_4_X; 853 break; 854 } 855 ppdu_info->rx_status.sgi = he_gi; 856 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 857 ppdu_info->rx_status.he_data5 |= value; 858 859 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 860 ppdu_info->rx_status.he_data5 |= value; 861 862 value = HAL_RX_GET(he_sig_a_mu_dl_info, 863 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 864 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 865 ppdu_info->rx_status.he_data5 |= value; 866 867 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 868 PACKET_EXTENSION_A_FACTOR); 869 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 870 ppdu_info->rx_status.he_data5 |= value; 871 872 873 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 874 PACKET_EXTENSION_PE_DISAMBIGUITY); 875 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 876 ppdu_info->rx_status.he_data5 |= value; 877 878 /*data6*/ 879 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 880 DOPPLER_INDICATION); 881 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 882 ppdu_info->rx_status.he_data6 |= value; 883 884 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 885 TXOP_DURATION); 886 value = value << QDF_MON_STATUS_TXOP_SHIFT; 887 ppdu_info->rx_status.he_data6 |= value; 888 889 /* HE-MU Flags */ 890 /* HE-MU-flags1 */ 891 ppdu_info->rx_status.he_flags1 = 892 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 893 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 894 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 895 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 896 QDF_MON_STATUS_RU_0_KNOWN; 897 898 value = HAL_RX_GET(he_sig_a_mu_dl_info, 899 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 900 ppdu_info->rx_status.he_flags1 |= value; 901 value = HAL_RX_GET(he_sig_a_mu_dl_info, 902 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 903 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 904 ppdu_info->rx_status.he_flags1 |= value; 905 906 /* HE-MU-flags2 */ 907 ppdu_info->rx_status.he_flags2 = 908 QDF_MON_STATUS_BW_KNOWN; 909 910 value = HAL_RX_GET(he_sig_a_mu_dl_info, 911 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 912 ppdu_info->rx_status.he_flags2 |= value; 913 value = HAL_RX_GET(he_sig_a_mu_dl_info, 914 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 915 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 916 ppdu_info->rx_status.he_flags2 |= value; 917 value = HAL_RX_GET(he_sig_a_mu_dl_info, 918 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 919 value = value - 1; 920 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 921 ppdu_info->rx_status.he_flags2 |= value; 922 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 923 break; 924 } 925 case WIFIPHYRX_HE_SIG_B1_MU_E: 926 { 927 928 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 929 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 930 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 931 932 ppdu_info->rx_status.he_sig_b_common_known |= 933 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 934 /* TODO: Check on the availability of other fields in 935 * sig_b_common 936 */ 937 938 value = HAL_RX_GET(he_sig_b1_mu_info, 939 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 940 ppdu_info->rx_status.he_RU[0] = value; 941 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 942 break; 943 } 944 case WIFIPHYRX_HE_SIG_B2_MU_E: 945 { 946 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 947 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 948 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 949 /* 950 * Not all "HE" fields can be updated from 951 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 952 * to populate rest of the "HE" fields for MU scenarios. 953 */ 954 955 /* HE-data1 */ 956 ppdu_info->rx_status.he_data1 |= 957 QDF_MON_STATUS_HE_MCS_KNOWN | 958 QDF_MON_STATUS_HE_CODING_KNOWN; 959 960 /* HE-data2 */ 961 962 /* HE-data3 */ 963 value = HAL_RX_GET(he_sig_b2_mu_info, 964 HE_SIG_B2_MU_INFO_0, STA_MCS); 965 ppdu_info->rx_status.mcs = value; 966 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 967 ppdu_info->rx_status.he_data3 |= value; 968 969 970 value = HAL_RX_GET(he_sig_b2_mu_info, 971 HE_SIG_B2_MU_INFO_0, STA_CODING); 972 value = value << QDF_MON_STATUS_CODING_SHIFT; 973 ppdu_info->rx_status.he_data3 |= value; 974 975 /* HE-data4 */ 976 value = HAL_RX_GET(he_sig_b2_mu_info, 977 HE_SIG_B2_MU_INFO_0, STA_ID); 978 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 979 ppdu_info->rx_status.he_data4 |= value; 980 981 /* HE-data5 */ 982 983 /* HE-data6 */ 984 value = HAL_RX_GET(he_sig_b2_mu_info, 985 HE_SIG_B2_MU_INFO_0, NSTS); 986 /* value n indicates n+1 spatial streams */ 987 value++; 988 ppdu_info->rx_status.nss = value; 989 ppdu_info->rx_status.he_data6 |= value; 990 991 break; 992 993 } 994 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 995 { 996 uint8_t *he_sig_b2_ofdma_info = 997 (uint8_t *)rx_tlv + 998 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 999 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1000 1001 /* 1002 * Not all "HE" fields can be updated from 1003 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1004 * to populate rest of "HE" fields for MU OFDMA scenarios. 1005 */ 1006 1007 /* HE-data1 */ 1008 ppdu_info->rx_status.he_data1 |= 1009 QDF_MON_STATUS_HE_MCS_KNOWN | 1010 QDF_MON_STATUS_HE_DCM_KNOWN | 1011 QDF_MON_STATUS_HE_CODING_KNOWN; 1012 1013 /* HE-data2 */ 1014 ppdu_info->rx_status.he_data2 |= 1015 QDF_MON_STATUS_TXBF_KNOWN; 1016 1017 /* HE-data3 */ 1018 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1019 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1020 ppdu_info->rx_status.mcs = value; 1021 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1022 ppdu_info->rx_status.he_data3 |= value; 1023 1024 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1025 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1026 he_dcm = value; 1027 value = value << QDF_MON_STATUS_DCM_SHIFT; 1028 ppdu_info->rx_status.he_data3 |= value; 1029 1030 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1031 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1032 value = value << QDF_MON_STATUS_CODING_SHIFT; 1033 ppdu_info->rx_status.he_data3 |= value; 1034 1035 /* HE-data4 */ 1036 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1037 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1038 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1039 ppdu_info->rx_status.he_data4 |= value; 1040 1041 /* HE-data5 */ 1042 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1043 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1044 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1045 ppdu_info->rx_status.he_data5 |= value; 1046 1047 /* HE-data6 */ 1048 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1049 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1050 /* value n indicates n+1 spatial streams */ 1051 value++; 1052 ppdu_info->rx_status.nss = value; 1053 ppdu_info->rx_status.he_data6 |= value; 1054 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1055 break; 1056 } 1057 case WIFIPHYRX_RSSI_LEGACY_E: 1058 { 1059 uint8_t reception_type; 1060 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1061 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_3, 1062 RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS); 1063 1064 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1065 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1066 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1067 ppdu_info->rx_status.he_re = 0; 1068 1069 reception_type = HAL_RX_GET(rx_tlv, 1070 PHYRX_RSSI_LEGACY_0, 1071 RECEPTION_TYPE); 1072 switch (reception_type) { 1073 case QDF_RECEPTION_TYPE_ULOFMDA: 1074 ppdu_info->rx_status.ulofdma_flag = 1; 1075 ppdu_info->rx_status.he_data1 = 1076 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1077 break; 1078 case QDF_RECEPTION_TYPE_ULMIMO: 1079 ppdu_info->rx_status.he_data1 = 1080 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1081 break; 1082 default: 1083 break; 1084 } 1085 value = HAL_RX_GET(rssi_info_tlv, 1086 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1087 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1088 "RSSI_PRI20_CHAIN0: %d\n", value); 1089 1090 value = HAL_RX_GET(rssi_info_tlv, 1091 RECEIVE_RSSI_INFO_0, RSSI_EXT20_CHAIN0); 1092 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1093 "RSSI_EXT20_CHAIN0: %d\n", value); 1094 1095 value = HAL_RX_GET(rssi_info_tlv, 1096 RECEIVE_RSSI_INFO_0, RSSI_EXT40_LOW20_CHAIN0); 1097 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1098 "RSSI_EXT40_LOW20_CHAIN0: %d\n", value); 1099 1100 value = HAL_RX_GET(rssi_info_tlv, 1101 RECEIVE_RSSI_INFO_0, RSSI_EXT40_HIGH20_CHAIN0); 1102 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1103 "RSSI_EXT40_HIGH20_CHAIN0: %d\n", value); 1104 1105 value = HAL_RX_GET(rssi_info_tlv, 1106 RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW20_CHAIN0); 1107 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1108 "RSSI_EXT80_LOW20_CHAIN0: %d\n", value); 1109 1110 value = HAL_RX_GET(rssi_info_tlv, 1111 RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW_HIGH20_CHAIN0); 1112 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1113 "RSSI_EXT80_LOW_HIGH20_CHAIN0: %d\n", value); 1114 1115 value = HAL_RX_GET(rssi_info_tlv, 1116 RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH_LOW20_CHAIN0); 1117 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1118 "RSSI_EXT80_HIGH_LOW20_CHAIN0: %d\n", value); 1119 1120 value = HAL_RX_GET(rssi_info_tlv, 1121 RECEIVE_RSSI_INFO_1, 1122 RSSI_EXT80_HIGH20_CHAIN0); 1123 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1124 "RSSI_EXT80_HIGH20_CHAIN0: %d\n", value); 1125 break; 1126 } 1127 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1128 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1129 ppdu_info); 1130 break; 1131 case WIFIRX_HEADER_E: 1132 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1133 ppdu_info->msdu_info.payload_len = tlv_len; 1134 break; 1135 case WIFIRX_MPDU_START_E: 1136 { 1137 uint8_t *rx_mpdu_start = 1138 (uint8_t *)rx_tlv + HAL_RX_OFFSET(UNIFIED_RX_MPDU_START_0, 1139 RX_MPDU_INFO_RX_MPDU_INFO_DETAILS); 1140 uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, 1141 PHY_PPDU_ID); 1142 uint8_t filter_category = 0; 1143 1144 ppdu_info->nac_info.fc_valid = 1145 HAL_RX_GET(rx_mpdu_start, 1146 RX_MPDU_INFO_2, 1147 MPDU_FRAME_CONTROL_VALID); 1148 1149 ppdu_info->nac_info.to_ds_flag = 1150 HAL_RX_GET(rx_mpdu_start, 1151 RX_MPDU_INFO_2, 1152 TO_DS); 1153 1154 ppdu_info->nac_info.mac_addr2_valid = 1155 HAL_RX_GET(rx_mpdu_start, 1156 RX_MPDU_INFO_2, 1157 MAC_ADDR_AD2_VALID); 1158 1159 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1160 HAL_RX_GET(rx_mpdu_start, 1161 RX_MPDU_INFO_16, 1162 MAC_ADDR_AD2_15_0); 1163 1164 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1165 HAL_RX_GET(rx_mpdu_start, 1166 RX_MPDU_INFO_17, 1167 MAC_ADDR_AD2_47_16); 1168 1169 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1170 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1171 ppdu_info->rx_status.ppdu_len = 1172 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1173 MPDU_LENGTH); 1174 } else { 1175 ppdu_info->rx_status.ppdu_len += 1176 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1177 MPDU_LENGTH); 1178 } 1179 1180 filter_category = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, 1181 RXPCU_MPDU_FILTER_IN_CATEGORY); 1182 if (filter_category == 1) 1183 ppdu_info->rx_status.monitor_direct_used = 1; 1184 break; 1185 } 1186 case 0: 1187 return HAL_TLV_STATUS_PPDU_DONE; 1188 1189 default: 1190 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1191 unhandled = false; 1192 else 1193 unhandled = true; 1194 break; 1195 } 1196 1197 if (!unhandled) 1198 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1199 "%s TLV type: %d, TLV len:%d %s", 1200 __func__, tlv_tag, tlv_len, 1201 unhandled == true ? "unhandled" : ""); 1202 1203 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1204 rx_tlv, tlv_len); 1205 1206 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1207 } 1208 /** 1209 * hal_reo_status_get_header_generic - Process reo desc info 1210 * @d - Pointer to reo descriptior 1211 * @b - tlv type info 1212 * @h1 - Pointer to hal_reo_status_header where info to be stored 1213 * 1214 * Return - none. 1215 * 1216 */ 1217 static void hal_reo_status_get_header_generic(uint32_t *d, int b, void *h1) 1218 { 1219 1220 uint32_t val1 = 0; 1221 struct hal_reo_status_header *h = 1222 (struct hal_reo_status_header *)h1; 1223 1224 switch (b) { 1225 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1226 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1227 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1228 break; 1229 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1230 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1231 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1232 break; 1233 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1234 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1235 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1236 break; 1237 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1238 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1239 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1240 break; 1241 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1242 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1243 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1244 break; 1245 case HAL_REO_DESC_THRES_STATUS_TLV: 1246 val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1247 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1248 break; 1249 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1250 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1251 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1252 break; 1253 default: 1254 pr_err("ERROR: Unknown tlv\n"); 1255 break; 1256 } 1257 h->cmd_num = 1258 HAL_GET_FIELD( 1259 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1260 val1); 1261 h->exec_time = 1262 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1263 CMD_EXECUTION_TIME, val1); 1264 h->status = 1265 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1266 REO_CMD_EXECUTION_STATUS, val1); 1267 switch (b) { 1268 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1269 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1270 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1271 break; 1272 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1273 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1274 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1275 break; 1276 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1277 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1278 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1279 break; 1280 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1281 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1282 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1283 break; 1284 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1285 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1286 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1287 break; 1288 case HAL_REO_DESC_THRES_STATUS_TLV: 1289 val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1290 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1291 break; 1292 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1293 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1294 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1295 break; 1296 default: 1297 pr_err("ERROR: Unknown tlv\n"); 1298 break; 1299 } 1300 h->tstamp = 1301 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1302 } 1303 1304 /** 1305 * hal_reo_setup - Initialize HW REO block 1306 * 1307 * @hal_soc: Opaque HAL SOC handle 1308 * @reo_params: parameters needed by HAL for REO config 1309 */ 1310 static void hal_reo_setup_generic(void *hal_soc, 1311 void *reoparams) 1312 { 1313 struct hal_soc *soc = (struct hal_soc *)hal_soc; 1314 uint32_t reg_val; 1315 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1316 1317 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1318 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1319 1320 reg_val &= ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK | 1321 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | 1322 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); 1323 1324 reg_val |= HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, 1325 FRAGMENT_DEST_RING, reo_params->frag_dst_ring) | 1326 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_LIST_ENABLE, 1) | 1327 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_FLUSH_ENABLE, 1); 1328 1329 HAL_REG_WRITE(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1330 SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); 1331 1332 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1333 1334 /* TODO: Setup destination ring mapping if enabled */ 1335 1336 /* TODO: Error destination ring setting is left to default. 1337 * Default setting is to send all errors to release ring. 1338 */ 1339 1340 HAL_REG_WRITE(soc, 1341 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 1342 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1343 HAL_DEFAULT_REO_TIMEOUT_MS * 1000); 1344 1345 HAL_REG_WRITE(soc, 1346 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 1347 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1348 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1349 1350 HAL_REG_WRITE(soc, 1351 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 1352 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1353 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1354 1355 HAL_REG_WRITE(soc, 1356 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 1357 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1358 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1359 1360 /* 1361 * When hash based routing is enabled, routing of the rx packet 1362 * is done based on the following value: 1 _ _ _ _ The last 4 1363 * bits are based on hash[3:0]. This means the possible values 1364 * are 0x10 to 0x1f. This value is used to look-up the 1365 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1366 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1367 * registers need to be configured to set-up the 16 entries to 1368 * map the hash values to a ring number. There are 3 bits per 1369 * hash entry – which are mapped as follows: 1370 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1371 * 7: NOT_USED. 1372 */ 1373 if (reo_params->rx_hash_enabled) { 1374 HAL_REG_WRITE(soc, 1375 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1376 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1377 reo_params->remap1); 1378 1379 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1380 FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x"), 1381 HAL_REG_READ(soc, 1382 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1383 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1384 1385 HAL_REG_WRITE(soc, 1386 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1387 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1388 reo_params->remap2); 1389 1390 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1391 FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x"), 1392 HAL_REG_READ(soc, 1393 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1394 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1395 } 1396 1397 1398 /* TODO: Check if the following registers shoould be setup by host: 1399 * AGING_CONTROL 1400 * HIGH_MEMORY_THRESHOLD 1401 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1402 * GLOBAL_LINK_DESC_COUNT_CTRL 1403 */ 1404 } 1405 1406 /** 1407 * hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring 1408 * @hal_soc: Opaque HAL SOC handle 1409 * @hal_ring: Source ring pointer 1410 * @headp: Head Pointer 1411 * @tailp: Tail Pointer 1412 * @ring: Ring type 1413 * 1414 * Return: Update tail pointer and head pointer in arguments. 1415 */ 1416 static inline 1417 void hal_get_hw_hptp_generic(struct hal_soc *soc, void *hal_ring, 1418 uint32_t *headp, uint32_t *tailp, 1419 uint8_t ring) 1420 { 1421 struct hal_srng *srng = (struct hal_srng *)hal_ring; 1422 struct hal_hw_srng_config *ring_config; 1423 enum hal_ring_type ring_type = (enum hal_ring_type)ring; 1424 1425 if (!soc || !srng) { 1426 QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_ERROR, 1427 "%s: Context is Null", __func__); 1428 return; 1429 } 1430 1431 ring_config = HAL_SRNG_CONFIG(soc, ring_type); 1432 if (!ring_config->lmac_ring) { 1433 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1434 *headp = 1435 (SRNG_SRC_REG_READ(srng, HP)) / srng->entry_size; 1436 *tailp = 1437 (SRNG_SRC_REG_READ(srng, TP)) / srng->entry_size; 1438 } else { 1439 *headp = 1440 (SRNG_DST_REG_READ(srng, HP)) / srng->entry_size; 1441 *tailp = 1442 (SRNG_DST_REG_READ(srng, TP)) / srng->entry_size; 1443 } 1444 } 1445 } 1446 1447 /** 1448 * hal_srng_src_hw_init - Private function to initialize SRNG 1449 * source ring HW 1450 * @hal_soc: HAL SOC handle 1451 * @srng: SRNG ring pointer 1452 */ 1453 static inline void hal_srng_src_hw_init_generic(void *halsoc, 1454 struct hal_srng *srng) 1455 { 1456 struct hal_soc *hal = (struct hal_soc *)halsoc; 1457 uint32_t reg_val = 0; 1458 uint64_t tp_addr = 0; 1459 1460 HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); 1461 1462 if (srng->flags & HAL_SRNG_MSI_INTR) { 1463 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 1464 srng->msi_addr & 0xffffffff); 1465 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 1466 (uint64_t)(srng->msi_addr) >> 32) | 1467 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 1468 MSI1_ENABLE), 1); 1469 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1470 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1471 } 1472 1473 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1474 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1475 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1476 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 1477 srng->entry_size * srng->num_entries); 1478 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 1479 1480 #if defined(WCSS_VERSION) && \ 1481 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 1482 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 1483 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1484 #else 1485 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, RING_ID), srng->ring_id) | 1486 SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1487 #endif 1488 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 1489 1490 /** 1491 * Interrupt setup: 1492 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1493 * if level mode is required 1494 */ 1495 reg_val = 0; 1496 1497 /* 1498 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 1499 * programmed in terms of 1us resolution instead of 8us resolution as 1500 * given in MLD. 1501 */ 1502 if (srng->intr_timer_thres_us) { 1503 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1504 INTERRUPT_TIMER_THRESHOLD), 1505 srng->intr_timer_thres_us); 1506 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 1507 } 1508 1509 if (srng->intr_batch_cntr_thres_entries) { 1510 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1511 BATCH_COUNTER_THRESHOLD), 1512 srng->intr_batch_cntr_thres_entries * 1513 srng->entry_size); 1514 } 1515 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 1516 1517 reg_val = 0; 1518 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 1519 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 1520 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 1521 } 1522 1523 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 1524 1525 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 1526 * remain 0 to avoid some WBM stability issues. Remote head/tail 1527 * pointers are not required since this ring is completely managed 1528 * by WBM HW 1529 */ 1530 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 1531 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1532 ((unsigned long)(srng->u.src_ring.tp_addr) - 1533 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1534 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 1535 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 1536 } 1537 1538 /* Initilaize head and tail pointers to indicate ring is empty */ 1539 SRNG_SRC_REG_WRITE(srng, HP, 0); 1540 SRNG_SRC_REG_WRITE(srng, TP, 0); 1541 *(srng->u.src_ring.tp_addr) = 0; 1542 1543 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1544 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1545 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1546 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1547 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1548 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1549 1550 /* Loop count is not used for SRC rings */ 1551 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 1552 1553 /* 1554 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1555 * todo: update fw_api and replace with above line 1556 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1557 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1558 */ 1559 reg_val |= 0x40; 1560 1561 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 1562 1563 } 1564 1565 /** 1566 * hal_srng_dst_hw_init - Private function to initialize SRNG 1567 * destination ring HW 1568 * @hal_soc: HAL SOC handle 1569 * @srng: SRNG ring pointer 1570 */ 1571 static inline void hal_srng_dst_hw_init_generic(void *halsoc, 1572 struct hal_srng *srng) 1573 { 1574 struct hal_soc *hal = (struct hal_soc *)halsoc; 1575 uint32_t reg_val = 0; 1576 uint64_t hp_addr = 0; 1577 1578 HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); 1579 1580 if (srng->flags & HAL_SRNG_MSI_INTR) { 1581 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 1582 srng->msi_addr & 0xffffffff); 1583 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 1584 (uint64_t)(srng->msi_addr) >> 32) | 1585 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 1586 MSI1_ENABLE), 1); 1587 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1588 SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1589 } 1590 1591 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1592 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1593 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1594 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 1595 srng->entry_size * srng->num_entries); 1596 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 1597 1598 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 1599 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 1600 SRNG_DST_REG_WRITE(srng, ID, reg_val); 1601 1602 1603 /** 1604 * Interrupt setup: 1605 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1606 * if level mode is required 1607 */ 1608 reg_val = 0; 1609 if (srng->intr_timer_thres_us) { 1610 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1611 INTERRUPT_TIMER_THRESHOLD), 1612 srng->intr_timer_thres_us >> 3); 1613 } 1614 1615 if (srng->intr_batch_cntr_thres_entries) { 1616 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1617 BATCH_COUNTER_THRESHOLD), 1618 srng->intr_batch_cntr_thres_entries * 1619 srng->entry_size); 1620 } 1621 1622 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 1623 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1624 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1625 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1626 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 1627 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 1628 1629 /* Initilaize head and tail pointers to indicate ring is empty */ 1630 SRNG_DST_REG_WRITE(srng, HP, 0); 1631 SRNG_DST_REG_WRITE(srng, TP, 0); 1632 *(srng->u.dst_ring.hp_addr) = 0; 1633 1634 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1635 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1636 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1637 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1638 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1639 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1640 1641 /* 1642 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1643 * todo: update fw_api and replace with above line 1644 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1645 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1646 */ 1647 reg_val |= 0x40; 1648 1649 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 1650 1651 } 1652 1653 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1654 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 1655 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 1656 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 1657 1658 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1659 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 1660 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 1661 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 1662 1663 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1664 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 1665 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 1666 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 1667 1668 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 1669 (((*(((uint32_t *) wbm_desc) + \ 1670 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 1671 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 1672 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 1673 1674 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 1675 (((*(((uint32_t *) wbm_desc) + \ 1676 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 1677 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 1678 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 1679 1680 /** 1681 * hal_rx_wbm_err_info_get_generic(): Retrieves WBM error code and reason and 1682 * save it to hal_wbm_err_desc_info structure passed by caller 1683 * @wbm_desc: wbm ring descriptor 1684 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 1685 * Return: void 1686 */ 1687 static inline void hal_rx_wbm_err_info_get_generic(void *wbm_desc, 1688 void *wbm_er_info1) 1689 { 1690 struct hal_wbm_err_desc_info *wbm_er_info = 1691 (struct hal_wbm_err_desc_info *)wbm_er_info1; 1692 1693 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 1694 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 1695 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 1696 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 1697 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 1698 } 1699 1700 /** 1701 * hal_tx_comp_get_release_reason_generic() - TQM Release reason 1702 * @hal_desc: completion ring descriptor pointer 1703 * 1704 * This function will return the type of pointer - buffer or descriptor 1705 * 1706 * Return: buffer type 1707 */ 1708 static inline uint8_t hal_tx_comp_get_release_reason_generic(void *hal_desc) 1709 { 1710 uint32_t comp_desc = 1711 *(uint32_t *) (((uint8_t *) hal_desc) + 1712 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1713 1714 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1715 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1716 } 1717 1718 /** 1719 * hal_rx_dump_mpdu_start_tlv_generic: dump RX mpdu_start TLV in structured 1720 * human readable format. 1721 * @mpdu_start: pointer the rx_attention TLV in pkt. 1722 * @dbg_level: log level. 1723 * 1724 * Return: void 1725 */ 1726 static inline void hal_rx_dump_mpdu_start_tlv_generic(void *mpdustart, 1727 uint8_t dbg_level) 1728 { 1729 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1730 struct rx_mpdu_info *mpdu_info = 1731 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1732 1733 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1734 "rx_mpdu_start tlv (1/5) - " 1735 "rxpcu_mpdu_filter_in_category: %x " 1736 "sw_frame_group_id: %x " 1737 "ndp_frame: %x " 1738 "phy_err: %x " 1739 "phy_err_during_mpdu_header: %x " 1740 "protocol_version_err: %x " 1741 "ast_based_lookup_valid: %x " 1742 "phy_ppdu_id: %x " 1743 "ast_index: %x " 1744 "sw_peer_id: %x " 1745 "mpdu_frame_control_valid: %x " 1746 "mpdu_duration_valid: %x " 1747 "mac_addr_ad1_valid: %x " 1748 "mac_addr_ad2_valid: %x " 1749 "mac_addr_ad3_valid: %x " 1750 "mac_addr_ad4_valid: %x " 1751 "mpdu_sequence_control_valid: %x " 1752 "mpdu_qos_control_valid: %x " 1753 "mpdu_ht_control_valid: %x " 1754 "frame_encryption_info_valid: %x ", 1755 mpdu_info->rxpcu_mpdu_filter_in_category, 1756 mpdu_info->sw_frame_group_id, 1757 mpdu_info->ndp_frame, 1758 mpdu_info->phy_err, 1759 mpdu_info->phy_err_during_mpdu_header, 1760 mpdu_info->protocol_version_err, 1761 mpdu_info->ast_based_lookup_valid, 1762 mpdu_info->phy_ppdu_id, 1763 mpdu_info->ast_index, 1764 mpdu_info->sw_peer_id, 1765 mpdu_info->mpdu_frame_control_valid, 1766 mpdu_info->mpdu_duration_valid, 1767 mpdu_info->mac_addr_ad1_valid, 1768 mpdu_info->mac_addr_ad2_valid, 1769 mpdu_info->mac_addr_ad3_valid, 1770 mpdu_info->mac_addr_ad4_valid, 1771 mpdu_info->mpdu_sequence_control_valid, 1772 mpdu_info->mpdu_qos_control_valid, 1773 mpdu_info->mpdu_ht_control_valid, 1774 mpdu_info->frame_encryption_info_valid); 1775 1776 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1777 "rx_mpdu_start tlv (2/5) - " 1778 "fr_ds: %x " 1779 "to_ds: %x " 1780 "encrypted: %x " 1781 "mpdu_retry: %x " 1782 "mpdu_sequence_number: %x " 1783 "epd_en: %x " 1784 "all_frames_shall_be_encrypted: %x " 1785 "encrypt_type: %x " 1786 "mesh_sta: %x " 1787 "bssid_hit: %x " 1788 "bssid_number: %x " 1789 "tid: %x " 1790 "pn_31_0: %x " 1791 "pn_63_32: %x " 1792 "pn_95_64: %x " 1793 "pn_127_96: %x " 1794 "peer_meta_data: %x " 1795 "rxpt_classify_info.reo_destination_indication: %x " 1796 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 1797 "rx_reo_queue_desc_addr_31_0: %x ", 1798 mpdu_info->fr_ds, 1799 mpdu_info->to_ds, 1800 mpdu_info->encrypted, 1801 mpdu_info->mpdu_retry, 1802 mpdu_info->mpdu_sequence_number, 1803 mpdu_info->epd_en, 1804 mpdu_info->all_frames_shall_be_encrypted, 1805 mpdu_info->encrypt_type, 1806 mpdu_info->mesh_sta, 1807 mpdu_info->bssid_hit, 1808 mpdu_info->bssid_number, 1809 mpdu_info->tid, 1810 mpdu_info->pn_31_0, 1811 mpdu_info->pn_63_32, 1812 mpdu_info->pn_95_64, 1813 mpdu_info->pn_127_96, 1814 mpdu_info->peer_meta_data, 1815 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 1816 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 1817 mpdu_info->rx_reo_queue_desc_addr_31_0); 1818 1819 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1820 "rx_mpdu_start tlv (3/5) - " 1821 "rx_reo_queue_desc_addr_39_32: %x " 1822 "receive_queue_number: %x " 1823 "pre_delim_err_warning: %x " 1824 "first_delim_err: %x " 1825 "key_id_octet: %x " 1826 "new_peer_entry: %x " 1827 "decrypt_needed: %x " 1828 "decap_type: %x " 1829 "rx_insert_vlan_c_tag_padding: %x " 1830 "rx_insert_vlan_s_tag_padding: %x " 1831 "strip_vlan_c_tag_decap: %x " 1832 "strip_vlan_s_tag_decap: %x " 1833 "pre_delim_count: %x " 1834 "ampdu_flag: %x " 1835 "bar_frame: %x " 1836 "mpdu_length: %x " 1837 "first_mpdu: %x " 1838 "mcast_bcast: %x " 1839 "ast_index_not_found: %x " 1840 "ast_index_timeout: %x ", 1841 mpdu_info->rx_reo_queue_desc_addr_39_32, 1842 mpdu_info->receive_queue_number, 1843 mpdu_info->pre_delim_err_warning, 1844 mpdu_info->first_delim_err, 1845 mpdu_info->key_id_octet, 1846 mpdu_info->new_peer_entry, 1847 mpdu_info->decrypt_needed, 1848 mpdu_info->decap_type, 1849 mpdu_info->rx_insert_vlan_c_tag_padding, 1850 mpdu_info->rx_insert_vlan_s_tag_padding, 1851 mpdu_info->strip_vlan_c_tag_decap, 1852 mpdu_info->strip_vlan_s_tag_decap, 1853 mpdu_info->pre_delim_count, 1854 mpdu_info->ampdu_flag, 1855 mpdu_info->bar_frame, 1856 mpdu_info->mpdu_length, 1857 mpdu_info->first_mpdu, 1858 mpdu_info->mcast_bcast, 1859 mpdu_info->ast_index_not_found, 1860 mpdu_info->ast_index_timeout); 1861 1862 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1863 "rx_mpdu_start tlv (4/5) - " 1864 "power_mgmt: %x " 1865 "non_qos: %x " 1866 "null_data: %x " 1867 "mgmt_type: %x " 1868 "ctrl_type: %x " 1869 "more_data: %x " 1870 "eosp: %x " 1871 "fragment_flag: %x " 1872 "order: %x " 1873 "u_apsd_trigger: %x " 1874 "encrypt_required: %x " 1875 "directed: %x " 1876 "mpdu_frame_control_field: %x " 1877 "mpdu_duration_field: %x " 1878 "mac_addr_ad1_31_0: %x " 1879 "mac_addr_ad1_47_32: %x " 1880 "mac_addr_ad2_15_0: %x " 1881 "mac_addr_ad2_47_16: %x " 1882 "mac_addr_ad3_31_0: %x " 1883 "mac_addr_ad3_47_32: %x ", 1884 mpdu_info->power_mgmt, 1885 mpdu_info->non_qos, 1886 mpdu_info->null_data, 1887 mpdu_info->mgmt_type, 1888 mpdu_info->ctrl_type, 1889 mpdu_info->more_data, 1890 mpdu_info->eosp, 1891 mpdu_info->fragment_flag, 1892 mpdu_info->order, 1893 mpdu_info->u_apsd_trigger, 1894 mpdu_info->encrypt_required, 1895 mpdu_info->directed, 1896 mpdu_info->mpdu_frame_control_field, 1897 mpdu_info->mpdu_duration_field, 1898 mpdu_info->mac_addr_ad1_31_0, 1899 mpdu_info->mac_addr_ad1_47_32, 1900 mpdu_info->mac_addr_ad2_15_0, 1901 mpdu_info->mac_addr_ad2_47_16, 1902 mpdu_info->mac_addr_ad3_31_0, 1903 mpdu_info->mac_addr_ad3_47_32); 1904 1905 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1906 "rx_mpdu_start tlv (5/5) - " 1907 "mpdu_sequence_control_field: %x " 1908 "mac_addr_ad4_31_0: %x " 1909 "mac_addr_ad4_47_32: %x " 1910 "mpdu_qos_control_field: %x " 1911 "mpdu_ht_control_field: %x ", 1912 mpdu_info->mpdu_sequence_control_field, 1913 mpdu_info->mac_addr_ad4_31_0, 1914 mpdu_info->mac_addr_ad4_47_32, 1915 mpdu_info->mpdu_qos_control_field, 1916 mpdu_info->mpdu_ht_control_field); 1917 } 1918 #endif 1919 1920 /** 1921 * hal_tx_desc_set_search_type - Set the search type value 1922 * @desc: Handle to Tx Descriptor 1923 * @search_type: search type 1924 * 0 – Normal search 1925 * 1 – Index based address search 1926 * 2 – Index based flow search 1927 * 1928 * Return: void 1929 */ 1930 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 1931 static void hal_tx_desc_set_search_type_generic(void *desc, 1932 uint8_t search_type) 1933 { 1934 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 1935 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 1936 } 1937 #else 1938 static void hal_tx_desc_set_search_type_generic(void *desc, 1939 uint8_t search_type) 1940 { 1941 } 1942 1943 #endif 1944 1945 /** 1946 * hal_tx_desc_set_search_index - Set the search index value 1947 * @desc: Handle to Tx Descriptor 1948 * @search_index: The index that will be used for index based address or 1949 * flow search. The field is valid when 'search_type' is 1950 * 1 0r 2 1951 * 1952 * Return: void 1953 */ 1954 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 1955 static void hal_tx_desc_set_search_index_generic(void *desc, 1956 uint32_t search_index) 1957 { 1958 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 1959 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 1960 } 1961 #else 1962 static void hal_tx_desc_set_search_index_generic(void *desc, 1963 uint32_t search_index) 1964 { 1965 } 1966 #endif 1967