1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #include <hal_rx.h> 22 23 /** 24 * hal_tx_comp_get_status() - TQM Release reason 25 * @hal_desc: completion ring Tx status 26 * 27 * This function will parse the WBM completion descriptor and populate in 28 * HAL structure 29 * 30 * Return: none 31 */ 32 static inline 33 void hal_tx_comp_get_status_generic(void *desc, 34 void *ts1, 35 struct hal_soc *hal) 36 { 37 uint8_t rate_stats_valid = 0; 38 uint32_t rate_stats = 0; 39 struct hal_tx_completion_status *ts = 40 (struct hal_tx_completion_status *)ts1; 41 42 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 43 TQM_STATUS_NUMBER); 44 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 45 ACK_FRAME_RSSI); 46 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 47 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 48 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 49 MSDU_PART_OF_AMSDU); 50 51 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 52 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 53 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 54 TRANSMIT_COUNT); 55 56 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 57 TX_RATE_STATS); 58 59 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 60 TX_RATE_STATS_INFO_VALID, rate_stats); 61 62 ts->valid = rate_stats_valid; 63 64 if (rate_stats_valid) { 65 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 66 rate_stats); 67 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 68 TRANSMIT_PKT_TYPE, rate_stats); 69 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 70 TRANSMIT_STBC, rate_stats); 71 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 72 rate_stats); 73 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 74 rate_stats); 75 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 76 rate_stats); 77 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 78 rate_stats); 79 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 80 rate_stats); 81 } 82 83 ts->release_src = hal_tx_comp_get_buffer_source(desc); 84 ts->status = hal_tx_comp_get_release_reason( 85 desc, 86 hal_soc_to_hal_soc_handle(hal)); 87 88 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 89 TX_RATE_STATS_INFO_TX_RATE_STATS); 90 } 91 92 /** 93 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 94 * @desc: Handle to Tx Descriptor 95 * @paddr: Physical Address 96 * @pool_id: Return Buffer Manager ID 97 * @desc_id: Descriptor ID 98 * @type: 0 - Address points to a MSDU buffer 99 * 1 - Address points to MSDU extension descriptor 100 * 101 * Return: void 102 */ 103 static inline void hal_tx_desc_set_buf_addr_generic(void *desc, 104 dma_addr_t paddr, uint8_t pool_id, 105 uint32_t desc_id, uint8_t type) 106 { 107 /* Set buffer_addr_info.buffer_addr_31_0 */ 108 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 109 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 110 111 /* Set buffer_addr_info.buffer_addr_39_32 */ 112 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 113 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 114 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 115 (((uint64_t) paddr) >> 32)); 116 117 /* Set buffer_addr_info.return_buffer_manager = pool id */ 118 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 119 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 120 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 121 RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID)); 122 123 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 124 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 125 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 126 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 127 128 /* Set Buffer or Ext Descriptor Type */ 129 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 130 BUF_OR_EXT_DESC_TYPE) |= 131 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 132 } 133 134 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 135 /** 136 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 137 * tlv_tag: Taf of the TLVs 138 * rx_tlv: the pointer to the TLVs 139 * @ppdu_info: pointer to ppdu_info 140 * 141 * Return: true if the tlv is handled, false if not 142 */ 143 static inline bool 144 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 145 struct hal_rx_ppdu_info *ppdu_info) 146 { 147 uint32_t value; 148 149 switch (tlv_tag) { 150 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 151 { 152 uint8_t *he_sig_a_mu_ul_info = 153 (uint8_t *)rx_tlv + 154 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 155 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 156 ppdu_info->rx_status.he_flags = 1; 157 158 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 159 FORMAT_INDICATION); 160 if (value == 0) { 161 ppdu_info->rx_status.he_data1 = 162 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 163 } else { 164 ppdu_info->rx_status.he_data1 = 165 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 166 } 167 168 /* data1 */ 169 ppdu_info->rx_status.he_data1 |= 170 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 171 QDF_MON_STATUS_HE_DL_UL_KNOWN | 172 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 173 174 /* data2 */ 175 ppdu_info->rx_status.he_data2 |= 176 QDF_MON_STATUS_TXOP_KNOWN; 177 178 /*data3*/ 179 value = HAL_RX_GET(he_sig_a_mu_ul_info, 180 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 181 ppdu_info->rx_status.he_data3 = value; 182 /* 1 for UL and 0 for DL */ 183 value = 1; 184 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 185 ppdu_info->rx_status.he_data3 |= value; 186 187 /*data4*/ 188 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 189 SPATIAL_REUSE); 190 ppdu_info->rx_status.he_data4 = value; 191 192 /*data5*/ 193 value = HAL_RX_GET(he_sig_a_mu_ul_info, 194 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 195 ppdu_info->rx_status.he_data5 = value; 196 ppdu_info->rx_status.bw = value; 197 198 /*data6*/ 199 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 200 TXOP_DURATION); 201 value = value << QDF_MON_STATUS_TXOP_SHIFT; 202 ppdu_info->rx_status.he_data6 |= value; 203 return true; 204 } 205 default: 206 return false; 207 } 208 } 209 #else 210 static inline bool 211 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 212 struct hal_rx_ppdu_info *ppdu_info) 213 { 214 return false; 215 } 216 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ 217 218 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \ 219 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 220 221 static inline void 222 hal_rx_handle_ofdma_info( 223 void *rx_tlv, 224 struct mon_rx_user_status *mon_rx_user_status) 225 { 226 mon_rx_user_status->ul_ofdma_user_v0_word0 = 227 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11, 228 SW_RESPONSE_REFERENCE_PTR); 229 230 mon_rx_user_status->ul_ofdma_user_v0_word1 = 231 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22, 232 SW_RESPONSE_REFERENCE_PTR_EXT); 233 } 234 235 static inline void 236 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 237 struct mon_rx_user_status *mon_rx_user_status) 238 { 239 uint32_t mpdu_ok_byte_count; 240 uint32_t mpdu_err_byte_count; 241 242 mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, 243 RX_PPDU_END_USER_STATS_17, 244 MPDU_OK_BYTE_COUNT); 245 mpdu_err_byte_count = HAL_RX_GET(rx_tlv, 246 RX_PPDU_END_USER_STATS_19, 247 MPDU_ERR_BYTE_COUNT); 248 249 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 250 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 251 } 252 #else 253 static inline void 254 hal_rx_handle_ofdma_info(void *rx_tlv, 255 struct mon_rx_user_status *mon_rx_user_status) 256 { 257 } 258 259 static inline void 260 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 261 struct mon_rx_user_status *mon_rx_user_status) 262 { 263 struct hal_rx_ppdu_info *ppdu_info = 264 (struct hal_rx_ppdu_info *)ppduinfo; 265 266 /* HKV1: doesn't support mpdu byte count */ 267 mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; 268 mon_rx_user_status->mpdu_err_byte_count = 0; 269 } 270 #endif 271 272 static inline void 273 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, 274 struct mon_rx_user_status *mon_rx_user_status) 275 { 276 struct hal_rx_ppdu_info *ppdu_info = 277 (struct hal_rx_ppdu_info *)ppduinfo; 278 279 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 280 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 281 mon_rx_user_status->tcp_msdu_count = 282 ppdu_info->rx_status.tcp_msdu_count; 283 mon_rx_user_status->udp_msdu_count = 284 ppdu_info->rx_status.udp_msdu_count; 285 mon_rx_user_status->other_msdu_count = 286 ppdu_info->rx_status.other_msdu_count; 287 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 288 mon_rx_user_status->frame_control_info_valid = 289 ppdu_info->rx_status.frame_control_info_valid; 290 mon_rx_user_status->data_sequence_control_info_valid = 291 ppdu_info->rx_status.data_sequence_control_info_valid; 292 mon_rx_user_status->first_data_seq_ctrl = 293 ppdu_info->rx_status.first_data_seq_ctrl; 294 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 295 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 296 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 297 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 298 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 299 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 300 301 mon_rx_user_status->mpdu_cnt_fcs_ok = 302 ppdu_info->com_info.mpdu_cnt_fcs_ok; 303 mon_rx_user_status->mpdu_cnt_fcs_err = 304 ppdu_info->com_info.mpdu_cnt_fcs_err; 305 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 306 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 307 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 308 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 309 310 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 311 } 312 313 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ 314 ppdu_info, rssi_info_tlv) \ 315 { \ 316 ppdu_info->rx_status.rssi_chain[chain][0] = \ 317 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 318 RSSI_PRI20_CHAIN##chain); \ 319 ppdu_info->rx_status.rssi_chain[chain][1] = \ 320 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 321 RSSI_EXT20_CHAIN##chain); \ 322 ppdu_info->rx_status.rssi_chain[chain][2] = \ 323 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 324 RSSI_EXT40_LOW20_CHAIN##chain); \ 325 ppdu_info->rx_status.rssi_chain[chain][3] = \ 326 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 327 RSSI_EXT40_HIGH20_CHAIN##chain); \ 328 ppdu_info->rx_status.rssi_chain[chain][4] = \ 329 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 330 RSSI_EXT80_LOW20_CHAIN##chain); \ 331 ppdu_info->rx_status.rssi_chain[chain][5] = \ 332 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 333 RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ 334 ppdu_info->rx_status.rssi_chain[chain][6] = \ 335 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 336 RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ 337 ppdu_info->rx_status.rssi_chain[chain][7] = \ 338 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 339 RSSI_EXT80_HIGH20_CHAIN##chain); \ 340 } \ 341 342 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 343 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ 344 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ 345 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ 346 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ 347 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ 348 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ 349 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ 350 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ 351 352 static inline uint32_t 353 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 354 uint8_t *rssi_info_tlv) 355 { 356 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 357 return 0; 358 } 359 360 /** 361 * hal_rx_status_get_tlv_info() - process receive info TLV 362 * @rx_tlv_hdr: pointer to TLV header 363 * @ppdu_info: pointer to ppdu_info 364 * 365 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 366 */ 367 static inline uint32_t 368 hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, 369 hal_soc_handle_t hal_soc_hdl, 370 qdf_nbuf_t nbuf) 371 { 372 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 373 uint32_t tlv_tag, user_id, tlv_len, value; 374 uint8_t group_id = 0; 375 uint8_t he_dcm = 0; 376 uint8_t he_stbc = 0; 377 uint16_t he_gi = 0; 378 uint16_t he_ltf = 0; 379 void *rx_tlv; 380 bool unhandled = false; 381 struct mon_rx_user_status *mon_rx_user_status; 382 struct hal_rx_ppdu_info *ppdu_info = 383 (struct hal_rx_ppdu_info *)ppduinfo; 384 385 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 386 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 387 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 388 389 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 390 391 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 392 rx_tlv, tlv_len); 393 394 switch (tlv_tag) { 395 396 case WIFIRX_PPDU_START_E: 397 { 398 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 399 400 ppdu_info->com_info.ppdu_id = 401 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 402 PHY_PPDU_ID); 403 /* channel number is set in PHY meta data */ 404 ppdu_info->rx_status.chan_num = 405 HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 406 SW_PHY_META_DATA); 407 ppdu_info->com_info.ppdu_timestamp = 408 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 409 PPDU_START_TIMESTAMP); 410 ppdu_info->rx_status.ppdu_timestamp = 411 ppdu_info->com_info.ppdu_timestamp; 412 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 413 414 /* If last ppdu_id doesn't match new ppdu_id, 415 * 1. reset mpdu_cnt 416 * 2. update last_ppdu_id with new 417 * 3. reset mpdu fcs bitmap 418 */ 419 if (com_info->ppdu_id != com_info->last_ppdu_id) { 420 com_info->mpdu_cnt = 0; 421 com_info->last_ppdu_id = 422 com_info->ppdu_id; 423 com_info->num_users = 0; 424 qdf_mem_zero(&com_info->mpdu_fcs_ok_bitmap, 425 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 426 sizeof(com_info->mpdu_fcs_ok_bitmap[0])); 427 } 428 break; 429 } 430 431 case WIFIRX_PPDU_START_USER_INFO_E: 432 break; 433 434 case WIFIRX_PPDU_END_E: 435 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 436 "[%s][%d] ppdu_end_e len=%d", 437 __func__, __LINE__, tlv_len); 438 /* This is followed by sub-TLVs of PPDU_END */ 439 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 440 break; 441 442 case WIFIRXPCU_PPDU_END_INFO_E: 443 ppdu_info->rx_status.rx_antenna = 444 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA); 445 ppdu_info->rx_status.tsft = 446 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 447 WB_TIMESTAMP_UPPER_32); 448 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 449 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 450 WB_TIMESTAMP_LOWER_32); 451 ppdu_info->rx_status.duration = 452 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 453 RX_PPDU_DURATION); 454 break; 455 456 /* 457 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 458 * for MU, based on num users we see this tlv that many times. 459 */ 460 case WIFIRX_PPDU_END_USER_STATS_E: 461 { 462 unsigned long tid = 0; 463 uint16_t seq = 0; 464 465 ppdu_info->rx_status.ast_index = 466 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 467 AST_INDEX); 468 469 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 470 RECEIVED_QOS_DATA_TID_BITMAP); 471 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 472 473 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 474 ppdu_info->rx_status.tid = HAL_TID_INVALID; 475 476 ppdu_info->rx_status.tcp_msdu_count = 477 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 478 TCP_MSDU_COUNT) + 479 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 480 TCP_ACK_MSDU_COUNT); 481 ppdu_info->rx_status.udp_msdu_count = 482 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 483 UDP_MSDU_COUNT); 484 ppdu_info->rx_status.other_msdu_count = 485 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 486 OTHER_MSDU_COUNT); 487 488 ppdu_info->rx_status.frame_control_info_valid = 489 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 490 FRAME_CONTROL_INFO_VALID); 491 492 if (ppdu_info->rx_status.frame_control_info_valid) 493 ppdu_info->rx_status.frame_control = 494 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 495 FRAME_CONTROL_FIELD); 496 497 ppdu_info->rx_status.data_sequence_control_info_valid = 498 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 499 DATA_SEQUENCE_CONTROL_INFO_VALID); 500 501 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 502 FIRST_DATA_SEQ_CTRL); 503 if (ppdu_info->rx_status.data_sequence_control_info_valid) 504 ppdu_info->rx_status.first_data_seq_ctrl = seq; 505 506 ppdu_info->rx_status.preamble_type = 507 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 508 HT_CONTROL_FIELD_PKT_TYPE); 509 switch (ppdu_info->rx_status.preamble_type) { 510 case HAL_RX_PKT_TYPE_11N: 511 ppdu_info->rx_status.ht_flags = 1; 512 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 513 break; 514 case HAL_RX_PKT_TYPE_11AC: 515 ppdu_info->rx_status.vht_flags = 1; 516 break; 517 case HAL_RX_PKT_TYPE_11AX: 518 ppdu_info->rx_status.he_flags = 1; 519 break; 520 default: 521 break; 522 } 523 524 ppdu_info->com_info.mpdu_cnt_fcs_ok = 525 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 526 MPDU_CNT_FCS_OK); 527 ppdu_info->com_info.mpdu_cnt_fcs_err = 528 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 529 MPDU_CNT_FCS_ERR); 530 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 531 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 532 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 533 else 534 ppdu_info->rx_status.rs_flags &= 535 (~IEEE80211_AMPDU_FLAG); 536 537 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 538 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7, 539 FCS_OK_BITMAP_31_0); 540 541 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 542 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8, 543 FCS_OK_BITMAP_63_32); 544 545 if (user_id < HAL_MAX_UL_MU_USERS) { 546 mon_rx_user_status = 547 &ppdu_info->rx_user_status[user_id]; 548 549 hal_rx_handle_ofdma_info(rx_tlv, mon_rx_user_status); 550 551 ppdu_info->com_info.num_users++; 552 553 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 554 mon_rx_user_status); 555 } 556 break; 557 } 558 559 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 560 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 561 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1, 562 FCS_OK_BITMAP_95_64); 563 564 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 565 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2, 566 FCS_OK_BITMAP_127_96); 567 568 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 569 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3, 570 FCS_OK_BITMAP_159_128); 571 572 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 573 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4, 574 FCS_OK_BITMAP_191_160); 575 576 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 577 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5, 578 FCS_OK_BITMAP_223_192); 579 580 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 581 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6, 582 FCS_OK_BITMAP_255_224); 583 break; 584 585 case WIFIRX_PPDU_END_STATUS_DONE_E: 586 return HAL_TLV_STATUS_PPDU_DONE; 587 588 case WIFIDUMMY_E: 589 return HAL_TLV_STATUS_BUF_DONE; 590 591 case WIFIPHYRX_HT_SIG_E: 592 { 593 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 594 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 595 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 596 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 597 FEC_CODING); 598 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 599 1 : 0; 600 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 601 HT_SIG_INFO_0, MCS); 602 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 603 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 604 HT_SIG_INFO_0, CBW); 605 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 606 HT_SIG_INFO_1, SHORT_GI); 607 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 608 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 609 HT_SIG_SU_NSS_SHIFT) + 1; 610 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 611 break; 612 } 613 614 case WIFIPHYRX_L_SIG_B_E: 615 { 616 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 617 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 618 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 619 620 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 621 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 622 switch (value) { 623 case 1: 624 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 625 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 626 break; 627 case 2: 628 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 629 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 630 break; 631 case 3: 632 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 633 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 634 break; 635 case 4: 636 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 637 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 638 break; 639 case 5: 640 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 641 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 642 break; 643 case 6: 644 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 645 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 646 break; 647 case 7: 648 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 649 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 650 break; 651 default: 652 break; 653 } 654 ppdu_info->rx_status.cck_flag = 1; 655 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 656 break; 657 } 658 659 case WIFIPHYRX_L_SIG_A_E: 660 { 661 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 662 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 663 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 664 665 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 666 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 667 switch (value) { 668 case 8: 669 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 670 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 671 break; 672 case 9: 673 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 674 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 675 break; 676 case 10: 677 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 678 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 679 break; 680 case 11: 681 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 682 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 683 break; 684 case 12: 685 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 686 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 687 break; 688 case 13: 689 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 690 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 691 break; 692 case 14: 693 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 694 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 695 break; 696 case 15: 697 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 698 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 699 break; 700 default: 701 break; 702 } 703 ppdu_info->rx_status.ofdm_flag = 1; 704 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 705 break; 706 } 707 708 case WIFIPHYRX_VHT_SIG_A_E: 709 { 710 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 711 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 712 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 713 714 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 715 SU_MU_CODING); 716 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 717 1 : 0; 718 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 719 ppdu_info->rx_status.vht_flag_values5 = group_id; 720 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 721 VHT_SIG_A_INFO_1, MCS); 722 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 723 VHT_SIG_A_INFO_1, GI_SETTING); 724 725 switch (hal->target_type) { 726 case TARGET_TYPE_QCA8074: 727 case TARGET_TYPE_QCA8074V2: 728 case TARGET_TYPE_QCA6018: 729 case TARGET_TYPE_QCN9000: 730 #ifdef QCA_WIFI_QCA6390 731 case TARGET_TYPE_QCA6390: 732 #endif 733 ppdu_info->rx_status.is_stbc = 734 HAL_RX_GET(vht_sig_a_info, 735 VHT_SIG_A_INFO_0, STBC); 736 value = HAL_RX_GET(vht_sig_a_info, 737 VHT_SIG_A_INFO_0, N_STS); 738 value = value & VHT_SIG_SU_NSS_MASK; 739 if (ppdu_info->rx_status.is_stbc && (value > 0)) 740 value = ((value + 1) >> 1) - 1; 741 ppdu_info->rx_status.nss = 742 ((value & VHT_SIG_SU_NSS_MASK) + 1); 743 744 break; 745 case TARGET_TYPE_QCA6290: 746 #if !defined(QCA_WIFI_QCA6290_11AX) 747 ppdu_info->rx_status.is_stbc = 748 HAL_RX_GET(vht_sig_a_info, 749 VHT_SIG_A_INFO_0, STBC); 750 value = HAL_RX_GET(vht_sig_a_info, 751 VHT_SIG_A_INFO_0, N_STS); 752 value = value & VHT_SIG_SU_NSS_MASK; 753 if (ppdu_info->rx_status.is_stbc && (value > 0)) 754 value = ((value + 1) >> 1) - 1; 755 ppdu_info->rx_status.nss = 756 ((value & VHT_SIG_SU_NSS_MASK) + 1); 757 #else 758 ppdu_info->rx_status.nss = 0; 759 #endif 760 break; 761 case TARGET_TYPE_QCA6490: 762 ppdu_info->rx_status.nss = 0; 763 break; 764 default: 765 break; 766 } 767 ppdu_info->rx_status.vht_flag_values3[0] = 768 (((ppdu_info->rx_status.mcs) << 4) 769 | ppdu_info->rx_status.nss); 770 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 771 VHT_SIG_A_INFO_0, BANDWIDTH); 772 ppdu_info->rx_status.vht_flag_values2 = 773 ppdu_info->rx_status.bw; 774 ppdu_info->rx_status.vht_flag_values4 = 775 HAL_RX_GET(vht_sig_a_info, 776 VHT_SIG_A_INFO_1, SU_MU_CODING); 777 778 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 779 VHT_SIG_A_INFO_1, BEAMFORMED); 780 if (group_id == 0 || group_id == 63) 781 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 782 else 783 ppdu_info->rx_status.reception_type = 784 HAL_RX_TYPE_MU_MIMO; 785 786 break; 787 } 788 case WIFIPHYRX_HE_SIG_A_SU_E: 789 { 790 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 791 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 792 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 793 ppdu_info->rx_status.he_flags = 1; 794 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 795 FORMAT_INDICATION); 796 if (value == 0) { 797 ppdu_info->rx_status.he_data1 = 798 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 799 } else { 800 ppdu_info->rx_status.he_data1 = 801 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 802 } 803 804 /* data1 */ 805 ppdu_info->rx_status.he_data1 |= 806 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 807 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 808 QDF_MON_STATUS_HE_DL_UL_KNOWN | 809 QDF_MON_STATUS_HE_MCS_KNOWN | 810 QDF_MON_STATUS_HE_DCM_KNOWN | 811 QDF_MON_STATUS_HE_CODING_KNOWN | 812 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 813 QDF_MON_STATUS_HE_STBC_KNOWN | 814 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 815 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 816 817 /* data2 */ 818 ppdu_info->rx_status.he_data2 = 819 QDF_MON_STATUS_HE_GI_KNOWN; 820 ppdu_info->rx_status.he_data2 |= 821 QDF_MON_STATUS_TXBF_KNOWN | 822 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 823 QDF_MON_STATUS_TXOP_KNOWN | 824 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 825 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 826 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 827 828 /* data3 */ 829 value = HAL_RX_GET(he_sig_a_su_info, 830 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 831 ppdu_info->rx_status.he_data3 = value; 832 value = HAL_RX_GET(he_sig_a_su_info, 833 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 834 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 835 ppdu_info->rx_status.he_data3 |= value; 836 value = HAL_RX_GET(he_sig_a_su_info, 837 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 838 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 839 ppdu_info->rx_status.he_data3 |= value; 840 841 value = HAL_RX_GET(he_sig_a_su_info, 842 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 843 ppdu_info->rx_status.mcs = value; 844 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 845 ppdu_info->rx_status.he_data3 |= value; 846 847 value = HAL_RX_GET(he_sig_a_su_info, 848 HE_SIG_A_SU_INFO_0, DCM); 849 he_dcm = value; 850 value = value << QDF_MON_STATUS_DCM_SHIFT; 851 ppdu_info->rx_status.he_data3 |= value; 852 value = HAL_RX_GET(he_sig_a_su_info, 853 HE_SIG_A_SU_INFO_1, CODING); 854 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 855 1 : 0; 856 value = value << QDF_MON_STATUS_CODING_SHIFT; 857 ppdu_info->rx_status.he_data3 |= value; 858 value = HAL_RX_GET(he_sig_a_su_info, 859 HE_SIG_A_SU_INFO_1, 860 LDPC_EXTRA_SYMBOL); 861 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 862 ppdu_info->rx_status.he_data3 |= value; 863 value = HAL_RX_GET(he_sig_a_su_info, 864 HE_SIG_A_SU_INFO_1, STBC); 865 he_stbc = value; 866 value = value << QDF_MON_STATUS_STBC_SHIFT; 867 ppdu_info->rx_status.he_data3 |= value; 868 869 /* data4 */ 870 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 871 SPATIAL_REUSE); 872 ppdu_info->rx_status.he_data4 = value; 873 874 /* data5 */ 875 value = HAL_RX_GET(he_sig_a_su_info, 876 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 877 ppdu_info->rx_status.he_data5 = value; 878 ppdu_info->rx_status.bw = value; 879 value = HAL_RX_GET(he_sig_a_su_info, 880 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 881 switch (value) { 882 case 0: 883 he_gi = HE_GI_0_8; 884 he_ltf = HE_LTF_1_X; 885 break; 886 case 1: 887 he_gi = HE_GI_0_8; 888 he_ltf = HE_LTF_2_X; 889 break; 890 case 2: 891 he_gi = HE_GI_1_6; 892 he_ltf = HE_LTF_2_X; 893 break; 894 case 3: 895 if (he_dcm && he_stbc) { 896 he_gi = HE_GI_0_8; 897 he_ltf = HE_LTF_4_X; 898 } else { 899 he_gi = HE_GI_3_2; 900 he_ltf = HE_LTF_4_X; 901 } 902 break; 903 } 904 ppdu_info->rx_status.sgi = he_gi; 905 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 906 ppdu_info->rx_status.he_data5 |= value; 907 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 908 ppdu_info->rx_status.ltf_size = he_ltf; 909 ppdu_info->rx_status.he_data5 |= value; 910 911 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 912 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 913 ppdu_info->rx_status.he_data5 |= value; 914 915 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 916 PACKET_EXTENSION_A_FACTOR); 917 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 918 ppdu_info->rx_status.he_data5 |= value; 919 920 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 921 value = value << QDF_MON_STATUS_TXBF_SHIFT; 922 ppdu_info->rx_status.he_data5 |= value; 923 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 924 PACKET_EXTENSION_PE_DISAMBIGUITY); 925 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 926 ppdu_info->rx_status.he_data5 |= value; 927 928 /* data6 */ 929 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 930 value++; 931 ppdu_info->rx_status.nss = value; 932 ppdu_info->rx_status.he_data6 = value; 933 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 934 DOPPLER_INDICATION); 935 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 936 ppdu_info->rx_status.he_data6 |= value; 937 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 938 TXOP_DURATION); 939 value = value << QDF_MON_STATUS_TXOP_SHIFT; 940 ppdu_info->rx_status.he_data6 |= value; 941 942 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 943 HE_SIG_A_SU_INFO_1, TXBF); 944 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 945 break; 946 } 947 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 948 { 949 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 950 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 951 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 952 953 ppdu_info->rx_status.he_mu_flags = 1; 954 955 /* HE Flags */ 956 /*data1*/ 957 ppdu_info->rx_status.he_data1 = 958 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 959 ppdu_info->rx_status.he_data1 |= 960 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 961 QDF_MON_STATUS_HE_DL_UL_KNOWN | 962 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 963 QDF_MON_STATUS_HE_STBC_KNOWN | 964 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 965 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 966 967 /* data2 */ 968 ppdu_info->rx_status.he_data2 = 969 QDF_MON_STATUS_HE_GI_KNOWN; 970 ppdu_info->rx_status.he_data2 |= 971 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 972 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 973 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 974 QDF_MON_STATUS_TXOP_KNOWN | 975 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 976 977 /*data3*/ 978 value = HAL_RX_GET(he_sig_a_mu_dl_info, 979 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 980 ppdu_info->rx_status.he_data3 = value; 981 982 value = HAL_RX_GET(he_sig_a_mu_dl_info, 983 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 984 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 985 ppdu_info->rx_status.he_data3 |= value; 986 987 value = HAL_RX_GET(he_sig_a_mu_dl_info, 988 HE_SIG_A_MU_DL_INFO_1, 989 LDPC_EXTRA_SYMBOL); 990 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 991 ppdu_info->rx_status.he_data3 |= value; 992 993 value = HAL_RX_GET(he_sig_a_mu_dl_info, 994 HE_SIG_A_MU_DL_INFO_1, STBC); 995 he_stbc = value; 996 value = value << QDF_MON_STATUS_STBC_SHIFT; 997 ppdu_info->rx_status.he_data3 |= value; 998 999 /*data4*/ 1000 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1001 SPATIAL_REUSE); 1002 ppdu_info->rx_status.he_data4 = value; 1003 1004 /*data5*/ 1005 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1006 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1007 ppdu_info->rx_status.he_data5 = value; 1008 ppdu_info->rx_status.bw = value; 1009 1010 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1011 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 1012 switch (value) { 1013 case 0: 1014 he_gi = HE_GI_0_8; 1015 he_ltf = HE_LTF_4_X; 1016 break; 1017 case 1: 1018 he_gi = HE_GI_0_8; 1019 he_ltf = HE_LTF_2_X; 1020 break; 1021 case 2: 1022 he_gi = HE_GI_1_6; 1023 he_ltf = HE_LTF_2_X; 1024 break; 1025 case 3: 1026 he_gi = HE_GI_3_2; 1027 he_ltf = HE_LTF_4_X; 1028 break; 1029 } 1030 ppdu_info->rx_status.sgi = he_gi; 1031 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1032 ppdu_info->rx_status.he_data5 |= value; 1033 1034 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1035 ppdu_info->rx_status.he_data5 |= value; 1036 1037 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1038 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 1039 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1040 ppdu_info->rx_status.he_data5 |= value; 1041 1042 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1043 PACKET_EXTENSION_A_FACTOR); 1044 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1045 ppdu_info->rx_status.he_data5 |= value; 1046 1047 1048 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1049 PACKET_EXTENSION_PE_DISAMBIGUITY); 1050 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1051 ppdu_info->rx_status.he_data5 |= value; 1052 1053 /*data6*/ 1054 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1055 DOPPLER_INDICATION); 1056 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1057 ppdu_info->rx_status.he_data6 |= value; 1058 1059 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1060 TXOP_DURATION); 1061 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1062 ppdu_info->rx_status.he_data6 |= value; 1063 1064 /* HE-MU Flags */ 1065 /* HE-MU-flags1 */ 1066 ppdu_info->rx_status.he_flags1 = 1067 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1068 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1069 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1070 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1071 QDF_MON_STATUS_RU_0_KNOWN; 1072 1073 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1074 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 1075 ppdu_info->rx_status.he_flags1 |= value; 1076 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1077 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 1078 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 1079 ppdu_info->rx_status.he_flags1 |= value; 1080 1081 /* HE-MU-flags2 */ 1082 ppdu_info->rx_status.he_flags2 = 1083 QDF_MON_STATUS_BW_KNOWN; 1084 1085 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1086 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1087 ppdu_info->rx_status.he_flags2 |= value; 1088 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1089 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 1090 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1091 ppdu_info->rx_status.he_flags2 |= value; 1092 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1093 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 1094 value = value - 1; 1095 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1096 ppdu_info->rx_status.he_flags2 |= value; 1097 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1098 break; 1099 } 1100 case WIFIPHYRX_HE_SIG_B1_MU_E: 1101 { 1102 1103 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 1104 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 1105 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 1106 1107 ppdu_info->rx_status.he_sig_b_common_known |= 1108 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 1109 /* TODO: Check on the availability of other fields in 1110 * sig_b_common 1111 */ 1112 1113 value = HAL_RX_GET(he_sig_b1_mu_info, 1114 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 1115 ppdu_info->rx_status.he_RU[0] = value; 1116 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1117 break; 1118 } 1119 case WIFIPHYRX_HE_SIG_B2_MU_E: 1120 { 1121 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 1122 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 1123 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 1124 /* 1125 * Not all "HE" fields can be updated from 1126 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1127 * to populate rest of the "HE" fields for MU scenarios. 1128 */ 1129 1130 /* HE-data1 */ 1131 ppdu_info->rx_status.he_data1 |= 1132 QDF_MON_STATUS_HE_MCS_KNOWN | 1133 QDF_MON_STATUS_HE_CODING_KNOWN; 1134 1135 /* HE-data2 */ 1136 1137 /* HE-data3 */ 1138 value = HAL_RX_GET(he_sig_b2_mu_info, 1139 HE_SIG_B2_MU_INFO_0, STA_MCS); 1140 ppdu_info->rx_status.mcs = value; 1141 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1142 ppdu_info->rx_status.he_data3 |= value; 1143 1144 1145 value = HAL_RX_GET(he_sig_b2_mu_info, 1146 HE_SIG_B2_MU_INFO_0, STA_CODING); 1147 value = value << QDF_MON_STATUS_CODING_SHIFT; 1148 ppdu_info->rx_status.he_data3 |= value; 1149 1150 /* HE-data4 */ 1151 value = HAL_RX_GET(he_sig_b2_mu_info, 1152 HE_SIG_B2_MU_INFO_0, STA_ID); 1153 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1154 ppdu_info->rx_status.he_data4 |= value; 1155 1156 /* HE-data5 */ 1157 1158 /* HE-data6 */ 1159 value = HAL_RX_GET(he_sig_b2_mu_info, 1160 HE_SIG_B2_MU_INFO_0, NSTS); 1161 /* value n indicates n+1 spatial streams */ 1162 value++; 1163 ppdu_info->rx_status.nss = value; 1164 ppdu_info->rx_status.he_data6 |= value; 1165 1166 break; 1167 1168 } 1169 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1170 { 1171 uint8_t *he_sig_b2_ofdma_info = 1172 (uint8_t *)rx_tlv + 1173 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1174 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1175 1176 /* 1177 * Not all "HE" fields can be updated from 1178 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1179 * to populate rest of "HE" fields for MU OFDMA scenarios. 1180 */ 1181 1182 /* HE-data1 */ 1183 ppdu_info->rx_status.he_data1 |= 1184 QDF_MON_STATUS_HE_MCS_KNOWN | 1185 QDF_MON_STATUS_HE_DCM_KNOWN | 1186 QDF_MON_STATUS_HE_CODING_KNOWN; 1187 1188 /* HE-data2 */ 1189 ppdu_info->rx_status.he_data2 |= 1190 QDF_MON_STATUS_TXBF_KNOWN; 1191 1192 /* HE-data3 */ 1193 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1194 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1195 ppdu_info->rx_status.mcs = value; 1196 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1197 ppdu_info->rx_status.he_data3 |= value; 1198 1199 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1200 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1201 he_dcm = value; 1202 value = value << QDF_MON_STATUS_DCM_SHIFT; 1203 ppdu_info->rx_status.he_data3 |= value; 1204 1205 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1206 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1207 value = value << QDF_MON_STATUS_CODING_SHIFT; 1208 ppdu_info->rx_status.he_data3 |= value; 1209 1210 /* HE-data4 */ 1211 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1212 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1213 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1214 ppdu_info->rx_status.he_data4 |= value; 1215 1216 /* HE-data5 */ 1217 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1218 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1219 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1220 ppdu_info->rx_status.he_data5 |= value; 1221 1222 /* HE-data6 */ 1223 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1224 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1225 /* value n indicates n+1 spatial streams */ 1226 value++; 1227 ppdu_info->rx_status.nss = value; 1228 ppdu_info->rx_status.he_data6 |= value; 1229 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1230 break; 1231 } 1232 case WIFIPHYRX_RSSI_LEGACY_E: 1233 { 1234 uint8_t reception_type; 1235 int8_t rssi_value; 1236 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1237 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1238 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1239 1240 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1241 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1242 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1243 ppdu_info->rx_status.he_re = 0; 1244 1245 reception_type = HAL_RX_GET(rx_tlv, 1246 PHYRX_RSSI_LEGACY_0, 1247 RECEPTION_TYPE); 1248 switch (reception_type) { 1249 case QDF_RECEPTION_TYPE_ULOFMDA: 1250 ppdu_info->rx_status.reception_type = 1251 HAL_RX_TYPE_MU_OFDMA; 1252 ppdu_info->rx_status.ulofdma_flag = 1; 1253 ppdu_info->rx_status.he_data1 = 1254 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1255 break; 1256 case QDF_RECEPTION_TYPE_ULMIMO: 1257 ppdu_info->rx_status.reception_type = 1258 HAL_RX_TYPE_MU_MIMO; 1259 ppdu_info->rx_status.he_data1 = 1260 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1261 break; 1262 default: 1263 ppdu_info->rx_status.reception_type = 1264 HAL_RX_TYPE_SU; 1265 break; 1266 } 1267 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 1268 rssi_value = HAL_RX_GET(rssi_info_tlv, 1269 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1270 ppdu_info->rx_status.rssi[0] = rssi_value; 1271 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1272 "RSSI_PRI20_CHAIN0: %d\n", rssi_value); 1273 1274 rssi_value = HAL_RX_GET(rssi_info_tlv, 1275 RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); 1276 ppdu_info->rx_status.rssi[1] = rssi_value; 1277 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1278 "RSSI_PRI20_CHAIN1: %d\n", rssi_value); 1279 1280 rssi_value = HAL_RX_GET(rssi_info_tlv, 1281 RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); 1282 ppdu_info->rx_status.rssi[2] = rssi_value; 1283 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1284 "RSSI_PRI20_CHAIN2: %d\n", rssi_value); 1285 1286 rssi_value = HAL_RX_GET(rssi_info_tlv, 1287 RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); 1288 ppdu_info->rx_status.rssi[3] = rssi_value; 1289 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1290 "RSSI_PRI20_CHAIN3: %d\n", rssi_value); 1291 1292 rssi_value = HAL_RX_GET(rssi_info_tlv, 1293 RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); 1294 ppdu_info->rx_status.rssi[4] = rssi_value; 1295 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1296 "RSSI_PRI20_CHAIN4: %d\n", rssi_value); 1297 1298 rssi_value = HAL_RX_GET(rssi_info_tlv, 1299 RECEIVE_RSSI_INFO_10, 1300 RSSI_PRI20_CHAIN5); 1301 ppdu_info->rx_status.rssi[5] = rssi_value; 1302 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1303 "RSSI_PRI20_CHAIN5: %d\n", rssi_value); 1304 1305 rssi_value = HAL_RX_GET(rssi_info_tlv, 1306 RECEIVE_RSSI_INFO_12, 1307 RSSI_PRI20_CHAIN6); 1308 ppdu_info->rx_status.rssi[6] = rssi_value; 1309 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1310 "RSSI_PRI20_CHAIN6: %d\n", rssi_value); 1311 1312 rssi_value = HAL_RX_GET(rssi_info_tlv, 1313 RECEIVE_RSSI_INFO_14, 1314 RSSI_PRI20_CHAIN7); 1315 ppdu_info->rx_status.rssi[7] = rssi_value; 1316 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1317 "RSSI_PRI20_CHAIN7: %d\n", rssi_value); 1318 break; 1319 } 1320 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1321 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1322 ppdu_info); 1323 break; 1324 case WIFIRX_HEADER_E: 1325 { 1326 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 1327 uint16_t mpdu_cnt = com_info->mpdu_cnt; 1328 1329 if (mpdu_cnt >= HAL_RX_MAX_MPDU) { 1330 hal_alert("Number of MPDUs per PPDU exceeded"); 1331 break; 1332 } 1333 /* Update first_msdu_payload for every mpdu and increment 1334 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 1335 */ 1336 ppdu_info->ppdu_msdu_info[mpdu_cnt].first_msdu_payload = 1337 rx_tlv; 1338 ppdu_info->ppdu_msdu_info[mpdu_cnt].payload_len = tlv_len; 1339 ppdu_info->ppdu_msdu_info[mpdu_cnt].nbuf = nbuf; 1340 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1341 ppdu_info->msdu_info.payload_len = tlv_len; 1342 ppdu_info->user_id = user_id; 1343 ppdu_info->hdr_len = tlv_len; 1344 ppdu_info->data = rx_tlv; 1345 ppdu_info->data += 4; 1346 1347 /* for every RX_HEADER TLV increment mpdu_cnt */ 1348 com_info->mpdu_cnt++; 1349 return HAL_TLV_STATUS_HEADER; 1350 } 1351 case WIFIRX_MPDU_START_E: 1352 { 1353 uint8_t *rx_mpdu_start = 1354 (uint8_t *)rx_tlv + HAL_RX_OFFSET(UNIFIED_RX_MPDU_START_0, 1355 RX_MPDU_INFO_RX_MPDU_INFO_DETAILS); 1356 uint32_t ppdu_id = 1357 HAL_RX_GET_PPDU_ID(rx_mpdu_start); 1358 uint8_t filter_category = 0; 1359 1360 ppdu_info->nac_info.fc_valid = 1361 HAL_RX_GET_FC_VALID(rx_mpdu_start); 1362 1363 ppdu_info->nac_info.to_ds_flag = 1364 HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start); 1365 1366 ppdu_info->nac_info.frame_control = 1367 HAL_RX_GET(rx_mpdu_start, 1368 RX_MPDU_INFO_14, 1369 MPDU_FRAME_CONTROL_FIELD); 1370 1371 ppdu_info->nac_info.mac_addr2_valid = 1372 HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start); 1373 1374 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1375 HAL_RX_GET(rx_mpdu_start, 1376 RX_MPDU_INFO_16, 1377 MAC_ADDR_AD2_15_0); 1378 1379 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1380 HAL_RX_GET(rx_mpdu_start, 1381 RX_MPDU_INFO_17, 1382 MAC_ADDR_AD2_47_16); 1383 1384 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1385 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1386 ppdu_info->rx_status.ppdu_len = 1387 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1388 MPDU_LENGTH); 1389 } else { 1390 ppdu_info->rx_status.ppdu_len += 1391 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1392 MPDU_LENGTH); 1393 } 1394 1395 filter_category = 1396 HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start); 1397 1398 if (filter_category == 0) 1399 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1400 else if (filter_category == 1) 1401 ppdu_info->rx_status.monitor_direct_used = 1; 1402 1403 ppdu_info->nac_info.mcast_bcast = 1404 HAL_RX_GET(rx_mpdu_start, 1405 RX_MPDU_INFO_13, 1406 MCAST_BCAST); 1407 break; 1408 } 1409 case WIFIRX_MPDU_END_E: 1410 ppdu_info->user_id = user_id; 1411 ppdu_info->fcs_err = 1412 HAL_RX_GET(rx_tlv, RX_MPDU_END_1, 1413 FCS_ERR); 1414 return HAL_TLV_STATUS_MPDU_END; 1415 case WIFIRX_MSDU_END_E: 1416 if (user_id < HAL_MAX_UL_MU_USERS) { 1417 ppdu_info->rx_msdu_info[user_id].cce_metadata = 1418 HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); 1419 ppdu_info->rx_msdu_info[user_id].fse_metadata = 1420 HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv); 1421 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 1422 HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv); 1423 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 1424 HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv); 1425 ppdu_info->rx_msdu_info[user_id].flow_idx = 1426 HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv); 1427 } 1428 return HAL_TLV_STATUS_MSDU_END; 1429 case 0: 1430 return HAL_TLV_STATUS_PPDU_DONE; 1431 1432 default: 1433 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1434 unhandled = false; 1435 else 1436 unhandled = true; 1437 break; 1438 } 1439 1440 if (!unhandled) 1441 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1442 "%s TLV type: %d, TLV len:%d %s", 1443 __func__, tlv_tag, tlv_len, 1444 unhandled == true ? "unhandled" : ""); 1445 1446 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1447 rx_tlv, tlv_len); 1448 1449 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1450 } 1451 1452 /** 1453 * hal_reo_setup - Initialize HW REO block 1454 * 1455 * @hal_soc: Opaque HAL SOC handle 1456 * @reo_params: parameters needed by HAL for REO config 1457 */ 1458 static void hal_reo_setup_generic(struct hal_soc *soc, 1459 void *reoparams) 1460 { 1461 uint32_t reg_val; 1462 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1463 1464 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1465 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1466 1467 hal_reo_config(soc, reg_val, reo_params); 1468 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1469 1470 /* TODO: Setup destination ring mapping if enabled */ 1471 1472 /* TODO: Error destination ring setting is left to default. 1473 * Default setting is to send all errors to release ring. 1474 */ 1475 1476 HAL_REG_WRITE(soc, 1477 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 1478 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1479 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1480 1481 HAL_REG_WRITE(soc, 1482 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 1483 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1484 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1485 1486 HAL_REG_WRITE(soc, 1487 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 1488 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1489 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1490 1491 HAL_REG_WRITE(soc, 1492 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 1493 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1494 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1495 1496 /* 1497 * When hash based routing is enabled, routing of the rx packet 1498 * is done based on the following value: 1 _ _ _ _ The last 4 1499 * bits are based on hash[3:0]. This means the possible values 1500 * are 0x10 to 0x1f. This value is used to look-up the 1501 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1502 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1503 * registers need to be configured to set-up the 16 entries to 1504 * map the hash values to a ring number. There are 3 bits per 1505 * hash entry – which are mapped as follows: 1506 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1507 * 7: NOT_USED. 1508 */ 1509 if (reo_params->rx_hash_enabled) { 1510 HAL_REG_WRITE(soc, 1511 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1512 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1513 reo_params->remap1); 1514 1515 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1516 HAL_REG_READ(soc, 1517 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1518 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1519 1520 HAL_REG_WRITE(soc, 1521 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1522 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1523 reo_params->remap2); 1524 1525 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1526 HAL_REG_READ(soc, 1527 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1528 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1529 1530 } 1531 1532 1533 /* TODO: Check if the following registers shoould be setup by host: 1534 * AGING_CONTROL 1535 * HIGH_MEMORY_THRESHOLD 1536 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1537 * GLOBAL_LINK_DESC_COUNT_CTRL 1538 */ 1539 } 1540 1541 /** 1542 * hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring 1543 * @hal_soc: Opaque HAL SOC handle 1544 * @hal_ring: Source ring pointer 1545 * @headp: Head Pointer 1546 * @tailp: Tail Pointer 1547 * @ring: Ring type 1548 * 1549 * Return: Update tail pointer and head pointer in arguments. 1550 */ 1551 static inline 1552 void hal_get_hw_hptp_generic(struct hal_soc *hal_soc, 1553 hal_ring_handle_t hal_ring_hdl, 1554 uint32_t *headp, uint32_t *tailp, 1555 uint8_t ring) 1556 { 1557 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1558 struct hal_hw_srng_config *ring_config; 1559 enum hal_ring_type ring_type = (enum hal_ring_type)ring; 1560 1561 if (!hal_soc || !srng) { 1562 QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_ERROR, 1563 "%s: Context is Null", __func__); 1564 return; 1565 } 1566 1567 ring_config = HAL_SRNG_CONFIG(hal_soc, ring_type); 1568 if (!ring_config->lmac_ring) { 1569 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1570 *headp = SRNG_SRC_REG_READ(srng, HP); 1571 *tailp = SRNG_SRC_REG_READ(srng, TP); 1572 } else { 1573 *headp = SRNG_DST_REG_READ(srng, HP); 1574 *tailp = SRNG_DST_REG_READ(srng, TP); 1575 } 1576 } 1577 } 1578 1579 /** 1580 * hal_srng_src_hw_init - Private function to initialize SRNG 1581 * source ring HW 1582 * @hal_soc: HAL SOC handle 1583 * @srng: SRNG ring pointer 1584 */ 1585 static inline 1586 void hal_srng_src_hw_init_generic(struct hal_soc *hal, 1587 struct hal_srng *srng) 1588 { 1589 uint32_t reg_val = 0; 1590 uint64_t tp_addr = 0; 1591 1592 hal_debug("hw_init srng %d", srng->ring_id); 1593 1594 if (srng->flags & HAL_SRNG_MSI_INTR) { 1595 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 1596 srng->msi_addr & 0xffffffff); 1597 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 1598 (uint64_t)(srng->msi_addr) >> 32) | 1599 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 1600 MSI1_ENABLE), 1); 1601 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1602 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1603 } 1604 1605 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1606 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1607 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1608 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 1609 srng->entry_size * srng->num_entries); 1610 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 1611 1612 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1613 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 1614 1615 /** 1616 * Interrupt setup: 1617 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1618 * if level mode is required 1619 */ 1620 reg_val = 0; 1621 1622 /* 1623 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 1624 * programmed in terms of 1us resolution instead of 8us resolution as 1625 * given in MLD. 1626 */ 1627 if (srng->intr_timer_thres_us) { 1628 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1629 INTERRUPT_TIMER_THRESHOLD), 1630 srng->intr_timer_thres_us); 1631 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 1632 } 1633 1634 if (srng->intr_batch_cntr_thres_entries) { 1635 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1636 BATCH_COUNTER_THRESHOLD), 1637 srng->intr_batch_cntr_thres_entries * 1638 srng->entry_size); 1639 } 1640 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 1641 1642 reg_val = 0; 1643 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 1644 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 1645 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 1646 } 1647 1648 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 1649 1650 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 1651 * remain 0 to avoid some WBM stability issues. Remote head/tail 1652 * pointers are not required since this ring is completely managed 1653 * by WBM HW 1654 */ 1655 reg_val = 0; 1656 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 1657 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1658 ((unsigned long)(srng->u.src_ring.tp_addr) - 1659 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1660 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 1661 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 1662 } else { 1663 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, RING_ID_DISABLE), 1); 1664 } 1665 1666 /* Initilaize head and tail pointers to indicate ring is empty */ 1667 SRNG_SRC_REG_WRITE(srng, HP, 0); 1668 SRNG_SRC_REG_WRITE(srng, TP, 0); 1669 *(srng->u.src_ring.tp_addr) = 0; 1670 1671 reg_val |= ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1672 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1673 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1674 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1675 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1676 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1677 1678 /* Loop count is not used for SRC rings */ 1679 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 1680 1681 /* 1682 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1683 * todo: update fw_api and replace with above line 1684 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1685 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1686 */ 1687 reg_val |= 0x40; 1688 1689 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 1690 } 1691 1692 /** 1693 * hal_srng_dst_hw_init - Private function to initialize SRNG 1694 * destination ring HW 1695 * @hal_soc: HAL SOC handle 1696 * @srng: SRNG ring pointer 1697 */ 1698 static inline 1699 void hal_srng_dst_hw_init_generic(struct hal_soc *hal, 1700 struct hal_srng *srng) 1701 { 1702 uint32_t reg_val = 0; 1703 uint64_t hp_addr = 0; 1704 1705 hal_debug("hw_init srng %d", srng->ring_id); 1706 1707 if (srng->flags & HAL_SRNG_MSI_INTR) { 1708 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 1709 srng->msi_addr & 0xffffffff); 1710 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 1711 (uint64_t)(srng->msi_addr) >> 32) | 1712 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 1713 MSI1_ENABLE), 1); 1714 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1715 SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1716 } 1717 1718 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1719 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1720 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1721 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 1722 srng->entry_size * srng->num_entries); 1723 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 1724 1725 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 1726 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 1727 SRNG_DST_REG_WRITE(srng, ID, reg_val); 1728 1729 1730 /** 1731 * Interrupt setup: 1732 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1733 * if level mode is required 1734 */ 1735 reg_val = 0; 1736 if (srng->intr_timer_thres_us) { 1737 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1738 INTERRUPT_TIMER_THRESHOLD), 1739 srng->intr_timer_thres_us >> 3); 1740 } 1741 1742 if (srng->intr_batch_cntr_thres_entries) { 1743 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1744 BATCH_COUNTER_THRESHOLD), 1745 srng->intr_batch_cntr_thres_entries * 1746 srng->entry_size); 1747 } 1748 1749 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 1750 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1751 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1752 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1753 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 1754 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 1755 1756 /* Initilaize head and tail pointers to indicate ring is empty */ 1757 SRNG_DST_REG_WRITE(srng, HP, 0); 1758 SRNG_DST_REG_WRITE(srng, TP, 0); 1759 *(srng->u.dst_ring.hp_addr) = 0; 1760 1761 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1762 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1763 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1764 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1765 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1766 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1767 1768 /* 1769 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1770 * todo: update fw_api and replace with above line 1771 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1772 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1773 */ 1774 reg_val |= 0x40; 1775 1776 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 1777 1778 } 1779 1780 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1781 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 1782 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 1783 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 1784 1785 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1786 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 1787 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 1788 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 1789 1790 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1791 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 1792 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 1793 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 1794 1795 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 1796 (((*(((uint32_t *) wbm_desc) + \ 1797 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 1798 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 1799 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 1800 1801 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 1802 (((*(((uint32_t *) wbm_desc) + \ 1803 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 1804 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 1805 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 1806 1807 /** 1808 * hal_rx_wbm_err_info_get_generic(): Retrieves WBM error code and reason and 1809 * save it to hal_wbm_err_desc_info structure passed by caller 1810 * @wbm_desc: wbm ring descriptor 1811 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 1812 * Return: void 1813 */ 1814 static inline void hal_rx_wbm_err_info_get_generic(void *wbm_desc, 1815 void *wbm_er_info1) 1816 { 1817 struct hal_wbm_err_desc_info *wbm_er_info = 1818 (struct hal_wbm_err_desc_info *)wbm_er_info1; 1819 1820 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 1821 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 1822 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 1823 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 1824 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 1825 } 1826 1827 /** 1828 * hal_tx_comp_get_release_reason_generic() - TQM Release reason 1829 * @hal_desc: completion ring descriptor pointer 1830 * 1831 * This function will return the type of pointer - buffer or descriptor 1832 * 1833 * Return: buffer type 1834 */ 1835 static inline uint8_t hal_tx_comp_get_release_reason_generic(void *hal_desc) 1836 { 1837 uint32_t comp_desc = 1838 *(uint32_t *) (((uint8_t *) hal_desc) + 1839 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1840 1841 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1842 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1843 } 1844 1845 /** 1846 * hal_rx_dump_mpdu_start_tlv_generic: dump RX mpdu_start TLV in structured 1847 * human readable format. 1848 * @mpdu_start: pointer the rx_attention TLV in pkt. 1849 * @dbg_level: log level. 1850 * 1851 * Return: void 1852 */ 1853 static inline void hal_rx_dump_mpdu_start_tlv_generic(void *mpdustart, 1854 uint8_t dbg_level) 1855 { 1856 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1857 struct rx_mpdu_info *mpdu_info = 1858 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1859 1860 hal_verbose_debug( 1861 "rx_mpdu_start tlv (1/5) - " 1862 "rxpcu_mpdu_filter_in_category: %x " 1863 "sw_frame_group_id: %x " 1864 "ndp_frame: %x " 1865 "phy_err: %x " 1866 "phy_err_during_mpdu_header: %x " 1867 "protocol_version_err: %x " 1868 "ast_based_lookup_valid: %x " 1869 "phy_ppdu_id: %x " 1870 "ast_index: %x " 1871 "sw_peer_id: %x " 1872 "mpdu_frame_control_valid: %x " 1873 "mpdu_duration_valid: %x " 1874 "mac_addr_ad1_valid: %x " 1875 "mac_addr_ad2_valid: %x " 1876 "mac_addr_ad3_valid: %x " 1877 "mac_addr_ad4_valid: %x " 1878 "mpdu_sequence_control_valid: %x " 1879 "mpdu_qos_control_valid: %x " 1880 "mpdu_ht_control_valid: %x " 1881 "frame_encryption_info_valid: %x ", 1882 mpdu_info->rxpcu_mpdu_filter_in_category, 1883 mpdu_info->sw_frame_group_id, 1884 mpdu_info->ndp_frame, 1885 mpdu_info->phy_err, 1886 mpdu_info->phy_err_during_mpdu_header, 1887 mpdu_info->protocol_version_err, 1888 mpdu_info->ast_based_lookup_valid, 1889 mpdu_info->phy_ppdu_id, 1890 mpdu_info->ast_index, 1891 mpdu_info->sw_peer_id, 1892 mpdu_info->mpdu_frame_control_valid, 1893 mpdu_info->mpdu_duration_valid, 1894 mpdu_info->mac_addr_ad1_valid, 1895 mpdu_info->mac_addr_ad2_valid, 1896 mpdu_info->mac_addr_ad3_valid, 1897 mpdu_info->mac_addr_ad4_valid, 1898 mpdu_info->mpdu_sequence_control_valid, 1899 mpdu_info->mpdu_qos_control_valid, 1900 mpdu_info->mpdu_ht_control_valid, 1901 mpdu_info->frame_encryption_info_valid); 1902 1903 hal_verbose_debug( 1904 "rx_mpdu_start tlv (2/5) - " 1905 "fr_ds: %x " 1906 "to_ds: %x " 1907 "encrypted: %x " 1908 "mpdu_retry: %x " 1909 "mpdu_sequence_number: %x " 1910 "epd_en: %x " 1911 "all_frames_shall_be_encrypted: %x " 1912 "encrypt_type: %x " 1913 "mesh_sta: %x " 1914 "bssid_hit: %x " 1915 "bssid_number: %x " 1916 "tid: %x " 1917 "pn_31_0: %x " 1918 "pn_63_32: %x " 1919 "pn_95_64: %x " 1920 "pn_127_96: %x " 1921 "peer_meta_data: %x " 1922 "rxpt_classify_info.reo_destination_indication: %x " 1923 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 1924 "rx_reo_queue_desc_addr_31_0: %x ", 1925 mpdu_info->fr_ds, 1926 mpdu_info->to_ds, 1927 mpdu_info->encrypted, 1928 mpdu_info->mpdu_retry, 1929 mpdu_info->mpdu_sequence_number, 1930 mpdu_info->epd_en, 1931 mpdu_info->all_frames_shall_be_encrypted, 1932 mpdu_info->encrypt_type, 1933 mpdu_info->mesh_sta, 1934 mpdu_info->bssid_hit, 1935 mpdu_info->bssid_number, 1936 mpdu_info->tid, 1937 mpdu_info->pn_31_0, 1938 mpdu_info->pn_63_32, 1939 mpdu_info->pn_95_64, 1940 mpdu_info->pn_127_96, 1941 mpdu_info->peer_meta_data, 1942 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 1943 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 1944 mpdu_info->rx_reo_queue_desc_addr_31_0); 1945 1946 hal_verbose_debug( 1947 "rx_mpdu_start tlv (3/5) - " 1948 "rx_reo_queue_desc_addr_39_32: %x " 1949 "receive_queue_number: %x " 1950 "pre_delim_err_warning: %x " 1951 "first_delim_err: %x " 1952 "key_id_octet: %x " 1953 "new_peer_entry: %x " 1954 "decrypt_needed: %x " 1955 "decap_type: %x " 1956 "rx_insert_vlan_c_tag_padding: %x " 1957 "rx_insert_vlan_s_tag_padding: %x " 1958 "strip_vlan_c_tag_decap: %x " 1959 "strip_vlan_s_tag_decap: %x " 1960 "pre_delim_count: %x " 1961 "ampdu_flag: %x " 1962 "bar_frame: %x " 1963 "mpdu_length: %x " 1964 "first_mpdu: %x " 1965 "mcast_bcast: %x " 1966 "ast_index_not_found: %x " 1967 "ast_index_timeout: %x ", 1968 mpdu_info->rx_reo_queue_desc_addr_39_32, 1969 mpdu_info->receive_queue_number, 1970 mpdu_info->pre_delim_err_warning, 1971 mpdu_info->first_delim_err, 1972 mpdu_info->key_id_octet, 1973 mpdu_info->new_peer_entry, 1974 mpdu_info->decrypt_needed, 1975 mpdu_info->decap_type, 1976 mpdu_info->rx_insert_vlan_c_tag_padding, 1977 mpdu_info->rx_insert_vlan_s_tag_padding, 1978 mpdu_info->strip_vlan_c_tag_decap, 1979 mpdu_info->strip_vlan_s_tag_decap, 1980 mpdu_info->pre_delim_count, 1981 mpdu_info->ampdu_flag, 1982 mpdu_info->bar_frame, 1983 mpdu_info->mpdu_length, 1984 mpdu_info->first_mpdu, 1985 mpdu_info->mcast_bcast, 1986 mpdu_info->ast_index_not_found, 1987 mpdu_info->ast_index_timeout); 1988 1989 hal_verbose_debug( 1990 "rx_mpdu_start tlv (4/5) - " 1991 "power_mgmt: %x " 1992 "non_qos: %x " 1993 "null_data: %x " 1994 "mgmt_type: %x " 1995 "ctrl_type: %x " 1996 "more_data: %x " 1997 "eosp: %x " 1998 "fragment_flag: %x " 1999 "order: %x " 2000 "u_apsd_trigger: %x " 2001 "encrypt_required: %x " 2002 "directed: %x " 2003 "mpdu_frame_control_field: %x " 2004 "mpdu_duration_field: %x " 2005 "mac_addr_ad1_31_0: %x " 2006 "mac_addr_ad1_47_32: %x " 2007 "mac_addr_ad2_15_0: %x " 2008 "mac_addr_ad2_47_16: %x " 2009 "mac_addr_ad3_31_0: %x " 2010 "mac_addr_ad3_47_32: %x ", 2011 mpdu_info->power_mgmt, 2012 mpdu_info->non_qos, 2013 mpdu_info->null_data, 2014 mpdu_info->mgmt_type, 2015 mpdu_info->ctrl_type, 2016 mpdu_info->more_data, 2017 mpdu_info->eosp, 2018 mpdu_info->fragment_flag, 2019 mpdu_info->order, 2020 mpdu_info->u_apsd_trigger, 2021 mpdu_info->encrypt_required, 2022 mpdu_info->directed, 2023 mpdu_info->mpdu_frame_control_field, 2024 mpdu_info->mpdu_duration_field, 2025 mpdu_info->mac_addr_ad1_31_0, 2026 mpdu_info->mac_addr_ad1_47_32, 2027 mpdu_info->mac_addr_ad2_15_0, 2028 mpdu_info->mac_addr_ad2_47_16, 2029 mpdu_info->mac_addr_ad3_31_0, 2030 mpdu_info->mac_addr_ad3_47_32); 2031 2032 hal_verbose_debug( 2033 "rx_mpdu_start tlv (5/5) - " 2034 "mpdu_sequence_control_field: %x " 2035 "mac_addr_ad4_31_0: %x " 2036 "mac_addr_ad4_47_32: %x " 2037 "mpdu_qos_control_field: %x " 2038 "mpdu_ht_control_field: %x ", 2039 mpdu_info->mpdu_sequence_control_field, 2040 mpdu_info->mac_addr_ad4_31_0, 2041 mpdu_info->mac_addr_ad4_47_32, 2042 mpdu_info->mpdu_qos_control_field, 2043 mpdu_info->mpdu_ht_control_field); 2044 } 2045 2046 /** 2047 * hal_tx_desc_set_search_type - Set the search type value 2048 * @desc: Handle to Tx Descriptor 2049 * @search_type: search type 2050 * 0 – Normal search 2051 * 1 – Index based address search 2052 * 2 – Index based flow search 2053 * 2054 * Return: void 2055 */ 2056 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 2057 static void hal_tx_desc_set_search_type_generic(void *desc, 2058 uint8_t search_type) 2059 { 2060 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 2061 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 2062 } 2063 #else 2064 static void hal_tx_desc_set_search_type_generic(void *desc, 2065 uint8_t search_type) 2066 { 2067 } 2068 2069 #endif 2070 2071 /** 2072 * hal_tx_desc_set_search_index - Set the search index value 2073 * @desc: Handle to Tx Descriptor 2074 * @search_index: The index that will be used for index based address or 2075 * flow search. The field is valid when 'search_type' is 2076 * 1 0r 2 2077 * 2078 * Return: void 2079 */ 2080 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 2081 static void hal_tx_desc_set_search_index_generic(void *desc, 2082 uint32_t search_index) 2083 { 2084 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 2085 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 2086 } 2087 #else 2088 static void hal_tx_desc_set_search_index_generic(void *desc, 2089 uint32_t search_index) 2090 { 2091 } 2092 #endif 2093 2094 /** 2095 * hal_tx_desc_set_cache_set_num_generic - Set the cache-set-num value 2096 * @desc: Handle to Tx Descriptor 2097 * @cache_num: Cache set number that should be used to cache the index 2098 * based search results, for address and flow search. 2099 * This value should be equal to LSB four bits of the hash value 2100 * of match data, in case of search index points to an entry 2101 * which may be used in content based search also. The value can 2102 * be anything when the entry pointed by search index will not be 2103 * used for content based search. 2104 * 2105 * Return: void 2106 */ 2107 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 2108 static void hal_tx_desc_set_cache_set_num_generic(void *desc, 2109 uint8_t cache_num) 2110 { 2111 HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |= 2112 HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num); 2113 } 2114 #else 2115 static void hal_tx_desc_set_cache_set_num_generic(void *desc, 2116 uint8_t cache_num) 2117 { 2118 } 2119 #endif 2120 2121 /** 2122 * hal_tx_set_pcp_tid_map_generic() - Configure default PCP to TID map table 2123 * @soc: HAL SoC context 2124 * @map: PCP-TID mapping table 2125 * 2126 * PCP are mapped to 8 TID values using TID values programmed 2127 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 2128 * The mapping register has TID mapping for 8 PCP values 2129 * 2130 * Return: none 2131 */ 2132 static void hal_tx_set_pcp_tid_map_generic(struct hal_soc *soc, uint8_t *map) 2133 { 2134 uint32_t addr, value; 2135 2136 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2137 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2138 2139 value = (map[0] | 2140 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 2141 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 2142 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 2143 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 2144 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 2145 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 2146 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 2147 2148 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2149 } 2150 2151 /** 2152 * hal_tx_update_pcp_tid_generic() - Update the pcp tid map table with 2153 * value received from user-space 2154 * @soc: HAL SoC context 2155 * @pcp: pcp value 2156 * @tid : tid value 2157 * 2158 * Return: void 2159 */ 2160 static 2161 void hal_tx_update_pcp_tid_generic(struct hal_soc *soc, 2162 uint8_t pcp, uint8_t tid) 2163 { 2164 uint32_t addr, value, regval; 2165 2166 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2167 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2168 2169 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 2170 2171 /* Read back previous PCP TID config and update 2172 * with new config. 2173 */ 2174 regval = HAL_REG_READ(soc, addr); 2175 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 2176 regval |= value; 2177 2178 HAL_REG_WRITE(soc, addr, 2179 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2180 } 2181 2182 /** 2183 * hal_tx_update_tidmap_prty_generic() - Update the tid map priority 2184 * @soc: HAL SoC context 2185 * @val: priority value 2186 * 2187 * Return: void 2188 */ 2189 static 2190 void hal_tx_update_tidmap_prty_generic(struct hal_soc *soc, uint8_t value) 2191 { 2192 uint32_t addr; 2193 2194 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 2195 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2196 2197 HAL_REG_WRITE(soc, addr, 2198 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 2199 } 2200 2201 #endif /* _HAL_GENERIC_API_H_ */ 2202