1 /* 2 * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_API_MON_H_ 20 #define _HAL_API_MON_H_ 21 22 #include "qdf_types.h" 23 #include "hal_internal.h" 24 #include <target_type.h> 25 26 #define HAL_RX_PHY_DATA_RADAR 0x01 27 #define HAL_SU_MU_CODING_LDPC 0x01 28 29 #define HAL_RX_FCS_LEN (4) 30 #define KEY_EXTIV 0x20 31 32 #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000 33 #define HAL_RX_USER_TLV32_TYPE_LSB 1 34 #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE 35 36 #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000 37 #define HAL_RX_USER_TLV32_LEN_LSB 10 38 #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00 39 40 #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000 41 #define HAL_RX_USER_TLV32_USERID_LSB 26 42 #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000 43 44 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 45 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 46 47 #define HAL_RX_TLV32_HDR_SIZE 4 48 49 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 50 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 51 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 52 HAL_RX_USER_TLV32_TYPE_LSB) 53 54 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 55 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 56 HAL_RX_USER_TLV32_LEN_MASK) >> \ 57 HAL_RX_USER_TLV32_LEN_LSB) 58 59 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 60 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 61 HAL_RX_USER_TLV32_USERID_MASK) >> \ 62 HAL_RX_USER_TLV32_USERID_LSB) 63 64 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 65 #define HAL_TLV_STATUS_PPDU_DONE 1 66 #define HAL_TLV_STATUS_BUF_DONE 2 67 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 68 #define HAL_TLV_STATUS_PPDU_START 4 69 #define HAL_TLV_STATUS_HEADER 5 70 #define HAL_TLV_STATUS_MPDU_END 6 71 #define HAL_TLV_STATUS_MSDU_START 7 72 #define HAL_TLV_STATUS_MSDU_END 8 73 74 #define HAL_MAX_UL_MU_USERS 37 75 76 #define HAL_RX_PKT_TYPE_11A 0 77 #define HAL_RX_PKT_TYPE_11B 1 78 #define HAL_RX_PKT_TYPE_11N 2 79 #define HAL_RX_PKT_TYPE_11AC 3 80 #define HAL_RX_PKT_TYPE_11AX 4 81 82 #define HAL_RX_RECEPTION_TYPE_SU 0 83 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 84 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 85 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 86 87 /* Multiply rate by 2 to avoid float point 88 * and get rate in units of 500kbps 89 */ 90 #define HAL_11B_RATE_0MCS 11*2 91 #define HAL_11B_RATE_1MCS 5.5*2 92 #define HAL_11B_RATE_2MCS 2*2 93 #define HAL_11B_RATE_3MCS 1*2 94 #define HAL_11B_RATE_4MCS 11*2 95 #define HAL_11B_RATE_5MCS 5.5*2 96 #define HAL_11B_RATE_6MCS 2*2 97 98 #define HAL_11A_RATE_0MCS 48*2 99 #define HAL_11A_RATE_1MCS 24*2 100 #define HAL_11A_RATE_2MCS 12*2 101 #define HAL_11A_RATE_3MCS 6*2 102 #define HAL_11A_RATE_4MCS 54*2 103 #define HAL_11A_RATE_5MCS 36*2 104 #define HAL_11A_RATE_6MCS 18*2 105 #define HAL_11A_RATE_7MCS 9*2 106 107 #define HAL_LEGACY_MCS0 0 108 #define HAL_LEGACY_MCS1 1 109 #define HAL_LEGACY_MCS2 2 110 #define HAL_LEGACY_MCS3 3 111 #define HAL_LEGACY_MCS4 4 112 #define HAL_LEGACY_MCS5 5 113 #define HAL_LEGACY_MCS6 6 114 #define HAL_LEGACY_MCS7 7 115 116 #define HE_GI_0_8 0 117 #define HE_GI_0_4 1 118 #define HE_GI_1_6 2 119 #define HE_GI_3_2 3 120 121 #define HT_SGI_PRESENT 0x80 122 123 #define HE_LTF_1_X 0 124 #define HE_LTF_2_X 1 125 #define HE_LTF_4_X 2 126 #define HE_LTF_UNKNOWN 3 127 #define VHT_SIG_SU_NSS_MASK 0x7 128 #define HT_SIG_SU_NSS_SHIFT 0x3 129 130 #define HAL_TID_INVALID 31 131 #define HAL_AST_IDX_INVALID 0xFFFF 132 133 #ifdef GET_MSDU_AGGREGATION 134 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 135 {\ 136 struct rx_msdu_end *rx_msdu_end;\ 137 bool first_msdu, last_msdu; \ 138 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 139 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 140 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 141 if (first_msdu && last_msdu)\ 142 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 143 else\ 144 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 145 } \ 146 147 #else 148 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 149 #endif 150 151 /* Max MPDUs per status buffer */ 152 #define HAL_RX_MAX_MPDU 256 153 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 154 155 /* Max pilot count */ 156 #define HAL_RX_MAX_SU_EVM_COUNT 32 157 158 /* 159 * Struct hal_rx_su_evm_info - SU evm info 160 * @number_of_symbols: number of symbols 161 * @nss_count: nss count 162 * @pilot_count: pilot count 163 * @pilot_evm: Array of pilot evm values 164 */ 165 struct hal_rx_su_evm_info { 166 uint32_t number_of_symbols; 167 uint8_t nss_count; 168 uint8_t pilot_count; 169 uint32_t pilot_evm[HAL_RX_MAX_SU_EVM_COUNT]; 170 }; 171 172 enum { 173 DP_PPDU_STATUS_START, 174 DP_PPDU_STATUS_DONE, 175 }; 176 177 static inline 178 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 179 { 180 return data; 181 } 182 183 static inline 184 uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr) 185 { 186 struct rx_attention *rx_attn; 187 struct rx_mon_pkt_tlvs *rx_desc = 188 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 189 190 rx_attn = &rx_desc->attn_tlv.rx_attn; 191 192 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 193 } 194 195 static inline 196 uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr) 197 { 198 struct rx_attention *rx_attn; 199 struct rx_mon_pkt_tlvs *rx_desc = 200 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 201 202 rx_attn = &rx_desc->attn_tlv.rx_attn; 203 204 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 205 } 206 207 /* 208 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 209 * start TLV of Hardware TLV descriptor 210 * @hw_desc_addr: Hardware desciptor address 211 * 212 * Return: bool: if TLV tag match 213 */ 214 static inline 215 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 216 { 217 struct rx_mon_pkt_tlvs *rx_desc = 218 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 219 uint32_t tlv_tag; 220 221 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 222 &rx_desc->mpdu_start_tlv); 223 224 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 225 } 226 227 228 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 229 230 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 231 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 232 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 233 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 234 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 235 236 #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \ 237 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 238 (((struct reo_entrance_ring *)reo_ent_desc) \ 239 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 240 241 #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \ 242 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 243 (((struct reo_entrance_ring *)reo_ent_desc) \ 244 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 245 246 #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \ 247 (HAL_RX_BUF_COOKIE_GET(& \ 248 (((struct reo_entrance_ring *)reo_ent_desc) \ 249 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 250 251 /** 252 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 253 * cookie from the REO entrance ring element 254 * 255 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 256 * the current descriptor 257 * @ buf_info: structure to return the buffer information 258 * @ msdu_cnt: pointer to msdu count in MPDU 259 * Return: void 260 */ 261 static inline 262 void hal_rx_reo_ent_buf_paddr_get(hal_rxdma_desc_t rx_desc, 263 struct hal_buf_info *buf_info, 264 uint32_t *msdu_cnt 265 ) 266 { 267 struct reo_entrance_ring *reo_ent_ring = 268 (struct reo_entrance_ring *)rx_desc; 269 struct buffer_addr_info *buf_addr_info; 270 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 271 uint32_t loop_cnt; 272 273 rx_mpdu_desc_info_details = 274 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 275 276 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 277 RX_MPDU_DESC_INFO_0, MSDU_COUNT); 278 279 loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT); 280 281 buf_addr_info = 282 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 283 284 buf_info->paddr = 285 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 286 ((uint64_t) 287 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 288 289 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 290 buf_info->rbm = HAL_RX_BUF_RBM_GET(buf_addr_info); 291 292 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 293 "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 294 __func__, __LINE__, reo_ent_ring, buf_addr_info, 295 (unsigned long long)buf_info->paddr, loop_cnt); 296 } 297 298 static inline 299 void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 300 struct hal_buf_info *buf_info) 301 { 302 struct rx_msdu_link *msdu_link = 303 (struct rx_msdu_link *)rx_msdu_link_desc; 304 struct buffer_addr_info *buf_addr_info; 305 306 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 307 308 buf_info->paddr = 309 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 310 ((uint64_t) 311 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 312 313 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 314 buf_info->rbm = HAL_RX_BUF_RBM_GET(buf_addr_info); 315 } 316 317 /** 318 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 319 * 320 * @ soc : HAL version of the SOC pointer 321 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 322 * @ buf_addr_info : void pointer to the buffer_addr_info 323 * 324 * Return: void 325 */ 326 327 static inline 328 void hal_rx_mon_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 329 void *src_srng_desc, 330 hal_buff_addrinfo_t buf_addr_info) 331 { 332 struct buffer_addr_info *wbm_srng_buffer_addr_info = 333 (struct buffer_addr_info *)src_srng_desc; 334 uint64_t paddr; 335 struct buffer_addr_info *p_buffer_addr_info = 336 (struct buffer_addr_info *)buf_addr_info; 337 338 paddr = 339 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 340 ((uint64_t) 341 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 342 343 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 344 "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 345 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 346 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 347 348 /* Structure copy !!! */ 349 *wbm_srng_buffer_addr_info = 350 *((struct buffer_addr_info *)buf_addr_info); 351 } 352 353 static inline 354 uint32 hal_get_rx_msdu_link_desc_size(void) 355 { 356 return sizeof(struct rx_msdu_link); 357 } 358 359 enum { 360 HAL_PKT_TYPE_OFDM = 0, 361 HAL_PKT_TYPE_CCK, 362 HAL_PKT_TYPE_HT, 363 HAL_PKT_TYPE_VHT, 364 HAL_PKT_TYPE_HE, 365 }; 366 367 enum { 368 HAL_SGI_0_8_US, 369 HAL_SGI_0_4_US, 370 HAL_SGI_1_6_US, 371 HAL_SGI_3_2_US, 372 }; 373 374 enum { 375 HAL_FULL_RX_BW_20, 376 HAL_FULL_RX_BW_40, 377 HAL_FULL_RX_BW_80, 378 HAL_FULL_RX_BW_160, 379 }; 380 381 enum { 382 HAL_RX_TYPE_SU, 383 HAL_RX_TYPE_MU_MIMO, 384 HAL_RX_TYPE_MU_OFDMA, 385 HAL_RX_TYPE_MU_OFDMA_MIMO, 386 }; 387 388 /** 389 * enum 390 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 391 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL 392 */ 393 enum { 394 HAL_RX_MON_PPDU_START = 0, 395 HAL_RX_MON_PPDU_END, 396 }; 397 398 /* struct hal_rx_ppdu_common_info - common ppdu info 399 * @ppdu_id - ppdu id number 400 * @ppdu_timestamp - timestamp at ppdu received 401 * @mpdu_cnt_fcs_ok - mpdu count in ppdu with fcs ok 402 * @mpdu_cnt_fcs_err - mpdu count in ppdu with fcs err 403 * @mpdu_fcs_ok_bitmap - fcs ok mpdu count in ppdu bitmap 404 * @last_ppdu_id - last received ppdu id 405 * @mpdu_cnt - total mpdu count 406 * @num_users - num users 407 */ 408 struct hal_rx_ppdu_common_info { 409 uint32_t ppdu_id; 410 uint32_t ppdu_timestamp; 411 uint32_t mpdu_cnt_fcs_ok; 412 uint32_t mpdu_cnt_fcs_err; 413 uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 414 uint32_t last_ppdu_id; 415 uint32_t mpdu_cnt; 416 uint8_t num_users; 417 }; 418 419 /** 420 * struct hal_rx_msdu_payload_info - msdu payload info 421 * @first_msdu_payload: pointer to first msdu payload 422 * @payload_len: payload len 423 * @nbuf: status network buffer to which msdu belongs to 424 */ 425 struct hal_rx_msdu_payload_info { 426 uint8_t *first_msdu_payload; 427 uint32_t payload_len; 428 qdf_nbuf_t nbuf; 429 }; 430 431 /** 432 * struct hal_rx_nac_info - struct for neighbour info 433 * @fc_valid: flag indicate if it has valid frame control information 434 * @frame_control: frame control from each MPDU 435 * @to_ds_flag: flag indicate to_ds bit 436 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 437 * @mac_addr2: mac address2 in wh 438 * @mcast_bcast: multicast/broadcast 439 */ 440 struct hal_rx_nac_info { 441 uint8_t fc_valid; 442 uint16_t frame_control; 443 uint8_t to_ds_flag; 444 uint8_t mac_addr2_valid; 445 uint8_t mac_addr2[QDF_MAC_ADDR_SIZE]; 446 uint8_t mcast_bcast; 447 }; 448 449 /** 450 * struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs 451 * @cce_metadata: cached CCE metadata value received in the MSDU_END TLV 452 * @is_flow_idx_timeout: flag to indicate if flow search timeout occurred 453 * @is_flow_idx_invalid: flag to indicate if flow idx is valid or not 454 * @fse_metadata: cached FSE metadata value received in the MSDU END TLV 455 * @flow_idx: flow idx matched in FSE received in the MSDU END TLV 456 */ 457 struct hal_rx_ppdu_msdu_info { 458 uint16_t cce_metadata; 459 bool is_flow_idx_timeout; 460 bool is_flow_idx_invalid; 461 uint32_t fse_metadata; 462 uint32_t flow_idx; 463 }; 464 465 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 466 /** 467 * struct hal_rx_ppdu_cfr_user_info - struct for storing peer info extracted 468 * from HW TLVs, this will be used for correlating CFR data with multiple peers 469 * in MU PPDUs 470 * 471 * @peer_macaddr: macaddr of the peer 472 * @ast_index: AST index of the peer 473 */ 474 struct hal_rx_ppdu_cfr_user_info { 475 uint8_t peer_macaddr[QDF_MAC_ADDR_SIZE]; 476 uint32_t ast_index; 477 }; 478 479 /** 480 * struct hal_rx_ppdu_cfr_info - struct for storing ppdu info extracted from HW 481 * TLVs, this will be used for CFR correlation 482 * 483 * @bb_captured_channel : Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 484 * sent to PHY, SW checks it to correlate current PPDU TLVs with uploaded 485 * channel information. 486 * 487 * @bb_captured_timeout : Set by RxPCU to indicate channel capture condition is 488 * met, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due to AST delay, 489 * which means the rx_frame_falling edge to FREEZE TLV ready time exceeds 490 * the threshold time defined by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 491 * Bb_captured_reason is still valid in this case. 492 * 493 * @rx_location_info_valid: Indicates whether CFR DMA address in the PPDU TLV 494 * is valid 495 * <enum 0 rx_location_info_is_not_valid> 496 * <enum 1 rx_location_info_is_valid> 497 * <legal all> 498 * 499 * @bb_captured_reason : Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL 500 * TLV to here for FW usage. Valid when bb_captured_channel or 501 * bb_captured_timeout is set. 502 * <enum 0 freeze_reason_TM> 503 * <enum 1 freeze_reason_FTM> 504 * <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 505 * <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 506 * <enum 4 freeze_reason_NDPA_NDP> 507 * <enum 5 freeze_reason_ALL_PACKET> 508 * <legal 0-5> 509 * 510 * @rtt_che_buffer_pointer_low32 : The low 32 bits of the 40 bits pointer to 511 * external RTT channel information buffer 512 * 513 * @rtt_che_buffer_pointer_high8 : The high 8 bits of the 40 bits pointer to 514 * external RTT channel information buffer 515 * 516 * @chan_capture_status : capture status reported by ucode 517 * a. CAPTURE_IDLE: FW has disabled "REPETITIVE_CHE_CAPTURE_CTRL" 518 * b. CAPTURE_BUSY: previous PPDU’s channel capture upload DMA ongoing. (Note 519 * that this upload is triggered after receiving freeze_channel_capture TLV 520 * after last PPDU is rx) 521 * c. CAPTURE_ACTIVE: channel capture is enabled and no previous channel 522 * capture ongoing 523 * d. CAPTURE_NO_BUFFER: next buffer in IPC ring not available 524 * 525 * @cfr_user_info: Peer mac for upto 4 MU users 526 */ 527 528 struct hal_rx_ppdu_cfr_info { 529 bool bb_captured_channel; 530 bool bb_captured_timeout; 531 uint8_t bb_captured_reason; 532 bool rx_location_info_valid; 533 uint8_t chan_capture_status; 534 uint8_t rtt_che_buffer_pointer_high8; 535 uint32_t rtt_che_buffer_pointer_low32; 536 struct hal_rx_ppdu_cfr_user_info cfr_user_info[HAL_MAX_UL_MU_USERS]; 537 }; 538 #else 539 struct hal_rx_ppdu_cfr_info {}; 540 #endif 541 542 struct mon_rx_info { 543 uint8_t qos_control_info_valid; 544 uint16_t qos_control; 545 uint8_t mac_addr1_valid; 546 uint8_t mac_addr1[QDF_MAC_ADDR_SIZE]; 547 }; 548 549 struct mon_rx_user_info { 550 uint16_t qos_control; 551 uint8_t qos_control_info_valid; 552 uint32_t bar_frame:1; 553 }; 554 555 struct hal_rx_ppdu_info { 556 struct hal_rx_ppdu_common_info com_info; 557 struct mon_rx_status rx_status; 558 struct mon_rx_user_status rx_user_status[HAL_MAX_UL_MU_USERS]; 559 struct mon_rx_info rx_info; 560 struct mon_rx_user_info rx_user_info[HAL_MAX_UL_MU_USERS]; 561 struct hal_rx_msdu_payload_info msdu_info; 562 struct hal_rx_msdu_payload_info fcs_ok_msdu_info; 563 struct hal_rx_nac_info nac_info; 564 /* status ring PPDU start and end state */ 565 uint32_t rx_state; 566 /* MU user id for status ring TLV */ 567 uint32_t user_id; 568 /* MPDU/MSDU truncated to 128 bytes header start addr in status skb */ 569 unsigned char *data; 570 /* MPDU/MSDU truncated to 128 bytes header real length */ 571 uint32_t hdr_len; 572 /* MPDU FCS error */ 573 bool fcs_err; 574 /* Id to indicate how to process mpdu */ 575 uint8_t sw_frame_group_id; 576 struct hal_rx_ppdu_msdu_info rx_msdu_info[HAL_MAX_UL_MU_USERS]; 577 /* first msdu payload for all mpdus in ppdu */ 578 struct hal_rx_msdu_payload_info ppdu_msdu_info[HAL_RX_MAX_MPDU]; 579 /* evm info */ 580 struct hal_rx_su_evm_info evm_info; 581 /** 582 * Will be used to store ppdu info extracted from HW TLVs, 583 * and for CFR correlation as well 584 */ 585 struct hal_rx_ppdu_cfr_info cfr_info; 586 }; 587 588 static inline uint32_t 589 hal_get_rx_status_buf_size(void) { 590 /* RX status buffer size is hard coded for now */ 591 return 2048; 592 } 593 594 static inline uint8_t* 595 hal_rx_status_get_next_tlv(uint8_t *rx_tlv) { 596 uint32_t tlv_len, tlv_tag; 597 598 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 599 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 600 601 /* The actual length of PPDU_END is the combined length of many PHY 602 * TLVs that follow. Skip the TLV header and 603 * rx_rxpcu_classification_overview that follows the header to get to 604 * next TLV. 605 */ 606 if (tlv_tag == WIFIRX_PPDU_END_E) 607 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 608 609 return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len + 610 HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3))); 611 } 612 613 /** 614 * hal_rx_proc_phyrx_other_receive_info_tlv() 615 * - process other receive info TLV 616 * @rx_tlv_hdr: pointer to TLV header 617 * @ppdu_info: pointer to ppdu_info 618 * 619 * Return: None 620 */ 621 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 622 void *rx_tlv_hdr, 623 struct hal_rx_ppdu_info 624 *ppdu_info) 625 { 626 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 627 (void *)ppdu_info); 628 } 629 630 /** 631 * hal_rx_status_get_tlv_info() - process receive info TLV 632 * @rx_tlv_hdr: pointer to TLV header 633 * @ppdu_info: pointer to ppdu_info 634 * @hal_soc: HAL soc handle 635 * @nbuf: PPDU status netowrk buffer 636 * 637 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 638 */ 639 static inline uint32_t 640 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 641 hal_soc_handle_t hal_soc_hdl, 642 qdf_nbuf_t nbuf) 643 { 644 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 645 646 return hal_soc->ops->hal_rx_status_get_tlv_info( 647 rx_tlv_hdr, 648 ppdu_info, 649 hal_soc_hdl, 650 nbuf); 651 } 652 653 static inline 654 uint32_t hal_get_rx_status_done_tlv_size(hal_soc_handle_t hal_soc_hdl) 655 { 656 return HAL_RX_TLV32_HDR_SIZE; 657 } 658 659 static inline QDF_STATUS 660 hal_get_rx_status_done(uint8_t *rx_tlv) 661 { 662 uint32_t tlv_tag; 663 664 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 665 666 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 667 return QDF_STATUS_SUCCESS; 668 else 669 return QDF_STATUS_E_EMPTY; 670 } 671 672 static inline QDF_STATUS 673 hal_clear_rx_status_done(uint8_t *rx_tlv) 674 { 675 *(uint32_t *)rx_tlv = 0; 676 return QDF_STATUS_SUCCESS; 677 } 678 679 #endif 680