1 /* 2 * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_API_MON_H_ 21 #define _HAL_API_MON_H_ 22 23 #include "qdf_types.h" 24 #include "hal_internal.h" 25 #include "hal_rx.h" 26 #include "hal_hw_headers.h" 27 #include <target_type.h> 28 29 #define HAL_RX_PHY_DATA_RADAR 0x01 30 #define HAL_SU_MU_CODING_LDPC 0x01 31 32 #define HAL_RX_FCS_LEN (4) 33 #define KEY_EXTIV 0x20 34 35 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 36 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 37 38 #define HAL_RX_TLV32_HDR_SIZE 4 39 40 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 41 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 42 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 43 HAL_RX_USER_TLV32_TYPE_LSB) 44 45 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 46 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 47 HAL_RX_USER_TLV32_LEN_MASK) >> \ 48 HAL_RX_USER_TLV32_LEN_LSB) 49 50 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 51 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 52 HAL_RX_USER_TLV32_USERID_MASK) >> \ 53 HAL_RX_USER_TLV32_USERID_LSB) 54 55 #define HAL_RX_TLV64_HDR_SIZE 8 56 57 #define HAL_RX_GET_USER_TLV64_TYPE(rx_status_tlv_ptr) \ 58 ((*((uint64_t *)(rx_status_tlv_ptr)) & \ 59 HAL_RX_USER_TLV64_TYPE_MASK) >> \ 60 HAL_RX_USER_TLV64_TYPE_LSB) 61 62 #define HAL_RX_GET_USER_TLV64_LEN(rx_status_tlv_ptr) \ 63 ((*((uint64_t *)(rx_status_tlv_ptr)) & \ 64 HAL_RX_USER_TLV64_LEN_MASK) >> \ 65 HAL_RX_USER_TLV64_LEN_LSB) 66 67 #define HAL_RX_GET_USER_TLV64_USERID(rx_status_tlv_ptr) \ 68 ((*((uint64_t *)(rx_status_tlv_ptr)) & \ 69 HAL_RX_USER_TLV64_USERID_MASK) >> \ 70 HAL_RX_USER_TLV64_USERID_LSB) 71 72 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 73 #define HAL_TLV_STATUS_PPDU_DONE 1 74 #define HAL_TLV_STATUS_BUF_DONE 2 75 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 76 #define HAL_TLV_STATUS_PPDU_START 4 77 #define HAL_TLV_STATUS_HEADER 5 78 #define HAL_TLV_STATUS_MPDU_END 6 79 #define HAL_TLV_STATUS_MSDU_START 7 80 #define HAL_TLV_STATUS_MSDU_END 8 81 #define HAL_TLV_STATUS_MON_BUF_ADDR 9 82 #define HAL_TLV_STATUS_MPDU_START 10 83 84 #define HAL_MAX_UL_MU_USERS 37 85 86 #define HAL_RX_PKT_TYPE_11A 0 87 #define HAL_RX_PKT_TYPE_11B 1 88 #define HAL_RX_PKT_TYPE_11N 2 89 #define HAL_RX_PKT_TYPE_11AC 3 90 #define HAL_RX_PKT_TYPE_11AX 4 91 #ifdef WLAN_FEATURE_11BE 92 #define HAL_RX_PKT_TYPE_11BE 6 93 #endif 94 95 #define HAL_RX_RECEPTION_TYPE_SU 0 96 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 97 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 98 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 99 100 /* Multiply rate by 2 to avoid float point 101 * and get rate in units of 500kbps 102 */ 103 #define HAL_11B_RATE_0MCS 11*2 104 #define HAL_11B_RATE_1MCS 5.5*2 105 #define HAL_11B_RATE_2MCS 2*2 106 #define HAL_11B_RATE_3MCS 1*2 107 #define HAL_11B_RATE_4MCS 11*2 108 #define HAL_11B_RATE_5MCS 5.5*2 109 #define HAL_11B_RATE_6MCS 2*2 110 111 #define HAL_11A_RATE_0MCS 48*2 112 #define HAL_11A_RATE_1MCS 24*2 113 #define HAL_11A_RATE_2MCS 12*2 114 #define HAL_11A_RATE_3MCS 6*2 115 #define HAL_11A_RATE_4MCS 54*2 116 #define HAL_11A_RATE_5MCS 36*2 117 #define HAL_11A_RATE_6MCS 18*2 118 #define HAL_11A_RATE_7MCS 9*2 119 120 #define HAL_LEGACY_MCS0 0 121 #define HAL_LEGACY_MCS1 1 122 #define HAL_LEGACY_MCS2 2 123 #define HAL_LEGACY_MCS3 3 124 #define HAL_LEGACY_MCS4 4 125 #define HAL_LEGACY_MCS5 5 126 #define HAL_LEGACY_MCS6 6 127 #define HAL_LEGACY_MCS7 7 128 129 #define HE_GI_0_8 0 130 #define HE_GI_0_4 1 131 #define HE_GI_1_6 2 132 #define HE_GI_3_2 3 133 134 #define HE_GI_RADIOTAP_0_8 0 135 #define HE_GI_RADIOTAP_1_6 1 136 #define HE_GI_RADIOTAP_3_2 2 137 #define HE_GI_RADIOTAP_RESERVED 3 138 139 #define HE_LTF_RADIOTAP_UNKNOWN 0 140 #define HE_LTF_RADIOTAP_1_X 1 141 #define HE_LTF_RADIOTAP_2_X 2 142 #define HE_LTF_RADIOTAP_4_X 3 143 144 #define HT_SGI_PRESENT 0x80 145 146 #define HE_LTF_1_X 0 147 #define HE_LTF_2_X 1 148 #define HE_LTF_4_X 2 149 #define HE_LTF_UNKNOWN 3 150 #define VHT_SIG_SU_NSS_MASK 0x7 151 #define HT_SIG_SU_NSS_SHIFT 0x3 152 153 #define HAL_TID_INVALID 31 154 #define HAL_AST_IDX_INVALID 0xFFFF 155 156 #ifdef GET_MSDU_AGGREGATION 157 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 158 {\ 159 struct rx_msdu_end *rx_msdu_end;\ 160 bool first_msdu, last_msdu; \ 161 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 162 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 163 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 164 if (first_msdu && last_msdu)\ 165 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 166 else\ 167 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 168 } \ 169 170 #define HAL_RX_SET_MSDU_AGGREGATION((rs_mpdu), (rs_ppdu))\ 171 {\ 172 if (rs_mpdu->rs_flags & IEEE80211_AMSDU_FLAG)\ 173 rs_ppdu->rs_flags |= IEEE80211_AMSDU_FLAG;\ 174 } \ 175 176 #else 177 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 178 #define HAL_RX_SET_MSDU_AGGREGATION(rs_mpdu, rs_ppdu) 179 #endif 180 181 /* Max MPDUs per status buffer */ 182 #define HAL_RX_MAX_MPDU 256 183 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 184 #define HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER 16 185 186 /* Max pilot count */ 187 #define HAL_RX_MAX_SU_EVM_COUNT 32 188 189 #define HAL_RX_FRAMECTRL_TYPE_MASK 0x0C 190 #define HAL_RX_GET_FRAME_CTRL_TYPE(fc)\ 191 (((fc) & HAL_RX_FRAMECTRL_TYPE_MASK) >> 2) 192 #define HAL_RX_FRAME_CTRL_TYPE_MGMT 0x0 193 #define HAL_RX_FRAME_CTRL_TYPE_CTRL 0x1 194 #define HAL_RX_FRAME_CTRL_TYPE_DATA 0x2 195 196 /** 197 * hal_dl_ul_flag - flag to indicate UL/DL 198 * @dl_ul_flag_is_dl_or_tdls: DL 199 * @dl_ul_flag_is_ul: UL 200 */ 201 enum hal_dl_ul_flag { 202 dl_ul_flag_is_dl_or_tdls, 203 dl_ul_flag_is_ul, 204 }; 205 206 /* 207 * hal_eht_ppdu_sig_cmn_type - PPDU type 208 * @eht_ppdu_sig_tb_or_dl_ofdma: TB/DL_OFDMA PPDU 209 * @eht_ppdu_sig_su: SU PPDU 210 * @eht_ppdu_sig_dl_mu_mimo: DL_MU_MIMO PPDU 211 */ 212 enum hal_eht_ppdu_sig_cmn_type { 213 eht_ppdu_sig_tb_or_dl_ofdma, 214 eht_ppdu_sig_su, 215 eht_ppdu_sig_dl_mu_mimo, 216 }; 217 218 /* 219 * hal_mon_packet_info - packet info 220 * @sw_cookie: 64-bit SW desc virtual address 221 * @dma_length: packet DMA length 222 * @msdu_continuation: msdu continulation in next buffer 223 * @truncated: packet is truncated 224 */ 225 struct hal_mon_packet_info { 226 uint64_t sw_cookie; 227 uint32_t dma_length : 16, 228 msdu_continuation : 1, 229 truncated : 1; 230 }; 231 232 /* 233 * hal_rx_mon_msdu_info - msdu info 234 * @first_buffer: first buffer of msdu 235 * @last_buffer: last buffer of msdu 236 * @first_mpdu: first MPDU 237 * @mpdu_length_err: MPDU length error 238 * @fcs_err: FCS error 239 * @first_msdu: first msdu 240 * @decap_type: decap type 241 * @last_msdu: last msdu 242 * @l3_header_padding: L3 padding header 243 * @stbc: stbc enabled 244 * @sgi: SGI value 245 * @reception_type: reception type 246 * @msdu_index: msdu index 247 * @buffer_len: buffer len 248 * @frag_len: frag len 249 * @msdu_len: msdu len 250 * @user_rssi: user rssi 251 */ 252 struct hal_rx_mon_msdu_info { 253 uint32_t first_buffer : 1, 254 last_buffer : 1, 255 first_mpdu : 1, 256 mpdu_length_err : 1, 257 fcs_err : 1, 258 first_msdu : 1, 259 decap_type : 3, 260 last_msdu : 1, 261 l3_header_padding : 3, 262 stbc : 1, 263 sgi : 2, 264 reception_type : 3, 265 msdu_index : 4; 266 uint16_t buffer_len : 12; 267 uint16_t frag_len : 12; 268 uint16_t msdu_len; 269 int16_t user_rssi; 270 }; 271 272 /* 273 * hal_rx_mon_mpdu_info - MPDU info 274 * @decap_type: decap_type 275 * @mpdu_length_err: MPDU length error 276 * @fcs_err: FCS error 277 * @overflow_err: overflow error 278 * @decrypt_err: decrypt error 279 * @mpdu_start_received: MPDU start received 280 * @full_pkt: Full MPDU received 281 * @first_rx_hdr_rcvd: First rx_hdr received 282 * @truncated: truncated MPDU 283 */ 284 struct hal_rx_mon_mpdu_info { 285 uint32_t decap_type : 8, 286 mpdu_length_err : 1, 287 fcs_err : 1, 288 overflow_err : 1, 289 decrypt_err : 1, 290 mpdu_start_received : 1, 291 full_pkt : 1, 292 first_rx_hdr_rcvd : 1, 293 truncated : 1; 294 }; 295 296 /** 297 * struct hal_rx_mon_desc_info () - HAL Rx Monitor descriptor info 298 * 299 * @ppdu_id: PHY ppdu id 300 * @status_ppdu_id: status PHY ppdu id 301 * @status_buf_count: number of status buffer count 302 * @rxdma_push_reason: rxdma push reason 303 * @rxdma_error_code: rxdma error code 304 * @msdu_cnt: msdu count 305 * @end_of_ppdu: end of ppdu 306 * @link_desc: msdu link descriptor address 307 * @status_buf: for a PPDU, status buffers can span acrosss 308 * multiple buffers, status_buf points to first 309 * status buffer address of PPDU 310 * @drop_ppdu: flag to indicate current destination 311 * ring ppdu drop 312 */ 313 struct hal_rx_mon_desc_info { 314 uint16_t ppdu_id; 315 uint16_t status_ppdu_id; 316 uint8_t status_buf_count; 317 uint8_t rxdma_push_reason; 318 uint8_t rxdma_error_code; 319 uint8_t msdu_count; 320 uint8_t end_of_ppdu; 321 struct hal_buf_info link_desc; 322 struct hal_buf_info status_buf; 323 bool drop_ppdu; 324 }; 325 326 /* 327 * Struct hal_rx_su_evm_info - SU evm info 328 * @number_of_symbols: number of symbols 329 * @nss_count: nss count 330 * @pilot_count: pilot count 331 * @pilot_evm: Array of pilot evm values 332 */ 333 struct hal_rx_su_evm_info { 334 uint32_t number_of_symbols; 335 uint8_t nss_count; 336 uint8_t pilot_count; 337 uint32_t pilot_evm[HAL_RX_MAX_SU_EVM_COUNT]; 338 }; 339 340 enum { 341 DP_PPDU_STATUS_START, 342 DP_PPDU_STATUS_DONE, 343 }; 344 345 static inline QDF_STATUS 346 hal_rx_reo_ent_get_src_link_id(hal_soc_handle_t hal_soc_hdl, 347 hal_rxdma_desc_t rx_desc, 348 uint8_t *src_link_id) 349 { 350 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 351 352 if (!hal_soc || !hal_soc->ops) { 353 hal_err("hal handle is NULL"); 354 QDF_BUG(0); 355 return QDF_STATUS_E_INVAL; 356 } 357 358 if (hal_soc->ops->hal_rx_reo_ent_get_src_link_id) 359 return hal_soc->ops->hal_rx_reo_ent_get_src_link_id(rx_desc, 360 src_link_id); 361 362 return QDF_STATUS_E_INVAL; 363 } 364 365 /** 366 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 367 * cookie from the REO entrance ring element 368 * @hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 369 * the current descriptor 370 * @ buf_info: structure to return the buffer information 371 * @ msdu_cnt: pointer to msdu count in MPDU 372 * 373 * CAUTION: This API calls a hal_soc ops, so be careful before calling this in 374 * per packet path 375 * 376 * Return: void 377 */ 378 static inline 379 void hal_rx_reo_ent_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 380 hal_rxdma_desc_t rx_desc, 381 struct hal_buf_info *buf_info, 382 uint32_t *msdu_cnt) 383 { 384 struct reo_entrance_ring *reo_ent_ring = 385 (struct reo_entrance_ring *)rx_desc; 386 struct buffer_addr_info *buf_addr_info; 387 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 388 uint32_t loop_cnt; 389 390 rx_mpdu_desc_info_details = 391 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 392 393 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 394 HAL_RX_MPDU_DESC_INFO, MSDU_COUNT); 395 396 loop_cnt = HAL_RX_GET(reo_ent_ring, HAL_REO_ENTRANCE_RING, 397 LOOPING_COUNT); 398 399 buf_addr_info = 400 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 401 402 hal_rx_buf_cookie_rbm_get(hal_soc_hdl, (uint32_t *)buf_addr_info, 403 buf_info); 404 buf_info->paddr = 405 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 406 ((uint64_t) 407 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 408 409 dp_nofl_debug("[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 410 __func__, __LINE__, reo_ent_ring, buf_addr_info, 411 (unsigned long long)buf_info->paddr, loop_cnt); 412 } 413 414 static inline 415 void hal_rx_mon_next_link_desc_get(hal_soc_handle_t hal_soc_hdl, 416 void *rx_msdu_link_desc, 417 struct hal_buf_info *buf_info) 418 { 419 struct rx_msdu_link *msdu_link = 420 (struct rx_msdu_link *)rx_msdu_link_desc; 421 struct buffer_addr_info *buf_addr_info; 422 423 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 424 425 hal_rx_buf_cookie_rbm_get(hal_soc_hdl, (uint32_t *)buf_addr_info, 426 buf_info); 427 428 buf_info->paddr = 429 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 430 ((uint64_t) 431 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 432 } 433 434 static inline 435 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 436 { 437 return data; 438 } 439 440 static inline uint32_t 441 hal_rx_tlv_mpdu_len_err_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 442 { 443 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 444 445 if (!hal_soc || !hal_soc->ops) { 446 hal_err("hal handle is NULL"); 447 QDF_BUG(0); 448 return 0; 449 } 450 451 if (hal_soc->ops->hal_rx_tlv_mpdu_len_err_get) 452 return hal_soc->ops->hal_rx_tlv_mpdu_len_err_get(hw_desc_addr); 453 454 return 0; 455 } 456 457 static inline uint32_t 458 hal_rx_tlv_mpdu_fcs_err_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 459 { 460 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 461 462 if (!hal_soc || !hal_soc->ops) { 463 hal_err("hal handle is NULL"); 464 QDF_BUG(0); 465 return 0; 466 } 467 468 if (hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get) 469 return hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get(hw_desc_addr); 470 471 return 0; 472 } 473 474 #ifdef notyet 475 /* 476 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 477 * start TLV of Hardware TLV descriptor 478 * @hw_desc_addr: Hardware descriptor address 479 * 480 * Return: bool: if TLV tag match 481 */ 482 static inline 483 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 484 { 485 struct rx_mon_pkt_tlvs *rx_desc = 486 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 487 uint32_t tlv_tag; 488 489 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 490 491 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 492 } 493 #endif 494 495 /* 496 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV user id in MPDU 497 * start TLV of Hardware TLV descriptor 498 * @hw_desc_addr: Hardware descriptor address 499 * 500 * Return: unit32_t: user id 501 */ 502 static inline uint32_t 503 hal_rx_hw_desc_mpdu_user_id(hal_soc_handle_t hal_soc_hdl, 504 void *hw_desc_addr) 505 { 506 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 507 508 if (!hal_soc || !hal_soc->ops) { 509 hal_err("hal handle is NULL"); 510 QDF_BUG(0); 511 return 0; 512 } 513 514 if (hal_soc->ops->hal_rx_hw_desc_mpdu_user_id) 515 return hal_soc->ops->hal_rx_hw_desc_mpdu_user_id(hw_desc_addr); 516 517 return 0; 518 } 519 520 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 521 522 /** 523 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 524 * 525 * @ soc : HAL version of the SOC pointer 526 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 527 * @ buf_addr_info : void pointer to the buffer_addr_info 528 * 529 * Return: void 530 */ 531 static inline 532 void hal_rx_mon_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 533 void *src_srng_desc, 534 hal_buff_addrinfo_t buf_addr_info) 535 { 536 struct buffer_addr_info *wbm_srng_buffer_addr_info = 537 (struct buffer_addr_info *)src_srng_desc; 538 uint64_t paddr; 539 struct buffer_addr_info *p_buffer_addr_info = 540 (struct buffer_addr_info *)buf_addr_info; 541 542 paddr = 543 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 544 ((uint64_t) 545 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 546 547 dp_nofl_debug("[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 548 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 549 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 550 551 /* Structure copy !!! */ 552 *wbm_srng_buffer_addr_info = 553 *((struct buffer_addr_info *)buf_addr_info); 554 } 555 556 /** 557 * hal_get_rx_msdu_link_desc_size() - Get msdu link descriptor size 558 * 559 * Return: size of rx_msdu_link 560 */ 561 static inline 562 uint32_t hal_get_rx_msdu_link_desc_size(void) 563 { 564 return sizeof(struct rx_msdu_link); 565 } 566 567 enum { 568 HAL_PKT_TYPE_OFDM = 0, 569 HAL_PKT_TYPE_CCK, 570 HAL_PKT_TYPE_HT, 571 HAL_PKT_TYPE_VHT, 572 HAL_PKT_TYPE_HE, 573 }; 574 575 enum { 576 HAL_SGI_0_8_US, 577 HAL_SGI_0_4_US, 578 HAL_SGI_1_6_US, 579 HAL_SGI_3_2_US, 580 }; 581 582 #ifdef WLAN_FEATURE_11BE 583 enum { 584 HAL_FULL_RX_BW_20, 585 HAL_FULL_RX_BW_40, 586 HAL_FULL_RX_BW_80, 587 HAL_FULL_RX_BW_160, 588 HAL_FULL_RX_BW_320, 589 }; 590 #else 591 enum { 592 HAL_FULL_RX_BW_20, 593 HAL_FULL_RX_BW_40, 594 HAL_FULL_RX_BW_80, 595 HAL_FULL_RX_BW_160, 596 }; 597 #endif 598 599 enum { 600 HAL_RX_TYPE_SU, 601 HAL_RX_TYPE_MU_MIMO, 602 HAL_RX_TYPE_MU_OFDMA, 603 HAL_RX_TYPE_MU_OFDMA_MIMO, 604 }; 605 606 enum { 607 HAL_RX_TYPE_DL, 608 HAL_RX_TYPE_UL, 609 }; 610 611 /* 612 * enum 613 * @HAL_RECEPTION_TYPE_SU: Basic SU reception 614 * @HAL_RECEPTION_TYPE_DL_MU_MIMO: DL MU_MIMO reception 615 * @HAL_RECEPTION_TYPE_DL_MU_OFMA: DL MU_OFMA reception 616 * @HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO: DL MU_OFDMA_MIMO reception 617 * @HAL_RECEPTION_TYPE_UL_MU_MIMO: UL MU_MIMO reception 618 * @HAL_RECEPTION_TYPE_UL_MU_OFDMA: UL MU_OFMA reception 619 * @HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO: UL MU_OFDMA_MIMO reception 620 */ 621 enum { 622 HAL_RECEPTION_TYPE_SU, 623 HAL_RECEPTION_TYPE_DL_MU_MIMO, 624 HAL_RECEPTION_TYPE_DL_MU_OFMA, 625 HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO, 626 HAL_RECEPTION_TYPE_UL_MU_MIMO, 627 HAL_RECEPTION_TYPE_UL_MU_OFDMA, 628 HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO 629 }; 630 631 /** 632 * enum 633 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 634 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decoded in HAL 635 * @HAL_RX_MON_PPDU_RESET: Not PPDU start and end TLV 636 */ 637 enum { 638 HAL_RX_MON_PPDU_START = 0, 639 HAL_RX_MON_PPDU_END, 640 HAL_RX_MON_PPDU_RESET, 641 }; 642 643 /* struct hal_rx_ppdu_common_info - common ppdu info 644 * @ppdu_id - ppdu id number 645 * @ppdu_timestamp - timestamp at ppdu received 646 * @mpdu_cnt_fcs_ok - mpdu count in ppdu with fcs ok 647 * @mpdu_cnt_fcs_err - mpdu count in ppdu with fcs err 648 * @mpdu_fcs_ok_bitmap - fcs ok mpdu count in ppdu bitmap 649 * @last_ppdu_id - last received ppdu id 650 * @mpdu_cnt - total mpdu count 651 * @num_users - num users 652 */ 653 struct hal_rx_ppdu_common_info { 654 uint32_t ppdu_id; 655 uint64_t ppdu_timestamp; 656 uint16_t mpdu_cnt_fcs_ok; 657 uint8_t mpdu_cnt_fcs_err; 658 uint8_t num_users; 659 uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 660 uint32_t last_ppdu_id; 661 uint16_t mpdu_cnt; 662 }; 663 664 /** 665 * struct hal_rx_msdu_payload_info - msdu payload info 666 * @first_msdu_payload: pointer to first msdu payload 667 * @payload_len: payload len 668 */ 669 struct hal_rx_msdu_payload_info { 670 uint8_t *first_msdu_payload; 671 uint8_t payload_len; 672 }; 673 674 /** 675 * struct hal_rx_nac_info - struct for neighbour info 676 * @fc_valid: flag indicate if it has valid frame control information 677 * @frame_control: frame control from each MPDU 678 * @to_ds_flag: flag indicate to_ds bit 679 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 680 * @mcast_bcast: multicast/broadcast 681 * @mac_addr2: mac address2 in wh 682 */ 683 struct hal_rx_nac_info { 684 uint32_t fc_valid : 1, 685 frame_control : 16, 686 to_ds_flag : 1, 687 mac_addr2_valid : 1, 688 mcast_bcast : 1; 689 uint8_t mac_addr2[QDF_MAC_ADDR_SIZE]; 690 }; 691 692 /** 693 * struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs 694 * @fse_metadata: cached FSE metadata value received in the MSDU END TLV 695 * @cce_metadata: cached CCE metadata value received in the MSDU_END TLV 696 * @is_flow_idx_timeout: flag to indicate if flow search timeout occurred 697 * @is_flow_idx_invalid: flag to indicate if flow idx is valid or not 698 * @flow_idx: flow idx matched in FSE received in the MSDU END TLV 699 */ 700 struct hal_rx_ppdu_msdu_info { 701 uint32_t fse_metadata; 702 uint32_t cce_metadata : 16, 703 is_flow_idx_timeout : 1, 704 is_flow_idx_invalid : 1; 705 uint32_t flow_idx : 20; 706 }; 707 708 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 709 /** 710 * struct hal_rx_ppdu_cfr_user_info - struct for storing peer info extracted 711 * from HW TLVs, this will be used for correlating CFR data with multiple peers 712 * in MU PPDUs 713 * 714 * @peer_macaddr: macaddr of the peer 715 * @ast_index: AST index of the peer 716 */ 717 struct hal_rx_ppdu_cfr_user_info { 718 uint8_t peer_macaddr[QDF_MAC_ADDR_SIZE]; 719 uint16_t ast_index; 720 }; 721 722 /** 723 * struct hal_rx_ppdu_cfr_info - struct for storing ppdu info extracted from HW 724 * TLVs, this will be used for CFR correlation 725 * 726 * @bb_captured_channel : Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 727 * sent to PHY, SW checks it to correlate current PPDU TLVs with uploaded 728 * channel information. 729 * 730 * @bb_captured_timeout : Set by RxPCU to indicate channel capture condition is 731 * met, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due to AST delay, 732 * which means the rx_frame_falling edge to FREEZE TLV ready time exceeds 733 * the threshold time defined by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 734 * Bb_captured_reason is still valid in this case. 735 * 736 * @rx_location_info_valid: Indicates whether CFR DMA address in the PPDU TLV 737 * is valid 738 * <enum 0 rx_location_info_is_not_valid> 739 * <enum 1 rx_location_info_is_valid> 740 * <legal all> 741 * 742 * @bb_captured_reason : Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL 743 * TLV to here for FW usage. Valid when bb_captured_channel or 744 * bb_captured_timeout is set. 745 * <enum 0 freeze_reason_TM> 746 * <enum 1 freeze_reason_FTM> 747 * <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 748 * <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 749 * <enum 4 freeze_reason_NDPA_NDP> 750 * <enum 5 freeze_reason_ALL_PACKET> 751 * <legal 0-5> 752 * 753 * @rtt_che_buffer_pointer_low32 : The low 32 bits of the 40 bits pointer to 754 * external RTT channel information buffer 755 * 756 * @rtt_che_buffer_pointer_high8 : The high 8 bits of the 40 bits pointer to 757 * external RTT channel information buffer 758 * 759 * @chan_capture_status : capture status reported by ucode 760 * a. CAPTURE_IDLE: FW has disabled "REPETITIVE_CHE_CAPTURE_CTRL" 761 * b. CAPTURE_BUSY: previous PPDU’s channel capture upload DMA ongoing. (Note 762 * that this upload is triggered after receiving freeze_channel_capture TLV 763 * after last PPDU is rx) 764 * c. CAPTURE_ACTIVE: channel capture is enabled and no previous channel 765 * capture ongoing 766 * d. CAPTURE_NO_BUFFER: next buffer in IPC ring not available 767 * 768 * @cfr_user_info: Peer mac for upto 4 MU users 769 * 770 * @rtt_cfo_measurement : raw cfo data extracted from hardware, which is 14 bit 771 * signed number. The first bit used for sign representation and 13 bits for 772 * fractional part. 773 * 774 * @agc_gain_info0: Chain 0 & chain 1 agc gain information reported by PHY 775 * 776 * @agc_gain_info1: Chain 2 & chain 3 agc gain information reported by PHY 777 * 778 * @agc_gain_info2: Chain 4 & chain 5 agc gain information reported by PHY 779 * 780 * @agc_gain_info3: Chain 6 & chain 7 agc gain information reported by PHY 781 * 782 * @rx_start_ts: Rx packet timestamp, the time the first L-STF ADC sample 783 * arrived at Rx antenna. 784 * 785 * @mcs_rate: Indicates the mcs/rate in which packet is received. 786 * If HT, 787 * 0-7: MCS0-MCS7 788 * If VHT, 789 * 0-9: MCS0 to MCS9 790 * If HE, 791 * 0-11: MCS0 to MCS11, 792 * 12-13: 4096QAM, 793 * 14-15: reserved 794 * If Legacy, 795 * 0: 48 Mbps 796 * 1: 24 Mbps 797 * 2: 12 Mbps 798 * 3: 6 Mbps 799 * 4: 54 Mbps 800 * 5: 36 Mbps 801 * 6: 18 Mbps 802 * 7: 9 Mbps 803 * 804 * @gi_type: Indicates the guard interval. 805 * 0: 0.8 us 806 * 1: 0.4 us 807 * 2: 1.6 us 808 * 3: 3.2 us 809 */ 810 struct hal_rx_ppdu_cfr_info { 811 bool bb_captured_channel; 812 bool bb_captured_timeout; 813 uint8_t bb_captured_reason; 814 bool rx_location_info_valid; 815 uint8_t chan_capture_status; 816 uint8_t rtt_che_buffer_pointer_high8; 817 uint32_t rtt_che_buffer_pointer_low32; 818 int16_t rtt_cfo_measurement; 819 uint32_t agc_gain_info0; 820 uint32_t agc_gain_info1; 821 uint32_t agc_gain_info2; 822 uint32_t agc_gain_info3; 823 uint32_t rx_start_ts; 824 uint32_t mcs_rate; 825 uint32_t gi_type; 826 }; 827 #else 828 struct hal_rx_ppdu_cfr_info {}; 829 #endif 830 831 struct mon_rx_info { 832 uint8_t qos_control_info_valid; 833 uint16_t qos_control; 834 uint8_t mac_addr1_valid; 835 uint8_t mac_addr1[QDF_MAC_ADDR_SIZE]; 836 uint16_t user_id; 837 }; 838 839 struct mon_rx_user_info { 840 uint16_t qos_control; 841 uint8_t qos_control_info_valid; 842 }; 843 844 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 845 struct hal_rx_frm_type_info { 846 uint8_t rx_mgmt_cnt; 847 uint8_t rx_ctrl_cnt; 848 uint8_t rx_data_cnt; 849 }; 850 #else 851 struct hal_rx_frm_type_info {}; 852 #endif 853 854 struct hal_mon_usig_cmn { 855 uint32_t phy_version : 3, 856 bw : 3, 857 ul_dl : 1, 858 bss_color : 6, 859 txop : 7, 860 disregard : 5, 861 validate_0 : 1, 862 reserved : 6; 863 }; 864 865 struct hal_mon_usig_tb { 866 uint32_t ppdu_type_comp_mode : 2, 867 validate_1 : 1, 868 spatial_reuse_1 : 4, 869 spatial_reuse_2 : 4, 870 disregard_1 : 5, 871 crc : 4, 872 tail : 6, 873 reserved : 5, 874 rx_integrity_check_passed : 1; 875 }; 876 877 struct hal_mon_usig_mu { 878 uint32_t ppdu_type_comp_mode : 2, 879 validate_1 : 1, 880 punc_ch_info : 5, 881 validate_2 : 1, 882 eht_sig_mcs : 2, 883 num_eht_sig_sym : 5, 884 crc : 4, 885 tail : 6, 886 reserved : 5, 887 rx_integrity_check_passed : 1; 888 }; 889 890 /** 891 * union hal_mon_usig_non_cmn: Version dependent USIG fields 892 * @tb: trigger based frame USIG header 893 * @mu: MU frame USIG header 894 */ 895 union hal_mon_usig_non_cmn { 896 struct hal_mon_usig_tb tb; 897 struct hal_mon_usig_mu mu; 898 }; 899 900 /** 901 * struct hal_mon_usig_hdr: U-SIG header for EHT (and subsequent) frames 902 * @usig_1: USIG common header fields 903 * @usig_2: USIG version dependent fields 904 */ 905 struct hal_mon_usig_hdr { 906 struct hal_mon_usig_cmn usig_1; 907 union hal_mon_usig_non_cmn usig_2; 908 }; 909 910 #define HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_MASK 0x0000000300000000 911 #define HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_LSB 32 912 913 #define HAL_RX_MON_USIG_GET_PPDU_TYPE_N_COMP_MODE(usig_tlv_ptr) \ 914 ((*((uint64_t *)(usig_tlv_ptr)) & \ 915 HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_MASK) >> \ 916 HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_LSB) 917 918 #define HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 919 #define HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_LSB 63 920 921 #define HAL_RX_MON_USIG_GET_RX_INTEGRITY_CHECK_PASSED(usig_tlv_ptr) \ 922 ((*((uint64_t *)(usig_tlv_ptr)) & \ 923 HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_MASK) >> \ 924 HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_LSB) 925 926 /** 927 * enum hal_eht_bw: Reception bandwidth 928 * @HAL_EHT_BW_20: 20Mhz 929 * @HAL_EHT_BW_40: 40Mhz 930 * @HAL_EHT_BW_80: 80Mhz 931 * @HAL_EHT_BW_160: 160Mhz 932 * @HAL_EHT_BW_320_1: 320_1 band 933 * @HAL_EHT_BW_320_2: 320_2 band 934 */ 935 enum hal_eht_bw { 936 HAL_EHT_BW_20 = 0, 937 HAL_EHT_BW_40, 938 HAL_EHT_BW_80, 939 HAL_EHT_BW_160, 940 HAL_EHT_BW_320_1, 941 HAL_EHT_BW_320_2, 942 }; 943 944 struct hal_eht_sig_mu_mimo_user_info { 945 uint32_t sta_id : 11, 946 mcs : 4, 947 coding : 1, 948 spatial_coding : 6, 949 crc : 4; 950 }; 951 952 struct hal_eht_sig_non_mu_mimo_user_info { 953 uint32_t sta_id : 11, 954 mcs : 4, 955 validate : 1, 956 nss : 4, 957 beamformed : 1, 958 coding : 1, 959 crc : 4; 960 }; 961 962 /** 963 * union hal_eht_sig_user_field: User field in EHTSIG 964 * @mu_mimo_usr: MU-MIMO user field information in EHTSIG 965 * @non_mu_mimo_usr: Non MU-MIMO user field information in EHTSIG 966 */ 967 union hal_eht_sig_user_field { 968 struct hal_eht_sig_mu_mimo_user_info mu_mimo_usr; 969 struct hal_eht_sig_non_mu_mimo_user_info non_mu_mimo_usr; 970 }; 971 972 struct hal_eht_sig_ofdma_cmn_eb1 { 973 uint64_t spatial_reuse : 4, 974 gi_ltf : 2, 975 num_ltf_sym : 3, 976 ldpc_extra_sym : 1, 977 pre_fec_pad_factor : 2, 978 pe_disambiguity : 1, 979 disregard : 4, 980 ru_allocation1_1 : 9, 981 ru_allocation1_2 : 9, 982 crc : 4; 983 }; 984 985 struct hal_eht_sig_ofdma_cmn_eb2 { 986 uint64_t ru_allocation2_1 : 9, 987 ru_allocation2_2 : 9, 988 ru_allocation2_3 : 9, 989 ru_allocation2_4 : 9, 990 ru_allocation2_5 : 9, 991 ru_allocation2_6 : 9, 992 crc : 4; 993 }; 994 995 struct hal_eht_sig_cc_usig_overflow { 996 uint32_t spatial_reuse : 4, 997 gi_ltf : 2, 998 num_ltf_sym : 3, 999 ldpc_extra_sym : 1, 1000 pre_fec_pad_factor : 2, 1001 pe_disambiguity : 1, 1002 disregard : 4; 1003 }; 1004 1005 struct hal_eht_sig_non_ofdma_cmn_eb { 1006 uint32_t spatial_reuse : 4, 1007 gi_ltf : 2, 1008 num_ltf_sym : 3, 1009 ldpc_extra_sym : 1, 1010 pre_fec_pad_factor : 2, 1011 pe_disambiguity : 1, 1012 disregard : 4, 1013 num_users : 3; 1014 union hal_eht_sig_user_field user_field; 1015 }; 1016 1017 struct hal_eht_sig_ndp_cmn_eb { 1018 uint32_t spatial_reuse : 4, 1019 gi_ltf : 2, 1020 num_ltf_sym : 3, 1021 nss : 4, 1022 beamformed : 1, 1023 disregard : 2, 1024 crc : 4; 1025 }; 1026 1027 /* Different allowed RU in 11BE */ 1028 #define HAL_EHT_RU_26 0ULL 1029 #define HAL_EHT_RU_52 1ULL 1030 #define HAL_EHT_RU_78 2ULL 1031 #define HAL_EHT_RU_106 3ULL 1032 #define HAL_EHT_RU_132 4ULL 1033 #define HAL_EHT_RU_242 5ULL 1034 #define HAL_EHT_RU_484 6ULL 1035 #define HAL_EHT_RU_726 7ULL 1036 #define HAL_EHT_RU_996 8ULL 1037 #define HAL_EHT_RU_996x2 9ULL 1038 #define HAL_EHT_RU_996x3 10ULL 1039 #define HAL_EHT_RU_996x4 11ULL 1040 #define HAL_EHT_RU_NONE 15ULL 1041 #define HAL_EHT_RU_INVALID 31ULL 1042 /* 1043 * MRUs spanning above 80Mhz 1044 * HAL_EHT_RU_996_484 = HAL_EHT_RU_484 + HAL_EHT_RU_996 + 4 (reserved) 1045 */ 1046 #define HAL_EHT_RU_996_484 18ULL 1047 #define HAL_EHT_RU_996x2_484 28ULL 1048 #define HAL_EHT_RU_996x3_484 40ULL 1049 #define HAL_EHT_RU_996_484_242 23ULL 1050 1051 /** 1052 * enum ieee80211_eht_ru_size: RU type id in EHTSIG radiotap header 1053 * @IEEE80211_EHT_RU_26: RU26 1054 * @IEEE80211_EHT_RU_52: RU52 1055 * @IEEE80211_EHT_RU_106: RU106 1056 * @IEEE80211_EHT_RU_242: RU242 1057 * @IEEE80211_EHT_RU_484: RU484 1058 * @IEEE80211_EHT_RU_996: RU996 1059 * @IEEE80211_EHT_RU_996x2: RU996x2 1060 * @IEEE80211_EHT_RU_996x4: RU996x4 1061 * @IEEE80211_EHT_RU_52_26: RU52+RU26 1062 * @IEEE80211_EHT_RU_106_26: RU106+RU26 1063 * @IEEE80211_EHT_RU_484_242: RU484+RU242 1064 * @IEEE80211_EHT_RU_996_484: RU996+RU484 1065 * @IEEE80211_EHT_RU_996_484_242: RU996+RU484+RU242 1066 * @IEEE80211_EHT_RU_996x2_484: RU996x2 + RU484 1067 * @IEEE80211_EHT_RU_996x3: RU996x3 1068 * @IEEE80211_EHT_RU_996x3_484: RU996x3 + RU484 1069 * @IEEE80211_EHT_RU_INVALID: Invalid/Max RU 1070 */ 1071 enum ieee80211_eht_ru_size { 1072 IEEE80211_EHT_RU_26, 1073 IEEE80211_EHT_RU_52, 1074 IEEE80211_EHT_RU_106, 1075 IEEE80211_EHT_RU_242, 1076 IEEE80211_EHT_RU_484, 1077 IEEE80211_EHT_RU_996, 1078 IEEE80211_EHT_RU_996x2, 1079 IEEE80211_EHT_RU_996x4, 1080 IEEE80211_EHT_RU_52_26, 1081 IEEE80211_EHT_RU_106_26, 1082 IEEE80211_EHT_RU_484_242, 1083 IEEE80211_EHT_RU_996_484, 1084 IEEE80211_EHT_RU_996_484_242, 1085 IEEE80211_EHT_RU_996x2_484, 1086 IEEE80211_EHT_RU_996x3, 1087 IEEE80211_EHT_RU_996x3_484, 1088 IEEE80211_EHT_RU_INVALID, 1089 }; 1090 1091 #define NUM_RU_BITS_PER80 16 1092 #define NUM_RU_BITS_PER20 4 1093 1094 /* Different per_80Mhz band in 320Mhz bandwidth */ 1095 #define HAL_80_0 0 1096 #define HAL_80_1 1 1097 #define HAL_80_2 2 1098 #define HAL_80_3 3 1099 1100 #define HAL_RU_SHIFT(num_80mhz_band, ru_index_per_80) \ 1101 ((NUM_RU_BITS_PER80 * (num_80mhz_band)) + \ 1102 (NUM_RU_BITS_PER20 * (ru_index_per_80))) 1103 1104 /* MRU-996+484 */ 1105 #define HAL_EHT_RU_996_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ 1106 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_1, 0))) 1107 #define HAL_EHT_RU_996_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1108 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_1, 0))) 1109 #define HAL_EHT_RU_996_484_2 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1110 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1))) 1111 #define HAL_EHT_RU_996_484_3 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1112 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0))) 1113 #define HAL_EHT_RU_996_484_4 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ 1114 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_3, 0))) 1115 #define HAL_EHT_RU_996_484_5 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1116 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_3, 0))) 1117 #define HAL_EHT_RU_996_484_6 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1118 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) 1119 #define HAL_EHT_RU_996_484_7 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1120 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) 1121 1122 /* MRU-996x2+484 */ 1123 #define HAL_EHT_RU_996x2_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ 1124 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1125 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1126 #define HAL_EHT_RU_996x2_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1127 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1128 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1129 #define HAL_EHT_RU_996x2_484_2 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1130 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ 1131 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1132 #define HAL_EHT_RU_996x2_484_3 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1133 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1134 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1135 #define HAL_EHT_RU_996x2_484_4 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1136 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1137 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1))) 1138 #define HAL_EHT_RU_996x2_484_5 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1139 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1140 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0))) 1141 #define HAL_EHT_RU_996x2_484_6 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ 1142 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1143 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1144 #define HAL_EHT_RU_996x2_484_7 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1145 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1146 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1147 #define HAL_EHT_RU_996x2_484_8 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1148 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ 1149 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1150 #define HAL_EHT_RU_996x2_484_9 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1151 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1152 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1153 #define HAL_EHT_RU_996x2_484_10 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1154 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1155 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) 1156 #define HAL_EHT_RU_996x2_484_11 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1157 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1158 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) 1159 1160 /* MRU-996x3+484 */ 1161 #define HAL_EHT_RU_996x3_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ 1162 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1163 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1164 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1165 #define HAL_EHT_RU_996x3_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1166 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1167 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1168 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1169 #define HAL_EHT_RU_996x3_484_2 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1170 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ 1171 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1172 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1173 #define HAL_EHT_RU_996x3_484_3 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1174 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1175 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1176 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1177 #define HAL_EHT_RU_996x3_484_4 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1178 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1179 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ 1180 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1181 #define HAL_EHT_RU_996x3_484_5 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1182 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1183 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1184 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1185 #define HAL_EHT_RU_996x3_484_6 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1186 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1187 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1188 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) 1189 #define HAL_EHT_RU_996x3_484_7 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1190 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1191 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1192 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) 1193 1194 #define HAL_RX_MON_MAX_AGGR_SIZE 128 1195 1196 /** 1197 * struct hal_rx_tlv_aggr_info - Data structure to hold 1198 * metadata for aggregatng repeated TLVs 1199 * @in_progress: Flag to indicate if TLV aggregation is in progress 1200 * @cur_len: Total length of currently aggregated TLV 1201 * @tlv_tag: TLV tag which is currently being aggregated 1202 * @buf: Buffer containing aggregated TLV data 1203 */ 1204 struct hal_rx_tlv_aggr_info { 1205 uint8_t in_progress; 1206 uint16_t cur_len; 1207 uint32_t tlv_tag; 1208 uint8_t buf[HAL_RX_MON_MAX_AGGR_SIZE]; 1209 }; 1210 1211 /* struct hal_rx_u_sig_info - Certain fields from U-SIG header which are used 1212 * for other header field parsing. 1213 * @ul_dl: UL or DL 1214 * @bw: EHT BW 1215 * @ppdu_type_comp_mode: PPDU TYPE 1216 * @eht_sig_mcs: EHT SIG MCS 1217 * @num_eht_sig_sym: Number of EHT SIG symbols 1218 */ 1219 struct hal_rx_u_sig_info { 1220 uint32_t ul_dl : 1, 1221 bw : 3, 1222 ppdu_type_comp_mode : 2, 1223 eht_sig_mcs : 2, 1224 num_eht_sig_sym : 5; 1225 }; 1226 1227 #ifdef WLAN_SUPPORT_CTRL_FRAME_STATS 1228 struct hal_rx_user_ctrl_frm_info { 1229 uint8_t bar : 1, 1230 ndpa : 1; 1231 }; 1232 #else 1233 struct hal_rx_user_ctrl_frm_info {}; 1234 #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */ 1235 1236 struct hal_rx_ppdu_info { 1237 struct hal_rx_ppdu_common_info com_info; 1238 struct hal_rx_u_sig_info u_sig_info; 1239 struct mon_rx_status rx_status; 1240 struct mon_rx_user_status rx_user_status[HAL_MAX_UL_MU_USERS]; 1241 struct mon_rx_info rx_info; 1242 struct mon_rx_user_info rx_user_info[HAL_MAX_UL_MU_USERS]; 1243 struct hal_rx_msdu_payload_info msdu_info; 1244 struct hal_rx_msdu_payload_info fcs_ok_msdu_info; 1245 struct hal_rx_nac_info nac_info; 1246 /* status ring PPDU start and end state */ 1247 uint8_t rx_state; 1248 /* MU user id for status ring TLV */ 1249 uint8_t user_id; 1250 /* MPDU/MSDU truncated to 128 bytes header start addr in status skb */ 1251 unsigned char *data; 1252 /* MPDU/MSDU truncated to 128 bytes header real length */ 1253 uint32_t hdr_len; 1254 /* MPDU FCS error */ 1255 bool fcs_err; 1256 /* Id to indicate how to process mpdu */ 1257 uint8_t sw_frame_group_id; 1258 struct hal_rx_ppdu_msdu_info rx_msdu_info[HAL_MAX_UL_MU_USERS]; 1259 /* fcs passed mpdu count in rx monitor status buffer */ 1260 uint8_t fcs_ok_cnt; 1261 /* fcs error mpdu count in rx monitor status buffer */ 1262 uint8_t fcs_err_cnt; 1263 /* MPDU FCS passed */ 1264 bool is_fcs_passed; 1265 /* first msdu payload for all mpdus in rx monitor status buffer */ 1266 struct hal_rx_msdu_payload_info ppdu_msdu_info[HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER]; 1267 /* evm info */ 1268 struct hal_rx_su_evm_info evm_info; 1269 /** 1270 * Will be used to store ppdu info extracted from HW TLVs, 1271 * and for CFR correlation as well 1272 */ 1273 struct hal_rx_ppdu_cfr_info cfr_info; 1274 /* per frame type counts */ 1275 struct hal_rx_frm_type_info frm_type_info; 1276 /* TLV aggregation metadata context */ 1277 struct hal_rx_tlv_aggr_info tlv_aggr; 1278 /* EHT SIG user info */ 1279 uint32_t eht_sig_user_info; 1280 /*per user mpdu count */ 1281 uint8_t mpdu_count[HAL_MAX_UL_MU_USERS]; 1282 /*per user msdu count */ 1283 uint8_t msdu_count[HAL_MAX_UL_MU_USERS]; 1284 /* Placeholder to update per user last processed msdu’s info */ 1285 struct hal_rx_mon_msdu_info msdu[HAL_MAX_UL_MU_USERS]; 1286 /* Placeholder to update per user last processed mpdu’s info */ 1287 struct hal_rx_mon_mpdu_info mpdu_info[HAL_MAX_UL_MU_USERS]; 1288 /* placeholder to hold packet buffer info */ 1289 struct hal_mon_packet_info packet_info; 1290 #ifdef QCA_MONITOR_2_0_SUPPORT 1291 /* per user per MPDU queue */ 1292 qdf_nbuf_queue_t mpdu_q[HAL_MAX_UL_MU_USERS]; 1293 #endif 1294 /* ppdu info list element */ 1295 TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_list_elem; 1296 /* ppdu info free list element */ 1297 TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_free_list_elem; 1298 /* placeholder to track if RX_HDR is received */ 1299 uint8_t rx_hdr_rcvd[HAL_MAX_UL_MU_USERS]; 1300 /* Per user BAR and NDPA bit flag */ 1301 struct hal_rx_user_ctrl_frm_info ctrl_frm_info[HAL_MAX_UL_MU_USERS]; 1302 /* PPDU end user stats count */ 1303 uint8_t end_user_stats_cnt; 1304 /* PPDU start user info count */ 1305 uint8_t start_user_info_cnt; 1306 }; 1307 1308 static inline uint32_t 1309 hal_get_rx_status_buf_size(void) { 1310 /* RX status buffer size is hard coded for now */ 1311 return 2048; 1312 } 1313 1314 static inline uint8_t* 1315 hal_rx_status_get_next_tlv(uint8_t *rx_tlv, bool is_tlv_hdr_64_bit) { 1316 uint32_t tlv_len, tlv_tag, tlv_hdr_size; 1317 1318 if (is_tlv_hdr_64_bit) { 1319 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 1320 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1321 1322 tlv_hdr_size = HAL_RX_TLV64_HDR_SIZE; 1323 } else { 1324 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 1325 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1326 1327 tlv_hdr_size = HAL_RX_TLV32_HDR_SIZE; 1328 } 1329 1330 /* The actual length of PPDU_END is the combined length of many PHY 1331 * TLVs that follow. Skip the TLV header and 1332 * rx_rxpcu_classification_overview that follows the header to get to 1333 * next TLV. 1334 */ 1335 if (tlv_tag == WIFIRX_PPDU_END_E) 1336 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 1337 1338 return (uint8_t *)(uintptr_t)qdf_align((uint64_t)((uintptr_t)rx_tlv + 1339 tlv_len + 1340 tlv_hdr_size), 1341 tlv_hdr_size); 1342 } 1343 1344 /** 1345 * hal_rx_proc_phyrx_other_receive_info_tlv() 1346 * - process other receive info TLV 1347 * @rx_tlv_hdr: pointer to TLV header 1348 * @ppdu_info: pointer to ppdu_info 1349 * 1350 * Return: None 1351 */ 1352 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 1353 void *rx_tlv_hdr, 1354 struct hal_rx_ppdu_info 1355 *ppdu_info) 1356 { 1357 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 1358 (void *)ppdu_info); 1359 } 1360 1361 /** 1362 * hal_rx_status_get_tlv_info() - process receive info TLV 1363 * @rx_tlv_hdr: pointer to TLV header 1364 * @ppdu_info: pointer to ppdu_info 1365 * @hal_soc: HAL soc handle 1366 * @nbuf: PPDU status network buffer 1367 * 1368 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 1369 */ 1370 static inline uint32_t 1371 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 1372 hal_soc_handle_t hal_soc_hdl, 1373 qdf_nbuf_t nbuf) 1374 { 1375 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1376 1377 return hal_soc->ops->hal_rx_status_get_tlv_info( 1378 rx_tlv_hdr, 1379 ppdu_info, 1380 hal_soc_hdl, 1381 nbuf); 1382 } 1383 1384 static inline 1385 uint32_t hal_get_rx_status_done_tlv_size(hal_soc_handle_t hal_soc_hdl) 1386 { 1387 return HAL_RX_TLV32_HDR_SIZE; 1388 } 1389 1390 static inline QDF_STATUS 1391 hal_get_rx_status_done(uint8_t *rx_tlv) 1392 { 1393 uint32_t tlv_tag; 1394 1395 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1396 1397 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 1398 return QDF_STATUS_SUCCESS; 1399 else 1400 return QDF_STATUS_E_EMPTY; 1401 } 1402 1403 static inline QDF_STATUS 1404 hal_clear_rx_status_done(uint8_t *rx_tlv) 1405 { 1406 *(uint32_t *)rx_tlv = 0; 1407 return QDF_STATUS_SUCCESS; 1408 } 1409 #endif 1410