1 /* 2 * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_API_MON_H_ 20 #define _HAL_API_MON_H_ 21 22 #include "qdf_types.h" 23 #include "hal_internal.h" 24 #include <target_type.h> 25 26 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 27 #define HAL_RX_LSB(block, field) block##_##field##_LSB 28 #define HAL_RX_MASk(block, field) block##_##field##_MASK 29 30 #define HAL_RX_GET(_ptr, block, field) \ 31 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 32 HAL_RX_MASk(block, field)) >> \ 33 HAL_RX_LSB(block, field)) 34 35 #define HAL_RX_PHY_DATA_RADAR 0x01 36 #define HAL_SU_MU_CODING_LDPC 0x01 37 38 #define HAL_RX_FCS_LEN (4) 39 #define KEY_EXTIV 0x20 40 41 #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000 42 #define HAL_RX_USER_TLV32_TYPE_LSB 1 43 #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE 44 45 #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000 46 #define HAL_RX_USER_TLV32_LEN_LSB 10 47 #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00 48 49 #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000 50 #define HAL_RX_USER_TLV32_USERID_LSB 26 51 #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000 52 53 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 54 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 55 56 #define HAL_RX_TLV32_HDR_SIZE 4 57 58 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 59 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 60 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 61 HAL_RX_USER_TLV32_TYPE_LSB) 62 63 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 64 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 65 HAL_RX_USER_TLV32_LEN_MASK) >> \ 66 HAL_RX_USER_TLV32_LEN_LSB) 67 68 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 69 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 70 HAL_RX_USER_TLV32_USERID_MASK) >> \ 71 HAL_RX_USER_TLV32_USERID_LSB) 72 73 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 74 #define HAL_TLV_STATUS_PPDU_DONE 1 75 #define HAL_TLV_STATUS_BUF_DONE 2 76 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 77 78 79 #define HAL_MAX_UL_MU_USERS 8 80 81 #define HAL_RX_PKT_TYPE_11A 0 82 #define HAL_RX_PKT_TYPE_11B 1 83 #define HAL_RX_PKT_TYPE_11N 2 84 #define HAL_RX_PKT_TYPE_11AC 3 85 #define HAL_RX_PKT_TYPE_11AX 4 86 87 #define HAL_RX_RECEPTION_TYPE_SU 0 88 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 89 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 90 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 91 92 /* Multiply rate by 2 to avoid float point 93 * and get rate in units of 500kbps 94 */ 95 #define HAL_11B_RATE_0MCS 11*2 96 #define HAL_11B_RATE_1MCS 5.5*2 97 #define HAL_11B_RATE_2MCS 2*2 98 #define HAL_11B_RATE_3MCS 1*2 99 #define HAL_11B_RATE_4MCS 11*2 100 #define HAL_11B_RATE_5MCS 5.5*2 101 #define HAL_11B_RATE_6MCS 2*2 102 103 #define HAL_11A_RATE_0MCS 48*2 104 #define HAL_11A_RATE_1MCS 24*2 105 #define HAL_11A_RATE_2MCS 12*2 106 #define HAL_11A_RATE_3MCS 6*2 107 #define HAL_11A_RATE_4MCS 54*2 108 #define HAL_11A_RATE_5MCS 36*2 109 #define HAL_11A_RATE_6MCS 18*2 110 #define HAL_11A_RATE_7MCS 9*2 111 112 #define HAL_LEGACY_MCS0 0 113 #define HAL_LEGACY_MCS1 1 114 #define HAL_LEGACY_MCS2 2 115 #define HAL_LEGACY_MCS3 3 116 #define HAL_LEGACY_MCS4 4 117 #define HAL_LEGACY_MCS5 5 118 #define HAL_LEGACY_MCS6 6 119 #define HAL_LEGACY_MCS7 7 120 121 #define HE_GI_0_8 0 122 #define HE_GI_0_4 1 123 #define HE_GI_1_6 2 124 #define HE_GI_3_2 3 125 126 #define HT_SGI_PRESENT 0x80 127 128 #define HE_LTF_1_X 0 129 #define HE_LTF_2_X 1 130 #define HE_LTF_4_X 2 131 #define VHT_SIG_SU_NSS_MASK 0x7 132 133 #define HAL_TID_INVALID 31 134 #define HAL_AST_IDX_INVALID 0xFFFF 135 136 #ifdef GET_MSDU_AGGREGATION 137 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 138 {\ 139 struct rx_msdu_end *rx_msdu_end;\ 140 bool first_msdu, last_msdu; \ 141 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 142 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 143 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 144 if (first_msdu && last_msdu)\ 145 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 146 else\ 147 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 148 } \ 149 150 #else 151 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 152 #endif 153 154 #define HAL_MAC_ADDR_LEN 6 155 156 enum { 157 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 158 HAL_HW_RX_DECAP_FORMAT_NWIFI, 159 HAL_HW_RX_DECAP_FORMAT_ETH2, 160 HAL_HW_RX_DECAP_FORMAT_8023, 161 }; 162 163 enum { 164 DP_PPDU_STATUS_START, 165 DP_PPDU_STATUS_DONE, 166 }; 167 168 static inline 169 uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void) 170 { 171 /* return the HW_RX_DESC size */ 172 return sizeof(struct rx_pkt_tlvs); 173 } 174 175 static inline 176 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 177 { 178 return data; 179 } 180 181 static inline 182 uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr) 183 { 184 struct rx_attention *rx_attn; 185 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 186 187 rx_attn = &rx_desc->attn_tlv.rx_attn; 188 189 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 190 } 191 192 static inline 193 uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr) 194 { 195 struct rx_attention *rx_attn; 196 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 197 198 rx_attn = &rx_desc->attn_tlv.rx_attn; 199 200 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 201 } 202 203 static inline 204 uint32_t 205 HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) { 206 struct rx_msdu_start *rx_msdu_start; 207 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 208 209 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 210 211 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 212 } 213 214 static inline 215 uint8_t * 216 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 217 uint8_t *rx_pkt_hdr; 218 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 219 220 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 221 222 return rx_pkt_hdr; 223 } 224 225 /* 226 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 227 * start TLV of Hardware TLV descriptor 228 * @hw_desc_addr: Hardware desciptor address 229 * 230 * Return: bool: if TLV tag match 231 */ 232 static inline 233 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 234 { 235 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 236 uint32_t tlv_tag; 237 238 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 239 &rx_desc->mpdu_start_tlv); 240 241 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 242 } 243 244 static inline 245 uint32_t HAL_RX_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr) 246 { 247 struct rx_mpdu_info *rx_mpdu_info; 248 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 249 250 rx_mpdu_info = 251 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 252 253 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 254 } 255 256 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 257 static inline 258 uint32_t hal_rx_desc_is_first_msdu(void *hw_desc_addr) 259 { 260 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 261 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 262 263 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 264 } 265 266 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 267 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 268 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 269 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 270 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 271 272 #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \ 273 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 274 (((struct reo_entrance_ring *)reo_ent_desc) \ 275 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 276 277 #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \ 278 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 279 (((struct reo_entrance_ring *)reo_ent_desc) \ 280 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 281 282 #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \ 283 (HAL_RX_BUF_COOKIE_GET(& \ 284 (((struct reo_entrance_ring *)reo_ent_desc) \ 285 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 286 287 /** 288 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 289 * cookie from the REO entrance ring element 290 * 291 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 292 * the current descriptor 293 * @ buf_info: structure to return the buffer information 294 * @ msdu_cnt: pointer to msdu count in MPDU 295 * Return: void 296 */ 297 static inline 298 void hal_rx_reo_ent_buf_paddr_get(void *rx_desc, 299 struct hal_buf_info *buf_info, 300 void **pp_buf_addr_info, 301 uint32_t *msdu_cnt 302 ) 303 { 304 struct reo_entrance_ring *reo_ent_ring = 305 (struct reo_entrance_ring *)rx_desc; 306 struct buffer_addr_info *buf_addr_info; 307 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 308 uint32_t loop_cnt; 309 310 rx_mpdu_desc_info_details = 311 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 312 313 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 314 RX_MPDU_DESC_INFO_0, MSDU_COUNT); 315 316 loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT); 317 318 buf_addr_info = 319 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 320 321 buf_info->paddr = 322 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 323 ((uint64_t) 324 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 325 326 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 327 328 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 329 "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 330 __func__, __LINE__, reo_ent_ring, buf_addr_info, 331 (unsigned long long)buf_info->paddr, loop_cnt); 332 333 *pp_buf_addr_info = (void *)buf_addr_info; 334 } 335 336 static inline 337 void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 338 struct hal_buf_info *buf_info, void **pp_buf_addr_info) 339 { 340 struct rx_msdu_link *msdu_link = 341 (struct rx_msdu_link *)rx_msdu_link_desc; 342 struct buffer_addr_info *buf_addr_info; 343 344 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 345 346 buf_info->paddr = 347 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 348 ((uint64_t) 349 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 350 351 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 352 353 *pp_buf_addr_info = (void *)buf_addr_info; 354 } 355 356 /** 357 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 358 * 359 * @ soc : HAL version of the SOC pointer 360 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 361 * @ buf_addr_info : void pointer to the buffer_addr_info 362 * 363 * Return: void 364 */ 365 366 static inline void hal_rx_mon_msdu_link_desc_set(struct hal_soc *soc, 367 void *src_srng_desc, void *buf_addr_info) 368 { 369 struct buffer_addr_info *wbm_srng_buffer_addr_info = 370 (struct buffer_addr_info *)src_srng_desc; 371 uint64_t paddr; 372 struct buffer_addr_info *p_buffer_addr_info = 373 (struct buffer_addr_info *)buf_addr_info; 374 375 paddr = 376 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 377 ((uint64_t) 378 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 379 380 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 381 "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 382 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 383 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 384 385 /* Structure copy !!! */ 386 *wbm_srng_buffer_addr_info = 387 *((struct buffer_addr_info *)buf_addr_info); 388 } 389 390 static inline 391 uint32 hal_get_rx_msdu_link_desc_size(void) 392 { 393 return sizeof(struct rx_msdu_link); 394 } 395 396 enum { 397 HAL_PKT_TYPE_OFDM = 0, 398 HAL_PKT_TYPE_CCK, 399 HAL_PKT_TYPE_HT, 400 HAL_PKT_TYPE_VHT, 401 HAL_PKT_TYPE_HE, 402 }; 403 404 enum { 405 HAL_SGI_0_8_US, 406 HAL_SGI_0_4_US, 407 HAL_SGI_1_6_US, 408 HAL_SGI_3_2_US, 409 }; 410 411 enum { 412 HAL_FULL_RX_BW_20, 413 HAL_FULL_RX_BW_40, 414 HAL_FULL_RX_BW_80, 415 HAL_FULL_RX_BW_160, 416 }; 417 418 enum { 419 HAL_RX_TYPE_SU, 420 HAL_RX_TYPE_MU_MIMO, 421 HAL_RX_TYPE_MU_OFDMA, 422 HAL_RX_TYPE_MU_OFDMA_MIMO, 423 }; 424 425 /** 426 * enum 427 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 428 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL 429 */ 430 enum { 431 HAL_RX_MON_PPDU_START = 0, 432 HAL_RX_MON_PPDU_END, 433 }; 434 435 struct hal_rx_ppdu_user_info { 436 437 }; 438 439 struct hal_rx_ppdu_common_info { 440 uint32_t ppdu_id; 441 uint32_t ppdu_timestamp; 442 uint32_t mpdu_cnt_fcs_ok; 443 uint32_t mpdu_cnt_fcs_err; 444 }; 445 446 struct hal_rx_msdu_payload_info { 447 uint8_t *first_msdu_payload; 448 uint32_t payload_len; 449 }; 450 451 /** 452 * struct hal_rx_nac_info - struct for neighbour info 453 * @fc_valid: flag indicate if it has valid frame control information 454 * @to_ds_flag: flag indicate to_ds bit 455 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 456 * @mac_addr2: mac address2 in wh 457 */ 458 struct hal_rx_nac_info { 459 uint8_t fc_valid; 460 uint8_t to_ds_flag; 461 uint8_t mac_addr2_valid; 462 uint8_t mac_addr2[HAL_MAC_ADDR_LEN]; 463 }; 464 465 struct hal_rx_ppdu_info { 466 struct hal_rx_ppdu_common_info com_info; 467 struct hal_rx_ppdu_user_info user_info[HAL_MAX_UL_MU_USERS]; 468 struct mon_rx_status rx_status; 469 struct hal_rx_msdu_payload_info msdu_info; 470 struct hal_rx_nac_info nac_info; 471 /* status ring PPDU start and end state */ 472 uint32_t rx_state; 473 }; 474 475 static inline uint32_t 476 hal_get_rx_status_buf_size(void) { 477 /* RX status buffer size is hard coded for now */ 478 return 2048; 479 } 480 481 static inline uint8_t* 482 hal_rx_status_get_next_tlv(uint8_t *rx_tlv) { 483 uint32_t tlv_len, tlv_tag; 484 485 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 486 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 487 488 /* The actual length of PPDU_END is the combined length of many PHY 489 * TLVs that follow. Skip the TLV header and 490 * rx_rxpcu_classification_overview that follows the header to get to 491 * next TLV. 492 */ 493 if (tlv_tag == WIFIRX_PPDU_END_E) 494 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 495 496 return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len + 497 HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3))); 498 } 499 500 /** 501 * hal_rx_proc_phyrx_other_receive_info_tlv() 502 * - process other receive info TLV 503 * @rx_tlv_hdr: pointer to TLV header 504 * @ppdu_info: pointer to ppdu_info 505 * 506 * Return: None 507 */ 508 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 509 void *rx_tlv_hdr, 510 struct hal_rx_ppdu_info 511 *ppdu_info) 512 { 513 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 514 (void *)ppdu_info); 515 } 516 517 /** 518 * hal_rx_status_get_tlv_info() - process receive info TLV 519 * @rx_tlv_hdr: pointer to TLV header 520 * @ppdu_info: pointer to ppdu_info 521 * 522 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 523 */ 524 static inline uint32_t 525 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 526 struct hal_soc *hal_soc) 527 { 528 return hal_soc->ops->hal_rx_status_get_tlv_info(rx_tlv_hdr, 529 ppdu_info, hal_soc); 530 } 531 532 static inline 533 uint32_t hal_get_rx_status_done_tlv_size(void *hal_soc) 534 { 535 return HAL_RX_TLV32_HDR_SIZE; 536 } 537 538 static inline QDF_STATUS 539 hal_get_rx_status_done(uint8_t *rx_tlv) 540 { 541 uint32_t tlv_tag; 542 543 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 544 545 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 546 return QDF_STATUS_SUCCESS; 547 else 548 return QDF_STATUS_E_EMPTY; 549 } 550 551 static inline QDF_STATUS 552 hal_clear_rx_status_done(uint8_t *rx_tlv) 553 { 554 *(uint32_t *)rx_tlv = 0; 555 return QDF_STATUS_SUCCESS; 556 } 557 558 #endif 559