1 /* 2 * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_API_MON_H_ 20 #define _HAL_API_MON_H_ 21 22 #include "qdf_types.h" 23 #include "hal_internal.h" 24 #include <target_type.h> 25 26 #define HAL_RX_PHY_DATA_RADAR 0x01 27 #define HAL_SU_MU_CODING_LDPC 0x01 28 29 #define HAL_RX_FCS_LEN (4) 30 #define KEY_EXTIV 0x20 31 32 #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000 33 #define HAL_RX_USER_TLV32_TYPE_LSB 1 34 #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE 35 36 #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000 37 #define HAL_RX_USER_TLV32_LEN_LSB 10 38 #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00 39 40 #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000 41 #define HAL_RX_USER_TLV32_USERID_LSB 26 42 #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000 43 44 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 45 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 46 47 #define HAL_RX_TLV32_HDR_SIZE 4 48 49 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 50 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 51 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 52 HAL_RX_USER_TLV32_TYPE_LSB) 53 54 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 55 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 56 HAL_RX_USER_TLV32_LEN_MASK) >> \ 57 HAL_RX_USER_TLV32_LEN_LSB) 58 59 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 60 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 61 HAL_RX_USER_TLV32_USERID_MASK) >> \ 62 HAL_RX_USER_TLV32_USERID_LSB) 63 64 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 65 #define HAL_TLV_STATUS_PPDU_DONE 1 66 #define HAL_TLV_STATUS_BUF_DONE 2 67 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 68 69 70 #define HAL_MAX_UL_MU_USERS 8 71 72 #define HAL_RX_PKT_TYPE_11A 0 73 #define HAL_RX_PKT_TYPE_11B 1 74 #define HAL_RX_PKT_TYPE_11N 2 75 #define HAL_RX_PKT_TYPE_11AC 3 76 #define HAL_RX_PKT_TYPE_11AX 4 77 78 #define HAL_RX_RECEPTION_TYPE_SU 0 79 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 80 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 81 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 82 83 /* Multiply rate by 2 to avoid float point 84 * and get rate in units of 500kbps 85 */ 86 #define HAL_11B_RATE_0MCS 11*2 87 #define HAL_11B_RATE_1MCS 5.5*2 88 #define HAL_11B_RATE_2MCS 2*2 89 #define HAL_11B_RATE_3MCS 1*2 90 #define HAL_11B_RATE_4MCS 11*2 91 #define HAL_11B_RATE_5MCS 5.5*2 92 #define HAL_11B_RATE_6MCS 2*2 93 94 #define HAL_11A_RATE_0MCS 48*2 95 #define HAL_11A_RATE_1MCS 24*2 96 #define HAL_11A_RATE_2MCS 12*2 97 #define HAL_11A_RATE_3MCS 6*2 98 #define HAL_11A_RATE_4MCS 54*2 99 #define HAL_11A_RATE_5MCS 36*2 100 #define HAL_11A_RATE_6MCS 18*2 101 #define HAL_11A_RATE_7MCS 9*2 102 103 #define HAL_LEGACY_MCS0 0 104 #define HAL_LEGACY_MCS1 1 105 #define HAL_LEGACY_MCS2 2 106 #define HAL_LEGACY_MCS3 3 107 #define HAL_LEGACY_MCS4 4 108 #define HAL_LEGACY_MCS5 5 109 #define HAL_LEGACY_MCS6 6 110 #define HAL_LEGACY_MCS7 7 111 112 #define HE_GI_0_8 0 113 #define HE_GI_0_4 1 114 #define HE_GI_1_6 2 115 #define HE_GI_3_2 3 116 117 #define HT_SGI_PRESENT 0x80 118 119 #define HE_LTF_1_X 1 120 #define HE_LTF_2_X 2 121 #define HE_LTF_4_X 3 122 #define HE_LTF_UNKNOWN 0 123 #define VHT_SIG_SU_NSS_MASK 0x7 124 #define HT_SIG_SU_NSS_SHIFT 0x3 125 126 #define HAL_TID_INVALID 31 127 #define HAL_AST_IDX_INVALID 0xFFFF 128 129 #ifdef GET_MSDU_AGGREGATION 130 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 131 {\ 132 struct rx_msdu_end *rx_msdu_end;\ 133 bool first_msdu, last_msdu; \ 134 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 135 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 136 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 137 if (first_msdu && last_msdu)\ 138 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 139 else\ 140 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 141 } \ 142 143 #else 144 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 145 #endif 146 147 #define HAL_MAC_ADDR_LEN 6 148 149 enum { 150 DP_PPDU_STATUS_START, 151 DP_PPDU_STATUS_DONE, 152 }; 153 154 static inline 155 uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void) 156 { 157 /* return the HW_RX_DESC size */ 158 return sizeof(struct rx_pkt_tlvs); 159 } 160 161 static inline 162 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 163 { 164 return data; 165 } 166 167 static inline 168 uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr) 169 { 170 struct rx_attention *rx_attn; 171 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 172 173 rx_attn = &rx_desc->attn_tlv.rx_attn; 174 175 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 176 } 177 178 static inline 179 uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr) 180 { 181 struct rx_attention *rx_attn; 182 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 183 184 rx_attn = &rx_desc->attn_tlv.rx_attn; 185 186 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 187 } 188 189 /* 190 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 191 * start TLV of Hardware TLV descriptor 192 * @hw_desc_addr: Hardware desciptor address 193 * 194 * Return: bool: if TLV tag match 195 */ 196 static inline 197 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 198 { 199 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 200 uint32_t tlv_tag; 201 202 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 203 &rx_desc->mpdu_start_tlv); 204 205 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 206 } 207 208 static inline 209 uint32_t HAL_RX_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr) 210 { 211 struct rx_mpdu_info *rx_mpdu_info; 212 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 213 214 rx_mpdu_info = 215 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 216 217 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 218 } 219 220 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 221 222 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 223 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 224 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 225 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 226 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 227 228 #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \ 229 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 230 (((struct reo_entrance_ring *)reo_ent_desc) \ 231 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 232 233 #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \ 234 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 235 (((struct reo_entrance_ring *)reo_ent_desc) \ 236 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 237 238 #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \ 239 (HAL_RX_BUF_COOKIE_GET(& \ 240 (((struct reo_entrance_ring *)reo_ent_desc) \ 241 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 242 243 /** 244 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 245 * cookie from the REO entrance ring element 246 * 247 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 248 * the current descriptor 249 * @ buf_info: structure to return the buffer information 250 * @ msdu_cnt: pointer to msdu count in MPDU 251 * Return: void 252 */ 253 static inline 254 void hal_rx_reo_ent_buf_paddr_get(void *rx_desc, 255 struct hal_buf_info *buf_info, 256 void **pp_buf_addr_info, 257 uint32_t *msdu_cnt 258 ) 259 { 260 struct reo_entrance_ring *reo_ent_ring = 261 (struct reo_entrance_ring *)rx_desc; 262 struct buffer_addr_info *buf_addr_info; 263 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 264 uint32_t loop_cnt; 265 266 rx_mpdu_desc_info_details = 267 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 268 269 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 270 RX_MPDU_DESC_INFO_0, MSDU_COUNT); 271 272 loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT); 273 274 buf_addr_info = 275 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 276 277 buf_info->paddr = 278 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 279 ((uint64_t) 280 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 281 282 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 283 284 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 285 "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 286 __func__, __LINE__, reo_ent_ring, buf_addr_info, 287 (unsigned long long)buf_info->paddr, loop_cnt); 288 289 *pp_buf_addr_info = (void *)buf_addr_info; 290 } 291 292 static inline 293 void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 294 struct hal_buf_info *buf_info, void **pp_buf_addr_info) 295 { 296 struct rx_msdu_link *msdu_link = 297 (struct rx_msdu_link *)rx_msdu_link_desc; 298 struct buffer_addr_info *buf_addr_info; 299 300 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 301 302 buf_info->paddr = 303 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 304 ((uint64_t) 305 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 306 307 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 308 309 *pp_buf_addr_info = (void *)buf_addr_info; 310 } 311 312 /** 313 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 314 * 315 * @ soc : HAL version of the SOC pointer 316 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 317 * @ buf_addr_info : void pointer to the buffer_addr_info 318 * 319 * Return: void 320 */ 321 322 static inline void hal_rx_mon_msdu_link_desc_set(struct hal_soc *soc, 323 void *src_srng_desc, void *buf_addr_info) 324 { 325 struct buffer_addr_info *wbm_srng_buffer_addr_info = 326 (struct buffer_addr_info *)src_srng_desc; 327 uint64_t paddr; 328 struct buffer_addr_info *p_buffer_addr_info = 329 (struct buffer_addr_info *)buf_addr_info; 330 331 paddr = 332 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 333 ((uint64_t) 334 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 335 336 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 337 "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 338 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 339 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 340 341 /* Structure copy !!! */ 342 *wbm_srng_buffer_addr_info = 343 *((struct buffer_addr_info *)buf_addr_info); 344 } 345 346 static inline 347 uint32 hal_get_rx_msdu_link_desc_size(void) 348 { 349 return sizeof(struct rx_msdu_link); 350 } 351 352 enum { 353 HAL_PKT_TYPE_OFDM = 0, 354 HAL_PKT_TYPE_CCK, 355 HAL_PKT_TYPE_HT, 356 HAL_PKT_TYPE_VHT, 357 HAL_PKT_TYPE_HE, 358 }; 359 360 enum { 361 HAL_SGI_0_8_US, 362 HAL_SGI_0_4_US, 363 HAL_SGI_1_6_US, 364 HAL_SGI_3_2_US, 365 }; 366 367 enum { 368 HAL_FULL_RX_BW_20, 369 HAL_FULL_RX_BW_40, 370 HAL_FULL_RX_BW_80, 371 HAL_FULL_RX_BW_160, 372 }; 373 374 enum { 375 HAL_RX_TYPE_SU, 376 HAL_RX_TYPE_MU_MIMO, 377 HAL_RX_TYPE_MU_OFDMA, 378 HAL_RX_TYPE_MU_OFDMA_MIMO, 379 }; 380 381 /** 382 * enum 383 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 384 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL 385 */ 386 enum { 387 HAL_RX_MON_PPDU_START = 0, 388 HAL_RX_MON_PPDU_END, 389 }; 390 391 struct hal_rx_ppdu_user_info { 392 393 }; 394 395 struct hal_rx_ppdu_common_info { 396 uint32_t ppdu_id; 397 uint32_t ppdu_timestamp; 398 uint32_t mpdu_cnt_fcs_ok; 399 uint32_t mpdu_cnt_fcs_err; 400 }; 401 402 struct hal_rx_msdu_payload_info { 403 uint8_t *first_msdu_payload; 404 uint32_t payload_len; 405 }; 406 407 /** 408 * struct hal_rx_nac_info - struct for neighbour info 409 * @fc_valid: flag indicate if it has valid frame control information 410 * @to_ds_flag: flag indicate to_ds bit 411 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 412 * @mac_addr2: mac address2 in wh 413 */ 414 struct hal_rx_nac_info { 415 uint8_t fc_valid; 416 uint8_t to_ds_flag; 417 uint8_t mac_addr2_valid; 418 uint8_t mac_addr2[HAL_MAC_ADDR_LEN]; 419 }; 420 421 struct hal_rx_ppdu_info { 422 struct hal_rx_ppdu_common_info com_info; 423 struct hal_rx_ppdu_user_info user_info[HAL_MAX_UL_MU_USERS]; 424 struct mon_rx_status rx_status; 425 struct hal_rx_msdu_payload_info msdu_info; 426 struct hal_rx_nac_info nac_info; 427 /* status ring PPDU start and end state */ 428 uint32_t rx_state; 429 }; 430 431 static inline uint32_t 432 hal_get_rx_status_buf_size(void) { 433 /* RX status buffer size is hard coded for now */ 434 return 2048; 435 } 436 437 static inline uint8_t* 438 hal_rx_status_get_next_tlv(uint8_t *rx_tlv) { 439 uint32_t tlv_len, tlv_tag; 440 441 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 442 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 443 444 /* The actual length of PPDU_END is the combined length of many PHY 445 * TLVs that follow. Skip the TLV header and 446 * rx_rxpcu_classification_overview that follows the header to get to 447 * next TLV. 448 */ 449 if (tlv_tag == WIFIRX_PPDU_END_E) 450 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 451 452 return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len + 453 HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3))); 454 } 455 456 /** 457 * hal_rx_proc_phyrx_other_receive_info_tlv() 458 * - process other receive info TLV 459 * @rx_tlv_hdr: pointer to TLV header 460 * @ppdu_info: pointer to ppdu_info 461 * 462 * Return: None 463 */ 464 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 465 void *rx_tlv_hdr, 466 struct hal_rx_ppdu_info 467 *ppdu_info) 468 { 469 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 470 (void *)ppdu_info); 471 } 472 473 /** 474 * hal_rx_status_get_tlv_info() - process receive info TLV 475 * @rx_tlv_hdr: pointer to TLV header 476 * @ppdu_info: pointer to ppdu_info 477 * 478 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 479 */ 480 static inline uint32_t 481 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 482 struct hal_soc *hal_soc) 483 { 484 return hal_soc->ops->hal_rx_status_get_tlv_info(rx_tlv_hdr, 485 ppdu_info, hal_soc); 486 } 487 488 static inline 489 uint32_t hal_get_rx_status_done_tlv_size(void *hal_soc) 490 { 491 return HAL_RX_TLV32_HDR_SIZE; 492 } 493 494 static inline QDF_STATUS 495 hal_get_rx_status_done(uint8_t *rx_tlv) 496 { 497 uint32_t tlv_tag; 498 499 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 500 501 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 502 return QDF_STATUS_SUCCESS; 503 else 504 return QDF_STATUS_E_EMPTY; 505 } 506 507 static inline QDF_STATUS 508 hal_clear_rx_status_done(uint8_t *rx_tlv) 509 { 510 *(uint32_t *)rx_tlv = 0; 511 return QDF_STATUS_SUCCESS; 512 } 513 514 #endif 515