1 /* 2 * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_API_MON_H_ 20 #define _HAL_API_MON_H_ 21 22 #include "qdf_types.h" 23 #include "hal_internal.h" 24 #include <target_type.h> 25 26 #define HAL_RX_PHY_DATA_RADAR 0x01 27 #define HAL_SU_MU_CODING_LDPC 0x01 28 29 #define HAL_RX_FCS_LEN (4) 30 #define KEY_EXTIV 0x20 31 32 #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000 33 #define HAL_RX_USER_TLV32_TYPE_LSB 1 34 #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE 35 36 #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000 37 #define HAL_RX_USER_TLV32_LEN_LSB 10 38 #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00 39 40 #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000 41 #define HAL_RX_USER_TLV32_USERID_LSB 26 42 #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000 43 44 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 45 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 46 47 #define HAL_RX_TLV32_HDR_SIZE 4 48 49 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 50 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 51 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 52 HAL_RX_USER_TLV32_TYPE_LSB) 53 54 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 55 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 56 HAL_RX_USER_TLV32_LEN_MASK) >> \ 57 HAL_RX_USER_TLV32_LEN_LSB) 58 59 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 60 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 61 HAL_RX_USER_TLV32_USERID_MASK) >> \ 62 HAL_RX_USER_TLV32_USERID_LSB) 63 64 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 65 #define HAL_TLV_STATUS_PPDU_DONE 1 66 #define HAL_TLV_STATUS_BUF_DONE 2 67 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 68 #define HAL_TLV_STATUS_PPDU_START 4 69 #define HAL_TLV_STATUS_HEADER 5 70 #define HAL_TLV_STATUS_MPDU_END 6 71 #define HAL_TLV_STATUS_MSDU_START 7 72 #define HAL_TLV_STATUS_MSDU_END 8 73 74 #define HAL_MAX_UL_MU_USERS 37 75 76 #define HAL_RX_PKT_TYPE_11A 0 77 #define HAL_RX_PKT_TYPE_11B 1 78 #define HAL_RX_PKT_TYPE_11N 2 79 #define HAL_RX_PKT_TYPE_11AC 3 80 #define HAL_RX_PKT_TYPE_11AX 4 81 82 #define HAL_RX_RECEPTION_TYPE_SU 0 83 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 84 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 85 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 86 87 /* Multiply rate by 2 to avoid float point 88 * and get rate in units of 500kbps 89 */ 90 #define HAL_11B_RATE_0MCS 11*2 91 #define HAL_11B_RATE_1MCS 5.5*2 92 #define HAL_11B_RATE_2MCS 2*2 93 #define HAL_11B_RATE_3MCS 1*2 94 #define HAL_11B_RATE_4MCS 11*2 95 #define HAL_11B_RATE_5MCS 5.5*2 96 #define HAL_11B_RATE_6MCS 2*2 97 98 #define HAL_11A_RATE_0MCS 48*2 99 #define HAL_11A_RATE_1MCS 24*2 100 #define HAL_11A_RATE_2MCS 12*2 101 #define HAL_11A_RATE_3MCS 6*2 102 #define HAL_11A_RATE_4MCS 54*2 103 #define HAL_11A_RATE_5MCS 36*2 104 #define HAL_11A_RATE_6MCS 18*2 105 #define HAL_11A_RATE_7MCS 9*2 106 107 #define HAL_LEGACY_MCS0 0 108 #define HAL_LEGACY_MCS1 1 109 #define HAL_LEGACY_MCS2 2 110 #define HAL_LEGACY_MCS3 3 111 #define HAL_LEGACY_MCS4 4 112 #define HAL_LEGACY_MCS5 5 113 #define HAL_LEGACY_MCS6 6 114 #define HAL_LEGACY_MCS7 7 115 116 #define HE_GI_0_8 0 117 #define HE_GI_0_4 1 118 #define HE_GI_1_6 2 119 #define HE_GI_3_2 3 120 121 #define HT_SGI_PRESENT 0x80 122 123 #define HE_LTF_1_X 0 124 #define HE_LTF_2_X 1 125 #define HE_LTF_4_X 2 126 #define HE_LTF_UNKNOWN 3 127 #define VHT_SIG_SU_NSS_MASK 0x7 128 #define HT_SIG_SU_NSS_SHIFT 0x3 129 130 #define HAL_TID_INVALID 31 131 #define HAL_AST_IDX_INVALID 0xFFFF 132 133 #ifdef GET_MSDU_AGGREGATION 134 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 135 {\ 136 struct rx_msdu_end *rx_msdu_end;\ 137 bool first_msdu, last_msdu; \ 138 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 139 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 140 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 141 if (first_msdu && last_msdu)\ 142 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 143 else\ 144 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 145 } \ 146 147 #else 148 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 149 #endif 150 151 /* Max MPDUs per status buffer */ 152 #define HAL_RX_MAX_MPDU 256 153 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 154 155 /* Max pilot count */ 156 #define HAL_RX_MAX_SU_EVM_COUNT 32 157 158 /* 159 * Struct hal_rx_su_evm_info - SU evm info 160 * @number_of_symbols: number of symbols 161 * @nss_count: nss count 162 * @pilot_count: pilot count 163 * @pilot_evm: Array of pilot evm values 164 */ 165 struct hal_rx_su_evm_info { 166 uint32_t number_of_symbols; 167 uint8_t nss_count; 168 uint8_t pilot_count; 169 uint32_t pilot_evm[HAL_RX_MAX_SU_EVM_COUNT]; 170 }; 171 172 enum { 173 DP_PPDU_STATUS_START, 174 DP_PPDU_STATUS_DONE, 175 }; 176 177 static inline 178 uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void) 179 { 180 /* return the HW_RX_DESC size */ 181 return sizeof(struct rx_pkt_tlvs); 182 } 183 184 static inline 185 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 186 { 187 return data; 188 } 189 190 static inline 191 uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr) 192 { 193 struct rx_attention *rx_attn; 194 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 195 196 rx_attn = &rx_desc->attn_tlv.rx_attn; 197 198 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 199 } 200 201 static inline 202 uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr) 203 { 204 struct rx_attention *rx_attn; 205 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 206 207 rx_attn = &rx_desc->attn_tlv.rx_attn; 208 209 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 210 } 211 212 /* 213 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 214 * start TLV of Hardware TLV descriptor 215 * @hw_desc_addr: Hardware desciptor address 216 * 217 * Return: bool: if TLV tag match 218 */ 219 static inline 220 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 221 { 222 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 223 uint32_t tlv_tag; 224 225 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 226 &rx_desc->mpdu_start_tlv); 227 228 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 229 } 230 231 232 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 233 234 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 235 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 236 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 237 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 238 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 239 240 #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \ 241 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 242 (((struct reo_entrance_ring *)reo_ent_desc) \ 243 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 244 245 #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \ 246 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 247 (((struct reo_entrance_ring *)reo_ent_desc) \ 248 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 249 250 #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \ 251 (HAL_RX_BUF_COOKIE_GET(& \ 252 (((struct reo_entrance_ring *)reo_ent_desc) \ 253 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 254 255 /** 256 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 257 * cookie from the REO entrance ring element 258 * 259 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 260 * the current descriptor 261 * @ buf_info: structure to return the buffer information 262 * @ msdu_cnt: pointer to msdu count in MPDU 263 * Return: void 264 */ 265 static inline 266 void hal_rx_reo_ent_buf_paddr_get(hal_rxdma_desc_t rx_desc, 267 struct hal_buf_info *buf_info, 268 uint32_t *msdu_cnt 269 ) 270 { 271 struct reo_entrance_ring *reo_ent_ring = 272 (struct reo_entrance_ring *)rx_desc; 273 struct buffer_addr_info *buf_addr_info; 274 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 275 uint32_t loop_cnt; 276 277 rx_mpdu_desc_info_details = 278 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 279 280 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 281 RX_MPDU_DESC_INFO_0, MSDU_COUNT); 282 283 loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT); 284 285 buf_addr_info = 286 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 287 288 buf_info->paddr = 289 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 290 ((uint64_t) 291 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 292 293 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 294 buf_info->rbm = HAL_RX_BUF_RBM_GET(buf_addr_info); 295 296 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 297 "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 298 __func__, __LINE__, reo_ent_ring, buf_addr_info, 299 (unsigned long long)buf_info->paddr, loop_cnt); 300 } 301 302 static inline 303 void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 304 struct hal_buf_info *buf_info) 305 { 306 struct rx_msdu_link *msdu_link = 307 (struct rx_msdu_link *)rx_msdu_link_desc; 308 struct buffer_addr_info *buf_addr_info; 309 310 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 311 312 buf_info->paddr = 313 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 314 ((uint64_t) 315 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 316 317 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 318 buf_info->rbm = HAL_RX_BUF_RBM_GET(buf_addr_info); 319 } 320 321 /** 322 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 323 * 324 * @ soc : HAL version of the SOC pointer 325 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 326 * @ buf_addr_info : void pointer to the buffer_addr_info 327 * 328 * Return: void 329 */ 330 331 static inline 332 void hal_rx_mon_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 333 void *src_srng_desc, 334 hal_buff_addrinfo_t buf_addr_info) 335 { 336 struct buffer_addr_info *wbm_srng_buffer_addr_info = 337 (struct buffer_addr_info *)src_srng_desc; 338 uint64_t paddr; 339 struct buffer_addr_info *p_buffer_addr_info = 340 (struct buffer_addr_info *)buf_addr_info; 341 342 paddr = 343 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 344 ((uint64_t) 345 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 346 347 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 348 "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 349 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 350 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 351 352 /* Structure copy !!! */ 353 *wbm_srng_buffer_addr_info = 354 *((struct buffer_addr_info *)buf_addr_info); 355 } 356 357 static inline 358 uint32 hal_get_rx_msdu_link_desc_size(void) 359 { 360 return sizeof(struct rx_msdu_link); 361 } 362 363 enum { 364 HAL_PKT_TYPE_OFDM = 0, 365 HAL_PKT_TYPE_CCK, 366 HAL_PKT_TYPE_HT, 367 HAL_PKT_TYPE_VHT, 368 HAL_PKT_TYPE_HE, 369 }; 370 371 enum { 372 HAL_SGI_0_8_US, 373 HAL_SGI_0_4_US, 374 HAL_SGI_1_6_US, 375 HAL_SGI_3_2_US, 376 }; 377 378 enum { 379 HAL_FULL_RX_BW_20, 380 HAL_FULL_RX_BW_40, 381 HAL_FULL_RX_BW_80, 382 HAL_FULL_RX_BW_160, 383 }; 384 385 enum { 386 HAL_RX_TYPE_SU, 387 HAL_RX_TYPE_MU_MIMO, 388 HAL_RX_TYPE_MU_OFDMA, 389 HAL_RX_TYPE_MU_OFDMA_MIMO, 390 }; 391 392 /** 393 * enum 394 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 395 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL 396 */ 397 enum { 398 HAL_RX_MON_PPDU_START = 0, 399 HAL_RX_MON_PPDU_END, 400 }; 401 402 /* struct hal_rx_ppdu_common_info - common ppdu info 403 * @ppdu_id - ppdu id number 404 * @ppdu_timestamp - timestamp at ppdu received 405 * @mpdu_cnt_fcs_ok - mpdu count in ppdu with fcs ok 406 * @mpdu_cnt_fcs_err - mpdu count in ppdu with fcs err 407 * @mpdu_fcs_ok_bitmap - fcs ok mpdu count in ppdu bitmap 408 * @last_ppdu_id - last received ppdu id 409 * @mpdu_cnt - total mpdu count 410 * @num_users - num users 411 */ 412 struct hal_rx_ppdu_common_info { 413 uint32_t ppdu_id; 414 uint32_t ppdu_timestamp; 415 uint32_t mpdu_cnt_fcs_ok; 416 uint32_t mpdu_cnt_fcs_err; 417 uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 418 uint32_t last_ppdu_id; 419 uint32_t mpdu_cnt; 420 uint8_t num_users; 421 }; 422 423 /** 424 * struct hal_rx_msdu_payload_info - msdu payload info 425 * @first_msdu_payload: pointer to first msdu payload 426 * @payload_len: payload len 427 * @nbuf: status network buffer to which msdu belongs to 428 */ 429 struct hal_rx_msdu_payload_info { 430 uint8_t *first_msdu_payload; 431 uint32_t payload_len; 432 qdf_nbuf_t nbuf; 433 }; 434 435 /** 436 * struct hal_rx_nac_info - struct for neighbour info 437 * @fc_valid: flag indicate if it has valid frame control information 438 * @frame_control: frame control from each MPDU 439 * @to_ds_flag: flag indicate to_ds bit 440 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 441 * @mac_addr2: mac address2 in wh 442 * @mcast_bcast: multicast/broadcast 443 */ 444 struct hal_rx_nac_info { 445 uint8_t fc_valid; 446 uint16_t frame_control; 447 uint8_t to_ds_flag; 448 uint8_t mac_addr2_valid; 449 uint8_t mac_addr2[QDF_MAC_ADDR_SIZE]; 450 uint8_t mcast_bcast; 451 }; 452 453 /** 454 * struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs 455 * @cce_metadata: cached CCE metadata value received in the MSDU_END TLV 456 * @is_flow_idx_timeout: flag to indicate if flow search timeout occurred 457 * @is_flow_idx_invalid: flag to indicate if flow idx is valid or not 458 * @fse_metadata: cached FSE metadata value received in the MSDU END TLV 459 * @flow_idx: flow idx matched in FSE received in the MSDU END TLV 460 */ 461 struct hal_rx_ppdu_msdu_info { 462 uint16_t cce_metadata; 463 bool is_flow_idx_timeout; 464 bool is_flow_idx_invalid; 465 uint32_t fse_metadata; 466 uint32_t flow_idx; 467 }; 468 469 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 470 /** 471 * struct hal_rx_ppdu_cfr_user_info - struct for storing peer info extracted 472 * from HW TLVs, this will be used for correlating CFR data with multiple peers 473 * in MU PPDUs 474 * 475 * @peer_macaddr: macaddr of the peer 476 * @ast_index: AST index of the peer 477 */ 478 struct hal_rx_ppdu_cfr_user_info { 479 uint8_t peer_macaddr[QDF_MAC_ADDR_SIZE]; 480 uint32_t ast_index; 481 }; 482 483 /** 484 * struct hal_rx_ppdu_cfr_info - struct for storing ppdu info extracted from HW 485 * TLVs, this will be used for CFR correlation 486 * 487 * @bb_captured_channel : Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 488 * sent to PHY, SW checks it to correlate current PPDU TLVs with uploaded 489 * channel information. 490 * 491 * @bb_captured_timeout : Set by RxPCU to indicate channel capture condition is 492 * met, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due to AST delay, 493 * which means the rx_frame_falling edge to FREEZE TLV ready time exceeds 494 * the threshold time defined by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 495 * Bb_captured_reason is still valid in this case. 496 * 497 * @rx_location_info_valid: Indicates whether CFR DMA address in the PPDU TLV 498 * is valid 499 * <enum 0 rx_location_info_is_not_valid> 500 * <enum 1 rx_location_info_is_valid> 501 * <legal all> 502 * 503 * @bb_captured_reason : Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL 504 * TLV to here for FW usage. Valid when bb_captured_channel or 505 * bb_captured_timeout is set. 506 * <enum 0 freeze_reason_TM> 507 * <enum 1 freeze_reason_FTM> 508 * <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 509 * <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 510 * <enum 4 freeze_reason_NDPA_NDP> 511 * <enum 5 freeze_reason_ALL_PACKET> 512 * <legal 0-5> 513 * 514 * @rtt_che_buffer_pointer_low32 : The low 32 bits of the 40 bits pointer to 515 * external RTT channel information buffer 516 * 517 * @rtt_che_buffer_pointer_high8 : The high 8 bits of the 40 bits pointer to 518 * external RTT channel information buffer 519 * 520 * @chan_capture_status : capture status reported by ucode 521 * a. CAPTURE_IDLE: FW has disabled "REPETITIVE_CHE_CAPTURE_CTRL" 522 * b. CAPTURE_BUSY: previous PPDU’s channel capture upload DMA ongoing. (Note 523 * that this upload is triggered after receiving freeze_channel_capture TLV 524 * after last PPDU is rx) 525 * c. CAPTURE_ACTIVE: channel capture is enabled and no previous channel 526 * capture ongoing 527 * d. CAPTURE_NO_BUFFER: next buffer in IPC ring not available 528 * 529 * @cfr_user_info: Peer mac for upto 4 MU users 530 */ 531 532 struct hal_rx_ppdu_cfr_info { 533 bool bb_captured_channel; 534 bool bb_captured_timeout; 535 uint8_t bb_captured_reason; 536 bool rx_location_info_valid; 537 uint8_t chan_capture_status; 538 uint8_t rtt_che_buffer_pointer_high8; 539 uint32_t rtt_che_buffer_pointer_low32; 540 struct hal_rx_ppdu_cfr_user_info cfr_user_info[HAL_MAX_UL_MU_USERS]; 541 }; 542 #else 543 struct hal_rx_ppdu_cfr_info {}; 544 #endif 545 546 struct hal_rx_ppdu_info { 547 struct hal_rx_ppdu_common_info com_info; 548 struct mon_rx_status rx_status; 549 struct mon_rx_user_status rx_user_status[HAL_MAX_UL_MU_USERS]; 550 struct hal_rx_msdu_payload_info msdu_info; 551 struct hal_rx_msdu_payload_info fcs_ok_msdu_info; 552 struct hal_rx_nac_info nac_info; 553 /* status ring PPDU start and end state */ 554 uint32_t rx_state; 555 /* MU user id for status ring TLV */ 556 uint32_t user_id; 557 /* MPDU/MSDU truncated to 128 bytes header start addr in status skb */ 558 unsigned char *data; 559 /* MPDU/MSDU truncated to 128 bytes header real length */ 560 uint32_t hdr_len; 561 /* MPDU FCS error */ 562 bool fcs_err; 563 /* Id to indicate how to process mpdu */ 564 uint8_t sw_frame_group_id; 565 struct hal_rx_ppdu_msdu_info rx_msdu_info[HAL_MAX_UL_MU_USERS]; 566 /* first msdu payload for all mpdus in ppdu */ 567 struct hal_rx_msdu_payload_info ppdu_msdu_info[HAL_RX_MAX_MPDU]; 568 /* evm info */ 569 struct hal_rx_su_evm_info evm_info; 570 /** 571 * Will be used to store ppdu info extracted from HW TLVs, 572 * and for CFR correlation as well 573 */ 574 struct hal_rx_ppdu_cfr_info cfr_info; 575 }; 576 577 static inline uint32_t 578 hal_get_rx_status_buf_size(void) { 579 /* RX status buffer size is hard coded for now */ 580 return 2048; 581 } 582 583 static inline uint8_t* 584 hal_rx_status_get_next_tlv(uint8_t *rx_tlv) { 585 uint32_t tlv_len, tlv_tag; 586 587 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 588 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 589 590 /* The actual length of PPDU_END is the combined length of many PHY 591 * TLVs that follow. Skip the TLV header and 592 * rx_rxpcu_classification_overview that follows the header to get to 593 * next TLV. 594 */ 595 if (tlv_tag == WIFIRX_PPDU_END_E) 596 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 597 598 return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len + 599 HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3))); 600 } 601 602 /** 603 * hal_rx_proc_phyrx_other_receive_info_tlv() 604 * - process other receive info TLV 605 * @rx_tlv_hdr: pointer to TLV header 606 * @ppdu_info: pointer to ppdu_info 607 * 608 * Return: None 609 */ 610 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 611 void *rx_tlv_hdr, 612 struct hal_rx_ppdu_info 613 *ppdu_info) 614 { 615 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 616 (void *)ppdu_info); 617 } 618 619 /** 620 * hal_rx_status_get_tlv_info() - process receive info TLV 621 * @rx_tlv_hdr: pointer to TLV header 622 * @ppdu_info: pointer to ppdu_info 623 * @hal_soc: HAL soc handle 624 * @nbuf: PPDU status netowrk buffer 625 * 626 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 627 */ 628 static inline uint32_t 629 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 630 hal_soc_handle_t hal_soc_hdl, 631 qdf_nbuf_t nbuf) 632 { 633 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 634 635 return hal_soc->ops->hal_rx_status_get_tlv_info( 636 rx_tlv_hdr, 637 ppdu_info, 638 hal_soc_hdl, 639 nbuf); 640 } 641 642 static inline 643 uint32_t hal_get_rx_status_done_tlv_size(hal_soc_handle_t hal_soc_hdl) 644 { 645 return HAL_RX_TLV32_HDR_SIZE; 646 } 647 648 static inline QDF_STATUS 649 hal_get_rx_status_done(uint8_t *rx_tlv) 650 { 651 uint32_t tlv_tag; 652 653 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 654 655 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 656 return QDF_STATUS_SUCCESS; 657 else 658 return QDF_STATUS_E_EMPTY; 659 } 660 661 static inline QDF_STATUS 662 hal_clear_rx_status_done(uint8_t *rx_tlv) 663 { 664 *(uint32_t *)rx_tlv = 0; 665 return QDF_STATUS_SUCCESS; 666 } 667 668 #endif 669