1 /* 2 * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_API_MON_H_ 20 #define _HAL_API_MON_H_ 21 22 #include "qdf_types.h" 23 #include "hal_internal.h" 24 #include <target_type.h> 25 26 #define HAL_RX_PHY_DATA_RADAR 0x01 27 #define HAL_SU_MU_CODING_LDPC 0x01 28 29 #define HAL_RX_FCS_LEN (4) 30 #define KEY_EXTIV 0x20 31 32 #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000 33 #define HAL_RX_USER_TLV32_TYPE_LSB 1 34 #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE 35 36 #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000 37 #define HAL_RX_USER_TLV32_LEN_LSB 10 38 #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00 39 40 #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000 41 #define HAL_RX_USER_TLV32_USERID_LSB 26 42 #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000 43 44 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 45 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 46 47 #define HAL_RX_TLV32_HDR_SIZE 4 48 49 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 50 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 51 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 52 HAL_RX_USER_TLV32_TYPE_LSB) 53 54 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 55 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 56 HAL_RX_USER_TLV32_LEN_MASK) >> \ 57 HAL_RX_USER_TLV32_LEN_LSB) 58 59 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 60 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 61 HAL_RX_USER_TLV32_USERID_MASK) >> \ 62 HAL_RX_USER_TLV32_USERID_LSB) 63 64 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 65 #define HAL_TLV_STATUS_PPDU_DONE 1 66 #define HAL_TLV_STATUS_BUF_DONE 2 67 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 68 #define HAL_TLV_STATUS_PPDU_START 4 69 #define HAL_TLV_STATUS_HEADER 5 70 #define HAL_TLV_STATUS_MPDU_END 6 71 #define HAL_TLV_STATUS_MSDU_START 7 72 #define HAL_TLV_STATUS_MSDU_END 8 73 74 #define HAL_MAX_UL_MU_USERS 37 75 76 #define HAL_RX_PKT_TYPE_11A 0 77 #define HAL_RX_PKT_TYPE_11B 1 78 #define HAL_RX_PKT_TYPE_11N 2 79 #define HAL_RX_PKT_TYPE_11AC 3 80 #define HAL_RX_PKT_TYPE_11AX 4 81 82 #define HAL_RX_RECEPTION_TYPE_SU 0 83 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 84 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 85 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 86 87 /* Multiply rate by 2 to avoid float point 88 * and get rate in units of 500kbps 89 */ 90 #define HAL_11B_RATE_0MCS 11*2 91 #define HAL_11B_RATE_1MCS 5.5*2 92 #define HAL_11B_RATE_2MCS 2*2 93 #define HAL_11B_RATE_3MCS 1*2 94 #define HAL_11B_RATE_4MCS 11*2 95 #define HAL_11B_RATE_5MCS 5.5*2 96 #define HAL_11B_RATE_6MCS 2*2 97 98 #define HAL_11A_RATE_0MCS 48*2 99 #define HAL_11A_RATE_1MCS 24*2 100 #define HAL_11A_RATE_2MCS 12*2 101 #define HAL_11A_RATE_3MCS 6*2 102 #define HAL_11A_RATE_4MCS 54*2 103 #define HAL_11A_RATE_5MCS 36*2 104 #define HAL_11A_RATE_6MCS 18*2 105 #define HAL_11A_RATE_7MCS 9*2 106 107 #define HAL_LEGACY_MCS0 0 108 #define HAL_LEGACY_MCS1 1 109 #define HAL_LEGACY_MCS2 2 110 #define HAL_LEGACY_MCS3 3 111 #define HAL_LEGACY_MCS4 4 112 #define HAL_LEGACY_MCS5 5 113 #define HAL_LEGACY_MCS6 6 114 #define HAL_LEGACY_MCS7 7 115 116 #define HE_GI_0_8 0 117 #define HE_GI_0_4 1 118 #define HE_GI_1_6 2 119 #define HE_GI_3_2 3 120 121 #define HE_GI_RADIOTAP_0_8 0 122 #define HE_GI_RADIOTAP_1_6 1 123 #define HE_GI_RADIOTAP_3_2 2 124 #define HE_GI_RADIOTAP_RESERVED 3 125 126 #define HE_LTF_RADIOTAP_UNKNOWN 0 127 #define HE_LTF_RADIOTAP_1_X 1 128 #define HE_LTF_RADIOTAP_2_X 2 129 #define HE_LTF_RADIOTAP_4_X 3 130 131 #define HT_SGI_PRESENT 0x80 132 133 #define HE_LTF_1_X 0 134 #define HE_LTF_2_X 1 135 #define HE_LTF_4_X 2 136 #define HE_LTF_UNKNOWN 3 137 #define VHT_SIG_SU_NSS_MASK 0x7 138 #define HT_SIG_SU_NSS_SHIFT 0x3 139 140 #define HAL_TID_INVALID 31 141 #define HAL_AST_IDX_INVALID 0xFFFF 142 143 #ifdef GET_MSDU_AGGREGATION 144 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 145 {\ 146 struct rx_msdu_end *rx_msdu_end;\ 147 bool first_msdu, last_msdu; \ 148 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 149 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 150 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 151 if (first_msdu && last_msdu)\ 152 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 153 else\ 154 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 155 } \ 156 157 #else 158 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 159 #endif 160 161 /* Max MPDUs per status buffer */ 162 #define HAL_RX_MAX_MPDU 256 163 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 164 #define HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER 16 165 166 /* Max pilot count */ 167 #define HAL_RX_MAX_SU_EVM_COUNT 32 168 169 /** 170 * struct hal_rx_mon_desc_info () - HAL Rx Monitor descriptor info 171 * 172 * @ppdu_id: PHY ppdu id 173 * @status_buf_count: number of status buffer count 174 * @rxdma_push_reason: rxdma push reason 175 * @rxdma_error_code: rxdma error code 176 * @msdu_cnt: msdu count 177 * @end_of_ppdu: end of ppdu 178 * @link_desc: msdu link descriptor address 179 * @status_buf: for a PPDU, status buffers can span acrosss 180 * multiple buffers, status_buf points to first 181 * status buffer address of PPDU 182 * @drop_ppdu: flag to indicate current destination 183 * ring ppdu drop 184 */ 185 struct hal_rx_mon_desc_info { 186 uint16_t ppdu_id; 187 uint8_t status_buf_count; 188 uint8_t rxdma_push_reason; 189 uint8_t rxdma_error_code; 190 uint8_t msdu_count; 191 uint8_t end_of_ppdu; 192 struct hal_buf_info link_desc; 193 struct hal_buf_info status_buf; 194 bool drop_ppdu; 195 }; 196 197 /* 198 * Struct hal_rx_su_evm_info - SU evm info 199 * @number_of_symbols: number of symbols 200 * @nss_count: nss count 201 * @pilot_count: pilot count 202 * @pilot_evm: Array of pilot evm values 203 */ 204 struct hal_rx_su_evm_info { 205 uint32_t number_of_symbols; 206 uint8_t nss_count; 207 uint8_t pilot_count; 208 uint32_t pilot_evm[HAL_RX_MAX_SU_EVM_COUNT]; 209 }; 210 211 enum { 212 DP_PPDU_STATUS_START, 213 DP_PPDU_STATUS_DONE, 214 }; 215 216 static inline 217 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 218 { 219 return data; 220 } 221 222 static inline 223 uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr) 224 { 225 struct rx_attention *rx_attn; 226 struct rx_mon_pkt_tlvs *rx_desc = 227 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 228 229 rx_attn = &rx_desc->attn_tlv.rx_attn; 230 231 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 232 } 233 234 static inline 235 uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr) 236 { 237 struct rx_attention *rx_attn; 238 struct rx_mon_pkt_tlvs *rx_desc = 239 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 240 241 rx_attn = &rx_desc->attn_tlv.rx_attn; 242 243 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 244 } 245 246 /* 247 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 248 * start TLV of Hardware TLV descriptor 249 * @hw_desc_addr: Hardware desciptor address 250 * 251 * Return: bool: if TLV tag match 252 */ 253 static inline 254 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 255 { 256 struct rx_mon_pkt_tlvs *rx_desc = 257 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 258 uint32_t tlv_tag; 259 260 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 261 &rx_desc->mpdu_start_tlv); 262 263 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 264 } 265 266 /* 267 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV user id in MPDU 268 * start TLV of Hardware TLV descriptor 269 * @hw_desc_addr: Hardware desciptor address 270 * 271 * Return: unit32_t: user id 272 */ 273 static inline 274 uint32_t HAL_RX_HW_DESC_MPDU_USER_ID(void *hw_desc_addr) 275 { 276 struct rx_mon_pkt_tlvs *rx_desc = 277 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 278 uint32_t user_id; 279 280 user_id = HAL_RX_GET_USER_TLV32_USERID( 281 &rx_desc->mpdu_start_tlv); 282 283 return user_id; 284 } 285 286 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 287 288 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 289 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 290 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 291 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 292 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 293 294 #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \ 295 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 296 (((struct reo_entrance_ring *)reo_ent_desc) \ 297 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 298 299 #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \ 300 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 301 (((struct reo_entrance_ring *)reo_ent_desc) \ 302 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 303 304 #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \ 305 (HAL_RX_BUF_COOKIE_GET(& \ 306 (((struct reo_entrance_ring *)reo_ent_desc) \ 307 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 308 309 /** 310 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 311 * cookie from the REO entrance ring element 312 * 313 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 314 * the current descriptor 315 * @ buf_info: structure to return the buffer information 316 * @ msdu_cnt: pointer to msdu count in MPDU 317 * Return: void 318 */ 319 static inline 320 void hal_rx_reo_ent_buf_paddr_get(hal_rxdma_desc_t rx_desc, 321 struct hal_buf_info *buf_info, 322 uint32_t *msdu_cnt 323 ) 324 { 325 struct reo_entrance_ring *reo_ent_ring = 326 (struct reo_entrance_ring *)rx_desc; 327 struct buffer_addr_info *buf_addr_info; 328 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 329 uint32_t loop_cnt; 330 331 rx_mpdu_desc_info_details = 332 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 333 334 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 335 RX_MPDU_DESC_INFO_0, MSDU_COUNT); 336 337 loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT); 338 339 buf_addr_info = 340 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 341 342 buf_info->paddr = 343 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 344 ((uint64_t) 345 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 346 347 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 348 buf_info->rbm = HAL_RX_BUF_RBM_GET(buf_addr_info); 349 350 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 351 "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 352 __func__, __LINE__, reo_ent_ring, buf_addr_info, 353 (unsigned long long)buf_info->paddr, loop_cnt); 354 } 355 356 static inline 357 void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 358 struct hal_buf_info *buf_info) 359 { 360 struct rx_msdu_link *msdu_link = 361 (struct rx_msdu_link *)rx_msdu_link_desc; 362 struct buffer_addr_info *buf_addr_info; 363 364 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 365 366 buf_info->paddr = 367 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 368 ((uint64_t) 369 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 370 371 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 372 buf_info->rbm = HAL_RX_BUF_RBM_GET(buf_addr_info); 373 } 374 375 /** 376 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 377 * 378 * @ soc : HAL version of the SOC pointer 379 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 380 * @ buf_addr_info : void pointer to the buffer_addr_info 381 * 382 * Return: void 383 */ 384 385 static inline 386 void hal_rx_mon_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 387 void *src_srng_desc, 388 hal_buff_addrinfo_t buf_addr_info) 389 { 390 struct buffer_addr_info *wbm_srng_buffer_addr_info = 391 (struct buffer_addr_info *)src_srng_desc; 392 uint64_t paddr; 393 struct buffer_addr_info *p_buffer_addr_info = 394 (struct buffer_addr_info *)buf_addr_info; 395 396 paddr = 397 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 398 ((uint64_t) 399 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 400 401 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 402 "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 403 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 404 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 405 406 /* Structure copy !!! */ 407 *wbm_srng_buffer_addr_info = 408 *((struct buffer_addr_info *)buf_addr_info); 409 } 410 411 static inline 412 uint32 hal_get_rx_msdu_link_desc_size(void) 413 { 414 return sizeof(struct rx_msdu_link); 415 } 416 417 enum { 418 HAL_PKT_TYPE_OFDM = 0, 419 HAL_PKT_TYPE_CCK, 420 HAL_PKT_TYPE_HT, 421 HAL_PKT_TYPE_VHT, 422 HAL_PKT_TYPE_HE, 423 }; 424 425 enum { 426 HAL_SGI_0_8_US, 427 HAL_SGI_0_4_US, 428 HAL_SGI_1_6_US, 429 HAL_SGI_3_2_US, 430 }; 431 432 enum { 433 HAL_FULL_RX_BW_20, 434 HAL_FULL_RX_BW_40, 435 HAL_FULL_RX_BW_80, 436 HAL_FULL_RX_BW_160, 437 }; 438 439 enum { 440 HAL_RX_TYPE_SU, 441 HAL_RX_TYPE_MU_MIMO, 442 HAL_RX_TYPE_MU_OFDMA, 443 HAL_RX_TYPE_MU_OFDMA_MIMO, 444 }; 445 446 /** 447 * enum 448 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 449 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decoded in HAL 450 * @HAL_RX_MON_PPDU_RESET: Not PPDU start and end TLV 451 */ 452 enum { 453 HAL_RX_MON_PPDU_START = 0, 454 HAL_RX_MON_PPDU_END, 455 HAL_RX_MON_PPDU_RESET, 456 }; 457 458 /* struct hal_rx_ppdu_common_info - common ppdu info 459 * @ppdu_id - ppdu id number 460 * @ppdu_timestamp - timestamp at ppdu received 461 * @mpdu_cnt_fcs_ok - mpdu count in ppdu with fcs ok 462 * @mpdu_cnt_fcs_err - mpdu count in ppdu with fcs err 463 * @mpdu_fcs_ok_bitmap - fcs ok mpdu count in ppdu bitmap 464 * @last_ppdu_id - last received ppdu id 465 * @mpdu_cnt - total mpdu count 466 * @num_users - num users 467 */ 468 struct hal_rx_ppdu_common_info { 469 uint32_t ppdu_id; 470 uint32_t ppdu_timestamp; 471 uint32_t mpdu_cnt_fcs_ok; 472 uint32_t mpdu_cnt_fcs_err; 473 uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 474 uint32_t last_ppdu_id; 475 uint32_t mpdu_cnt; 476 uint8_t num_users; 477 }; 478 479 /** 480 * struct hal_rx_msdu_payload_info - msdu payload info 481 * @first_msdu_payload: pointer to first msdu payload 482 * @payload_len: payload len 483 */ 484 struct hal_rx_msdu_payload_info { 485 uint8_t *first_msdu_payload; 486 uint32_t payload_len; 487 }; 488 489 /** 490 * struct hal_rx_nac_info - struct for neighbour info 491 * @fc_valid: flag indicate if it has valid frame control information 492 * @frame_control: frame control from each MPDU 493 * @to_ds_flag: flag indicate to_ds bit 494 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 495 * @mac_addr2: mac address2 in wh 496 * @mcast_bcast: multicast/broadcast 497 */ 498 struct hal_rx_nac_info { 499 uint8_t fc_valid; 500 uint16_t frame_control; 501 uint8_t to_ds_flag; 502 uint8_t mac_addr2_valid; 503 uint8_t mac_addr2[QDF_MAC_ADDR_SIZE]; 504 uint8_t mcast_bcast; 505 }; 506 507 /** 508 * struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs 509 * @cce_metadata: cached CCE metadata value received in the MSDU_END TLV 510 * @is_flow_idx_timeout: flag to indicate if flow search timeout occurred 511 * @is_flow_idx_invalid: flag to indicate if flow idx is valid or not 512 * @fse_metadata: cached FSE metadata value received in the MSDU END TLV 513 * @flow_idx: flow idx matched in FSE received in the MSDU END TLV 514 */ 515 struct hal_rx_ppdu_msdu_info { 516 uint16_t cce_metadata; 517 bool is_flow_idx_timeout; 518 bool is_flow_idx_invalid; 519 uint32_t fse_metadata; 520 uint32_t flow_idx; 521 }; 522 523 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 524 /** 525 * struct hal_rx_ppdu_cfr_user_info - struct for storing peer info extracted 526 * from HW TLVs, this will be used for correlating CFR data with multiple peers 527 * in MU PPDUs 528 * 529 * @peer_macaddr: macaddr of the peer 530 * @ast_index: AST index of the peer 531 */ 532 struct hal_rx_ppdu_cfr_user_info { 533 uint8_t peer_macaddr[QDF_MAC_ADDR_SIZE]; 534 uint32_t ast_index; 535 }; 536 537 /** 538 * struct hal_rx_ppdu_cfr_info - struct for storing ppdu info extracted from HW 539 * TLVs, this will be used for CFR correlation 540 * 541 * @bb_captured_channel : Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 542 * sent to PHY, SW checks it to correlate current PPDU TLVs with uploaded 543 * channel information. 544 * 545 * @bb_captured_timeout : Set by RxPCU to indicate channel capture condition is 546 * met, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due to AST delay, 547 * which means the rx_frame_falling edge to FREEZE TLV ready time exceeds 548 * the threshold time defined by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 549 * Bb_captured_reason is still valid in this case. 550 * 551 * @rx_location_info_valid: Indicates whether CFR DMA address in the PPDU TLV 552 * is valid 553 * <enum 0 rx_location_info_is_not_valid> 554 * <enum 1 rx_location_info_is_valid> 555 * <legal all> 556 * 557 * @bb_captured_reason : Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL 558 * TLV to here for FW usage. Valid when bb_captured_channel or 559 * bb_captured_timeout is set. 560 * <enum 0 freeze_reason_TM> 561 * <enum 1 freeze_reason_FTM> 562 * <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 563 * <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 564 * <enum 4 freeze_reason_NDPA_NDP> 565 * <enum 5 freeze_reason_ALL_PACKET> 566 * <legal 0-5> 567 * 568 * @rtt_che_buffer_pointer_low32 : The low 32 bits of the 40 bits pointer to 569 * external RTT channel information buffer 570 * 571 * @rtt_che_buffer_pointer_high8 : The high 8 bits of the 40 bits pointer to 572 * external RTT channel information buffer 573 * 574 * @chan_capture_status : capture status reported by ucode 575 * a. CAPTURE_IDLE: FW has disabled "REPETITIVE_CHE_CAPTURE_CTRL" 576 * b. CAPTURE_BUSY: previous PPDU’s channel capture upload DMA ongoing. (Note 577 * that this upload is triggered after receiving freeze_channel_capture TLV 578 * after last PPDU is rx) 579 * c. CAPTURE_ACTIVE: channel capture is enabled and no previous channel 580 * capture ongoing 581 * d. CAPTURE_NO_BUFFER: next buffer in IPC ring not available 582 * 583 * @cfr_user_info: Peer mac for upto 4 MU users 584 */ 585 586 struct hal_rx_ppdu_cfr_info { 587 bool bb_captured_channel; 588 bool bb_captured_timeout; 589 uint8_t bb_captured_reason; 590 bool rx_location_info_valid; 591 uint8_t chan_capture_status; 592 uint8_t rtt_che_buffer_pointer_high8; 593 uint32_t rtt_che_buffer_pointer_low32; 594 struct hal_rx_ppdu_cfr_user_info cfr_user_info[HAL_MAX_UL_MU_USERS]; 595 }; 596 #else 597 struct hal_rx_ppdu_cfr_info {}; 598 #endif 599 600 struct mon_rx_info { 601 uint8_t qos_control_info_valid; 602 uint16_t qos_control; 603 uint8_t mac_addr1_valid; 604 uint8_t mac_addr1[QDF_MAC_ADDR_SIZE]; 605 uint32_t user_id; 606 }; 607 608 struct mon_rx_user_info { 609 uint16_t qos_control; 610 uint8_t qos_control_info_valid; 611 }; 612 613 struct hal_rx_ppdu_info { 614 struct hal_rx_ppdu_common_info com_info; 615 struct mon_rx_status rx_status; 616 struct mon_rx_user_status rx_user_status[HAL_MAX_UL_MU_USERS]; 617 struct mon_rx_info rx_info; 618 struct mon_rx_user_info rx_user_info[HAL_MAX_UL_MU_USERS]; 619 struct hal_rx_msdu_payload_info msdu_info; 620 struct hal_rx_msdu_payload_info fcs_ok_msdu_info; 621 struct hal_rx_nac_info nac_info; 622 /* status ring PPDU start and end state */ 623 uint32_t rx_state; 624 /* MU user id for status ring TLV */ 625 uint32_t user_id; 626 /* MPDU/MSDU truncated to 128 bytes header start addr in status skb */ 627 unsigned char *data; 628 /* MPDU/MSDU truncated to 128 bytes header real length */ 629 uint32_t hdr_len; 630 /* MPDU FCS error */ 631 bool fcs_err; 632 /* Id to indicate how to process mpdu */ 633 uint8_t sw_frame_group_id; 634 struct hal_rx_ppdu_msdu_info rx_msdu_info[HAL_MAX_UL_MU_USERS]; 635 /* fcs passed mpdu count in rx monitor status buffer */ 636 uint8_t fcs_ok_cnt; 637 /* fcs error mpdu count in rx monitor status buffer */ 638 uint8_t fcs_err_cnt; 639 /* MPDU FCS passed */ 640 bool is_fcs_passed; 641 /* first msdu payload for all mpdus in rx monitor status buffer */ 642 struct hal_rx_msdu_payload_info ppdu_msdu_info[HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER]; 643 /* evm info */ 644 struct hal_rx_su_evm_info evm_info; 645 /** 646 * Will be used to store ppdu info extracted from HW TLVs, 647 * and for CFR correlation as well 648 */ 649 struct hal_rx_ppdu_cfr_info cfr_info; 650 }; 651 652 static inline uint32_t 653 hal_get_rx_status_buf_size(void) { 654 /* RX status buffer size is hard coded for now */ 655 return 2048; 656 } 657 658 static inline uint8_t* 659 hal_rx_status_get_next_tlv(uint8_t *rx_tlv) { 660 uint32_t tlv_len, tlv_tag; 661 662 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 663 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 664 665 /* The actual length of PPDU_END is the combined length of many PHY 666 * TLVs that follow. Skip the TLV header and 667 * rx_rxpcu_classification_overview that follows the header to get to 668 * next TLV. 669 */ 670 if (tlv_tag == WIFIRX_PPDU_END_E) 671 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 672 673 return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len + 674 HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3))); 675 } 676 677 /** 678 * hal_rx_proc_phyrx_other_receive_info_tlv() 679 * - process other receive info TLV 680 * @rx_tlv_hdr: pointer to TLV header 681 * @ppdu_info: pointer to ppdu_info 682 * 683 * Return: None 684 */ 685 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 686 void *rx_tlv_hdr, 687 struct hal_rx_ppdu_info 688 *ppdu_info) 689 { 690 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 691 (void *)ppdu_info); 692 } 693 694 /** 695 * hal_rx_status_get_tlv_info() - process receive info TLV 696 * @rx_tlv_hdr: pointer to TLV header 697 * @ppdu_info: pointer to ppdu_info 698 * @hal_soc: HAL soc handle 699 * @nbuf: PPDU status netowrk buffer 700 * 701 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 702 */ 703 static inline uint32_t 704 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 705 hal_soc_handle_t hal_soc_hdl, 706 qdf_nbuf_t nbuf) 707 { 708 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 709 710 return hal_soc->ops->hal_rx_status_get_tlv_info( 711 rx_tlv_hdr, 712 ppdu_info, 713 hal_soc_hdl, 714 nbuf); 715 } 716 717 static inline 718 uint32_t hal_get_rx_status_done_tlv_size(hal_soc_handle_t hal_soc_hdl) 719 { 720 return HAL_RX_TLV32_HDR_SIZE; 721 } 722 723 static inline QDF_STATUS 724 hal_get_rx_status_done(uint8_t *rx_tlv) 725 { 726 uint32_t tlv_tag; 727 728 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 729 730 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 731 return QDF_STATUS_SUCCESS; 732 else 733 return QDF_STATUS_E_EMPTY; 734 } 735 736 static inline QDF_STATUS 737 hal_clear_rx_status_done(uint8_t *rx_tlv) 738 { 739 *(uint32_t *)rx_tlv = 0; 740 return QDF_STATUS_SUCCESS; 741 } 742 743 #endif 744