1 /* 2 * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_API_MON_H_ 20 #define _HAL_API_MON_H_ 21 22 #include "qdf_types.h" 23 #include "hal_internal.h" 24 #include <target_type.h> 25 26 #define HAL_RX_PHY_DATA_RADAR 0x01 27 #define HAL_SU_MU_CODING_LDPC 0x01 28 29 #define HAL_RX_FCS_LEN (4) 30 #define KEY_EXTIV 0x20 31 32 #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000 33 #define HAL_RX_USER_TLV32_TYPE_LSB 1 34 #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE 35 36 #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000 37 #define HAL_RX_USER_TLV32_LEN_LSB 10 38 #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00 39 40 #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000 41 #define HAL_RX_USER_TLV32_USERID_LSB 26 42 #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000 43 44 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 45 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 46 47 #define HAL_RX_TLV32_HDR_SIZE 4 48 49 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 50 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 51 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 52 HAL_RX_USER_TLV32_TYPE_LSB) 53 54 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 55 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 56 HAL_RX_USER_TLV32_LEN_MASK) >> \ 57 HAL_RX_USER_TLV32_LEN_LSB) 58 59 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 60 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 61 HAL_RX_USER_TLV32_USERID_MASK) >> \ 62 HAL_RX_USER_TLV32_USERID_LSB) 63 64 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 65 #define HAL_TLV_STATUS_PPDU_DONE 1 66 #define HAL_TLV_STATUS_BUF_DONE 2 67 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 68 #define HAL_TLV_STATUS_PPDU_START 4 69 #define HAL_TLV_STATUS_HEADER 5 70 #define HAL_TLV_STATUS_MPDU_END 6 71 #define HAL_TLV_STATUS_MSDU_START 7 72 #define HAL_TLV_STATUS_MSDU_END 8 73 74 #define HAL_MAX_UL_MU_USERS 37 75 76 #define HAL_RX_PKT_TYPE_11A 0 77 #define HAL_RX_PKT_TYPE_11B 1 78 #define HAL_RX_PKT_TYPE_11N 2 79 #define HAL_RX_PKT_TYPE_11AC 3 80 #define HAL_RX_PKT_TYPE_11AX 4 81 82 #define HAL_RX_RECEPTION_TYPE_SU 0 83 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 84 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 85 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 86 87 /* Multiply rate by 2 to avoid float point 88 * and get rate in units of 500kbps 89 */ 90 #define HAL_11B_RATE_0MCS 11*2 91 #define HAL_11B_RATE_1MCS 5.5*2 92 #define HAL_11B_RATE_2MCS 2*2 93 #define HAL_11B_RATE_3MCS 1*2 94 #define HAL_11B_RATE_4MCS 11*2 95 #define HAL_11B_RATE_5MCS 5.5*2 96 #define HAL_11B_RATE_6MCS 2*2 97 98 #define HAL_11A_RATE_0MCS 48*2 99 #define HAL_11A_RATE_1MCS 24*2 100 #define HAL_11A_RATE_2MCS 12*2 101 #define HAL_11A_RATE_3MCS 6*2 102 #define HAL_11A_RATE_4MCS 54*2 103 #define HAL_11A_RATE_5MCS 36*2 104 #define HAL_11A_RATE_6MCS 18*2 105 #define HAL_11A_RATE_7MCS 9*2 106 107 #define HAL_LEGACY_MCS0 0 108 #define HAL_LEGACY_MCS1 1 109 #define HAL_LEGACY_MCS2 2 110 #define HAL_LEGACY_MCS3 3 111 #define HAL_LEGACY_MCS4 4 112 #define HAL_LEGACY_MCS5 5 113 #define HAL_LEGACY_MCS6 6 114 #define HAL_LEGACY_MCS7 7 115 116 #define HE_GI_0_8 0 117 #define HE_GI_0_4 1 118 #define HE_GI_1_6 2 119 #define HE_GI_3_2 3 120 121 #define HE_GI_RADIOTAP_0_8 0 122 #define HE_GI_RADIOTAP_1_6 1 123 #define HE_GI_RADIOTAP_3_2 2 124 #define HE_GI_RADIOTAP_RESERVED 3 125 126 #define HE_LTF_RADIOTAP_UNKNOWN 0 127 #define HE_LTF_RADIOTAP_1_X 1 128 #define HE_LTF_RADIOTAP_2_X 2 129 #define HE_LTF_RADIOTAP_4_X 3 130 131 #define HT_SGI_PRESENT 0x80 132 133 #define HE_LTF_1_X 0 134 #define HE_LTF_2_X 1 135 #define HE_LTF_4_X 2 136 #define HE_LTF_UNKNOWN 3 137 #define VHT_SIG_SU_NSS_MASK 0x7 138 #define HT_SIG_SU_NSS_SHIFT 0x3 139 140 #define HAL_TID_INVALID 31 141 #define HAL_AST_IDX_INVALID 0xFFFF 142 143 #ifdef GET_MSDU_AGGREGATION 144 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 145 {\ 146 struct rx_msdu_end *rx_msdu_end;\ 147 bool first_msdu, last_msdu; \ 148 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 149 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 150 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 151 if (first_msdu && last_msdu)\ 152 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 153 else\ 154 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 155 } \ 156 157 #define HAL_RX_SET_MSDU_AGGREGATION((rs_mpdu), (rs_ppdu))\ 158 {\ 159 if (rs_mpdu->rs_flags & IEEE80211_AMSDU_FLAG)\ 160 rs_ppdu->rs_flags |= IEEE80211_AMSDU_FLAG;\ 161 } \ 162 163 #else 164 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 165 #define HAL_RX_SET_MSDU_AGGREGATION(rs_mpdu, rs_ppdu) 166 #endif 167 168 /* Max MPDUs per status buffer */ 169 #define HAL_RX_MAX_MPDU 256 170 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 171 #define HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER 16 172 173 /* Max pilot count */ 174 #define HAL_RX_MAX_SU_EVM_COUNT 32 175 176 /** 177 * struct hal_rx_mon_desc_info () - HAL Rx Monitor descriptor info 178 * 179 * @ppdu_id: PHY ppdu id 180 * @status_ppdu_id: status PHY ppdu id 181 * @status_buf_count: number of status buffer count 182 * @rxdma_push_reason: rxdma push reason 183 * @rxdma_error_code: rxdma error code 184 * @msdu_cnt: msdu count 185 * @end_of_ppdu: end of ppdu 186 * @link_desc: msdu link descriptor address 187 * @status_buf: for a PPDU, status buffers can span acrosss 188 * multiple buffers, status_buf points to first 189 * status buffer address of PPDU 190 * @drop_ppdu: flag to indicate current destination 191 * ring ppdu drop 192 */ 193 struct hal_rx_mon_desc_info { 194 uint16_t ppdu_id; 195 uint16_t status_ppdu_id; 196 uint8_t status_buf_count; 197 uint8_t rxdma_push_reason; 198 uint8_t rxdma_error_code; 199 uint8_t msdu_count; 200 uint8_t end_of_ppdu; 201 struct hal_buf_info link_desc; 202 struct hal_buf_info status_buf; 203 bool drop_ppdu; 204 }; 205 206 /* 207 * Struct hal_rx_su_evm_info - SU evm info 208 * @number_of_symbols: number of symbols 209 * @nss_count: nss count 210 * @pilot_count: pilot count 211 * @pilot_evm: Array of pilot evm values 212 */ 213 struct hal_rx_su_evm_info { 214 uint32_t number_of_symbols; 215 uint8_t nss_count; 216 uint8_t pilot_count; 217 uint32_t pilot_evm[HAL_RX_MAX_SU_EVM_COUNT]; 218 }; 219 220 enum { 221 DP_PPDU_STATUS_START, 222 DP_PPDU_STATUS_DONE, 223 }; 224 225 static inline 226 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 227 { 228 return data; 229 } 230 231 static inline 232 uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr) 233 { 234 struct rx_attention *rx_attn; 235 struct rx_mon_pkt_tlvs *rx_desc = 236 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 237 238 rx_attn = &rx_desc->attn_tlv.rx_attn; 239 240 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 241 } 242 243 static inline 244 uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr) 245 { 246 struct rx_attention *rx_attn; 247 struct rx_mon_pkt_tlvs *rx_desc = 248 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 249 250 rx_attn = &rx_desc->attn_tlv.rx_attn; 251 252 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 253 } 254 255 /* 256 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 257 * start TLV of Hardware TLV descriptor 258 * @hw_desc_addr: Hardware desciptor address 259 * 260 * Return: bool: if TLV tag match 261 */ 262 static inline 263 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 264 { 265 struct rx_mon_pkt_tlvs *rx_desc = 266 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 267 uint32_t tlv_tag; 268 269 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 270 &rx_desc->mpdu_start_tlv); 271 272 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 273 } 274 275 /* 276 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV user id in MPDU 277 * start TLV of Hardware TLV descriptor 278 * @hw_desc_addr: Hardware desciptor address 279 * 280 * Return: unit32_t: user id 281 */ 282 static inline 283 uint32_t HAL_RX_HW_DESC_MPDU_USER_ID(void *hw_desc_addr) 284 { 285 struct rx_mon_pkt_tlvs *rx_desc = 286 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 287 uint32_t user_id; 288 289 user_id = HAL_RX_GET_USER_TLV32_USERID( 290 &rx_desc->mpdu_start_tlv); 291 292 return user_id; 293 } 294 295 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 296 297 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 298 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 299 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 300 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 301 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 302 303 #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \ 304 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 305 (((struct reo_entrance_ring *)reo_ent_desc) \ 306 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 307 308 #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \ 309 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 310 (((struct reo_entrance_ring *)reo_ent_desc) \ 311 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 312 313 #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \ 314 (HAL_RX_BUF_COOKIE_GET(& \ 315 (((struct reo_entrance_ring *)reo_ent_desc) \ 316 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 317 318 /** 319 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 320 * cookie from the REO entrance ring element 321 * 322 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 323 * the current descriptor 324 * @ buf_info: structure to return the buffer information 325 * @ msdu_cnt: pointer to msdu count in MPDU 326 * Return: void 327 */ 328 static inline 329 void hal_rx_reo_ent_buf_paddr_get(hal_rxdma_desc_t rx_desc, 330 struct hal_buf_info *buf_info, 331 uint32_t *msdu_cnt 332 ) 333 { 334 struct reo_entrance_ring *reo_ent_ring = 335 (struct reo_entrance_ring *)rx_desc; 336 struct buffer_addr_info *buf_addr_info; 337 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 338 uint32_t loop_cnt; 339 340 rx_mpdu_desc_info_details = 341 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 342 343 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 344 RX_MPDU_DESC_INFO_0, MSDU_COUNT); 345 346 loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT); 347 348 buf_addr_info = 349 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 350 351 buf_info->paddr = 352 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 353 ((uint64_t) 354 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 355 356 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 357 buf_info->rbm = HAL_RX_BUF_RBM_GET(buf_addr_info); 358 359 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 360 "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 361 __func__, __LINE__, reo_ent_ring, buf_addr_info, 362 (unsigned long long)buf_info->paddr, loop_cnt); 363 } 364 365 static inline 366 void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 367 struct hal_buf_info *buf_info) 368 { 369 struct rx_msdu_link *msdu_link = 370 (struct rx_msdu_link *)rx_msdu_link_desc; 371 struct buffer_addr_info *buf_addr_info; 372 373 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 374 375 buf_info->paddr = 376 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 377 ((uint64_t) 378 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 379 380 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 381 buf_info->rbm = HAL_RX_BUF_RBM_GET(buf_addr_info); 382 } 383 384 /** 385 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 386 * 387 * @ soc : HAL version of the SOC pointer 388 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 389 * @ buf_addr_info : void pointer to the buffer_addr_info 390 * 391 * Return: void 392 */ 393 394 static inline 395 void hal_rx_mon_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 396 void *src_srng_desc, 397 hal_buff_addrinfo_t buf_addr_info) 398 { 399 struct buffer_addr_info *wbm_srng_buffer_addr_info = 400 (struct buffer_addr_info *)src_srng_desc; 401 uint64_t paddr; 402 struct buffer_addr_info *p_buffer_addr_info = 403 (struct buffer_addr_info *)buf_addr_info; 404 405 paddr = 406 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 407 ((uint64_t) 408 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 409 410 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 411 "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 412 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 413 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 414 415 /* Structure copy !!! */ 416 *wbm_srng_buffer_addr_info = 417 *((struct buffer_addr_info *)buf_addr_info); 418 } 419 420 static inline 421 uint32 hal_get_rx_msdu_link_desc_size(void) 422 { 423 return sizeof(struct rx_msdu_link); 424 } 425 426 enum { 427 HAL_PKT_TYPE_OFDM = 0, 428 HAL_PKT_TYPE_CCK, 429 HAL_PKT_TYPE_HT, 430 HAL_PKT_TYPE_VHT, 431 HAL_PKT_TYPE_HE, 432 }; 433 434 enum { 435 HAL_SGI_0_8_US, 436 HAL_SGI_0_4_US, 437 HAL_SGI_1_6_US, 438 HAL_SGI_3_2_US, 439 }; 440 441 enum { 442 HAL_FULL_RX_BW_20, 443 HAL_FULL_RX_BW_40, 444 HAL_FULL_RX_BW_80, 445 HAL_FULL_RX_BW_160, 446 }; 447 448 enum { 449 HAL_RX_TYPE_SU, 450 HAL_RX_TYPE_MU_MIMO, 451 HAL_RX_TYPE_MU_OFDMA, 452 HAL_RX_TYPE_MU_OFDMA_MIMO, 453 }; 454 455 /** 456 * enum 457 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 458 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decoded in HAL 459 * @HAL_RX_MON_PPDU_RESET: Not PPDU start and end TLV 460 */ 461 enum { 462 HAL_RX_MON_PPDU_START = 0, 463 HAL_RX_MON_PPDU_END, 464 HAL_RX_MON_PPDU_RESET, 465 }; 466 467 /* struct hal_rx_ppdu_common_info - common ppdu info 468 * @ppdu_id - ppdu id number 469 * @ppdu_timestamp - timestamp at ppdu received 470 * @mpdu_cnt_fcs_ok - mpdu count in ppdu with fcs ok 471 * @mpdu_cnt_fcs_err - mpdu count in ppdu with fcs err 472 * @mpdu_fcs_ok_bitmap - fcs ok mpdu count in ppdu bitmap 473 * @last_ppdu_id - last received ppdu id 474 * @mpdu_cnt - total mpdu count 475 * @num_users - num users 476 */ 477 struct hal_rx_ppdu_common_info { 478 uint32_t ppdu_id; 479 uint32_t ppdu_timestamp; 480 uint32_t mpdu_cnt_fcs_ok; 481 uint32_t mpdu_cnt_fcs_err; 482 uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 483 uint32_t last_ppdu_id; 484 uint32_t mpdu_cnt; 485 uint8_t num_users; 486 }; 487 488 /** 489 * struct hal_rx_msdu_payload_info - msdu payload info 490 * @first_msdu_payload: pointer to first msdu payload 491 * @payload_len: payload len 492 */ 493 struct hal_rx_msdu_payload_info { 494 uint8_t *first_msdu_payload; 495 uint32_t payload_len; 496 }; 497 498 /** 499 * struct hal_rx_nac_info - struct for neighbour info 500 * @fc_valid: flag indicate if it has valid frame control information 501 * @frame_control: frame control from each MPDU 502 * @to_ds_flag: flag indicate to_ds bit 503 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 504 * @mac_addr2: mac address2 in wh 505 * @mcast_bcast: multicast/broadcast 506 */ 507 struct hal_rx_nac_info { 508 uint8_t fc_valid; 509 uint16_t frame_control; 510 uint8_t to_ds_flag; 511 uint8_t mac_addr2_valid; 512 uint8_t mac_addr2[QDF_MAC_ADDR_SIZE]; 513 uint8_t mcast_bcast; 514 }; 515 516 /** 517 * struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs 518 * @cce_metadata: cached CCE metadata value received in the MSDU_END TLV 519 * @is_flow_idx_timeout: flag to indicate if flow search timeout occurred 520 * @is_flow_idx_invalid: flag to indicate if flow idx is valid or not 521 * @fse_metadata: cached FSE metadata value received in the MSDU END TLV 522 * @flow_idx: flow idx matched in FSE received in the MSDU END TLV 523 */ 524 struct hal_rx_ppdu_msdu_info { 525 uint16_t cce_metadata; 526 bool is_flow_idx_timeout; 527 bool is_flow_idx_invalid; 528 uint32_t fse_metadata; 529 uint32_t flow_idx; 530 }; 531 532 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 533 /** 534 * struct hal_rx_ppdu_cfr_user_info - struct for storing peer info extracted 535 * from HW TLVs, this will be used for correlating CFR data with multiple peers 536 * in MU PPDUs 537 * 538 * @peer_macaddr: macaddr of the peer 539 * @ast_index: AST index of the peer 540 */ 541 struct hal_rx_ppdu_cfr_user_info { 542 uint8_t peer_macaddr[QDF_MAC_ADDR_SIZE]; 543 uint32_t ast_index; 544 }; 545 546 /** 547 * struct hal_rx_ppdu_cfr_info - struct for storing ppdu info extracted from HW 548 * TLVs, this will be used for CFR correlation 549 * 550 * @bb_captured_channel : Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 551 * sent to PHY, SW checks it to correlate current PPDU TLVs with uploaded 552 * channel information. 553 * 554 * @bb_captured_timeout : Set by RxPCU to indicate channel capture condition is 555 * met, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due to AST delay, 556 * which means the rx_frame_falling edge to FREEZE TLV ready time exceeds 557 * the threshold time defined by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 558 * Bb_captured_reason is still valid in this case. 559 * 560 * @rx_location_info_valid: Indicates whether CFR DMA address in the PPDU TLV 561 * is valid 562 * <enum 0 rx_location_info_is_not_valid> 563 * <enum 1 rx_location_info_is_valid> 564 * <legal all> 565 * 566 * @bb_captured_reason : Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL 567 * TLV to here for FW usage. Valid when bb_captured_channel or 568 * bb_captured_timeout is set. 569 * <enum 0 freeze_reason_TM> 570 * <enum 1 freeze_reason_FTM> 571 * <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 572 * <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 573 * <enum 4 freeze_reason_NDPA_NDP> 574 * <enum 5 freeze_reason_ALL_PACKET> 575 * <legal 0-5> 576 * 577 * @rtt_che_buffer_pointer_low32 : The low 32 bits of the 40 bits pointer to 578 * external RTT channel information buffer 579 * 580 * @rtt_che_buffer_pointer_high8 : The high 8 bits of the 40 bits pointer to 581 * external RTT channel information buffer 582 * 583 * @chan_capture_status : capture status reported by ucode 584 * a. CAPTURE_IDLE: FW has disabled "REPETITIVE_CHE_CAPTURE_CTRL" 585 * b. CAPTURE_BUSY: previous PPDU’s channel capture upload DMA ongoing. (Note 586 * that this upload is triggered after receiving freeze_channel_capture TLV 587 * after last PPDU is rx) 588 * c. CAPTURE_ACTIVE: channel capture is enabled and no previous channel 589 * capture ongoing 590 * d. CAPTURE_NO_BUFFER: next buffer in IPC ring not available 591 * 592 * @cfr_user_info: Peer mac for upto 4 MU users 593 */ 594 595 struct hal_rx_ppdu_cfr_info { 596 bool bb_captured_channel; 597 bool bb_captured_timeout; 598 uint8_t bb_captured_reason; 599 bool rx_location_info_valid; 600 uint8_t chan_capture_status; 601 uint8_t rtt_che_buffer_pointer_high8; 602 uint32_t rtt_che_buffer_pointer_low32; 603 struct hal_rx_ppdu_cfr_user_info cfr_user_info[HAL_MAX_UL_MU_USERS]; 604 }; 605 #else 606 struct hal_rx_ppdu_cfr_info {}; 607 #endif 608 609 struct mon_rx_info { 610 uint8_t qos_control_info_valid; 611 uint16_t qos_control; 612 uint8_t mac_addr1_valid; 613 uint8_t mac_addr1[QDF_MAC_ADDR_SIZE]; 614 uint32_t user_id; 615 }; 616 617 struct mon_rx_user_info { 618 uint16_t qos_control; 619 uint8_t qos_control_info_valid; 620 }; 621 622 struct hal_rx_ppdu_info { 623 struct hal_rx_ppdu_common_info com_info; 624 struct mon_rx_status rx_status; 625 struct mon_rx_user_status rx_user_status[HAL_MAX_UL_MU_USERS]; 626 struct mon_rx_info rx_info; 627 struct mon_rx_user_info rx_user_info[HAL_MAX_UL_MU_USERS]; 628 struct hal_rx_msdu_payload_info msdu_info; 629 struct hal_rx_msdu_payload_info fcs_ok_msdu_info; 630 struct hal_rx_nac_info nac_info; 631 /* status ring PPDU start and end state */ 632 uint32_t rx_state; 633 /* MU user id for status ring TLV */ 634 uint32_t user_id; 635 /* MPDU/MSDU truncated to 128 bytes header start addr in status skb */ 636 unsigned char *data; 637 /* MPDU/MSDU truncated to 128 bytes header real length */ 638 uint32_t hdr_len; 639 /* MPDU FCS error */ 640 bool fcs_err; 641 /* Id to indicate how to process mpdu */ 642 uint8_t sw_frame_group_id; 643 struct hal_rx_ppdu_msdu_info rx_msdu_info[HAL_MAX_UL_MU_USERS]; 644 /* fcs passed mpdu count in rx monitor status buffer */ 645 uint8_t fcs_ok_cnt; 646 /* fcs error mpdu count in rx monitor status buffer */ 647 uint8_t fcs_err_cnt; 648 /* MPDU FCS passed */ 649 bool is_fcs_passed; 650 /* first msdu payload for all mpdus in rx monitor status buffer */ 651 struct hal_rx_msdu_payload_info ppdu_msdu_info[HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER]; 652 /* evm info */ 653 struct hal_rx_su_evm_info evm_info; 654 /** 655 * Will be used to store ppdu info extracted from HW TLVs, 656 * and for CFR correlation as well 657 */ 658 struct hal_rx_ppdu_cfr_info cfr_info; 659 }; 660 661 static inline uint32_t 662 hal_get_rx_status_buf_size(void) { 663 /* RX status buffer size is hard coded for now */ 664 return 2048; 665 } 666 667 static inline uint8_t* 668 hal_rx_status_get_next_tlv(uint8_t *rx_tlv) { 669 uint32_t tlv_len, tlv_tag; 670 671 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 672 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 673 674 /* The actual length of PPDU_END is the combined length of many PHY 675 * TLVs that follow. Skip the TLV header and 676 * rx_rxpcu_classification_overview that follows the header to get to 677 * next TLV. 678 */ 679 if (tlv_tag == WIFIRX_PPDU_END_E) 680 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 681 682 return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len + 683 HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3))); 684 } 685 686 /** 687 * hal_rx_proc_phyrx_other_receive_info_tlv() 688 * - process other receive info TLV 689 * @rx_tlv_hdr: pointer to TLV header 690 * @ppdu_info: pointer to ppdu_info 691 * 692 * Return: None 693 */ 694 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 695 void *rx_tlv_hdr, 696 struct hal_rx_ppdu_info 697 *ppdu_info) 698 { 699 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 700 (void *)ppdu_info); 701 } 702 703 /** 704 * hal_rx_status_get_tlv_info() - process receive info TLV 705 * @rx_tlv_hdr: pointer to TLV header 706 * @ppdu_info: pointer to ppdu_info 707 * @hal_soc: HAL soc handle 708 * @nbuf: PPDU status netowrk buffer 709 * 710 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 711 */ 712 static inline uint32_t 713 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 714 hal_soc_handle_t hal_soc_hdl, 715 qdf_nbuf_t nbuf) 716 { 717 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 718 719 return hal_soc->ops->hal_rx_status_get_tlv_info( 720 rx_tlv_hdr, 721 ppdu_info, 722 hal_soc_hdl, 723 nbuf); 724 } 725 726 static inline 727 uint32_t hal_get_rx_status_done_tlv_size(hal_soc_handle_t hal_soc_hdl) 728 { 729 return HAL_RX_TLV32_HDR_SIZE; 730 } 731 732 static inline QDF_STATUS 733 hal_get_rx_status_done(uint8_t *rx_tlv) 734 { 735 uint32_t tlv_tag; 736 737 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 738 739 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 740 return QDF_STATUS_SUCCESS; 741 else 742 return QDF_STATUS_E_EMPTY; 743 } 744 745 static inline QDF_STATUS 746 hal_clear_rx_status_done(uint8_t *rx_tlv) 747 { 748 *(uint32_t *)rx_tlv = 0; 749 return QDF_STATUS_SUCCESS; 750 } 751 752 #endif 753