1 /* 2 * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_API_MON_H_ 21 #define _HAL_API_MON_H_ 22 23 #include "qdf_types.h" 24 #include "hal_internal.h" 25 #include "hal_rx.h" 26 #include "hal_hw_headers.h" 27 #include <target_type.h> 28 29 #define HAL_RX_PHY_DATA_RADAR 0x01 30 #define HAL_SU_MU_CODING_LDPC 0x01 31 32 #define HAL_RX_FCS_LEN (4) 33 #define KEY_EXTIV 0x20 34 35 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 36 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 37 38 #define HAL_RX_TLV32_HDR_SIZE 4 39 40 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 41 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 42 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 43 HAL_RX_USER_TLV32_TYPE_LSB) 44 45 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 46 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 47 HAL_RX_USER_TLV32_LEN_MASK) >> \ 48 HAL_RX_USER_TLV32_LEN_LSB) 49 50 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 51 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 52 HAL_RX_USER_TLV32_USERID_MASK) >> \ 53 HAL_RX_USER_TLV32_USERID_LSB) 54 55 #define HAL_RX_TLV64_HDR_SIZE 8 56 57 #define HAL_RX_GET_USER_TLV64_TYPE(rx_status_tlv_ptr) \ 58 ((*((uint64_t *)(rx_status_tlv_ptr)) & \ 59 HAL_RX_USER_TLV64_TYPE_MASK) >> \ 60 HAL_RX_USER_TLV64_TYPE_LSB) 61 62 #define HAL_RX_GET_USER_TLV64_LEN(rx_status_tlv_ptr) \ 63 ((*((uint64_t *)(rx_status_tlv_ptr)) & \ 64 HAL_RX_USER_TLV64_LEN_MASK) >> \ 65 HAL_RX_USER_TLV64_LEN_LSB) 66 67 #define HAL_RX_GET_USER_TLV64_USERID(rx_status_tlv_ptr) \ 68 ((*((uint64_t *)(rx_status_tlv_ptr)) & \ 69 HAL_RX_USER_TLV64_USERID_MASK) >> \ 70 HAL_RX_USER_TLV64_USERID_LSB) 71 72 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 73 #define HAL_TLV_STATUS_PPDU_DONE 1 74 #define HAL_TLV_STATUS_BUF_DONE 2 75 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 76 #define HAL_TLV_STATUS_PPDU_START 4 77 #define HAL_TLV_STATUS_HEADER 5 78 #define HAL_TLV_STATUS_MPDU_END 6 79 #define HAL_TLV_STATUS_MSDU_START 7 80 #define HAL_TLV_STATUS_MSDU_END 8 81 #define HAL_TLV_STATUS_MON_BUF_ADDR 9 82 #define HAL_TLV_STATUS_MPDU_START 10 83 84 #define HAL_MAX_UL_MU_USERS 37 85 86 #define HAL_RX_PKT_TYPE_11A 0 87 #define HAL_RX_PKT_TYPE_11B 1 88 #define HAL_RX_PKT_TYPE_11N 2 89 #define HAL_RX_PKT_TYPE_11AC 3 90 #define HAL_RX_PKT_TYPE_11AX 4 91 #ifdef WLAN_FEATURE_11BE 92 #define HAL_RX_PKT_TYPE_11BE 6 93 #endif 94 95 #define HAL_RX_RECEPTION_TYPE_SU 0 96 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 97 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 98 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 99 100 /* Multiply rate by 2 to avoid float point 101 * and get rate in units of 500kbps 102 */ 103 #define HAL_11B_RATE_0MCS 11*2 104 #define HAL_11B_RATE_1MCS 5.5*2 105 #define HAL_11B_RATE_2MCS 2*2 106 #define HAL_11B_RATE_3MCS 1*2 107 #define HAL_11B_RATE_4MCS 11*2 108 #define HAL_11B_RATE_5MCS 5.5*2 109 #define HAL_11B_RATE_6MCS 2*2 110 111 #define HAL_11A_RATE_0MCS 48*2 112 #define HAL_11A_RATE_1MCS 24*2 113 #define HAL_11A_RATE_2MCS 12*2 114 #define HAL_11A_RATE_3MCS 6*2 115 #define HAL_11A_RATE_4MCS 54*2 116 #define HAL_11A_RATE_5MCS 36*2 117 #define HAL_11A_RATE_6MCS 18*2 118 #define HAL_11A_RATE_7MCS 9*2 119 120 #define HAL_LEGACY_MCS0 0 121 #define HAL_LEGACY_MCS1 1 122 #define HAL_LEGACY_MCS2 2 123 #define HAL_LEGACY_MCS3 3 124 #define HAL_LEGACY_MCS4 4 125 #define HAL_LEGACY_MCS5 5 126 #define HAL_LEGACY_MCS6 6 127 #define HAL_LEGACY_MCS7 7 128 129 #define HE_GI_0_8 0 130 #define HE_GI_0_4 1 131 #define HE_GI_1_6 2 132 #define HE_GI_3_2 3 133 134 #define HE_GI_RADIOTAP_0_8 0 135 #define HE_GI_RADIOTAP_1_6 1 136 #define HE_GI_RADIOTAP_3_2 2 137 #define HE_GI_RADIOTAP_RESERVED 3 138 139 #define HE_LTF_RADIOTAP_UNKNOWN 0 140 #define HE_LTF_RADIOTAP_1_X 1 141 #define HE_LTF_RADIOTAP_2_X 2 142 #define HE_LTF_RADIOTAP_4_X 3 143 144 #define HT_SGI_PRESENT 0x80 145 146 #define HE_LTF_1_X 0 147 #define HE_LTF_2_X 1 148 #define HE_LTF_4_X 2 149 #define HE_LTF_UNKNOWN 3 150 #define VHT_SIG_SU_NSS_MASK 0x7 151 #define HT_SIG_SU_NSS_SHIFT 0x3 152 153 #define HAL_TID_INVALID 31 154 #define HAL_AST_IDX_INVALID 0xFFFF 155 156 #ifdef GET_MSDU_AGGREGATION 157 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 158 {\ 159 struct rx_msdu_end *rx_msdu_end;\ 160 bool first_msdu, last_msdu; \ 161 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 162 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 163 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 164 if (first_msdu && last_msdu)\ 165 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 166 else\ 167 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 168 } \ 169 170 #define HAL_RX_SET_MSDU_AGGREGATION((rs_mpdu), (rs_ppdu))\ 171 {\ 172 if (rs_mpdu->rs_flags & IEEE80211_AMSDU_FLAG)\ 173 rs_ppdu->rs_flags |= IEEE80211_AMSDU_FLAG;\ 174 } \ 175 176 #else 177 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 178 #define HAL_RX_SET_MSDU_AGGREGATION(rs_mpdu, rs_ppdu) 179 #endif 180 181 /* Max MPDUs per status buffer */ 182 #define HAL_RX_MAX_MPDU 256 183 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 184 #define HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER 16 185 186 /* Max pilot count */ 187 #define HAL_RX_MAX_SU_EVM_COUNT 32 188 189 #define HAL_RX_FRAMECTRL_TYPE_MASK 0x0C 190 #define HAL_RX_GET_FRAME_CTRL_TYPE(fc)\ 191 (((fc) & HAL_RX_FRAMECTRL_TYPE_MASK) >> 2) 192 #define HAL_RX_FRAME_CTRL_TYPE_MGMT 0x0 193 #define HAL_RX_FRAME_CTRL_TYPE_CTRL 0x1 194 #define HAL_RX_FRAME_CTRL_TYPE_DATA 0x2 195 196 /** 197 * hal_dl_ul_flag - flag to indicate UL/DL 198 * @dl_ul_flag_is_dl_or_tdls: DL 199 * @dl_ul_flag_is_ul: UL 200 */ 201 enum hal_dl_ul_flag { 202 dl_ul_flag_is_dl_or_tdls, 203 dl_ul_flag_is_ul, 204 }; 205 206 /* 207 * hal_eht_ppdu_sig_cmn_type - PPDU type 208 * @eht_ppdu_sig_tb_or_dl_ofdma: TB/DL_OFDMA PPDU 209 * @eht_ppdu_sig_su: SU PPDU 210 * @eht_ppdu_sig_dl_mu_mimo: DL_MU_MIMO PPDU 211 */ 212 enum hal_eht_ppdu_sig_cmn_type { 213 eht_ppdu_sig_tb_or_dl_ofdma, 214 eht_ppdu_sig_su, 215 eht_ppdu_sig_dl_mu_mimo, 216 }; 217 218 /* 219 * hal_mon_packet_info - packet info 220 * @sw_cookie: 64-bit SW desc virtual address 221 * @dma_length: packet DMA length 222 * @msdu_continuation: msdu continulation in next buffer 223 * @truncated: packet is truncated 224 */ 225 struct hal_mon_packet_info { 226 uint64_t sw_cookie; 227 uint32_t dma_length : 16, 228 msdu_continuation : 1, 229 truncated : 1; 230 }; 231 232 /* 233 * hal_rx_mon_msdu_info - msdu info 234 * @first_buffer: first buffer of msdu 235 * @last_buffer: last buffer of msdu 236 * @first_mpdu: first MPDU 237 * @mpdu_length_err: MPDU length error 238 * @fcs_err: FCS error 239 * @first_msdu: first msdu 240 * @decap_type: decap type 241 * @last_msdu: last msdu 242 * @l3_header_padding: L3 padding header 243 * @stbc: stbc enabled 244 * @sgi: SGI value 245 * @reception_type: reception type 246 * @msdu_index: msdu index 247 * @buffer_len: buffer len 248 * @frag_len: frag len 249 * @msdu_len: msdu len 250 * @user_rssi: user rssi 251 */ 252 struct hal_rx_mon_msdu_info { 253 uint32_t first_buffer : 1, 254 last_buffer : 1, 255 first_mpdu : 1, 256 mpdu_length_err : 1, 257 fcs_err : 1, 258 first_msdu : 1, 259 decap_type : 3, 260 last_msdu : 1, 261 l3_header_padding : 3, 262 stbc : 1, 263 sgi : 2, 264 reception_type : 3, 265 msdu_index : 4; 266 uint16_t buffer_len : 12; 267 uint16_t frag_len : 12; 268 uint16_t msdu_len; 269 int16_t user_rssi; 270 }; 271 272 /* 273 * hal_rx_mon_mpdu_info - MPDU info 274 * @decap_type: decap_type 275 * @mpdu_length_err: MPDU length error 276 * @fcs_err: FCS error 277 * @overflow_err: overflow error 278 * @decrypt_err: decrypt error 279 * @mpdu_start_received: MPDU start received 280 * @full_pkt: Full MPDU received 281 * @first_rx_hdr_rcvd: First rx_hdr received 282 * @truncated: truncated MPDU 283 */ 284 struct hal_rx_mon_mpdu_info { 285 uint32_t decap_type : 8, 286 mpdu_length_err : 1, 287 fcs_err : 1, 288 overflow_err : 1, 289 decrypt_err : 1, 290 mpdu_start_received : 1, 291 full_pkt : 1, 292 first_rx_hdr_rcvd : 1, 293 truncated : 1; 294 }; 295 296 /** 297 * struct hal_rx_mon_desc_info () - HAL Rx Monitor descriptor info 298 * 299 * @ppdu_id: PHY ppdu id 300 * @status_ppdu_id: status PHY ppdu id 301 * @status_buf_count: number of status buffer count 302 * @rxdma_push_reason: rxdma push reason 303 * @rxdma_error_code: rxdma error code 304 * @msdu_cnt: msdu count 305 * @end_of_ppdu: end of ppdu 306 * @link_desc: msdu link descriptor address 307 * @status_buf: for a PPDU, status buffers can span acrosss 308 * multiple buffers, status_buf points to first 309 * status buffer address of PPDU 310 * @drop_ppdu: flag to indicate current destination 311 * ring ppdu drop 312 */ 313 struct hal_rx_mon_desc_info { 314 uint16_t ppdu_id; 315 uint16_t status_ppdu_id; 316 uint8_t status_buf_count; 317 uint8_t rxdma_push_reason; 318 uint8_t rxdma_error_code; 319 uint8_t msdu_count; 320 uint8_t end_of_ppdu; 321 struct hal_buf_info link_desc; 322 struct hal_buf_info status_buf; 323 bool drop_ppdu; 324 }; 325 326 /* 327 * Struct hal_rx_su_evm_info - SU evm info 328 * @number_of_symbols: number of symbols 329 * @nss_count: nss count 330 * @pilot_count: pilot count 331 * @pilot_evm: Array of pilot evm values 332 */ 333 struct hal_rx_su_evm_info { 334 uint32_t number_of_symbols; 335 uint8_t nss_count; 336 uint8_t pilot_count; 337 uint32_t pilot_evm[HAL_RX_MAX_SU_EVM_COUNT]; 338 }; 339 340 enum { 341 DP_PPDU_STATUS_START, 342 DP_PPDU_STATUS_DONE, 343 }; 344 345 /** 346 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 347 * cookie from the REO entrance ring element 348 * @hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 349 * the current descriptor 350 * @ buf_info: structure to return the buffer information 351 * @ msdu_cnt: pointer to msdu count in MPDU 352 * 353 * CAUTION: This API calls a hal_soc ops, so be careful before calling this in 354 * per packet path 355 * 356 * Return: void 357 */ 358 static inline 359 void hal_rx_reo_ent_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 360 hal_rxdma_desc_t rx_desc, 361 struct hal_buf_info *buf_info, 362 uint32_t *msdu_cnt) 363 { 364 struct reo_entrance_ring *reo_ent_ring = 365 (struct reo_entrance_ring *)rx_desc; 366 struct buffer_addr_info *buf_addr_info; 367 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 368 uint32_t loop_cnt; 369 370 rx_mpdu_desc_info_details = 371 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 372 373 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 374 HAL_RX_MPDU_DESC_INFO, MSDU_COUNT); 375 376 loop_cnt = HAL_RX_GET(reo_ent_ring, HAL_REO_ENTRANCE_RING, 377 LOOPING_COUNT); 378 379 buf_addr_info = 380 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 381 382 hal_rx_buf_cookie_rbm_get(hal_soc_hdl, (uint32_t *)buf_addr_info, 383 buf_info); 384 buf_info->paddr = 385 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 386 ((uint64_t) 387 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 388 389 dp_nofl_debug("[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 390 __func__, __LINE__, reo_ent_ring, buf_addr_info, 391 (unsigned long long)buf_info->paddr, loop_cnt); 392 } 393 394 static inline 395 void hal_rx_mon_next_link_desc_get(hal_soc_handle_t hal_soc_hdl, 396 void *rx_msdu_link_desc, 397 struct hal_buf_info *buf_info) 398 { 399 struct rx_msdu_link *msdu_link = 400 (struct rx_msdu_link *)rx_msdu_link_desc; 401 struct buffer_addr_info *buf_addr_info; 402 403 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 404 405 hal_rx_buf_cookie_rbm_get(hal_soc_hdl, (uint32_t *)buf_addr_info, 406 buf_info); 407 408 buf_info->paddr = 409 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 410 ((uint64_t) 411 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 412 } 413 414 static inline 415 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 416 { 417 return data; 418 } 419 420 static inline uint32_t 421 hal_rx_tlv_mpdu_len_err_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 422 { 423 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 424 425 if (!hal_soc || !hal_soc->ops) { 426 hal_err("hal handle is NULL"); 427 QDF_BUG(0); 428 return 0; 429 } 430 431 if (hal_soc->ops->hal_rx_tlv_mpdu_len_err_get) 432 return hal_soc->ops->hal_rx_tlv_mpdu_len_err_get(hw_desc_addr); 433 434 return 0; 435 } 436 437 static inline uint32_t 438 hal_rx_tlv_mpdu_fcs_err_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 439 { 440 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 441 442 if (!hal_soc || !hal_soc->ops) { 443 hal_err("hal handle is NULL"); 444 QDF_BUG(0); 445 return 0; 446 } 447 448 if (hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get) 449 return hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get(hw_desc_addr); 450 451 return 0; 452 } 453 454 #ifdef notyet 455 /* 456 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 457 * start TLV of Hardware TLV descriptor 458 * @hw_desc_addr: Hardware descriptor address 459 * 460 * Return: bool: if TLV tag match 461 */ 462 static inline 463 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 464 { 465 struct rx_mon_pkt_tlvs *rx_desc = 466 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 467 uint32_t tlv_tag; 468 469 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 470 471 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 472 } 473 #endif 474 475 /* 476 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV user id in MPDU 477 * start TLV of Hardware TLV descriptor 478 * @hw_desc_addr: Hardware descriptor address 479 * 480 * Return: unit32_t: user id 481 */ 482 static inline uint32_t 483 hal_rx_hw_desc_mpdu_user_id(hal_soc_handle_t hal_soc_hdl, 484 void *hw_desc_addr) 485 { 486 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 487 488 if (!hal_soc || !hal_soc->ops) { 489 hal_err("hal handle is NULL"); 490 QDF_BUG(0); 491 return 0; 492 } 493 494 if (hal_soc->ops->hal_rx_hw_desc_mpdu_user_id) 495 return hal_soc->ops->hal_rx_hw_desc_mpdu_user_id(hw_desc_addr); 496 497 return 0; 498 } 499 500 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 501 502 /** 503 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 504 * 505 * @ soc : HAL version of the SOC pointer 506 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 507 * @ buf_addr_info : void pointer to the buffer_addr_info 508 * 509 * Return: void 510 */ 511 static inline 512 void hal_rx_mon_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 513 void *src_srng_desc, 514 hal_buff_addrinfo_t buf_addr_info) 515 { 516 struct buffer_addr_info *wbm_srng_buffer_addr_info = 517 (struct buffer_addr_info *)src_srng_desc; 518 uint64_t paddr; 519 struct buffer_addr_info *p_buffer_addr_info = 520 (struct buffer_addr_info *)buf_addr_info; 521 522 paddr = 523 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 524 ((uint64_t) 525 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 526 527 dp_nofl_debug("[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 528 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 529 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 530 531 /* Structure copy !!! */ 532 *wbm_srng_buffer_addr_info = 533 *((struct buffer_addr_info *)buf_addr_info); 534 } 535 536 /** 537 * hal_get_rx_msdu_link_desc_size() - Get msdu link descriptor size 538 * 539 * Return: size of rx_msdu_link 540 */ 541 static inline 542 uint32_t hal_get_rx_msdu_link_desc_size(void) 543 { 544 return sizeof(struct rx_msdu_link); 545 } 546 547 enum { 548 HAL_PKT_TYPE_OFDM = 0, 549 HAL_PKT_TYPE_CCK, 550 HAL_PKT_TYPE_HT, 551 HAL_PKT_TYPE_VHT, 552 HAL_PKT_TYPE_HE, 553 }; 554 555 enum { 556 HAL_SGI_0_8_US, 557 HAL_SGI_0_4_US, 558 HAL_SGI_1_6_US, 559 HAL_SGI_3_2_US, 560 }; 561 562 #ifdef WLAN_FEATURE_11BE 563 enum { 564 HAL_FULL_RX_BW_20, 565 HAL_FULL_RX_BW_40, 566 HAL_FULL_RX_BW_80, 567 HAL_FULL_RX_BW_160, 568 HAL_FULL_RX_BW_320, 569 }; 570 #else 571 enum { 572 HAL_FULL_RX_BW_20, 573 HAL_FULL_RX_BW_40, 574 HAL_FULL_RX_BW_80, 575 HAL_FULL_RX_BW_160, 576 }; 577 #endif 578 579 enum { 580 HAL_RX_TYPE_SU, 581 HAL_RX_TYPE_MU_MIMO, 582 HAL_RX_TYPE_MU_OFDMA, 583 HAL_RX_TYPE_MU_OFDMA_MIMO, 584 }; 585 586 /* 587 * enum 588 * @HAL_RECEPTION_TYPE_SU: Basic SU reception 589 * @HAL_RECEPTION_TYPE_DL_MU_MIMO: DL MU_MIMO reception 590 * @HAL_RECEPTION_TYPE_DL_MU_OFMA: DL MU_OFMA reception 591 * @HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO: DL MU_OFDMA_MIMO reception 592 * @HAL_RECEPTION_TYPE_UL_MU_MIMO: UL MU_MIMO reception 593 * @HAL_RECEPTION_TYPE_UL_MU_OFDMA: UL MU_OFMA reception 594 * @HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO: UL MU_OFDMA_MIMO reception 595 */ 596 enum { 597 HAL_RECEPTION_TYPE_SU, 598 HAL_RECEPTION_TYPE_DL_MU_MIMO, 599 HAL_RECEPTION_TYPE_DL_MU_OFMA, 600 HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO, 601 HAL_RECEPTION_TYPE_UL_MU_MIMO, 602 HAL_RECEPTION_TYPE_UL_MU_OFDMA, 603 HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO 604 }; 605 606 /** 607 * enum 608 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 609 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decoded in HAL 610 * @HAL_RX_MON_PPDU_RESET: Not PPDU start and end TLV 611 */ 612 enum { 613 HAL_RX_MON_PPDU_START = 0, 614 HAL_RX_MON_PPDU_END, 615 HAL_RX_MON_PPDU_RESET, 616 }; 617 618 /* struct hal_rx_ppdu_common_info - common ppdu info 619 * @ppdu_id - ppdu id number 620 * @ppdu_timestamp - timestamp at ppdu received 621 * @mpdu_cnt_fcs_ok - mpdu count in ppdu with fcs ok 622 * @mpdu_cnt_fcs_err - mpdu count in ppdu with fcs err 623 * @mpdu_fcs_ok_bitmap - fcs ok mpdu count in ppdu bitmap 624 * @last_ppdu_id - last received ppdu id 625 * @mpdu_cnt - total mpdu count 626 * @num_users - num users 627 */ 628 struct hal_rx_ppdu_common_info { 629 uint32_t ppdu_id; 630 uint64_t ppdu_timestamp; 631 uint16_t mpdu_cnt_fcs_ok; 632 uint8_t mpdu_cnt_fcs_err; 633 uint8_t num_users; 634 uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 635 uint32_t last_ppdu_id; 636 uint16_t mpdu_cnt; 637 }; 638 639 /** 640 * struct hal_rx_msdu_payload_info - msdu payload info 641 * @first_msdu_payload: pointer to first msdu payload 642 * @payload_len: payload len 643 */ 644 struct hal_rx_msdu_payload_info { 645 uint8_t *first_msdu_payload; 646 uint8_t payload_len; 647 }; 648 649 /** 650 * struct hal_rx_nac_info - struct for neighbour info 651 * @fc_valid: flag indicate if it has valid frame control information 652 * @frame_control: frame control from each MPDU 653 * @to_ds_flag: flag indicate to_ds bit 654 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 655 * @mcast_bcast: multicast/broadcast 656 * @mac_addr2: mac address2 in wh 657 */ 658 struct hal_rx_nac_info { 659 uint32_t fc_valid : 1, 660 frame_control : 16, 661 to_ds_flag : 1, 662 mac_addr2_valid : 1, 663 mcast_bcast : 1; 664 uint8_t mac_addr2[QDF_MAC_ADDR_SIZE]; 665 }; 666 667 /** 668 * struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs 669 * @fse_metadata: cached FSE metadata value received in the MSDU END TLV 670 * @cce_metadata: cached CCE metadata value received in the MSDU_END TLV 671 * @is_flow_idx_timeout: flag to indicate if flow search timeout occurred 672 * @is_flow_idx_invalid: flag to indicate if flow idx is valid or not 673 * @flow_idx: flow idx matched in FSE received in the MSDU END TLV 674 */ 675 struct hal_rx_ppdu_msdu_info { 676 uint32_t fse_metadata; 677 uint32_t cce_metadata : 16, 678 is_flow_idx_timeout : 1, 679 is_flow_idx_invalid : 1; 680 uint32_t flow_idx : 20; 681 }; 682 683 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 684 /** 685 * struct hal_rx_ppdu_cfr_user_info - struct for storing peer info extracted 686 * from HW TLVs, this will be used for correlating CFR data with multiple peers 687 * in MU PPDUs 688 * 689 * @peer_macaddr: macaddr of the peer 690 * @ast_index: AST index of the peer 691 */ 692 struct hal_rx_ppdu_cfr_user_info { 693 uint8_t peer_macaddr[QDF_MAC_ADDR_SIZE]; 694 uint16_t ast_index; 695 }; 696 697 /** 698 * struct hal_rx_ppdu_cfr_info - struct for storing ppdu info extracted from HW 699 * TLVs, this will be used for CFR correlation 700 * 701 * @bb_captured_channel : Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 702 * sent to PHY, SW checks it to correlate current PPDU TLVs with uploaded 703 * channel information. 704 * 705 * @bb_captured_timeout : Set by RxPCU to indicate channel capture condition is 706 * met, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due to AST delay, 707 * which means the rx_frame_falling edge to FREEZE TLV ready time exceeds 708 * the threshold time defined by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 709 * Bb_captured_reason is still valid in this case. 710 * 711 * @rx_location_info_valid: Indicates whether CFR DMA address in the PPDU TLV 712 * is valid 713 * <enum 0 rx_location_info_is_not_valid> 714 * <enum 1 rx_location_info_is_valid> 715 * <legal all> 716 * 717 * @bb_captured_reason : Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL 718 * TLV to here for FW usage. Valid when bb_captured_channel or 719 * bb_captured_timeout is set. 720 * <enum 0 freeze_reason_TM> 721 * <enum 1 freeze_reason_FTM> 722 * <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 723 * <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 724 * <enum 4 freeze_reason_NDPA_NDP> 725 * <enum 5 freeze_reason_ALL_PACKET> 726 * <legal 0-5> 727 * 728 * @rtt_che_buffer_pointer_low32 : The low 32 bits of the 40 bits pointer to 729 * external RTT channel information buffer 730 * 731 * @rtt_che_buffer_pointer_high8 : The high 8 bits of the 40 bits pointer to 732 * external RTT channel information buffer 733 * 734 * @chan_capture_status : capture status reported by ucode 735 * a. CAPTURE_IDLE: FW has disabled "REPETITIVE_CHE_CAPTURE_CTRL" 736 * b. CAPTURE_BUSY: previous PPDU’s channel capture upload DMA ongoing. (Note 737 * that this upload is triggered after receiving freeze_channel_capture TLV 738 * after last PPDU is rx) 739 * c. CAPTURE_ACTIVE: channel capture is enabled and no previous channel 740 * capture ongoing 741 * d. CAPTURE_NO_BUFFER: next buffer in IPC ring not available 742 * 743 * @cfr_user_info: Peer mac for upto 4 MU users 744 * 745 * @rtt_cfo_measurement : raw cfo data extracted from hardware, which is 14 bit 746 * signed number. The first bit used for sign representation and 13 bits for 747 * fractional part. 748 * 749 * @agc_gain_info0: Chain 0 & chain 1 agc gain information reported by PHY 750 * 751 * @agc_gain_info1: Chain 2 & chain 3 agc gain information reported by PHY 752 * 753 * @agc_gain_info2: Chain 4 & chain 5 agc gain information reported by PHY 754 * 755 * @agc_gain_info3: Chain 6 & chain 7 agc gain information reported by PHY 756 * 757 * @rx_start_ts: Rx packet timestamp, the time the first L-STF ADC sample 758 * arrived at Rx antenna. 759 * 760 * @mcs_rate: Indicates the mcs/rate in which packet is received. 761 * If HT, 762 * 0-7: MCS0-MCS7 763 * If VHT, 764 * 0-9: MCS0 to MCS9 765 * If HE, 766 * 0-11: MCS0 to MCS11, 767 * 12-13: 4096QAM, 768 * 14-15: reserved 769 * If Legacy, 770 * 0: 48 Mbps 771 * 1: 24 Mbps 772 * 2: 12 Mbps 773 * 3: 6 Mbps 774 * 4: 54 Mbps 775 * 5: 36 Mbps 776 * 6: 18 Mbps 777 * 7: 9 Mbps 778 * 779 * @gi_type: Indicates the guard interval. 780 * 0: 0.8 us 781 * 1: 0.4 us 782 * 2: 1.6 us 783 * 3: 3.2 us 784 */ 785 struct hal_rx_ppdu_cfr_info { 786 bool bb_captured_channel; 787 bool bb_captured_timeout; 788 uint8_t bb_captured_reason; 789 bool rx_location_info_valid; 790 uint8_t chan_capture_status; 791 uint8_t rtt_che_buffer_pointer_high8; 792 uint32_t rtt_che_buffer_pointer_low32; 793 int16_t rtt_cfo_measurement; 794 uint32_t agc_gain_info0; 795 uint32_t agc_gain_info1; 796 uint32_t agc_gain_info2; 797 uint32_t agc_gain_info3; 798 uint32_t rx_start_ts; 799 uint32_t mcs_rate; 800 uint32_t gi_type; 801 }; 802 #else 803 struct hal_rx_ppdu_cfr_info {}; 804 #endif 805 806 struct mon_rx_info { 807 uint8_t qos_control_info_valid; 808 uint16_t qos_control; 809 uint8_t mac_addr1_valid; 810 uint8_t mac_addr1[QDF_MAC_ADDR_SIZE]; 811 uint16_t user_id; 812 }; 813 814 struct mon_rx_user_info { 815 uint16_t qos_control; 816 uint8_t qos_control_info_valid; 817 }; 818 819 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 820 struct hal_rx_frm_type_info { 821 uint8_t rx_mgmt_cnt; 822 uint8_t rx_ctrl_cnt; 823 uint8_t rx_data_cnt; 824 }; 825 #else 826 struct hal_rx_frm_type_info {}; 827 #endif 828 829 struct hal_mon_usig_cmn { 830 uint32_t phy_version : 3, 831 bw : 3, 832 ul_dl : 1, 833 bss_color : 6, 834 txop : 7, 835 disregard : 5, 836 validate_0 : 1, 837 reserved : 6; 838 }; 839 840 struct hal_mon_usig_tb { 841 uint32_t ppdu_type_comp_mode : 2, 842 validate_1 : 1, 843 spatial_reuse_1 : 4, 844 spatial_reuse_2 : 4, 845 disregard_1 : 5, 846 crc : 4, 847 tail : 6, 848 reserved : 5, 849 rx_integrity_check_passed : 1; 850 }; 851 852 struct hal_mon_usig_mu { 853 uint32_t ppdu_type_comp_mode : 2, 854 validate_1 : 1, 855 punc_ch_info : 5, 856 validate_2 : 1, 857 eht_sig_mcs : 2, 858 num_eht_sig_sym : 5, 859 crc : 4, 860 tail : 6, 861 reserved : 5, 862 rx_integrity_check_passed : 1; 863 }; 864 865 /** 866 * union hal_mon_usig_non_cmn: Version dependent USIG fields 867 * @tb: trigger based frame USIG header 868 * @mu: MU frame USIG header 869 */ 870 union hal_mon_usig_non_cmn { 871 struct hal_mon_usig_tb tb; 872 struct hal_mon_usig_mu mu; 873 }; 874 875 /** 876 * struct hal_mon_usig_hdr: U-SIG header for EHT (and subsequent) frames 877 * @usig_1: USIG common header fields 878 * @usig_2: USIG version dependent fields 879 */ 880 struct hal_mon_usig_hdr { 881 struct hal_mon_usig_cmn usig_1; 882 union hal_mon_usig_non_cmn usig_2; 883 }; 884 885 #define HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_MASK 0x0000000300000000 886 #define HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_LSB 32 887 888 #define HAL_RX_MON_USIG_GET_PPDU_TYPE_N_COMP_MODE(usig_tlv_ptr) \ 889 ((*((uint64_t *)(usig_tlv_ptr)) & \ 890 HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_MASK) >> \ 891 HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_LSB) 892 893 #define HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 894 #define HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_LSB 63 895 896 #define HAL_RX_MON_USIG_GET_RX_INTEGRITY_CHECK_PASSED(usig_tlv_ptr) \ 897 ((*((uint64_t *)(usig_tlv_ptr)) & \ 898 HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_MASK) >> \ 899 HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_LSB) 900 901 /** 902 * enum hal_eht_bw: Reception bandwidth 903 * @HAL_EHT_BW_20: 20Mhz 904 * @HAL_EHT_BW_40: 40Mhz 905 * @HAL_EHT_BW_80: 80Mhz 906 * @HAL_EHT_BW_160: 160Mhz 907 * @HAL_EHT_BW_320_1: 320_1 band 908 * @HAL_EHT_BW_320_2: 320_2 band 909 */ 910 enum hal_eht_bw { 911 HAL_EHT_BW_20 = 0, 912 HAL_EHT_BW_40, 913 HAL_EHT_BW_80, 914 HAL_EHT_BW_160, 915 HAL_EHT_BW_320_1, 916 HAL_EHT_BW_320_2, 917 }; 918 919 struct hal_eht_sig_mu_mimo_user_info { 920 uint32_t sta_id : 11, 921 mcs : 4, 922 coding : 1, 923 spatial_coding : 6, 924 crc : 4; 925 }; 926 927 struct hal_eht_sig_non_mu_mimo_user_info { 928 uint32_t sta_id : 11, 929 mcs : 4, 930 validate : 1, 931 nss : 4, 932 beamformed : 1, 933 coding : 1, 934 crc : 4; 935 }; 936 937 /** 938 * union hal_eht_sig_user_field: User field in EHTSIG 939 * @mu_mimo_usr: MU-MIMO user field information in EHTSIG 940 * @non_mu_mimo_usr: Non MU-MIMO user field information in EHTSIG 941 */ 942 union hal_eht_sig_user_field { 943 struct hal_eht_sig_mu_mimo_user_info mu_mimo_usr; 944 struct hal_eht_sig_non_mu_mimo_user_info non_mu_mimo_usr; 945 }; 946 947 struct hal_eht_sig_ofdma_cmn_eb1 { 948 uint64_t spatial_reuse : 4, 949 gi_ltf : 2, 950 num_ltf_sym : 3, 951 ldpc_extra_sym : 1, 952 pre_fec_pad_factor : 2, 953 pe_disambiguity : 1, 954 disregard : 4, 955 ru_allocation1_1 : 9, 956 ru_allocation1_2 : 9, 957 crc : 4; 958 }; 959 960 struct hal_eht_sig_ofdma_cmn_eb2 { 961 uint64_t ru_allocation2_1 : 9, 962 ru_allocation2_2 : 9, 963 ru_allocation2_3 : 9, 964 ru_allocation2_4 : 9, 965 ru_allocation2_5 : 9, 966 ru_allocation2_6 : 9, 967 crc : 4; 968 }; 969 970 struct hal_eht_sig_cc_usig_overflow { 971 uint32_t spatial_reuse : 4, 972 gi_ltf : 2, 973 num_ltf_sym : 3, 974 ldpc_extra_sym : 1, 975 pre_fec_pad_factor : 2, 976 pe_disambiguity : 1, 977 disregard : 4; 978 }; 979 980 struct hal_eht_sig_non_ofdma_cmn_eb { 981 uint32_t spatial_reuse : 4, 982 gi_ltf : 2, 983 num_ltf_sym : 3, 984 ldpc_extra_sym : 1, 985 pre_fec_pad_factor : 2, 986 pe_disambiguity : 1, 987 disregard : 4, 988 num_users : 3; 989 union hal_eht_sig_user_field user_field; 990 }; 991 992 struct hal_eht_sig_ndp_cmn_eb { 993 uint32_t spatial_reuse : 4, 994 gi_ltf : 2, 995 num_ltf_sym : 3, 996 nss : 4, 997 beamformed : 1, 998 disregard : 2, 999 crc : 4; 1000 }; 1001 1002 /* Different allowed RU in 11BE */ 1003 #define HAL_EHT_RU_26 0ULL 1004 #define HAL_EHT_RU_52 1ULL 1005 #define HAL_EHT_RU_78 2ULL 1006 #define HAL_EHT_RU_106 3ULL 1007 #define HAL_EHT_RU_132 4ULL 1008 #define HAL_EHT_RU_242 5ULL 1009 #define HAL_EHT_RU_484 6ULL 1010 #define HAL_EHT_RU_726 7ULL 1011 #define HAL_EHT_RU_996 8ULL 1012 #define HAL_EHT_RU_996x2 9ULL 1013 #define HAL_EHT_RU_996x3 10ULL 1014 #define HAL_EHT_RU_996x4 11ULL 1015 #define HAL_EHT_RU_NONE 15ULL 1016 #define HAL_EHT_RU_INVALID 31ULL 1017 /* 1018 * MRUs spanning above 80Mhz 1019 * HAL_EHT_RU_996_484 = HAL_EHT_RU_484 + HAL_EHT_RU_996 + 4 (reserved) 1020 */ 1021 #define HAL_EHT_RU_996_484 18ULL 1022 #define HAL_EHT_RU_996x2_484 28ULL 1023 #define HAL_EHT_RU_996x3_484 40ULL 1024 #define HAL_EHT_RU_996_484_242 23ULL 1025 1026 /** 1027 * enum ieee80211_eht_ru_size: RU type id in EHTSIG radiotap header 1028 * @IEEE80211_EHT_RU_26: RU26 1029 * @IEEE80211_EHT_RU_52: RU52 1030 * @IEEE80211_EHT_RU_106: RU106 1031 * @IEEE80211_EHT_RU_242: RU242 1032 * @IEEE80211_EHT_RU_484: RU484 1033 * @IEEE80211_EHT_RU_996: RU996 1034 * @IEEE80211_EHT_RU_996x2: RU996x2 1035 * @IEEE80211_EHT_RU_996x4: RU996x4 1036 * @IEEE80211_EHT_RU_52_26: RU52+RU26 1037 * @IEEE80211_EHT_RU_106_26: RU106+RU26 1038 * @IEEE80211_EHT_RU_484_242: RU484+RU242 1039 * @IEEE80211_EHT_RU_996_484: RU996+RU484 1040 * @IEEE80211_EHT_RU_996_484_242: RU996+RU484+RU242 1041 * @IEEE80211_EHT_RU_996x2_484: RU996x2 + RU484 1042 * @IEEE80211_EHT_RU_996x3: RU996x3 1043 * @IEEE80211_EHT_RU_996x3_484: RU996x3 + RU484 1044 * @IEEE80211_EHT_RU_INVALID: Invalid/Max RU 1045 */ 1046 enum ieee80211_eht_ru_size { 1047 IEEE80211_EHT_RU_26, 1048 IEEE80211_EHT_RU_52, 1049 IEEE80211_EHT_RU_106, 1050 IEEE80211_EHT_RU_242, 1051 IEEE80211_EHT_RU_484, 1052 IEEE80211_EHT_RU_996, 1053 IEEE80211_EHT_RU_996x2, 1054 IEEE80211_EHT_RU_996x4, 1055 IEEE80211_EHT_RU_52_26, 1056 IEEE80211_EHT_RU_106_26, 1057 IEEE80211_EHT_RU_484_242, 1058 IEEE80211_EHT_RU_996_484, 1059 IEEE80211_EHT_RU_996_484_242, 1060 IEEE80211_EHT_RU_996x2_484, 1061 IEEE80211_EHT_RU_996x3, 1062 IEEE80211_EHT_RU_996x3_484, 1063 IEEE80211_EHT_RU_INVALID, 1064 }; 1065 1066 #define NUM_RU_BITS_PER80 16 1067 #define NUM_RU_BITS_PER20 4 1068 1069 /* Different per_80Mhz band in 320Mhz bandwidth */ 1070 #define HAL_80_0 0 1071 #define HAL_80_1 1 1072 #define HAL_80_2 2 1073 #define HAL_80_3 3 1074 1075 #define HAL_RU_SHIFT(num_80mhz_band, ru_index_per_80) \ 1076 ((NUM_RU_BITS_PER80 * (num_80mhz_band)) + \ 1077 (NUM_RU_BITS_PER20 * (ru_index_per_80))) 1078 1079 /* MRU-996+484 */ 1080 #define HAL_EHT_RU_996_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ 1081 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_1, 0))) 1082 #define HAL_EHT_RU_996_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1083 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_1, 0))) 1084 #define HAL_EHT_RU_996_484_2 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1085 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1))) 1086 #define HAL_EHT_RU_996_484_3 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1087 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0))) 1088 #define HAL_EHT_RU_996_484_4 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ 1089 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_3, 0))) 1090 #define HAL_EHT_RU_996_484_5 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1091 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_3, 0))) 1092 #define HAL_EHT_RU_996_484_6 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1093 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) 1094 #define HAL_EHT_RU_996_484_7 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1095 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) 1096 1097 /* MRU-996x2+484 */ 1098 #define HAL_EHT_RU_996x2_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ 1099 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1100 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1101 #define HAL_EHT_RU_996x2_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1102 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1103 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1104 #define HAL_EHT_RU_996x2_484_2 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1105 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ 1106 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1107 #define HAL_EHT_RU_996x2_484_3 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1108 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1109 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1110 #define HAL_EHT_RU_996x2_484_4 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1111 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1112 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1))) 1113 #define HAL_EHT_RU_996x2_484_5 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1114 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1115 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0))) 1116 #define HAL_EHT_RU_996x2_484_6 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ 1117 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1118 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1119 #define HAL_EHT_RU_996x2_484_7 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1120 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1121 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1122 #define HAL_EHT_RU_996x2_484_8 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1123 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ 1124 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1125 #define HAL_EHT_RU_996x2_484_9 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1126 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1127 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1128 #define HAL_EHT_RU_996x2_484_10 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1129 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1130 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) 1131 #define HAL_EHT_RU_996x2_484_11 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1132 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1133 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) 1134 1135 /* MRU-996x3+484 */ 1136 #define HAL_EHT_RU_996x3_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ 1137 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1138 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1139 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1140 #define HAL_EHT_RU_996x3_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1141 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1142 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1143 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1144 #define HAL_EHT_RU_996x3_484_2 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1145 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ 1146 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1147 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1148 #define HAL_EHT_RU_996x3_484_3 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1149 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1150 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1151 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1152 #define HAL_EHT_RU_996x3_484_4 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1153 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1154 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ 1155 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1156 #define HAL_EHT_RU_996x3_484_5 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1157 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1158 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1159 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1160 #define HAL_EHT_RU_996x3_484_6 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1161 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1162 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1163 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) 1164 #define HAL_EHT_RU_996x3_484_7 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1165 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1166 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1167 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) 1168 1169 #define HAL_RX_MON_MAX_AGGR_SIZE 128 1170 1171 /** 1172 * struct hal_rx_tlv_aggr_info - Data structure to hold 1173 * metadata for aggregatng repeated TLVs 1174 * @in_progress: Flag to indicate if TLV aggregation is in progress 1175 * @cur_len: Total length of currently aggregated TLV 1176 * @tlv_tag: TLV tag which is currently being aggregated 1177 * @buf: Buffer containing aggregated TLV data 1178 */ 1179 struct hal_rx_tlv_aggr_info { 1180 uint8_t in_progress; 1181 uint16_t cur_len; 1182 uint32_t tlv_tag; 1183 uint8_t buf[HAL_RX_MON_MAX_AGGR_SIZE]; 1184 }; 1185 1186 /* struct hal_rx_u_sig_info - Certain fields from U-SIG header which are used 1187 * for other header field parsing. 1188 * @ul_dl: UL or DL 1189 * @bw: EHT BW 1190 * @ppdu_type_comp_mode: PPDU TYPE 1191 * @eht_sig_mcs: EHT SIG MCS 1192 * @num_eht_sig_sym: Number of EHT SIG symbols 1193 */ 1194 struct hal_rx_u_sig_info { 1195 uint32_t ul_dl : 1, 1196 bw : 3, 1197 ppdu_type_comp_mode : 2, 1198 eht_sig_mcs : 2, 1199 num_eht_sig_sym : 5; 1200 }; 1201 1202 #ifdef WLAN_SUPPORT_CTRL_FRAME_STATS 1203 struct hal_rx_user_ctrl_frm_info { 1204 uint8_t bar : 1, 1205 ndpa : 1; 1206 }; 1207 #else 1208 struct hal_rx_user_ctrl_frm_info {}; 1209 #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */ 1210 1211 struct hal_rx_ppdu_info { 1212 struct hal_rx_ppdu_common_info com_info; 1213 struct hal_rx_u_sig_info u_sig_info; 1214 struct mon_rx_status rx_status; 1215 struct mon_rx_user_status rx_user_status[HAL_MAX_UL_MU_USERS]; 1216 struct mon_rx_info rx_info; 1217 struct mon_rx_user_info rx_user_info[HAL_MAX_UL_MU_USERS]; 1218 struct hal_rx_msdu_payload_info msdu_info; 1219 struct hal_rx_msdu_payload_info fcs_ok_msdu_info; 1220 struct hal_rx_nac_info nac_info; 1221 /* status ring PPDU start and end state */ 1222 uint8_t rx_state; 1223 /* MU user id for status ring TLV */ 1224 uint8_t user_id; 1225 /* MPDU/MSDU truncated to 128 bytes header start addr in status skb */ 1226 unsigned char *data; 1227 /* MPDU/MSDU truncated to 128 bytes header real length */ 1228 uint32_t hdr_len; 1229 /* MPDU FCS error */ 1230 bool fcs_err; 1231 /* Id to indicate how to process mpdu */ 1232 uint8_t sw_frame_group_id; 1233 struct hal_rx_ppdu_msdu_info rx_msdu_info[HAL_MAX_UL_MU_USERS]; 1234 /* fcs passed mpdu count in rx monitor status buffer */ 1235 uint8_t fcs_ok_cnt; 1236 /* fcs error mpdu count in rx monitor status buffer */ 1237 uint8_t fcs_err_cnt; 1238 /* MPDU FCS passed */ 1239 bool is_fcs_passed; 1240 /* first msdu payload for all mpdus in rx monitor status buffer */ 1241 struct hal_rx_msdu_payload_info ppdu_msdu_info[HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER]; 1242 /* evm info */ 1243 struct hal_rx_su_evm_info evm_info; 1244 /** 1245 * Will be used to store ppdu info extracted from HW TLVs, 1246 * and for CFR correlation as well 1247 */ 1248 struct hal_rx_ppdu_cfr_info cfr_info; 1249 /* per frame type counts */ 1250 struct hal_rx_frm_type_info frm_type_info; 1251 /* TLV aggregation metadata context */ 1252 struct hal_rx_tlv_aggr_info tlv_aggr; 1253 /* EHT SIG user info */ 1254 uint32_t eht_sig_user_info; 1255 /*per user mpdu count */ 1256 uint8_t mpdu_count[HAL_MAX_UL_MU_USERS]; 1257 /*per user msdu count */ 1258 uint8_t msdu_count[HAL_MAX_UL_MU_USERS]; 1259 /* Placeholder to update per user last processed msdu’s info */ 1260 struct hal_rx_mon_msdu_info msdu[HAL_MAX_UL_MU_USERS]; 1261 /* Placeholder to update per user last processed mpdu’s info */ 1262 struct hal_rx_mon_mpdu_info mpdu_info[HAL_MAX_UL_MU_USERS]; 1263 /* placeholder to hold packet buffer info */ 1264 struct hal_mon_packet_info packet_info; 1265 #ifdef QCA_MONITOR_2_0_SUPPORT 1266 /* per user per MPDU queue */ 1267 qdf_nbuf_queue_t mpdu_q[HAL_MAX_UL_MU_USERS]; 1268 #endif 1269 /* ppdu info list element */ 1270 TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_list_elem; 1271 /* ppdu info free list element */ 1272 TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_free_list_elem; 1273 /* placeholder to track if RX_HDR is received */ 1274 uint8_t rx_hdr_rcvd[HAL_MAX_UL_MU_USERS]; 1275 /* Per user BAR and NDPA bit flag */ 1276 struct hal_rx_user_ctrl_frm_info ctrl_frm_info[HAL_MAX_UL_MU_USERS]; 1277 }; 1278 1279 static inline uint32_t 1280 hal_get_rx_status_buf_size(void) { 1281 /* RX status buffer size is hard coded for now */ 1282 return 2048; 1283 } 1284 1285 static inline uint8_t* 1286 hal_rx_status_get_next_tlv(uint8_t *rx_tlv, bool is_tlv_hdr_64_bit) { 1287 uint32_t tlv_len, tlv_tag, tlv_hdr_size; 1288 1289 if (is_tlv_hdr_64_bit) { 1290 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 1291 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1292 1293 tlv_hdr_size = HAL_RX_TLV64_HDR_SIZE; 1294 } else { 1295 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 1296 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1297 1298 tlv_hdr_size = HAL_RX_TLV32_HDR_SIZE; 1299 } 1300 1301 /* The actual length of PPDU_END is the combined length of many PHY 1302 * TLVs that follow. Skip the TLV header and 1303 * rx_rxpcu_classification_overview that follows the header to get to 1304 * next TLV. 1305 */ 1306 if (tlv_tag == WIFIRX_PPDU_END_E) 1307 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 1308 1309 return (uint8_t *)(uintptr_t)qdf_align((uint64_t)((uintptr_t)rx_tlv + 1310 tlv_len + 1311 tlv_hdr_size), 1312 tlv_hdr_size); 1313 } 1314 1315 /** 1316 * hal_rx_proc_phyrx_other_receive_info_tlv() 1317 * - process other receive info TLV 1318 * @rx_tlv_hdr: pointer to TLV header 1319 * @ppdu_info: pointer to ppdu_info 1320 * 1321 * Return: None 1322 */ 1323 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 1324 void *rx_tlv_hdr, 1325 struct hal_rx_ppdu_info 1326 *ppdu_info) 1327 { 1328 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 1329 (void *)ppdu_info); 1330 } 1331 1332 /** 1333 * hal_rx_status_get_tlv_info() - process receive info TLV 1334 * @rx_tlv_hdr: pointer to TLV header 1335 * @ppdu_info: pointer to ppdu_info 1336 * @hal_soc: HAL soc handle 1337 * @nbuf: PPDU status network buffer 1338 * 1339 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 1340 */ 1341 static inline uint32_t 1342 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 1343 hal_soc_handle_t hal_soc_hdl, 1344 qdf_nbuf_t nbuf) 1345 { 1346 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1347 1348 return hal_soc->ops->hal_rx_status_get_tlv_info( 1349 rx_tlv_hdr, 1350 ppdu_info, 1351 hal_soc_hdl, 1352 nbuf); 1353 } 1354 1355 static inline 1356 uint32_t hal_get_rx_status_done_tlv_size(hal_soc_handle_t hal_soc_hdl) 1357 { 1358 return HAL_RX_TLV32_HDR_SIZE; 1359 } 1360 1361 static inline QDF_STATUS 1362 hal_get_rx_status_done(uint8_t *rx_tlv) 1363 { 1364 uint32_t tlv_tag; 1365 1366 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1367 1368 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 1369 return QDF_STATUS_SUCCESS; 1370 else 1371 return QDF_STATUS_E_EMPTY; 1372 } 1373 1374 static inline QDF_STATUS 1375 hal_clear_rx_status_done(uint8_t *rx_tlv) 1376 { 1377 *(uint32_t *)rx_tlv = 0; 1378 return QDF_STATUS_SUCCESS; 1379 } 1380 #endif 1381