1 /* 2 * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_API_MON_H_ 21 #define _HAL_API_MON_H_ 22 23 #include "qdf_types.h" 24 #include "hal_internal.h" 25 #include "hal_rx.h" 26 #include "hal_hw_headers.h" 27 #include <target_type.h> 28 29 #define HAL_RX_PHY_DATA_RADAR 0x01 30 #define HAL_SU_MU_CODING_LDPC 0x01 31 32 #define HAL_RX_FCS_LEN (4) 33 #define KEY_EXTIV 0x20 34 35 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 36 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 37 38 #define HAL_RX_TLV32_HDR_SIZE 4 39 40 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 41 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 42 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 43 HAL_RX_USER_TLV32_TYPE_LSB) 44 45 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 46 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 47 HAL_RX_USER_TLV32_LEN_MASK) >> \ 48 HAL_RX_USER_TLV32_LEN_LSB) 49 50 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 51 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 52 HAL_RX_USER_TLV32_USERID_MASK) >> \ 53 HAL_RX_USER_TLV32_USERID_LSB) 54 55 #define HAL_RX_TLV64_HDR_SIZE 8 56 57 #define HAL_RX_GET_USER_TLV64_TYPE(rx_status_tlv_ptr) \ 58 ((*((uint64_t *)(rx_status_tlv_ptr)) & \ 59 HAL_RX_USER_TLV64_TYPE_MASK) >> \ 60 HAL_RX_USER_TLV64_TYPE_LSB) 61 62 #define HAL_RX_GET_USER_TLV64_LEN(rx_status_tlv_ptr) \ 63 ((*((uint64_t *)(rx_status_tlv_ptr)) & \ 64 HAL_RX_USER_TLV64_LEN_MASK) >> \ 65 HAL_RX_USER_TLV64_LEN_LSB) 66 67 #define HAL_RX_GET_USER_TLV64_USERID(rx_status_tlv_ptr) \ 68 ((*((uint64_t *)(rx_status_tlv_ptr)) & \ 69 HAL_RX_USER_TLV64_USERID_MASK) >> \ 70 HAL_RX_USER_TLV64_USERID_LSB) 71 72 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 73 #define HAL_TLV_STATUS_PPDU_DONE 1 74 #define HAL_TLV_STATUS_BUF_DONE 2 75 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 76 #define HAL_TLV_STATUS_PPDU_START 4 77 #define HAL_TLV_STATUS_HEADER 5 78 #define HAL_TLV_STATUS_MPDU_END 6 79 #define HAL_TLV_STATUS_MSDU_START 7 80 #define HAL_TLV_STATUS_MSDU_END 8 81 #define HAL_TLV_STATUS_MON_BUF_ADDR 9 82 #define HAL_TLV_STATUS_MPDU_START 10 83 #define HAL_TLV_STATUS_MON_DROP 11 84 85 #define HAL_MAX_UL_MU_USERS 37 86 87 #define HAL_RX_PKT_TYPE_11A 0 88 #define HAL_RX_PKT_TYPE_11B 1 89 #define HAL_RX_PKT_TYPE_11N 2 90 #define HAL_RX_PKT_TYPE_11AC 3 91 #define HAL_RX_PKT_TYPE_11AX 4 92 #ifdef WLAN_FEATURE_11BE 93 #define HAL_RX_PKT_TYPE_11BE 6 94 #endif 95 96 #define HAL_RX_RECEPTION_TYPE_SU 0 97 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 98 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 99 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 100 101 /* Multiply rate by 2 to avoid float point 102 * and get rate in units of 500kbps 103 */ 104 #define HAL_11B_RATE_0MCS 11*2 105 #define HAL_11B_RATE_1MCS 5.5*2 106 #define HAL_11B_RATE_2MCS 2*2 107 #define HAL_11B_RATE_3MCS 1*2 108 #define HAL_11B_RATE_4MCS 11*2 109 #define HAL_11B_RATE_5MCS 5.5*2 110 #define HAL_11B_RATE_6MCS 2*2 111 112 #define HAL_11A_RATE_0MCS 48*2 113 #define HAL_11A_RATE_1MCS 24*2 114 #define HAL_11A_RATE_2MCS 12*2 115 #define HAL_11A_RATE_3MCS 6*2 116 #define HAL_11A_RATE_4MCS 54*2 117 #define HAL_11A_RATE_5MCS 36*2 118 #define HAL_11A_RATE_6MCS 18*2 119 #define HAL_11A_RATE_7MCS 9*2 120 121 #define HAL_LEGACY_MCS0 0 122 #define HAL_LEGACY_MCS1 1 123 #define HAL_LEGACY_MCS2 2 124 #define HAL_LEGACY_MCS3 3 125 #define HAL_LEGACY_MCS4 4 126 #define HAL_LEGACY_MCS5 5 127 #define HAL_LEGACY_MCS6 6 128 #define HAL_LEGACY_MCS7 7 129 130 #define HE_GI_0_8 0 131 #define HE_GI_0_4 1 132 #define HE_GI_1_6 2 133 #define HE_GI_3_2 3 134 135 #define HE_GI_RADIOTAP_0_8 0 136 #define HE_GI_RADIOTAP_1_6 1 137 #define HE_GI_RADIOTAP_3_2 2 138 #define HE_GI_RADIOTAP_RESERVED 3 139 140 #define HE_LTF_RADIOTAP_UNKNOWN 0 141 #define HE_LTF_RADIOTAP_1_X 1 142 #define HE_LTF_RADIOTAP_2_X 2 143 #define HE_LTF_RADIOTAP_4_X 3 144 145 #define HT_SGI_PRESENT 0x80 146 147 #define HE_LTF_1_X 0 148 #define HE_LTF_2_X 1 149 #define HE_LTF_4_X 2 150 #define HE_LTF_UNKNOWN 3 151 #define VHT_SIG_SU_NSS_MASK 0x7 152 #define HT_SIG_SU_NSS_SHIFT 0x3 153 154 #define HAL_TID_INVALID 31 155 #define HAL_AST_IDX_INVALID 0xFFFF 156 157 #ifdef GET_MSDU_AGGREGATION 158 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 159 {\ 160 struct rx_msdu_end *rx_msdu_end;\ 161 bool first_msdu, last_msdu; \ 162 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 163 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 164 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 165 if (first_msdu && last_msdu)\ 166 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 167 else\ 168 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 169 } \ 170 171 #define HAL_RX_SET_MSDU_AGGREGATION((rs_mpdu), (rs_ppdu))\ 172 {\ 173 if (rs_mpdu->rs_flags & IEEE80211_AMSDU_FLAG)\ 174 rs_ppdu->rs_flags |= IEEE80211_AMSDU_FLAG;\ 175 } \ 176 177 #else 178 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 179 #define HAL_RX_SET_MSDU_AGGREGATION(rs_mpdu, rs_ppdu) 180 #endif 181 182 /* Max MPDUs per status buffer */ 183 #define HAL_RX_MAX_MPDU 256 184 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 185 #define HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER 16 186 187 /* Max pilot count */ 188 #define HAL_RX_MAX_SU_EVM_COUNT 32 189 190 #define HAL_RX_FRAMECTRL_TYPE_MASK 0x0C 191 #define HAL_RX_GET_FRAME_CTRL_TYPE(fc)\ 192 (((fc) & HAL_RX_FRAMECTRL_TYPE_MASK) >> 2) 193 #define HAL_RX_FRAME_CTRL_TYPE_MGMT 0x0 194 #define HAL_RX_FRAME_CTRL_TYPE_CTRL 0x1 195 #define HAL_RX_FRAME_CTRL_TYPE_DATA 0x2 196 197 /** 198 * hal_dl_ul_flag - flag to indicate UL/DL 199 * @dl_ul_flag_is_dl_or_tdls: DL 200 * @dl_ul_flag_is_ul: UL 201 */ 202 enum hal_dl_ul_flag { 203 dl_ul_flag_is_dl_or_tdls, 204 dl_ul_flag_is_ul, 205 }; 206 207 /* 208 * hal_eht_ppdu_sig_cmn_type - PPDU type 209 * @eht_ppdu_sig_tb_or_dl_ofdma: TB/DL_OFDMA PPDU 210 * @eht_ppdu_sig_su: SU PPDU 211 * @eht_ppdu_sig_dl_mu_mimo: DL_MU_MIMO PPDU 212 */ 213 enum hal_eht_ppdu_sig_cmn_type { 214 eht_ppdu_sig_tb_or_dl_ofdma, 215 eht_ppdu_sig_su, 216 eht_ppdu_sig_dl_mu_mimo, 217 }; 218 219 /* 220 * hal_mon_packet_info - packet info 221 * @sw_cookie: 64-bit SW desc virtual address 222 * @dma_length: packet DMA length 223 * @msdu_continuation: msdu continulation in next buffer 224 * @truncated: packet is truncated 225 */ 226 struct hal_mon_packet_info { 227 uint64_t sw_cookie; 228 uint32_t dma_length : 16, 229 msdu_continuation : 1, 230 truncated : 1; 231 }; 232 233 /* 234 * hal_rx_mon_msdu_info - msdu info 235 * @first_buffer: first buffer of msdu 236 * @last_buffer: last buffer of msdu 237 * @first_mpdu: first MPDU 238 * @mpdu_length_err: MPDU length error 239 * @fcs_err: FCS error 240 * @first_msdu: first msdu 241 * @decap_type: decap type 242 * @last_msdu: last msdu 243 * @l3_header_padding: L3 padding header 244 * @stbc: stbc enabled 245 * @sgi: SGI value 246 * @reception_type: reception type 247 * @msdu_index: msdu index 248 * @buffer_len: buffer len 249 * @frag_len: frag len 250 * @msdu_len: msdu len 251 * @user_rssi: user rssi 252 */ 253 struct hal_rx_mon_msdu_info { 254 uint32_t first_buffer : 1, 255 last_buffer : 1, 256 first_mpdu : 1, 257 mpdu_length_err : 1, 258 fcs_err : 1, 259 first_msdu : 1, 260 decap_type : 3, 261 last_msdu : 1, 262 l3_header_padding : 3, 263 stbc : 1, 264 sgi : 2, 265 reception_type : 3, 266 msdu_index : 4; 267 uint16_t buffer_len : 12; 268 uint16_t frag_len : 12; 269 uint16_t msdu_len; 270 int16_t user_rssi; 271 }; 272 273 /* 274 * hal_rx_mon_mpdu_info - MPDU info 275 * @decap_type: decap_type 276 * @mpdu_length_err: MPDU length error 277 * @fcs_err: FCS error 278 * @overflow_err: overflow error 279 * @decrypt_err: decrypt error 280 * @mpdu_start_received: MPDU start received 281 * @full_pkt: Full MPDU received 282 * @first_rx_hdr_rcvd: First rx_hdr received 283 * @truncated: truncated MPDU 284 */ 285 struct hal_rx_mon_mpdu_info { 286 uint32_t decap_type : 8, 287 mpdu_length_err : 1, 288 fcs_err : 1, 289 overflow_err : 1, 290 decrypt_err : 1, 291 mpdu_start_received : 1, 292 full_pkt : 1, 293 first_rx_hdr_rcvd : 1, 294 truncated : 1; 295 }; 296 297 /** 298 * struct hal_rx_mon_desc_info () - HAL Rx Monitor descriptor info 299 * 300 * @ppdu_id: PHY ppdu id 301 * @status_ppdu_id: status PHY ppdu id 302 * @status_buf_count: number of status buffer count 303 * @rxdma_push_reason: rxdma push reason 304 * @rxdma_error_code: rxdma error code 305 * @msdu_cnt: msdu count 306 * @end_of_ppdu: end of ppdu 307 * @link_desc: msdu link descriptor address 308 * @status_buf: for a PPDU, status buffers can span acrosss 309 * multiple buffers, status_buf points to first 310 * status buffer address of PPDU 311 * @drop_ppdu: flag to indicate current destination 312 * ring ppdu drop 313 */ 314 struct hal_rx_mon_desc_info { 315 uint16_t ppdu_id; 316 uint16_t status_ppdu_id; 317 uint8_t status_buf_count; 318 uint8_t rxdma_push_reason; 319 uint8_t rxdma_error_code; 320 uint8_t msdu_count; 321 uint8_t end_of_ppdu; 322 struct hal_buf_info link_desc; 323 struct hal_buf_info status_buf; 324 bool drop_ppdu; 325 }; 326 327 /* 328 * Struct hal_rx_su_evm_info - SU evm info 329 * @number_of_symbols: number of symbols 330 * @nss_count: nss count 331 * @pilot_count: pilot count 332 * @pilot_evm: Array of pilot evm values 333 */ 334 struct hal_rx_su_evm_info { 335 uint32_t number_of_symbols; 336 uint8_t nss_count; 337 uint8_t pilot_count; 338 uint32_t pilot_evm[HAL_RX_MAX_SU_EVM_COUNT]; 339 }; 340 341 enum { 342 DP_PPDU_STATUS_START, 343 DP_PPDU_STATUS_DONE, 344 }; 345 346 /** 347 * struct hal_rx_ppdu_drop_cnt - PPDU drop count 348 * @ppdu_drop_cnt: PPDU drop count 349 * @mpdu_drop_cnt: MPDU drop count 350 * @end_of_ppdu_drop_cnt: End of PPDU drop count 351 * @tlv_drop_cnt: TLV drop count 352 */ 353 struct hal_rx_ppdu_drop_cnt { 354 uint8_t ppdu_drop_cnt; 355 uint16_t mpdu_drop_cnt; 356 uint8_t end_of_ppdu_drop_cnt; 357 uint16_t tlv_drop_cnt; 358 }; 359 360 static inline QDF_STATUS 361 hal_rx_reo_ent_get_src_link_id(hal_soc_handle_t hal_soc_hdl, 362 hal_rxdma_desc_t rx_desc, 363 uint8_t *src_link_id) 364 { 365 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 366 367 if (!hal_soc || !hal_soc->ops) { 368 hal_err("hal handle is NULL"); 369 QDF_BUG(0); 370 return QDF_STATUS_E_INVAL; 371 } 372 373 if (hal_soc->ops->hal_rx_reo_ent_get_src_link_id) 374 return hal_soc->ops->hal_rx_reo_ent_get_src_link_id(rx_desc, 375 src_link_id); 376 377 return QDF_STATUS_E_INVAL; 378 } 379 380 /** 381 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 382 * cookie from the REO entrance ring element 383 * @hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 384 * the current descriptor 385 * @ buf_info: structure to return the buffer information 386 * @ msdu_cnt: pointer to msdu count in MPDU 387 * 388 * CAUTION: This API calls a hal_soc ops, so be careful before calling this in 389 * per packet path 390 * 391 * Return: void 392 */ 393 static inline 394 void hal_rx_reo_ent_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 395 hal_rxdma_desc_t rx_desc, 396 struct hal_buf_info *buf_info, 397 uint32_t *msdu_cnt) 398 { 399 struct reo_entrance_ring *reo_ent_ring = 400 (struct reo_entrance_ring *)rx_desc; 401 struct buffer_addr_info *buf_addr_info; 402 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 403 uint32_t loop_cnt; 404 405 rx_mpdu_desc_info_details = 406 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 407 408 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 409 HAL_RX_MPDU_DESC_INFO, MSDU_COUNT); 410 411 loop_cnt = HAL_RX_GET(reo_ent_ring, HAL_REO_ENTRANCE_RING, 412 LOOPING_COUNT); 413 414 buf_addr_info = 415 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 416 417 hal_rx_buf_cookie_rbm_get(hal_soc_hdl, (uint32_t *)buf_addr_info, 418 buf_info); 419 buf_info->paddr = 420 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 421 ((uint64_t) 422 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 423 424 dp_nofl_debug("[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 425 __func__, __LINE__, reo_ent_ring, buf_addr_info, 426 (unsigned long long)buf_info->paddr, loop_cnt); 427 } 428 429 static inline 430 void hal_rx_mon_next_link_desc_get(hal_soc_handle_t hal_soc_hdl, 431 void *rx_msdu_link_desc, 432 struct hal_buf_info *buf_info) 433 { 434 struct rx_msdu_link *msdu_link = 435 (struct rx_msdu_link *)rx_msdu_link_desc; 436 struct buffer_addr_info *buf_addr_info; 437 438 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 439 440 hal_rx_buf_cookie_rbm_get(hal_soc_hdl, (uint32_t *)buf_addr_info, 441 buf_info); 442 443 buf_info->paddr = 444 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 445 ((uint64_t) 446 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 447 } 448 449 static inline 450 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 451 { 452 return data; 453 } 454 455 static inline uint32_t 456 hal_rx_tlv_mpdu_len_err_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 457 { 458 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 459 460 if (!hal_soc || !hal_soc->ops) { 461 hal_err("hal handle is NULL"); 462 QDF_BUG(0); 463 return 0; 464 } 465 466 if (hal_soc->ops->hal_rx_tlv_mpdu_len_err_get) 467 return hal_soc->ops->hal_rx_tlv_mpdu_len_err_get(hw_desc_addr); 468 469 return 0; 470 } 471 472 static inline uint32_t 473 hal_rx_tlv_mpdu_fcs_err_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 474 { 475 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 476 477 if (!hal_soc || !hal_soc->ops) { 478 hal_err("hal handle is NULL"); 479 QDF_BUG(0); 480 return 0; 481 } 482 483 if (hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get) 484 return hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get(hw_desc_addr); 485 486 return 0; 487 } 488 489 #ifdef notyet 490 /* 491 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 492 * start TLV of Hardware TLV descriptor 493 * @hw_desc_addr: Hardware descriptor address 494 * 495 * Return: bool: if TLV tag match 496 */ 497 static inline 498 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 499 { 500 struct rx_mon_pkt_tlvs *rx_desc = 501 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 502 uint32_t tlv_tag; 503 504 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 505 506 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 507 } 508 #endif 509 510 /* 511 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV user id in MPDU 512 * start TLV of Hardware TLV descriptor 513 * @hw_desc_addr: Hardware descriptor address 514 * 515 * Return: unit32_t: user id 516 */ 517 static inline uint32_t 518 hal_rx_hw_desc_mpdu_user_id(hal_soc_handle_t hal_soc_hdl, 519 void *hw_desc_addr) 520 { 521 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 522 523 if (!hal_soc || !hal_soc->ops) { 524 hal_err("hal handle is NULL"); 525 QDF_BUG(0); 526 return 0; 527 } 528 529 if (hal_soc->ops->hal_rx_hw_desc_mpdu_user_id) 530 return hal_soc->ops->hal_rx_hw_desc_mpdu_user_id(hw_desc_addr); 531 532 return 0; 533 } 534 535 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 536 537 /** 538 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 539 * 540 * @ soc : HAL version of the SOC pointer 541 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 542 * @ buf_addr_info : void pointer to the buffer_addr_info 543 * 544 * Return: void 545 */ 546 static inline 547 void hal_rx_mon_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 548 void *src_srng_desc, 549 hal_buff_addrinfo_t buf_addr_info) 550 { 551 struct buffer_addr_info *wbm_srng_buffer_addr_info = 552 (struct buffer_addr_info *)src_srng_desc; 553 uint64_t paddr; 554 struct buffer_addr_info *p_buffer_addr_info = 555 (struct buffer_addr_info *)buf_addr_info; 556 557 paddr = 558 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 559 ((uint64_t) 560 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 561 562 dp_nofl_debug("[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 563 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 564 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 565 566 /* Structure copy !!! */ 567 *wbm_srng_buffer_addr_info = 568 *((struct buffer_addr_info *)buf_addr_info); 569 } 570 571 /** 572 * hal_get_rx_msdu_link_desc_size() - Get msdu link descriptor size 573 * 574 * Return: size of rx_msdu_link 575 */ 576 static inline 577 uint32_t hal_get_rx_msdu_link_desc_size(void) 578 { 579 return sizeof(struct rx_msdu_link); 580 } 581 582 enum { 583 HAL_PKT_TYPE_OFDM = 0, 584 HAL_PKT_TYPE_CCK, 585 HAL_PKT_TYPE_HT, 586 HAL_PKT_TYPE_VHT, 587 HAL_PKT_TYPE_HE, 588 }; 589 590 enum { 591 HAL_SGI_0_8_US, 592 HAL_SGI_0_4_US, 593 HAL_SGI_1_6_US, 594 HAL_SGI_3_2_US, 595 }; 596 597 #ifdef WLAN_FEATURE_11BE 598 enum { 599 HAL_FULL_RX_BW_20, 600 HAL_FULL_RX_BW_40, 601 HAL_FULL_RX_BW_80, 602 HAL_FULL_RX_BW_160, 603 HAL_FULL_RX_BW_320, 604 }; 605 #else 606 enum { 607 HAL_FULL_RX_BW_20, 608 HAL_FULL_RX_BW_40, 609 HAL_FULL_RX_BW_80, 610 HAL_FULL_RX_BW_160, 611 }; 612 #endif 613 614 enum { 615 HAL_RX_TYPE_SU, 616 HAL_RX_TYPE_MU_MIMO, 617 HAL_RX_TYPE_MU_OFDMA, 618 HAL_RX_TYPE_MU_OFDMA_MIMO, 619 }; 620 621 enum { 622 HAL_RX_TYPE_DL, 623 HAL_RX_TYPE_UL, 624 }; 625 626 /* 627 * enum 628 * @HAL_RECEPTION_TYPE_SU: Basic SU reception 629 * @HAL_RECEPTION_TYPE_DL_MU_MIMO: DL MU_MIMO reception 630 * @HAL_RECEPTION_TYPE_DL_MU_OFMA: DL MU_OFMA reception 631 * @HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO: DL MU_OFDMA_MIMO reception 632 * @HAL_RECEPTION_TYPE_UL_MU_MIMO: UL MU_MIMO reception 633 * @HAL_RECEPTION_TYPE_UL_MU_OFDMA: UL MU_OFMA reception 634 * @HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO: UL MU_OFDMA_MIMO reception 635 */ 636 enum { 637 HAL_RECEPTION_TYPE_SU, 638 HAL_RECEPTION_TYPE_DL_MU_MIMO, 639 HAL_RECEPTION_TYPE_DL_MU_OFMA, 640 HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO, 641 HAL_RECEPTION_TYPE_UL_MU_MIMO, 642 HAL_RECEPTION_TYPE_UL_MU_OFDMA, 643 HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO 644 }; 645 646 /** 647 * enum 648 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 649 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decoded in HAL 650 * @HAL_RX_MON_PPDU_RESET: Not PPDU start and end TLV 651 */ 652 enum { 653 HAL_RX_MON_PPDU_START = 0, 654 HAL_RX_MON_PPDU_END, 655 HAL_RX_MON_PPDU_RESET, 656 }; 657 658 /* struct hal_rx_ppdu_common_info - common ppdu info 659 * @ppdu_id - ppdu id number 660 * @ppdu_timestamp - timestamp at ppdu received 661 * @mpdu_cnt_fcs_ok - mpdu count in ppdu with fcs ok 662 * @mpdu_cnt_fcs_err - mpdu count in ppdu with fcs err 663 * @mpdu_fcs_ok_bitmap - fcs ok mpdu count in ppdu bitmap 664 * @last_ppdu_id - last received ppdu id 665 * @mpdu_cnt - total mpdu count 666 * @num_users - num users 667 */ 668 struct hal_rx_ppdu_common_info { 669 uint32_t ppdu_id; 670 uint64_t ppdu_timestamp; 671 uint16_t mpdu_cnt_fcs_ok; 672 uint8_t mpdu_cnt_fcs_err; 673 uint8_t num_users; 674 uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 675 uint32_t last_ppdu_id; 676 uint16_t mpdu_cnt; 677 }; 678 679 /** 680 * struct hal_rx_msdu_payload_info - msdu payload info 681 * @first_msdu_payload: pointer to first msdu payload 682 * @payload_len: payload len 683 */ 684 struct hal_rx_msdu_payload_info { 685 uint8_t *first_msdu_payload; 686 uint8_t payload_len; 687 }; 688 689 /** 690 * struct hal_rx_nac_info - struct for neighbour info 691 * @fc_valid: flag indicate if it has valid frame control information 692 * @frame_control: frame control from each MPDU 693 * @to_ds_flag: flag indicate to_ds bit 694 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 695 * @mcast_bcast: multicast/broadcast 696 * @mac_addr2: mac address2 in wh 697 */ 698 struct hal_rx_nac_info { 699 uint32_t fc_valid : 1, 700 frame_control : 16, 701 to_ds_flag : 1, 702 mac_addr2_valid : 1, 703 mcast_bcast : 1; 704 uint8_t mac_addr2[QDF_MAC_ADDR_SIZE]; 705 }; 706 707 /** 708 * struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs 709 * @fse_metadata: cached FSE metadata value received in the MSDU END TLV 710 * @cce_metadata: cached CCE metadata value received in the MSDU_END TLV 711 * @is_flow_idx_timeout: flag to indicate if flow search timeout occurred 712 * @is_flow_idx_invalid: flag to indicate if flow idx is valid or not 713 * @flow_idx: flow idx matched in FSE received in the MSDU END TLV 714 */ 715 struct hal_rx_ppdu_msdu_info { 716 uint32_t fse_metadata; 717 uint32_t cce_metadata : 16, 718 is_flow_idx_timeout : 1, 719 is_flow_idx_invalid : 1; 720 uint32_t flow_idx : 20; 721 }; 722 723 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 724 /** 725 * struct hal_rx_ppdu_cfr_user_info - struct for storing peer info extracted 726 * from HW TLVs, this will be used for correlating CFR data with multiple peers 727 * in MU PPDUs 728 * 729 * @peer_macaddr: macaddr of the peer 730 * @ast_index: AST index of the peer 731 */ 732 struct hal_rx_ppdu_cfr_user_info { 733 uint8_t peer_macaddr[QDF_MAC_ADDR_SIZE]; 734 uint16_t ast_index; 735 }; 736 737 /** 738 * struct hal_rx_ppdu_cfr_info - struct for storing ppdu info extracted from HW 739 * TLVs, this will be used for CFR correlation 740 * 741 * @bb_captured_channel : Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 742 * sent to PHY, SW checks it to correlate current PPDU TLVs with uploaded 743 * channel information. 744 * 745 * @bb_captured_timeout : Set by RxPCU to indicate channel capture condition is 746 * met, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due to AST delay, 747 * which means the rx_frame_falling edge to FREEZE TLV ready time exceeds 748 * the threshold time defined by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 749 * Bb_captured_reason is still valid in this case. 750 * 751 * @rx_location_info_valid: Indicates whether CFR DMA address in the PPDU TLV 752 * is valid 753 * <enum 0 rx_location_info_is_not_valid> 754 * <enum 1 rx_location_info_is_valid> 755 * <legal all> 756 * 757 * @bb_captured_reason : Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL 758 * TLV to here for FW usage. Valid when bb_captured_channel or 759 * bb_captured_timeout is set. 760 * <enum 0 freeze_reason_TM> 761 * <enum 1 freeze_reason_FTM> 762 * <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 763 * <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 764 * <enum 4 freeze_reason_NDPA_NDP> 765 * <enum 5 freeze_reason_ALL_PACKET> 766 * <legal 0-5> 767 * 768 * @rtt_che_buffer_pointer_low32 : The low 32 bits of the 40 bits pointer to 769 * external RTT channel information buffer 770 * 771 * @rtt_che_buffer_pointer_high8 : The high 8 bits of the 40 bits pointer to 772 * external RTT channel information buffer 773 * 774 * @chan_capture_status : capture status reported by ucode 775 * a. CAPTURE_IDLE: FW has disabled "REPETITIVE_CHE_CAPTURE_CTRL" 776 * b. CAPTURE_BUSY: previous PPDU’s channel capture upload DMA ongoing. (Note 777 * that this upload is triggered after receiving freeze_channel_capture TLV 778 * after last PPDU is rx) 779 * c. CAPTURE_ACTIVE: channel capture is enabled and no previous channel 780 * capture ongoing 781 * d. CAPTURE_NO_BUFFER: next buffer in IPC ring not available 782 * 783 * @cfr_user_info: Peer mac for upto 4 MU users 784 * 785 * @rtt_cfo_measurement : raw cfo data extracted from hardware, which is 14 bit 786 * signed number. The first bit used for sign representation and 13 bits for 787 * fractional part. 788 * 789 * @agc_gain_info0: Chain 0 & chain 1 agc gain information reported by PHY 790 * 791 * @agc_gain_info1: Chain 2 & chain 3 agc gain information reported by PHY 792 * 793 * @agc_gain_info2: Chain 4 & chain 5 agc gain information reported by PHY 794 * 795 * @agc_gain_info3: Chain 6 & chain 7 agc gain information reported by PHY 796 * 797 * @rx_start_ts: Rx packet timestamp, the time the first L-STF ADC sample 798 * arrived at Rx antenna. 799 * 800 * @mcs_rate: Indicates the mcs/rate in which packet is received. 801 * If HT, 802 * 0-7: MCS0-MCS7 803 * If VHT, 804 * 0-9: MCS0 to MCS9 805 * If HE, 806 * 0-11: MCS0 to MCS11, 807 * 12-13: 4096QAM, 808 * 14-15: reserved 809 * If Legacy, 810 * 0: 48 Mbps 811 * 1: 24 Mbps 812 * 2: 12 Mbps 813 * 3: 6 Mbps 814 * 4: 54 Mbps 815 * 5: 36 Mbps 816 * 6: 18 Mbps 817 * 7: 9 Mbps 818 * 819 * @gi_type: Indicates the guard interval. 820 * 0: 0.8 us 821 * 1: 0.4 us 822 * 2: 1.6 us 823 * 3: 3.2 us 824 */ 825 struct hal_rx_ppdu_cfr_info { 826 bool bb_captured_channel; 827 bool bb_captured_timeout; 828 uint8_t bb_captured_reason; 829 bool rx_location_info_valid; 830 uint8_t chan_capture_status; 831 uint8_t rtt_che_buffer_pointer_high8; 832 uint32_t rtt_che_buffer_pointer_low32; 833 int16_t rtt_cfo_measurement; 834 uint32_t agc_gain_info0; 835 uint32_t agc_gain_info1; 836 uint32_t agc_gain_info2; 837 uint32_t agc_gain_info3; 838 uint32_t rx_start_ts; 839 uint32_t mcs_rate; 840 uint32_t gi_type; 841 }; 842 #else 843 struct hal_rx_ppdu_cfr_info {}; 844 #endif 845 846 struct mon_rx_info { 847 uint8_t qos_control_info_valid; 848 uint16_t qos_control; 849 uint8_t mac_addr1_valid; 850 uint8_t mac_addr1[QDF_MAC_ADDR_SIZE]; 851 uint16_t user_id; 852 }; 853 854 struct mon_rx_user_info { 855 uint16_t qos_control; 856 uint8_t qos_control_info_valid; 857 }; 858 859 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 860 struct hal_rx_frm_type_info { 861 uint8_t rx_mgmt_cnt; 862 uint8_t rx_ctrl_cnt; 863 uint8_t rx_data_cnt; 864 }; 865 #else 866 struct hal_rx_frm_type_info {}; 867 #endif 868 869 struct hal_mon_usig_cmn { 870 uint32_t phy_version : 3, 871 bw : 3, 872 ul_dl : 1, 873 bss_color : 6, 874 txop : 7, 875 disregard : 5, 876 validate_0 : 1, 877 reserved : 6; 878 }; 879 880 struct hal_mon_usig_tb { 881 uint32_t ppdu_type_comp_mode : 2, 882 validate_1 : 1, 883 spatial_reuse_1 : 4, 884 spatial_reuse_2 : 4, 885 disregard_1 : 5, 886 crc : 4, 887 tail : 6, 888 reserved : 5, 889 rx_integrity_check_passed : 1; 890 }; 891 892 struct hal_mon_usig_mu { 893 uint32_t ppdu_type_comp_mode : 2, 894 validate_1 : 1, 895 punc_ch_info : 5, 896 validate_2 : 1, 897 eht_sig_mcs : 2, 898 num_eht_sig_sym : 5, 899 crc : 4, 900 tail : 6, 901 reserved : 5, 902 rx_integrity_check_passed : 1; 903 }; 904 905 /** 906 * union hal_mon_usig_non_cmn: Version dependent USIG fields 907 * @tb: trigger based frame USIG header 908 * @mu: MU frame USIG header 909 */ 910 union hal_mon_usig_non_cmn { 911 struct hal_mon_usig_tb tb; 912 struct hal_mon_usig_mu mu; 913 }; 914 915 /** 916 * struct hal_mon_usig_hdr: U-SIG header for EHT (and subsequent) frames 917 * @usig_1: USIG common header fields 918 * @usig_2: USIG version dependent fields 919 */ 920 struct hal_mon_usig_hdr { 921 struct hal_mon_usig_cmn usig_1; 922 union hal_mon_usig_non_cmn usig_2; 923 }; 924 925 #define HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_MASK 0x0000000300000000 926 #define HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_LSB 32 927 928 #define HAL_RX_MON_USIG_GET_PPDU_TYPE_N_COMP_MODE(usig_tlv_ptr) \ 929 ((*((uint64_t *)(usig_tlv_ptr)) & \ 930 HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_MASK) >> \ 931 HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_LSB) 932 933 #define HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 934 #define HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_LSB 63 935 936 #define HAL_RX_MON_USIG_GET_RX_INTEGRITY_CHECK_PASSED(usig_tlv_ptr) \ 937 ((*((uint64_t *)(usig_tlv_ptr)) & \ 938 HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_MASK) >> \ 939 HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_LSB) 940 941 /** 942 * enum hal_eht_bw: Reception bandwidth 943 * @HAL_EHT_BW_20: 20Mhz 944 * @HAL_EHT_BW_40: 40Mhz 945 * @HAL_EHT_BW_80: 80Mhz 946 * @HAL_EHT_BW_160: 160Mhz 947 * @HAL_EHT_BW_320_1: 320_1 band 948 * @HAL_EHT_BW_320_2: 320_2 band 949 */ 950 enum hal_eht_bw { 951 HAL_EHT_BW_20 = 0, 952 HAL_EHT_BW_40, 953 HAL_EHT_BW_80, 954 HAL_EHT_BW_160, 955 HAL_EHT_BW_320_1, 956 HAL_EHT_BW_320_2, 957 }; 958 959 struct hal_eht_sig_mu_mimo_user_info { 960 uint32_t sta_id : 11, 961 mcs : 4, 962 coding : 1, 963 spatial_coding : 6, 964 crc : 4; 965 }; 966 967 struct hal_eht_sig_non_mu_mimo_user_info { 968 uint32_t sta_id : 11, 969 mcs : 4, 970 validate : 1, 971 nss : 4, 972 beamformed : 1, 973 coding : 1, 974 crc : 4; 975 }; 976 977 /** 978 * union hal_eht_sig_user_field: User field in EHTSIG 979 * @mu_mimo_usr: MU-MIMO user field information in EHTSIG 980 * @non_mu_mimo_usr: Non MU-MIMO user field information in EHTSIG 981 */ 982 union hal_eht_sig_user_field { 983 struct hal_eht_sig_mu_mimo_user_info mu_mimo_usr; 984 struct hal_eht_sig_non_mu_mimo_user_info non_mu_mimo_usr; 985 }; 986 987 struct hal_eht_sig_ofdma_cmn_eb1 { 988 uint64_t spatial_reuse : 4, 989 gi_ltf : 2, 990 num_ltf_sym : 3, 991 ldpc_extra_sym : 1, 992 pre_fec_pad_factor : 2, 993 pe_disambiguity : 1, 994 disregard : 4, 995 ru_allocation1_1 : 9, 996 ru_allocation1_2 : 9, 997 crc : 4; 998 }; 999 1000 struct hal_eht_sig_ofdma_cmn_eb2 { 1001 uint64_t ru_allocation2_1 : 9, 1002 ru_allocation2_2 : 9, 1003 ru_allocation2_3 : 9, 1004 ru_allocation2_4 : 9, 1005 ru_allocation2_5 : 9, 1006 ru_allocation2_6 : 9, 1007 crc : 4; 1008 }; 1009 1010 struct hal_eht_sig_cc_usig_overflow { 1011 uint32_t spatial_reuse : 4, 1012 gi_ltf : 2, 1013 num_ltf_sym : 3, 1014 ldpc_extra_sym : 1, 1015 pre_fec_pad_factor : 2, 1016 pe_disambiguity : 1, 1017 disregard : 4; 1018 }; 1019 1020 struct hal_eht_sig_non_ofdma_cmn_eb { 1021 uint32_t spatial_reuse : 4, 1022 gi_ltf : 2, 1023 num_ltf_sym : 3, 1024 ldpc_extra_sym : 1, 1025 pre_fec_pad_factor : 2, 1026 pe_disambiguity : 1, 1027 disregard : 4, 1028 num_users : 3; 1029 union hal_eht_sig_user_field user_field; 1030 }; 1031 1032 struct hal_eht_sig_ndp_cmn_eb { 1033 uint32_t spatial_reuse : 4, 1034 gi_ltf : 2, 1035 num_ltf_sym : 3, 1036 nss : 4, 1037 beamformed : 1, 1038 disregard : 2, 1039 crc : 4; 1040 }; 1041 1042 /* Different allowed RU in 11BE */ 1043 #define HAL_EHT_RU_26 0ULL 1044 #define HAL_EHT_RU_52 1ULL 1045 #define HAL_EHT_RU_78 2ULL 1046 #define HAL_EHT_RU_106 3ULL 1047 #define HAL_EHT_RU_132 4ULL 1048 #define HAL_EHT_RU_242 5ULL 1049 #define HAL_EHT_RU_484 6ULL 1050 #define HAL_EHT_RU_726 7ULL 1051 #define HAL_EHT_RU_996 8ULL 1052 #define HAL_EHT_RU_996x2 9ULL 1053 #define HAL_EHT_RU_996x3 10ULL 1054 #define HAL_EHT_RU_996x4 11ULL 1055 #define HAL_EHT_RU_NONE 15ULL 1056 #define HAL_EHT_RU_INVALID 31ULL 1057 /* 1058 * MRUs spanning above 80Mhz 1059 * HAL_EHT_RU_996_484 = HAL_EHT_RU_484 + HAL_EHT_RU_996 + 4 (reserved) 1060 */ 1061 #define HAL_EHT_RU_996_484 18ULL 1062 #define HAL_EHT_RU_996x2_484 28ULL 1063 #define HAL_EHT_RU_996x3_484 40ULL 1064 #define HAL_EHT_RU_996_484_242 23ULL 1065 1066 /** 1067 * enum ieee80211_eht_ru_size: RU type id in EHTSIG radiotap header 1068 * @IEEE80211_EHT_RU_26: RU26 1069 * @IEEE80211_EHT_RU_52: RU52 1070 * @IEEE80211_EHT_RU_106: RU106 1071 * @IEEE80211_EHT_RU_242: RU242 1072 * @IEEE80211_EHT_RU_484: RU484 1073 * @IEEE80211_EHT_RU_996: RU996 1074 * @IEEE80211_EHT_RU_996x2: RU996x2 1075 * @IEEE80211_EHT_RU_996x4: RU996x4 1076 * @IEEE80211_EHT_RU_52_26: RU52+RU26 1077 * @IEEE80211_EHT_RU_106_26: RU106+RU26 1078 * @IEEE80211_EHT_RU_484_242: RU484+RU242 1079 * @IEEE80211_EHT_RU_996_484: RU996+RU484 1080 * @IEEE80211_EHT_RU_996_484_242: RU996+RU484+RU242 1081 * @IEEE80211_EHT_RU_996x2_484: RU996x2 + RU484 1082 * @IEEE80211_EHT_RU_996x3: RU996x3 1083 * @IEEE80211_EHT_RU_996x3_484: RU996x3 + RU484 1084 * @IEEE80211_EHT_RU_INVALID: Invalid/Max RU 1085 */ 1086 enum ieee80211_eht_ru_size { 1087 IEEE80211_EHT_RU_26, 1088 IEEE80211_EHT_RU_52, 1089 IEEE80211_EHT_RU_106, 1090 IEEE80211_EHT_RU_242, 1091 IEEE80211_EHT_RU_484, 1092 IEEE80211_EHT_RU_996, 1093 IEEE80211_EHT_RU_996x2, 1094 IEEE80211_EHT_RU_996x4, 1095 IEEE80211_EHT_RU_52_26, 1096 IEEE80211_EHT_RU_106_26, 1097 IEEE80211_EHT_RU_484_242, 1098 IEEE80211_EHT_RU_996_484, 1099 IEEE80211_EHT_RU_996_484_242, 1100 IEEE80211_EHT_RU_996x2_484, 1101 IEEE80211_EHT_RU_996x3, 1102 IEEE80211_EHT_RU_996x3_484, 1103 IEEE80211_EHT_RU_INVALID, 1104 }; 1105 1106 #define NUM_RU_BITS_PER80 16 1107 #define NUM_RU_BITS_PER20 4 1108 1109 /* Different per_80Mhz band in 320Mhz bandwidth */ 1110 #define HAL_80_0 0 1111 #define HAL_80_1 1 1112 #define HAL_80_2 2 1113 #define HAL_80_3 3 1114 1115 #define HAL_RU_SHIFT(num_80mhz_band, ru_index_per_80) \ 1116 ((NUM_RU_BITS_PER80 * (num_80mhz_band)) + \ 1117 (NUM_RU_BITS_PER20 * (ru_index_per_80))) 1118 1119 /* MRU-996+484 */ 1120 #define HAL_EHT_RU_996_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ 1121 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_1, 0))) 1122 #define HAL_EHT_RU_996_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1123 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_1, 0))) 1124 #define HAL_EHT_RU_996_484_2 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1125 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1))) 1126 #define HAL_EHT_RU_996_484_3 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1127 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0))) 1128 #define HAL_EHT_RU_996_484_4 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ 1129 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_3, 0))) 1130 #define HAL_EHT_RU_996_484_5 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1131 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_3, 0))) 1132 #define HAL_EHT_RU_996_484_6 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1133 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) 1134 #define HAL_EHT_RU_996_484_7 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1135 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) 1136 1137 /* MRU-996x2+484 */ 1138 #define HAL_EHT_RU_996x2_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ 1139 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1140 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1141 #define HAL_EHT_RU_996x2_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1142 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1143 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1144 #define HAL_EHT_RU_996x2_484_2 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1145 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ 1146 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1147 #define HAL_EHT_RU_996x2_484_3 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1148 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1149 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1150 #define HAL_EHT_RU_996x2_484_4 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1151 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1152 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1))) 1153 #define HAL_EHT_RU_996x2_484_5 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1154 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1155 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0))) 1156 #define HAL_EHT_RU_996x2_484_6 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ 1157 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1158 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1159 #define HAL_EHT_RU_996x2_484_7 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1160 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1161 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1162 #define HAL_EHT_RU_996x2_484_8 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1163 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ 1164 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1165 #define HAL_EHT_RU_996x2_484_9 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1166 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1167 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1168 #define HAL_EHT_RU_996x2_484_10 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1169 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1170 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) 1171 #define HAL_EHT_RU_996x2_484_11 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1172 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1173 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) 1174 1175 /* MRU-996x3+484 */ 1176 #define HAL_EHT_RU_996x3_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ 1177 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1178 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1179 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1180 #define HAL_EHT_RU_996x3_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1181 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1182 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1183 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1184 #define HAL_EHT_RU_996x3_484_2 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1185 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ 1186 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1187 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1188 #define HAL_EHT_RU_996x3_484_3 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1189 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1190 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1191 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1192 #define HAL_EHT_RU_996x3_484_4 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1193 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1194 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ 1195 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1196 #define HAL_EHT_RU_996x3_484_5 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1197 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1198 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1199 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1200 #define HAL_EHT_RU_996x3_484_6 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1201 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1202 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1203 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) 1204 #define HAL_EHT_RU_996x3_484_7 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1205 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1206 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1207 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) 1208 1209 #define HAL_RX_MON_MAX_AGGR_SIZE 128 1210 1211 /** 1212 * struct hal_rx_tlv_aggr_info - Data structure to hold 1213 * metadata for aggregatng repeated TLVs 1214 * @in_progress: Flag to indicate if TLV aggregation is in progress 1215 * @cur_len: Total length of currently aggregated TLV 1216 * @tlv_tag: TLV tag which is currently being aggregated 1217 * @buf: Buffer containing aggregated TLV data 1218 */ 1219 struct hal_rx_tlv_aggr_info { 1220 uint8_t in_progress; 1221 uint16_t cur_len; 1222 uint32_t tlv_tag; 1223 uint8_t buf[HAL_RX_MON_MAX_AGGR_SIZE]; 1224 }; 1225 1226 /* struct hal_rx_u_sig_info - Certain fields from U-SIG header which are used 1227 * for other header field parsing. 1228 * @ul_dl: UL or DL 1229 * @bw: EHT BW 1230 * @ppdu_type_comp_mode: PPDU TYPE 1231 * @eht_sig_mcs: EHT SIG MCS 1232 * @num_eht_sig_sym: Number of EHT SIG symbols 1233 */ 1234 struct hal_rx_u_sig_info { 1235 uint32_t ul_dl : 1, 1236 bw : 3, 1237 ppdu_type_comp_mode : 2, 1238 eht_sig_mcs : 2, 1239 num_eht_sig_sym : 5; 1240 }; 1241 1242 #ifdef WLAN_SUPPORT_CTRL_FRAME_STATS 1243 struct hal_rx_user_ctrl_frm_info { 1244 uint8_t bar : 1, 1245 ndpa : 1; 1246 }; 1247 #else 1248 struct hal_rx_user_ctrl_frm_info {}; 1249 #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */ 1250 1251 struct hal_rx_ppdu_info { 1252 struct hal_rx_ppdu_common_info com_info; 1253 struct hal_rx_u_sig_info u_sig_info; 1254 struct mon_rx_status rx_status; 1255 struct mon_rx_user_status rx_user_status[HAL_MAX_UL_MU_USERS]; 1256 struct mon_rx_info rx_info; 1257 struct mon_rx_user_info rx_user_info[HAL_MAX_UL_MU_USERS]; 1258 struct hal_rx_msdu_payload_info msdu_info; 1259 struct hal_rx_msdu_payload_info fcs_ok_msdu_info; 1260 struct hal_rx_nac_info nac_info; 1261 /* status ring PPDU start and end state */ 1262 uint8_t rx_state; 1263 /* MU user id for status ring TLV */ 1264 uint8_t user_id; 1265 /* MPDU/MSDU truncated to 128 bytes header start addr in status skb */ 1266 unsigned char *data; 1267 /* MPDU/MSDU truncated to 128 bytes header real length */ 1268 uint32_t hdr_len; 1269 /* MPDU FCS error */ 1270 bool fcs_err; 1271 /* Id to indicate how to process mpdu */ 1272 uint8_t sw_frame_group_id; 1273 struct hal_rx_ppdu_msdu_info rx_msdu_info[HAL_MAX_UL_MU_USERS]; 1274 /* fcs passed mpdu count in rx monitor status buffer */ 1275 uint8_t fcs_ok_cnt; 1276 /* fcs error mpdu count in rx monitor status buffer */ 1277 uint8_t fcs_err_cnt; 1278 /* MPDU FCS passed */ 1279 bool is_fcs_passed; 1280 /* first msdu payload for all mpdus in rx monitor status buffer */ 1281 struct hal_rx_msdu_payload_info ppdu_msdu_info[HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER]; 1282 /* evm info */ 1283 struct hal_rx_su_evm_info evm_info; 1284 /** 1285 * Will be used to store ppdu info extracted from HW TLVs, 1286 * and for CFR correlation as well 1287 */ 1288 struct hal_rx_ppdu_cfr_info cfr_info; 1289 /* per frame type counts */ 1290 struct hal_rx_frm_type_info frm_type_info; 1291 /* TLV aggregation metadata context */ 1292 struct hal_rx_tlv_aggr_info tlv_aggr; 1293 /* EHT SIG user info */ 1294 uint32_t eht_sig_user_info; 1295 /*per user mpdu count */ 1296 uint8_t mpdu_count[HAL_MAX_UL_MU_USERS]; 1297 /*per user msdu count */ 1298 uint8_t msdu_count[HAL_MAX_UL_MU_USERS]; 1299 /* Placeholder to update per user last processed msdu’s info */ 1300 struct hal_rx_mon_msdu_info msdu[HAL_MAX_UL_MU_USERS]; 1301 /* Placeholder to update per user last processed mpdu’s info */ 1302 struct hal_rx_mon_mpdu_info mpdu_info[HAL_MAX_UL_MU_USERS]; 1303 /* placeholder to hold packet buffer info */ 1304 struct hal_mon_packet_info packet_info; 1305 #ifdef QCA_MONITOR_2_0_SUPPORT 1306 /* per user per MPDU queue */ 1307 qdf_nbuf_queue_t mpdu_q[HAL_MAX_UL_MU_USERS]; 1308 #endif 1309 /* ppdu info list element */ 1310 TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_list_elem; 1311 /* ppdu info free list element */ 1312 TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_free_list_elem; 1313 /* placeholder to track if RX_HDR is received */ 1314 uint8_t rx_hdr_rcvd[HAL_MAX_UL_MU_USERS]; 1315 /* Per user BAR and NDPA bit flag */ 1316 struct hal_rx_user_ctrl_frm_info ctrl_frm_info[HAL_MAX_UL_MU_USERS]; 1317 /* PPDU end user stats count */ 1318 uint8_t end_user_stats_cnt; 1319 /* PPDU start user info count */ 1320 uint8_t start_user_info_cnt; 1321 /* PPDU drop cnt */ 1322 struct hal_rx_ppdu_drop_cnt drop_cnt; 1323 }; 1324 1325 static inline uint32_t 1326 hal_get_rx_status_buf_size(void) { 1327 /* RX status buffer size is hard coded for now */ 1328 return 2048; 1329 } 1330 1331 static inline uint8_t* 1332 hal_rx_status_get_next_tlv(uint8_t *rx_tlv, bool is_tlv_hdr_64_bit) { 1333 uint32_t tlv_len, tlv_tag, tlv_hdr_size; 1334 1335 if (is_tlv_hdr_64_bit) { 1336 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 1337 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1338 1339 tlv_hdr_size = HAL_RX_TLV64_HDR_SIZE; 1340 } else { 1341 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 1342 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1343 1344 tlv_hdr_size = HAL_RX_TLV32_HDR_SIZE; 1345 } 1346 1347 /* The actual length of PPDU_END is the combined length of many PHY 1348 * TLVs that follow. Skip the TLV header and 1349 * rx_rxpcu_classification_overview that follows the header to get to 1350 * next TLV. 1351 */ 1352 if (tlv_tag == WIFIRX_PPDU_END_E) 1353 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 1354 1355 return (uint8_t *)(uintptr_t)qdf_align((uint64_t)((uintptr_t)rx_tlv + 1356 tlv_len + 1357 tlv_hdr_size), 1358 tlv_hdr_size); 1359 } 1360 1361 /** 1362 * hal_rx_proc_phyrx_other_receive_info_tlv() 1363 * - process other receive info TLV 1364 * @rx_tlv_hdr: pointer to TLV header 1365 * @ppdu_info: pointer to ppdu_info 1366 * 1367 * Return: None 1368 */ 1369 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 1370 void *rx_tlv_hdr, 1371 struct hal_rx_ppdu_info 1372 *ppdu_info) 1373 { 1374 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 1375 (void *)ppdu_info); 1376 } 1377 1378 /** 1379 * hal_rx_status_get_tlv_info() - process receive info TLV 1380 * @rx_tlv_hdr: pointer to TLV header 1381 * @ppdu_info: pointer to ppdu_info 1382 * @hal_soc: HAL soc handle 1383 * @nbuf: PPDU status network buffer 1384 * 1385 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 1386 */ 1387 static inline uint32_t 1388 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 1389 hal_soc_handle_t hal_soc_hdl, 1390 qdf_nbuf_t nbuf) 1391 { 1392 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1393 1394 return hal_soc->ops->hal_rx_status_get_tlv_info( 1395 rx_tlv_hdr, 1396 ppdu_info, 1397 hal_soc_hdl, 1398 nbuf); 1399 } 1400 1401 static inline 1402 uint32_t hal_get_rx_status_done_tlv_size(hal_soc_handle_t hal_soc_hdl) 1403 { 1404 return HAL_RX_TLV32_HDR_SIZE; 1405 } 1406 1407 static inline QDF_STATUS 1408 hal_get_rx_status_done(uint8_t *rx_tlv) 1409 { 1410 uint32_t tlv_tag; 1411 1412 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1413 1414 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 1415 return QDF_STATUS_SUCCESS; 1416 else 1417 return QDF_STATUS_E_EMPTY; 1418 } 1419 1420 static inline QDF_STATUS 1421 hal_clear_rx_status_done(uint8_t *rx_tlv) 1422 { 1423 *(uint32_t *)rx_tlv = 0; 1424 return QDF_STATUS_SUCCESS; 1425 } 1426 #endif 1427