1 /* 2 * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_API_MON_H_ 20 #define _HAL_API_MON_H_ 21 22 #include "qdf_types.h" 23 #include "hal_internal.h" 24 25 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 26 #define HAL_RX_LSB(block, field) block##_##field##_LSB 27 #define HAL_RX_MASk(block, field) block##_##field##_MASK 28 29 #define HAL_RX_GET(_ptr, block, field) \ 30 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 31 HAL_RX_MASk(block, field)) >> \ 32 HAL_RX_LSB(block, field)) 33 34 #define HAL_RX_PHY_DATA_RADAR 0x01 35 #define HAL_SU_MU_CODING_LDPC 0x01 36 37 #define HAL_RX_FCS_LEN (4) 38 #define KEY_EXTIV 0x20 39 40 #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000 41 #define HAL_RX_USER_TLV32_TYPE_LSB 1 42 #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE 43 44 #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000 45 #define HAL_RX_USER_TLV32_LEN_LSB 10 46 #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00 47 48 #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000 49 #define HAL_RX_USER_TLV32_USERID_LSB 26 50 #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000 51 52 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 53 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 54 55 #define HAL_RX_TLV32_HDR_SIZE 4 56 57 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 58 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 59 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 60 HAL_RX_USER_TLV32_TYPE_LSB) 61 62 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 63 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 64 HAL_RX_USER_TLV32_LEN_MASK) >> \ 65 HAL_RX_USER_TLV32_LEN_LSB) 66 67 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 68 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 69 HAL_RX_USER_TLV32_USERID_MASK) >> \ 70 HAL_RX_USER_TLV32_USERID_LSB) 71 72 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 73 #define HAL_TLV_STATUS_PPDU_DONE 1 74 #define HAL_TLV_STATUS_BUF_DONE 2 75 76 #define HAL_MAX_UL_MU_USERS 8 77 78 #define HAL_RX_PKT_TYPE_11A 0 79 #define HAL_RX_PKT_TYPE_11B 1 80 #define HAL_RX_PKT_TYPE_11N 2 81 #define HAL_RX_PKT_TYPE_11AC 3 82 #define HAL_RX_PKT_TYPE_11AX 4 83 84 #define HAL_RX_RECEPTION_TYPE_SU 0 85 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 86 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 87 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 88 89 /* Multiply rate by 2 to avoid float point 90 * and get rate in units of 500kbps 91 */ 92 #define HAL_11B_RATE_0MCS 11*2 93 #define HAL_11B_RATE_1MCS 5.5*2 94 #define HAL_11B_RATE_2MCS 2*2 95 #define HAL_11B_RATE_3MCS 1*2 96 #define HAL_11B_RATE_4MCS 11*2 97 #define HAL_11B_RATE_5MCS 5.5*2 98 #define HAL_11B_RATE_6MCS 2*2 99 100 #define HAL_11A_RATE_0MCS 48*2 101 #define HAL_11A_RATE_1MCS 24*2 102 #define HAL_11A_RATE_2MCS 12*2 103 #define HAL_11A_RATE_3MCS 6*2 104 #define HAL_11A_RATE_4MCS 54*2 105 #define HAL_11A_RATE_5MCS 36*2 106 #define HAL_11A_RATE_6MCS 18*2 107 #define HAL_11A_RATE_7MCS 9*2 108 109 #define HE_GI_0_8 0 110 #define HE_GI_1_6 1 111 #define HE_GI_3_2 2 112 113 #define HT_SGI_PRESENT 0x80 114 115 #define HE_LTF_1_X 0 116 #define HE_LTF_2_X 1 117 #define HE_LTF_4_X 2 118 #define VHT_SIG_SU_NSS_MASK 0x7 119 120 #define HAL_TID_INVALID 31 121 #define HAL_AST_IDX_INVALID 0xFFFF 122 123 #ifdef GET_MSDU_AGGREGATION 124 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 125 {\ 126 struct rx_msdu_end *rx_msdu_end;\ 127 bool first_msdu, last_msdu; \ 128 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 129 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 130 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 131 if (first_msdu && last_msdu)\ 132 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 133 else\ 134 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 135 } \ 136 137 #else 138 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 139 #endif 140 141 enum { 142 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 143 HAL_HW_RX_DECAP_FORMAT_NWIFI, 144 HAL_HW_RX_DECAP_FORMAT_ETH2, 145 HAL_HW_RX_DECAP_FORMAT_8023, 146 }; 147 148 enum { 149 DP_PPDU_STATUS_START, 150 DP_PPDU_STATUS_DONE, 151 }; 152 153 static inline 154 uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void) 155 { 156 /* return the HW_RX_DESC size */ 157 return sizeof(struct rx_pkt_tlvs); 158 } 159 160 static inline 161 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 162 { 163 return data; 164 } 165 166 static inline 167 uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr) 168 { 169 struct rx_attention *rx_attn; 170 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 171 172 rx_attn = &rx_desc->attn_tlv.rx_attn; 173 174 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 175 } 176 177 static inline 178 uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr) 179 { 180 struct rx_attention *rx_attn; 181 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 182 183 rx_attn = &rx_desc->attn_tlv.rx_attn; 184 185 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 186 } 187 188 static inline 189 uint32_t 190 HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) { 191 struct rx_msdu_start *rx_msdu_start; 192 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 193 194 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 195 196 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 197 } 198 199 static inline 200 uint8_t * 201 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 202 uint8_t *rx_pkt_hdr; 203 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 204 205 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 206 207 return rx_pkt_hdr; 208 } 209 210 static inline 211 uint32_t HAL_RX_MON_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr) 212 { 213 struct rx_mpdu_info *rx_mpdu_info; 214 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 215 216 rx_mpdu_info = 217 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 218 219 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 220 } 221 222 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 223 static inline 224 uint32_t hal_rx_desc_is_first_msdu(void *hw_desc_addr) 225 { 226 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 227 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 228 229 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 230 } 231 232 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 233 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 234 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 235 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 236 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 237 238 #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \ 239 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 240 (((struct reo_entrance_ring *)reo_ent_desc) \ 241 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 242 243 #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \ 244 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 245 (((struct reo_entrance_ring *)reo_ent_desc) \ 246 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 247 248 #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \ 249 (HAL_RX_BUF_COOKIE_GET(& \ 250 (((struct reo_entrance_ring *)reo_ent_desc) \ 251 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 252 253 /** 254 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 255 * cookie from the REO entrance ring element 256 * 257 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 258 * the current descriptor 259 * @ buf_info: structure to return the buffer information 260 * @ msdu_cnt: pointer to msdu count in MPDU 261 * Return: void 262 */ 263 static inline 264 void hal_rx_reo_ent_buf_paddr_get(void *rx_desc, 265 struct hal_buf_info *buf_info, 266 void **pp_buf_addr_info, 267 uint32_t *msdu_cnt 268 ) 269 { 270 struct reo_entrance_ring *reo_ent_ring = 271 (struct reo_entrance_ring *)rx_desc; 272 struct buffer_addr_info *buf_addr_info; 273 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 274 uint32_t loop_cnt; 275 276 rx_mpdu_desc_info_details = 277 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 278 279 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 280 RX_MPDU_DESC_INFO_0, MSDU_COUNT); 281 282 loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT); 283 284 buf_addr_info = 285 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 286 287 buf_info->paddr = 288 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 289 ((uint64_t) 290 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 291 292 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 293 294 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 295 "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d\n", 296 __func__, __LINE__, reo_ent_ring, buf_addr_info, 297 (unsigned long long)buf_info->paddr, loop_cnt); 298 299 *pp_buf_addr_info = (void *)buf_addr_info; 300 } 301 302 static inline 303 void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 304 struct hal_buf_info *buf_info, void **pp_buf_addr_info) 305 { 306 struct rx_msdu_link *msdu_link = 307 (struct rx_msdu_link *)rx_msdu_link_desc; 308 struct buffer_addr_info *buf_addr_info; 309 310 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 311 312 buf_info->paddr = 313 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 314 ((uint64_t) 315 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 316 317 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 318 319 *pp_buf_addr_info = (void *)buf_addr_info; 320 } 321 322 /** 323 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 324 * 325 * @ soc : HAL version of the SOC pointer 326 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 327 * @ buf_addr_info : void pointer to the buffer_addr_info 328 * 329 * Return: void 330 */ 331 332 static inline void hal_rx_mon_msdu_link_desc_set(struct hal_soc *soc, 333 void *src_srng_desc, void *buf_addr_info) 334 { 335 struct buffer_addr_info *wbm_srng_buffer_addr_info = 336 (struct buffer_addr_info *)src_srng_desc; 337 uint64_t paddr; 338 struct buffer_addr_info *p_buffer_addr_info = 339 (struct buffer_addr_info *)buf_addr_info; 340 341 paddr = 342 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 343 ((uint64_t) 344 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 345 346 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 347 "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx\n", 348 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 349 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 350 351 /* Structure copy !!! */ 352 *wbm_srng_buffer_addr_info = 353 *((struct buffer_addr_info *)buf_addr_info); 354 } 355 356 static inline 357 uint32 hal_get_rx_msdu_link_desc_size(void) 358 { 359 return sizeof(struct rx_msdu_link); 360 } 361 362 enum { 363 HAL_PKT_TYPE_OFDM = 0, 364 HAL_PKT_TYPE_CCK, 365 HAL_PKT_TYPE_HT, 366 HAL_PKT_TYPE_VHT, 367 HAL_PKT_TYPE_HE, 368 }; 369 370 enum { 371 HAL_SGI_0_8_US, 372 HAL_SGI_0_4_US, 373 HAL_SGI_1_6_US, 374 HAL_SGI_3_2_US, 375 }; 376 377 enum { 378 HAL_FULL_RX_BW_20, 379 HAL_FULL_RX_BW_40, 380 HAL_FULL_RX_BW_80, 381 HAL_FULL_RX_BW_160, 382 }; 383 384 enum { 385 HAL_RX_TYPE_SU, 386 HAL_RX_TYPE_MU_MIMO, 387 HAL_RX_TYPE_MU_OFDMA, 388 HAL_RX_TYPE_MU_OFDMA_MIMO, 389 }; 390 391 /** 392 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 393 * 394 * @ hw_desc_addr: Start address of Rx HW TLVs 395 * @ rs: Status for monitor mode 396 * 397 * Return: void 398 */ 399 static inline 400 void hal_rx_mon_hw_desc_get_mpdu_status(void *hw_desc_addr, 401 struct mon_rx_status *rs) 402 { 403 struct rx_msdu_start *rx_msdu_start; 404 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 405 uint32_t reg_value; 406 static uint32_t sgi_hw_to_cdp[] = { 407 CDP_SGI_0_8_US, 408 CDP_SGI_0_4_US, 409 CDP_SGI_1_6_US, 410 CDP_SGI_3_2_US, 411 }; 412 413 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 414 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 415 416 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 417 RX_MSDU_START_5, USER_RSSI); 418 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 419 420 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 421 rs->sgi = sgi_hw_to_cdp[reg_value]; 422 #if !defined(QCA_WIFI_QCA6290_11AX) 423 rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS); 424 #endif 425 426 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 427 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 428 /* TODO: rs->beamformed should be set for SU beamforming also */ 429 } 430 431 struct hal_rx_ppdu_user_info { 432 433 }; 434 435 struct hal_rx_ppdu_common_info { 436 uint32_t ppdu_id; 437 uint32_t last_ppdu_id; 438 uint32_t ppdu_timestamp; 439 uint32_t mpdu_cnt_fcs_ok; 440 uint32_t mpdu_cnt_fcs_err; 441 }; 442 443 struct hal_rx_ppdu_info { 444 struct hal_rx_ppdu_common_info com_info; 445 struct hal_rx_ppdu_user_info user_info[HAL_MAX_UL_MU_USERS]; 446 struct mon_rx_status rx_status; 447 uint8_t *first_msdu_payload; 448 }; 449 450 static inline uint32_t 451 hal_get_rx_status_buf_size(void) { 452 /* RX status buffer size is hard coded for now */ 453 return 2048; 454 } 455 456 static inline uint8_t* 457 hal_rx_status_get_next_tlv(uint8_t *rx_tlv) { 458 uint32_t tlv_len, tlv_tag; 459 460 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 461 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 462 463 /* The actual length of PPDU_END is the combined lenght of many PHY 464 * TLVs that follow. Skip the TLV header and 465 * rx_rxpcu_classification_overview that follows the header to get to 466 * next TLV. 467 */ 468 if (tlv_tag == WIFIRX_PPDU_END_E) 469 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 470 471 return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len + 472 HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3))); 473 } 474 475 static inline uint32_t 476 hal_rx_status_get_tlv_info(void *rx_tlv, struct hal_rx_ppdu_info *ppdu_info) 477 { 478 uint32_t tlv_tag, user_id, tlv_len, value; 479 uint8_t group_id = 0; 480 uint8_t he_dcm = 0; 481 uint8_t he_stbc = 0; 482 uint16_t he_gi = 0; 483 uint16_t he_ltf = 0; 484 485 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 486 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv); 487 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 488 489 rx_tlv = (uint8_t *) rx_tlv + HAL_RX_TLV32_HDR_SIZE; 490 switch (tlv_tag) { 491 492 case WIFIRX_PPDU_START_E: 493 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 494 "[%s][%d] ppdu_start_e len=%d", 495 __func__, __LINE__, tlv_len); 496 ppdu_info->com_info.ppdu_id = 497 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 498 PHY_PPDU_ID); 499 /* channel number is set in PHY meta data */ 500 ppdu_info->rx_status.chan_num = 501 HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 502 SW_PHY_META_DATA); 503 ppdu_info->com_info.ppdu_timestamp = 504 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 505 PPDU_START_TIMESTAMP); 506 break; 507 508 case WIFIRX_PPDU_START_USER_INFO_E: 509 break; 510 511 case WIFIRX_PPDU_END_E: 512 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 513 "[%s][%d] ppdu_end_e len=%d", 514 __func__, __LINE__, tlv_len); 515 /* This is followed by sub-TLVs of PPDU_END */ 516 break; 517 518 case WIFIRXPCU_PPDU_END_INFO_E: 519 ppdu_info->rx_status.tsft = 520 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 521 WB_TIMESTAMP_UPPER_32); 522 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 523 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 524 WB_TIMESTAMP_LOWER_32); 525 ppdu_info->rx_status.duration = 526 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_8, 527 RX_PPDU_DURATION); 528 break; 529 530 case WIFIRX_PPDU_END_USER_STATS_E: 531 { 532 unsigned long tid = 0; 533 uint16_t seq = 0; 534 535 ppdu_info->rx_status.ast_index = 536 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 537 AST_INDEX); 538 ppdu_info->rx_status.mcs = 539 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_1, MCS); 540 541 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 542 RECEIVED_QOS_DATA_TID_BITMAP); 543 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 544 545 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 546 ppdu_info->rx_status.tid = HAL_TID_INVALID; 547 548 ppdu_info->rx_status.tcp_msdu_count = 549 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 550 TCP_MSDU_COUNT) + 551 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 552 TCP_ACK_MSDU_COUNT); 553 ppdu_info->rx_status.udp_msdu_count = 554 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 555 UDP_MSDU_COUNT); 556 ppdu_info->rx_status.other_msdu_count = 557 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 558 OTHER_MSDU_COUNT); 559 560 ppdu_info->rx_status.frame_control_info_valid = 561 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 562 DATA_SEQUENCE_CONTROL_INFO_VALID); 563 564 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 565 FIRST_DATA_SEQ_CTRL); 566 if (ppdu_info->rx_status.frame_control_info_valid) 567 ppdu_info->rx_status.first_data_seq_ctrl = seq; 568 569 ppdu_info->rx_status.preamble_type = 570 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 571 HT_CONTROL_FIELD_PKT_TYPE); 572 switch (ppdu_info->rx_status.preamble_type) { 573 case HAL_RX_PKT_TYPE_11N: 574 ppdu_info->rx_status.ht_flags = 1; 575 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 576 break; 577 case HAL_RX_PKT_TYPE_11AC: 578 ppdu_info->rx_status.vht_flags = 1; 579 break; 580 case HAL_RX_PKT_TYPE_11AX: 581 ppdu_info->rx_status.he_flags = 1; 582 break; 583 default: 584 break; 585 } 586 587 ppdu_info->com_info.mpdu_cnt_fcs_ok = 588 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 589 MPDU_CNT_FCS_OK); 590 ppdu_info->com_info.mpdu_cnt_fcs_err = 591 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 592 MPDU_CNT_FCS_ERR); 593 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 594 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 595 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 596 else 597 ppdu_info->rx_status.rs_flags &= 598 (~IEEE80211_AMPDU_FLAG); 599 break; 600 } 601 602 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 603 break; 604 605 case WIFIRX_PPDU_END_STATUS_DONE_E: 606 return HAL_TLV_STATUS_PPDU_DONE; 607 608 case WIFIDUMMY_E: 609 return HAL_TLV_STATUS_BUF_DONE; 610 611 case WIFIPHYRX_HT_SIG_E: 612 { 613 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 614 HAL_RX_OFFSET(PHYRX_HT_SIG_0, 615 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 616 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 617 FEC_CODING); 618 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 619 1 : 0; 620 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 621 HT_SIG_INFO_0, MCS); 622 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 623 HT_SIG_INFO_0, CBW); 624 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 625 HT_SIG_INFO_1, SHORT_GI); 626 break; 627 } 628 629 case WIFIPHYRX_L_SIG_B_E: 630 { 631 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 632 HAL_RX_OFFSET(PHYRX_L_SIG_B_0, 633 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 634 635 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 636 switch (value) { 637 case 1: 638 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 639 break; 640 case 2: 641 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 642 break; 643 case 3: 644 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 645 break; 646 case 4: 647 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 648 break; 649 case 5: 650 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 651 break; 652 case 6: 653 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 654 break; 655 case 7: 656 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 657 break; 658 default: 659 break; 660 } 661 ppdu_info->rx_status.cck_flag = 1; 662 break; 663 } 664 665 case WIFIPHYRX_L_SIG_A_E: 666 { 667 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 668 HAL_RX_OFFSET(PHYRX_L_SIG_A_0, 669 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 670 671 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 672 switch (value) { 673 case 8: 674 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 675 break; 676 case 9: 677 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 678 break; 679 case 10: 680 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 681 break; 682 case 11: 683 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 684 break; 685 case 12: 686 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 687 break; 688 case 13: 689 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 690 break; 691 case 14: 692 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 693 break; 694 case 15: 695 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 696 break; 697 default: 698 break; 699 } 700 ppdu_info->rx_status.ofdm_flag = 1; 701 break; 702 } 703 704 case WIFIPHYRX_VHT_SIG_A_E: 705 { 706 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 707 HAL_RX_OFFSET(PHYRX_VHT_SIG_A_0, 708 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 709 710 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 711 SU_MU_CODING); 712 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 713 1 : 0; 714 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 715 ppdu_info->rx_status.vht_flag_values5 = group_id; 716 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 717 VHT_SIG_A_INFO_1, MCS); 718 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 719 VHT_SIG_A_INFO_1, GI_SETTING); 720 #if !defined(QCA_WIFI_QCA6290_11AX) 721 value = HAL_RX_GET(vht_sig_a_info, 722 VHT_SIG_A_INFO_0, N_STS); 723 ppdu_info->rx_status.nss = ((value & VHT_SIG_SU_NSS_MASK) + 1); 724 #else 725 ppdu_info->rx_status.nss = 0; 726 #endif 727 ppdu_info->rx_status.vht_flag_values3[0] = 728 (((ppdu_info->rx_status.mcs) << 4) 729 | ppdu_info->rx_status.nss); 730 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 731 VHT_SIG_A_INFO_0, BANDWIDTH); 732 ppdu_info->rx_status.vht_flag_values2 = 733 ppdu_info->rx_status.bw; 734 ppdu_info->rx_status.vht_flag_values4 = 735 HAL_RX_GET(vht_sig_a_info, 736 VHT_SIG_A_INFO_1, SU_MU_CODING); 737 break; 738 } 739 case WIFIPHYRX_HE_SIG_A_SU_E: 740 { 741 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 742 HAL_RX_OFFSET(PHYRX_HE_SIG_A_SU_0, 743 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 744 ppdu_info->rx_status.he_flags = 1; 745 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 746 FORMAT_INDICATION); 747 if (value == 0) { 748 ppdu_info->rx_status.he_data1 = 749 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 750 } else { 751 ppdu_info->rx_status.he_data1 = 752 QDF_MON_STATUS_HE_SU_OR_EXT_SU_FORMAT_TYPE; 753 } 754 755 /*data1*/ 756 ppdu_info->rx_status.he_data1 |= 757 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 758 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 759 QDF_MON_STATUS_HE_DL_UL_KNOWN | 760 QDF_MON_STATUS_HE_MCS_KNOWN | 761 QDF_MON_STATUS_HE_DCM_KNOWN | 762 QDF_MON_STATUS_HE_CODING_KNOWN | 763 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 764 QDF_MON_STATUS_HE_STBC_KNOWN | 765 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 766 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 767 768 /*data2*/ 769 ppdu_info->rx_status.he_data2 = 770 QDF_MON_STATUS_HE_GI_KNOWN; 771 ppdu_info->rx_status.he_data2 |= 772 QDF_MON_STATUS_TXBF_KNOWN | 773 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 774 QDF_MON_STATUS_TXOP_KNOWN | 775 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 776 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 777 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 778 779 /*data3*/ 780 value = HAL_RX_GET(he_sig_a_su_info, 781 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 782 ppdu_info->rx_status.he_data3 = value; 783 value = HAL_RX_GET(he_sig_a_su_info, 784 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 785 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 786 ppdu_info->rx_status.he_data3 |= value; 787 value = HAL_RX_GET(he_sig_a_su_info, 788 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 789 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 790 ppdu_info->rx_status.he_data3 |= value; 791 value = HAL_RX_GET(he_sig_a_su_info, 792 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 793 ppdu_info->rx_status.mcs = value; 794 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 795 ppdu_info->rx_status.he_data3 |= value; 796 value = HAL_RX_GET(he_sig_a_su_info, 797 HE_SIG_A_SU_INFO_0, DCM); 798 he_dcm = value; 799 value = value << QDF_MON_STATUS_DCM_SHIFT; 800 ppdu_info->rx_status.he_data3 |= value; 801 value = HAL_RX_GET(he_sig_a_su_info, 802 HE_SIG_A_SU_INFO_1, CODING); 803 value = value << QDF_MON_STATUS_CODING_SHIFT; 804 ppdu_info->rx_status.he_data3 |= value; 805 value = HAL_RX_GET(he_sig_a_su_info, 806 HE_SIG_A_SU_INFO_1, 807 LDPC_EXTRA_SYMBOL); 808 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 809 ppdu_info->rx_status.he_data3 |= value; 810 value = HAL_RX_GET(he_sig_a_su_info, 811 HE_SIG_A_SU_INFO_1, STBC); 812 he_stbc = value; 813 value = value << QDF_MON_STATUS_STBC_SHIFT; 814 ppdu_info->rx_status.he_data3 |= value; 815 816 /*data4*/ 817 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 818 SPATIAL_REUSE); 819 ppdu_info->rx_status.he_data4 = value; 820 821 /*data5*/ 822 value = HAL_RX_GET(he_sig_a_su_info, 823 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 824 ppdu_info->rx_status.he_data5 = value; 825 ppdu_info->rx_status.bw = value; 826 value = HAL_RX_GET(he_sig_a_su_info, 827 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 828 switch (value) { 829 case 0: 830 he_gi = HE_GI_0_8; 831 he_ltf = HE_LTF_1_X; 832 break; 833 case 1: 834 he_gi = HE_GI_0_8; 835 he_ltf = HE_LTF_2_X; 836 break; 837 case 2: 838 he_gi = HE_GI_1_6; 839 he_ltf = HE_LTF_2_X; 840 break; 841 case 3: 842 if (he_dcm && he_stbc) { 843 he_gi = HE_GI_0_8; 844 he_ltf = HE_LTF_4_X; 845 } else { 846 he_gi = HE_GI_3_2; 847 he_ltf = HE_LTF_4_X; 848 } 849 break; 850 } 851 ppdu_info->rx_status.sgi = he_gi; 852 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 853 ppdu_info->rx_status.he_data5 |= value; 854 value = he_ltf << QDF_MON_STATUS_HE_LTF_SHIFT; 855 ppdu_info->rx_status.he_data5 |= value; 856 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 857 PACKET_EXTENSION_A_FACTOR); 858 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 859 ppdu_info->rx_status.he_data5 |= value; 860 861 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 862 value = value << QDF_MON_STATUS_TXBF_SHIFT; 863 ppdu_info->rx_status.he_data5 |= value; 864 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 865 PACKET_EXTENSION_PE_DISAMBIGUITY); 866 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 867 ppdu_info->rx_status.he_data5 |= value; 868 869 /*data6*/ 870 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 871 value++; 872 ppdu_info->rx_status.nss = value; 873 ppdu_info->rx_status.he_data6 = value; 874 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 875 DOPPLER_INDICATION); 876 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 877 ppdu_info->rx_status.he_data6 |= value; 878 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 879 TXOP_DURATION); 880 value = value << QDF_MON_STATUS_TXOP_SHIFT; 881 ppdu_info->rx_status.he_data6 |= value; 882 883 break; 884 } 885 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 886 ppdu_info->rx_status.he_sig_A1 = 887 *((uint32_t *)((uint8_t *)rx_tlv + 888 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_DL_0, 889 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS))); 890 ppdu_info->rx_status.he_sig_A1 |= 891 QDF_MON_STATUS_HE_SIG_A1_HE_FORMAT_MU; 892 ppdu_info->rx_status.he_sig_A1_known = 893 QDF_MON_STATUS_HE_SIG_A1_MU_KNOWN_ALL; 894 895 ppdu_info->rx_status.he_sig_A2 = 896 *((uint32_t *)((uint8_t *)rx_tlv + 897 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_DL_1, 898 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS))); 899 ppdu_info->rx_status.he_sig_A2_known = 900 QDF_MON_STATUS_HE_SIG_A2_MU_KNOWN_ALL; 901 break; 902 case WIFIPHYRX_HE_SIG_B1_MU_E: 903 { 904 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 905 *((uint32_t *)((uint8_t *)rx_tlv + 906 HAL_RX_OFFSET(PHYRX_HE_SIG_B1_MU_0, 907 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS))); 908 909 ppdu_info->rx_status.he_sig_b_common_RU[0] = 910 HAL_RX_GET(he_sig_b1_mu_info, HE_SIG_B1_MU_INFO_0, 911 RU_ALLOCATION); 912 913 ppdu_info->rx_status.he_sig_b_common_known = 914 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 915 /* TODO: Check on the availability of other fields in 916 * sig_b_common 917 */ 918 break; 919 } 920 case WIFIPHYRX_HE_SIG_B2_MU_E: 921 ppdu_info->rx_status.he_sig_b_user = 922 *((uint32_t *)((uint8_t *)rx_tlv + 923 HAL_RX_OFFSET(PHYRX_HE_SIG_B2_MU_0, 924 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS))); 925 ppdu_info->rx_status.he_sig_b_user_known = 926 QDF_MON_STATUS_HE_SIG_B_USER_KNOWN_SIG_B_ALL; 927 break; 928 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 929 ppdu_info->rx_status.he_sig_b_user = 930 *((uint32_t *)((uint8_t *)rx_tlv + 931 HAL_RX_OFFSET(PHYRX_HE_SIG_B2_OFDMA_0, 932 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS))); 933 ppdu_info->rx_status.he_sig_b_user_known = 934 QDF_MON_STATUS_HE_SIG_B_USER_KNOWN_SIG_B_ALL; 935 break; 936 case WIFIPHYRX_RSSI_LEGACY_E: 937 { 938 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 939 HAL_RX_OFFSET(PHYRX_RSSI_LEGACY_3, 940 RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS); 941 942 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 943 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 944 ppdu_info->rx_status.bw = HAL_RX_GET(rx_tlv, 945 #if !defined(QCA_WIFI_QCA6290_11AX) 946 PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH); 947 #else 948 PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 949 #endif 950 ppdu_info->rx_status.he_re = 0; 951 952 ppdu_info->rx_status.reception_type = HAL_RX_GET(rx_tlv, 953 PHYRX_RSSI_LEGACY_0, RECEPTION_TYPE); 954 955 value = HAL_RX_GET(rssi_info_tlv, 956 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 957 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 958 "RSSI_PRI20_CHAIN0: %d\n", value); 959 960 value = HAL_RX_GET(rssi_info_tlv, 961 RECEIVE_RSSI_INFO_0, RSSI_EXT20_CHAIN0); 962 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 963 "RSSI_EXT20_CHAIN0: %d\n", value); 964 965 value = HAL_RX_GET(rssi_info_tlv, 966 RECEIVE_RSSI_INFO_0, RSSI_EXT40_LOW20_CHAIN0); 967 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 968 "RSSI_EXT40_LOW20_CHAIN0: %d\n", value); 969 970 value = HAL_RX_GET(rssi_info_tlv, 971 RECEIVE_RSSI_INFO_0, RSSI_EXT40_HIGH20_CHAIN0); 972 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 973 "RSSI_EXT40_HIGH20_CHAIN0: %d\n", value); 974 975 value = HAL_RX_GET(rssi_info_tlv, 976 RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW20_CHAIN0); 977 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 978 "RSSI_EXT80_LOW20_CHAIN0: %d\n", value); 979 980 value = HAL_RX_GET(rssi_info_tlv, 981 RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW_HIGH20_CHAIN0); 982 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 983 "RSSI_EXT80_LOW_HIGH20_CHAIN0: %d\n", value); 984 985 value = HAL_RX_GET(rssi_info_tlv, 986 RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH_LOW20_CHAIN0); 987 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 988 "RSSI_EXT80_HIGH_LOW20_CHAIN0: %d\n", value); 989 990 value = HAL_RX_GET(rssi_info_tlv, 991 RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH20_CHAIN0); 992 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 993 "RSSI_EXT80_HIGH20_CHAIN0: %d\n", value); 994 break; 995 } 996 case WIFIRX_HEADER_E: 997 ppdu_info->first_msdu_payload = rx_tlv; 998 break; 999 case 0: 1000 return HAL_TLV_STATUS_PPDU_DONE; 1001 1002 default: 1003 break; 1004 } 1005 1006 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1007 "%s TLV type: %d, TLV len:%d", 1008 __func__, tlv_tag, tlv_len); 1009 1010 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1011 } 1012 1013 static inline 1014 uint32_t hal_get_rx_status_done_tlv_size(void *hal_soc) 1015 { 1016 return HAL_RX_TLV32_HDR_SIZE; 1017 } 1018 1019 static inline QDF_STATUS 1020 hal_get_rx_status_done(uint8_t *rx_tlv) 1021 { 1022 uint32_t tlv_tag; 1023 1024 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1025 1026 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 1027 return QDF_STATUS_SUCCESS; 1028 else 1029 return QDF_STATUS_E_EMPTY; 1030 } 1031 1032 static inline QDF_STATUS 1033 hal_clear_rx_status_done(uint8_t *rx_tlv) 1034 { 1035 *(uint32_t *)rx_tlv = 0; 1036 return QDF_STATUS_SUCCESS; 1037 } 1038 1039 #endif 1040