1 /* 2 * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_API_MON_H_ 20 #define _HAL_API_MON_H_ 21 22 #include "qdf_types.h" 23 #include "hal_internal.h" 24 #include <target_type.h> 25 26 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 27 #define HAL_RX_LSB(block, field) block##_##field##_LSB 28 #define HAL_RX_MASk(block, field) block##_##field##_MASK 29 30 #define HAL_RX_GET(_ptr, block, field) \ 31 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 32 HAL_RX_MASk(block, field)) >> \ 33 HAL_RX_LSB(block, field)) 34 35 #define HAL_RX_PHY_DATA_RADAR 0x01 36 #define HAL_SU_MU_CODING_LDPC 0x01 37 38 #define HAL_RX_FCS_LEN (4) 39 #define KEY_EXTIV 0x20 40 41 #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000 42 #define HAL_RX_USER_TLV32_TYPE_LSB 1 43 #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE 44 45 #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000 46 #define HAL_RX_USER_TLV32_LEN_LSB 10 47 #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00 48 49 #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000 50 #define HAL_RX_USER_TLV32_USERID_LSB 26 51 #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000 52 53 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 54 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 55 56 #define HAL_RX_TLV32_HDR_SIZE 4 57 58 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 59 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 60 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 61 HAL_RX_USER_TLV32_TYPE_LSB) 62 63 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 64 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 65 HAL_RX_USER_TLV32_LEN_MASK) >> \ 66 HAL_RX_USER_TLV32_LEN_LSB) 67 68 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 69 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 70 HAL_RX_USER_TLV32_USERID_MASK) >> \ 71 HAL_RX_USER_TLV32_USERID_LSB) 72 73 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 74 #define HAL_TLV_STATUS_PPDU_DONE 1 75 #define HAL_TLV_STATUS_BUF_DONE 2 76 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 77 78 79 #define HAL_MAX_UL_MU_USERS 8 80 81 #define HAL_RX_PKT_TYPE_11A 0 82 #define HAL_RX_PKT_TYPE_11B 1 83 #define HAL_RX_PKT_TYPE_11N 2 84 #define HAL_RX_PKT_TYPE_11AC 3 85 #define HAL_RX_PKT_TYPE_11AX 4 86 87 #define HAL_RX_RECEPTION_TYPE_SU 0 88 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 89 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 90 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 91 92 /* Multiply rate by 2 to avoid float point 93 * and get rate in units of 500kbps 94 */ 95 #define HAL_11B_RATE_0MCS 11*2 96 #define HAL_11B_RATE_1MCS 5.5*2 97 #define HAL_11B_RATE_2MCS 2*2 98 #define HAL_11B_RATE_3MCS 1*2 99 #define HAL_11B_RATE_4MCS 11*2 100 #define HAL_11B_RATE_5MCS 5.5*2 101 #define HAL_11B_RATE_6MCS 2*2 102 103 #define HAL_11A_RATE_0MCS 48*2 104 #define HAL_11A_RATE_1MCS 24*2 105 #define HAL_11A_RATE_2MCS 12*2 106 #define HAL_11A_RATE_3MCS 6*2 107 #define HAL_11A_RATE_4MCS 54*2 108 #define HAL_11A_RATE_5MCS 36*2 109 #define HAL_11A_RATE_6MCS 18*2 110 #define HAL_11A_RATE_7MCS 9*2 111 112 #define HE_GI_0_8 0 113 #define HE_GI_1_6 1 114 #define HE_GI_3_2 2 115 116 #define HT_SGI_PRESENT 0x80 117 118 #define HE_LTF_1_X 0 119 #define HE_LTF_2_X 1 120 #define HE_LTF_4_X 2 121 #define VHT_SIG_SU_NSS_MASK 0x7 122 123 #define HAL_TID_INVALID 31 124 #define HAL_AST_IDX_INVALID 0xFFFF 125 126 #ifdef GET_MSDU_AGGREGATION 127 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 128 {\ 129 struct rx_msdu_end *rx_msdu_end;\ 130 bool first_msdu, last_msdu; \ 131 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 132 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 133 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 134 if (first_msdu && last_msdu)\ 135 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 136 else\ 137 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 138 } \ 139 140 #else 141 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 142 #endif 143 144 #define HAL_MAC_ADDR_LEN 6 145 146 enum { 147 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 148 HAL_HW_RX_DECAP_FORMAT_NWIFI, 149 HAL_HW_RX_DECAP_FORMAT_ETH2, 150 HAL_HW_RX_DECAP_FORMAT_8023, 151 }; 152 153 enum { 154 DP_PPDU_STATUS_START, 155 DP_PPDU_STATUS_DONE, 156 }; 157 158 static inline 159 uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void) 160 { 161 /* return the HW_RX_DESC size */ 162 return sizeof(struct rx_pkt_tlvs); 163 } 164 165 static inline 166 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 167 { 168 return data; 169 } 170 171 static inline 172 uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr) 173 { 174 struct rx_attention *rx_attn; 175 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 176 177 rx_attn = &rx_desc->attn_tlv.rx_attn; 178 179 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 180 } 181 182 static inline 183 uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr) 184 { 185 struct rx_attention *rx_attn; 186 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 187 188 rx_attn = &rx_desc->attn_tlv.rx_attn; 189 190 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 191 } 192 193 static inline 194 uint32_t 195 HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) { 196 struct rx_msdu_start *rx_msdu_start; 197 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 198 199 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 200 201 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 202 } 203 204 static inline 205 uint8_t * 206 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 207 uint8_t *rx_pkt_hdr; 208 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 209 210 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 211 212 return rx_pkt_hdr; 213 } 214 215 /* 216 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 217 * start TLV of Hardware TLV descriptor 218 * @hw_desc_addr: Hardware desciptor address 219 * 220 * Return: bool: if TLV tag match 221 */ 222 static inline 223 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 224 { 225 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 226 uint32_t tlv_tag; 227 228 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 229 &rx_desc->mpdu_start_tlv); 230 231 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 232 } 233 234 static inline 235 uint32_t HAL_RX_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr) 236 { 237 struct rx_mpdu_info *rx_mpdu_info; 238 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 239 240 rx_mpdu_info = 241 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 242 243 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 244 } 245 246 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 247 static inline 248 uint32_t hal_rx_desc_is_first_msdu(void *hw_desc_addr) 249 { 250 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 251 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 252 253 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 254 } 255 256 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 257 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 258 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 259 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 260 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 261 262 #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \ 263 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 264 (((struct reo_entrance_ring *)reo_ent_desc) \ 265 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 266 267 #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \ 268 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 269 (((struct reo_entrance_ring *)reo_ent_desc) \ 270 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 271 272 #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \ 273 (HAL_RX_BUF_COOKIE_GET(& \ 274 (((struct reo_entrance_ring *)reo_ent_desc) \ 275 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 276 277 /** 278 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 279 * cookie from the REO entrance ring element 280 * 281 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 282 * the current descriptor 283 * @ buf_info: structure to return the buffer information 284 * @ msdu_cnt: pointer to msdu count in MPDU 285 * Return: void 286 */ 287 static inline 288 void hal_rx_reo_ent_buf_paddr_get(void *rx_desc, 289 struct hal_buf_info *buf_info, 290 void **pp_buf_addr_info, 291 uint32_t *msdu_cnt 292 ) 293 { 294 struct reo_entrance_ring *reo_ent_ring = 295 (struct reo_entrance_ring *)rx_desc; 296 struct buffer_addr_info *buf_addr_info; 297 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 298 uint32_t loop_cnt; 299 300 rx_mpdu_desc_info_details = 301 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 302 303 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 304 RX_MPDU_DESC_INFO_0, MSDU_COUNT); 305 306 loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT); 307 308 buf_addr_info = 309 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 310 311 buf_info->paddr = 312 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 313 ((uint64_t) 314 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 315 316 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 317 318 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 319 "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 320 __func__, __LINE__, reo_ent_ring, buf_addr_info, 321 (unsigned long long)buf_info->paddr, loop_cnt); 322 323 *pp_buf_addr_info = (void *)buf_addr_info; 324 } 325 326 static inline 327 void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 328 struct hal_buf_info *buf_info, void **pp_buf_addr_info) 329 { 330 struct rx_msdu_link *msdu_link = 331 (struct rx_msdu_link *)rx_msdu_link_desc; 332 struct buffer_addr_info *buf_addr_info; 333 334 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 335 336 buf_info->paddr = 337 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 338 ((uint64_t) 339 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 340 341 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 342 343 *pp_buf_addr_info = (void *)buf_addr_info; 344 } 345 346 /** 347 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 348 * 349 * @ soc : HAL version of the SOC pointer 350 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 351 * @ buf_addr_info : void pointer to the buffer_addr_info 352 * 353 * Return: void 354 */ 355 356 static inline void hal_rx_mon_msdu_link_desc_set(struct hal_soc *soc, 357 void *src_srng_desc, void *buf_addr_info) 358 { 359 struct buffer_addr_info *wbm_srng_buffer_addr_info = 360 (struct buffer_addr_info *)src_srng_desc; 361 uint64_t paddr; 362 struct buffer_addr_info *p_buffer_addr_info = 363 (struct buffer_addr_info *)buf_addr_info; 364 365 paddr = 366 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 367 ((uint64_t) 368 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 369 370 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 371 "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 372 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 373 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 374 375 /* Structure copy !!! */ 376 *wbm_srng_buffer_addr_info = 377 *((struct buffer_addr_info *)buf_addr_info); 378 } 379 380 static inline 381 uint32 hal_get_rx_msdu_link_desc_size(void) 382 { 383 return sizeof(struct rx_msdu_link); 384 } 385 386 enum { 387 HAL_PKT_TYPE_OFDM = 0, 388 HAL_PKT_TYPE_CCK, 389 HAL_PKT_TYPE_HT, 390 HAL_PKT_TYPE_VHT, 391 HAL_PKT_TYPE_HE, 392 }; 393 394 enum { 395 HAL_SGI_0_8_US, 396 HAL_SGI_0_4_US, 397 HAL_SGI_1_6_US, 398 HAL_SGI_3_2_US, 399 }; 400 401 enum { 402 HAL_FULL_RX_BW_20, 403 HAL_FULL_RX_BW_40, 404 HAL_FULL_RX_BW_80, 405 HAL_FULL_RX_BW_160, 406 }; 407 408 enum { 409 HAL_RX_TYPE_SU, 410 HAL_RX_TYPE_MU_MIMO, 411 HAL_RX_TYPE_MU_OFDMA, 412 HAL_RX_TYPE_MU_OFDMA_MIMO, 413 }; 414 415 /** 416 * enum 417 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 418 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL 419 */ 420 enum { 421 HAL_RX_MON_PPDU_START = 0, 422 HAL_RX_MON_PPDU_END, 423 }; 424 425 struct hal_rx_ppdu_user_info { 426 427 }; 428 429 struct hal_rx_ppdu_common_info { 430 uint32_t ppdu_id; 431 uint32_t ppdu_timestamp; 432 uint32_t mpdu_cnt_fcs_ok; 433 uint32_t mpdu_cnt_fcs_err; 434 }; 435 436 struct hal_rx_msdu_payload_info { 437 uint8_t *first_msdu_payload; 438 uint32_t payload_len; 439 }; 440 441 /** 442 * struct hal_rx_nac_info - struct for neighbour info 443 * @fc_valid: flag indicate if it has valid frame control information 444 * @to_ds_flag: flag indicate to_ds bit 445 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 446 * @mac_addr2: mac address2 in wh 447 */ 448 struct hal_rx_nac_info { 449 uint8_t fc_valid; 450 uint8_t to_ds_flag; 451 uint8_t mac_addr2_valid; 452 uint8_t mac_addr2[HAL_MAC_ADDR_LEN]; 453 }; 454 455 struct hal_rx_ppdu_info { 456 struct hal_rx_ppdu_common_info com_info; 457 struct hal_rx_ppdu_user_info user_info[HAL_MAX_UL_MU_USERS]; 458 struct mon_rx_status rx_status; 459 struct hal_rx_msdu_payload_info msdu_info; 460 struct hal_rx_nac_info nac_info; 461 /* status ring PPDU start and end state */ 462 uint32_t rx_state; 463 }; 464 465 static inline uint32_t 466 hal_get_rx_status_buf_size(void) { 467 /* RX status buffer size is hard coded for now */ 468 return 2048; 469 } 470 471 static inline uint8_t* 472 hal_rx_status_get_next_tlv(uint8_t *rx_tlv) { 473 uint32_t tlv_len, tlv_tag; 474 475 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 476 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 477 478 /* The actual length of PPDU_END is the combined length of many PHY 479 * TLVs that follow. Skip the TLV header and 480 * rx_rxpcu_classification_overview that follows the header to get to 481 * next TLV. 482 */ 483 if (tlv_tag == WIFIRX_PPDU_END_E) 484 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 485 486 return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len + 487 HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3))); 488 } 489 490 /** 491 * hal_rx_proc_phyrx_other_receive_info_tlv() 492 * - process other receive info TLV 493 * @rx_tlv_hdr: pointer to TLV header 494 * @ppdu_info: pointer to ppdu_info 495 * 496 * Return: None 497 */ 498 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 499 void *rx_tlv_hdr, 500 struct hal_rx_ppdu_info 501 *ppdu_info) 502 { 503 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 504 (void *)ppdu_info); 505 } 506 507 /** 508 * hal_rx_status_get_tlv_info() - process receive info TLV 509 * @rx_tlv_hdr: pointer to TLV header 510 * @ppdu_info: pointer to ppdu_info 511 * 512 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 513 */ 514 static inline uint32_t 515 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 516 struct hal_soc *hal_soc) 517 { 518 return hal_soc->ops->hal_rx_status_get_tlv_info(rx_tlv_hdr, 519 ppdu_info, hal_soc); 520 } 521 522 static inline 523 uint32_t hal_get_rx_status_done_tlv_size(void *hal_soc) 524 { 525 return HAL_RX_TLV32_HDR_SIZE; 526 } 527 528 static inline QDF_STATUS 529 hal_get_rx_status_done(uint8_t *rx_tlv) 530 { 531 uint32_t tlv_tag; 532 533 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 534 535 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 536 return QDF_STATUS_SUCCESS; 537 else 538 return QDF_STATUS_E_EMPTY; 539 } 540 541 static inline QDF_STATUS 542 hal_clear_rx_status_done(uint8_t *rx_tlv) 543 { 544 *(uint32_t *)rx_tlv = 0; 545 return QDF_STATUS_SUCCESS; 546 } 547 548 #endif 549