1 /* 2 * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_API_MON_H_ 20 #define _HAL_API_MON_H_ 21 22 #include "qdf_types.h" 23 #include "hal_internal.h" 24 #include "hal_hw_headers.h" 25 #include <target_type.h> 26 27 #define HAL_RX_PHY_DATA_RADAR 0x01 28 #define HAL_SU_MU_CODING_LDPC 0x01 29 30 #define HAL_RX_FCS_LEN (4) 31 #define KEY_EXTIV 0x20 32 33 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 34 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 35 36 #define HAL_RX_TLV32_HDR_SIZE 4 37 38 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 39 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 40 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 41 HAL_RX_USER_TLV32_TYPE_LSB) 42 43 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 44 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 45 HAL_RX_USER_TLV32_LEN_MASK) >> \ 46 HAL_RX_USER_TLV32_LEN_LSB) 47 48 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 49 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 50 HAL_RX_USER_TLV32_USERID_MASK) >> \ 51 HAL_RX_USER_TLV32_USERID_LSB) 52 53 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 54 #define HAL_TLV_STATUS_PPDU_DONE 1 55 #define HAL_TLV_STATUS_BUF_DONE 2 56 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 57 #define HAL_TLV_STATUS_PPDU_START 4 58 #define HAL_TLV_STATUS_HEADER 5 59 #define HAL_TLV_STATUS_MPDU_END 6 60 #define HAL_TLV_STATUS_MSDU_START 7 61 #define HAL_TLV_STATUS_MSDU_END 8 62 63 #define HAL_MAX_UL_MU_USERS 37 64 65 #define HAL_RX_PKT_TYPE_11A 0 66 #define HAL_RX_PKT_TYPE_11B 1 67 #define HAL_RX_PKT_TYPE_11N 2 68 #define HAL_RX_PKT_TYPE_11AC 3 69 #define HAL_RX_PKT_TYPE_11AX 4 70 71 #define HAL_RX_RECEPTION_TYPE_SU 0 72 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 73 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 74 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 75 76 /* Multiply rate by 2 to avoid float point 77 * and get rate in units of 500kbps 78 */ 79 #define HAL_11B_RATE_0MCS 11*2 80 #define HAL_11B_RATE_1MCS 5.5*2 81 #define HAL_11B_RATE_2MCS 2*2 82 #define HAL_11B_RATE_3MCS 1*2 83 #define HAL_11B_RATE_4MCS 11*2 84 #define HAL_11B_RATE_5MCS 5.5*2 85 #define HAL_11B_RATE_6MCS 2*2 86 87 #define HAL_11A_RATE_0MCS 48*2 88 #define HAL_11A_RATE_1MCS 24*2 89 #define HAL_11A_RATE_2MCS 12*2 90 #define HAL_11A_RATE_3MCS 6*2 91 #define HAL_11A_RATE_4MCS 54*2 92 #define HAL_11A_RATE_5MCS 36*2 93 #define HAL_11A_RATE_6MCS 18*2 94 #define HAL_11A_RATE_7MCS 9*2 95 96 #define HAL_LEGACY_MCS0 0 97 #define HAL_LEGACY_MCS1 1 98 #define HAL_LEGACY_MCS2 2 99 #define HAL_LEGACY_MCS3 3 100 #define HAL_LEGACY_MCS4 4 101 #define HAL_LEGACY_MCS5 5 102 #define HAL_LEGACY_MCS6 6 103 #define HAL_LEGACY_MCS7 7 104 105 #define HE_GI_0_8 0 106 #define HE_GI_0_4 1 107 #define HE_GI_1_6 2 108 #define HE_GI_3_2 3 109 110 #define HE_GI_RADIOTAP_0_8 0 111 #define HE_GI_RADIOTAP_1_6 1 112 #define HE_GI_RADIOTAP_3_2 2 113 #define HE_GI_RADIOTAP_RESERVED 3 114 115 #define HE_LTF_RADIOTAP_UNKNOWN 0 116 #define HE_LTF_RADIOTAP_1_X 1 117 #define HE_LTF_RADIOTAP_2_X 2 118 #define HE_LTF_RADIOTAP_4_X 3 119 120 #define HT_SGI_PRESENT 0x80 121 122 #define HE_LTF_1_X 0 123 #define HE_LTF_2_X 1 124 #define HE_LTF_4_X 2 125 #define HE_LTF_UNKNOWN 3 126 #define VHT_SIG_SU_NSS_MASK 0x7 127 #define HT_SIG_SU_NSS_SHIFT 0x3 128 129 #define HAL_TID_INVALID 31 130 #define HAL_AST_IDX_INVALID 0xFFFF 131 132 #ifdef GET_MSDU_AGGREGATION 133 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 134 {\ 135 struct rx_msdu_end *rx_msdu_end;\ 136 bool first_msdu, last_msdu; \ 137 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 138 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 139 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 140 if (first_msdu && last_msdu)\ 141 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 142 else\ 143 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 144 } \ 145 146 #define HAL_RX_SET_MSDU_AGGREGATION((rs_mpdu), (rs_ppdu))\ 147 {\ 148 if (rs_mpdu->rs_flags & IEEE80211_AMSDU_FLAG)\ 149 rs_ppdu->rs_flags |= IEEE80211_AMSDU_FLAG;\ 150 } \ 151 152 #else 153 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 154 #define HAL_RX_SET_MSDU_AGGREGATION(rs_mpdu, rs_ppdu) 155 #endif 156 157 /* Max MPDUs per status buffer */ 158 #define HAL_RX_MAX_MPDU 256 159 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 160 #define HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER 16 161 162 /* Max pilot count */ 163 #define HAL_RX_MAX_SU_EVM_COUNT 32 164 165 #define HAL_RX_FRAMECTRL_TYPE_MASK 0x0C 166 #define HAL_RX_GET_FRAME_CTRL_TYPE(fc)\ 167 (((fc) & HAL_RX_FRAMECTRL_TYPE_MASK) >> 2) 168 #define HAL_RX_FRAME_CTRL_TYPE_MGMT 0x0 169 #define HAL_RX_FRAME_CTRL_TYPE_CTRL 0x1 170 #define HAL_RX_FRAME_CTRL_TYPE_DATA 0x2 171 172 /** 173 * struct hal_rx_mon_desc_info () - HAL Rx Monitor descriptor info 174 * 175 * @ppdu_id: PHY ppdu id 176 * @status_ppdu_id: status PHY ppdu id 177 * @status_buf_count: number of status buffer count 178 * @rxdma_push_reason: rxdma push reason 179 * @rxdma_error_code: rxdma error code 180 * @msdu_cnt: msdu count 181 * @end_of_ppdu: end of ppdu 182 * @link_desc: msdu link descriptor address 183 * @status_buf: for a PPDU, status buffers can span acrosss 184 * multiple buffers, status_buf points to first 185 * status buffer address of PPDU 186 * @drop_ppdu: flag to indicate current destination 187 * ring ppdu drop 188 */ 189 struct hal_rx_mon_desc_info { 190 uint16_t ppdu_id; 191 uint16_t status_ppdu_id; 192 uint8_t status_buf_count; 193 uint8_t rxdma_push_reason; 194 uint8_t rxdma_error_code; 195 uint8_t msdu_count; 196 uint8_t end_of_ppdu; 197 struct hal_buf_info link_desc; 198 struct hal_buf_info status_buf; 199 bool drop_ppdu; 200 }; 201 202 /* 203 * Struct hal_rx_su_evm_info - SU evm info 204 * @number_of_symbols: number of symbols 205 * @nss_count: nss count 206 * @pilot_count: pilot count 207 * @pilot_evm: Array of pilot evm values 208 */ 209 struct hal_rx_su_evm_info { 210 uint32_t number_of_symbols; 211 uint8_t nss_count; 212 uint8_t pilot_count; 213 uint32_t pilot_evm[HAL_RX_MAX_SU_EVM_COUNT]; 214 }; 215 216 enum { 217 DP_PPDU_STATUS_START, 218 DP_PPDU_STATUS_DONE, 219 }; 220 221 /** 222 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 223 * cookie from the REO entrance ring element 224 * @hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 225 * the current descriptor 226 * @ buf_info: structure to return the buffer information 227 * @ msdu_cnt: pointer to msdu count in MPDU 228 * 229 * CAUTION: This API calls a hal_soc ops, so be careful before calling this in 230 * per packet path 231 * 232 * Return: void 233 */ 234 static inline 235 void hal_rx_reo_ent_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 236 hal_rxdma_desc_t rx_desc, 237 struct hal_buf_info *buf_info, 238 uint32_t *msdu_cnt) 239 { 240 struct reo_entrance_ring *reo_ent_ring = 241 (struct reo_entrance_ring *)rx_desc; 242 struct buffer_addr_info *buf_addr_info; 243 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 244 uint32_t loop_cnt; 245 246 rx_mpdu_desc_info_details = 247 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 248 249 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 250 HAL_RX_MPDU_DESC_INFO, MSDU_COUNT); 251 252 loop_cnt = HAL_RX_GET(reo_ent_ring, HAL_REO_ENTRANCE_RING, 253 LOOPING_COUNT); 254 255 buf_addr_info = 256 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 257 258 hal_rx_buf_cookie_rbm_get(hal_soc_hdl, (uint32_t *)buf_addr_info, 259 buf_info); 260 buf_info->paddr = 261 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 262 ((uint64_t) 263 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 264 265 dp_nofl_debug("[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 266 __func__, __LINE__, reo_ent_ring, buf_addr_info, 267 (unsigned long long)buf_info->paddr, loop_cnt); 268 } 269 270 static inline 271 void hal_rx_mon_next_link_desc_get(hal_soc_handle_t hal_soc_hdl, 272 void *rx_msdu_link_desc, 273 struct hal_buf_info *buf_info) 274 { 275 struct rx_msdu_link *msdu_link = 276 (struct rx_msdu_link *)rx_msdu_link_desc; 277 struct buffer_addr_info *buf_addr_info; 278 279 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 280 281 hal_rx_buf_cookie_rbm_get(hal_soc_hdl, (uint32_t *)buf_addr_info, 282 buf_info); 283 284 buf_info->paddr = 285 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 286 ((uint64_t) 287 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 288 } 289 290 static inline 291 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 292 { 293 return data; 294 } 295 296 static inline uint32_t 297 hal_rx_tlv_mpdu_len_err_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 298 { 299 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 300 301 if (!hal_soc || !hal_soc->ops) { 302 hal_err("hal handle is NULL"); 303 QDF_BUG(0); 304 return 0; 305 } 306 307 if (hal_soc->ops->hal_rx_tlv_mpdu_len_err_get) 308 return hal_soc->ops->hal_rx_tlv_mpdu_len_err_get(hw_desc_addr); 309 310 return 0; 311 } 312 313 static inline uint32_t 314 hal_rx_tlv_mpdu_fcs_err_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 315 { 316 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 317 318 if (!hal_soc || !hal_soc->ops) { 319 hal_err("hal handle is NULL"); 320 QDF_BUG(0); 321 return 0; 322 } 323 324 if (hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get) 325 return hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get(hw_desc_addr); 326 327 return 0; 328 } 329 330 #ifdef notyet 331 /* 332 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 333 * start TLV of Hardware TLV descriptor 334 * @hw_desc_addr: Hardware descriptor address 335 * 336 * Return: bool: if TLV tag match 337 */ 338 static inline 339 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 340 { 341 struct rx_mon_pkt_tlvs *rx_desc = 342 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 343 uint32_t tlv_tag; 344 345 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 346 347 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 348 } 349 #endif 350 351 /* 352 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV user id in MPDU 353 * start TLV of Hardware TLV descriptor 354 * @hw_desc_addr: Hardware descriptor address 355 * 356 * Return: unit32_t: user id 357 */ 358 static inline uint32_t 359 hal_rx_hw_desc_mpdu_user_id(hal_soc_handle_t hal_soc_hdl, 360 void *hw_desc_addr) 361 { 362 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 363 364 if (!hal_soc || !hal_soc->ops) { 365 hal_err("hal handle is NULL"); 366 QDF_BUG(0); 367 return 0; 368 } 369 370 if (hal_soc->ops->hal_rx_hw_desc_mpdu_user_id) 371 return hal_soc->ops->hal_rx_hw_desc_mpdu_user_id(hw_desc_addr); 372 373 return 0; 374 } 375 376 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 377 378 /** 379 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 380 * 381 * @ soc : HAL version of the SOC pointer 382 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 383 * @ buf_addr_info : void pointer to the buffer_addr_info 384 * 385 * Return: void 386 */ 387 static inline 388 void hal_rx_mon_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 389 void *src_srng_desc, 390 hal_buff_addrinfo_t buf_addr_info) 391 { 392 struct buffer_addr_info *wbm_srng_buffer_addr_info = 393 (struct buffer_addr_info *)src_srng_desc; 394 uint64_t paddr; 395 struct buffer_addr_info *p_buffer_addr_info = 396 (struct buffer_addr_info *)buf_addr_info; 397 398 paddr = 399 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 400 ((uint64_t) 401 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 402 403 dp_nofl_debug("[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 404 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 405 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 406 407 /* Structure copy !!! */ 408 *wbm_srng_buffer_addr_info = 409 *((struct buffer_addr_info *)buf_addr_info); 410 } 411 412 /** 413 * hal_get_rx_msdu_link_desc_size() - Get msdu link descriptor size 414 * 415 * Return: size of rx_msdu_link 416 */ 417 static inline 418 uint32_t hal_get_rx_msdu_link_desc_size(void) 419 { 420 return sizeof(struct rx_msdu_link); 421 } 422 423 enum { 424 HAL_PKT_TYPE_OFDM = 0, 425 HAL_PKT_TYPE_CCK, 426 HAL_PKT_TYPE_HT, 427 HAL_PKT_TYPE_VHT, 428 HAL_PKT_TYPE_HE, 429 }; 430 431 enum { 432 HAL_SGI_0_8_US, 433 HAL_SGI_0_4_US, 434 HAL_SGI_1_6_US, 435 HAL_SGI_3_2_US, 436 }; 437 438 enum { 439 HAL_FULL_RX_BW_20, 440 HAL_FULL_RX_BW_40, 441 HAL_FULL_RX_BW_80, 442 HAL_FULL_RX_BW_160, 443 }; 444 445 enum { 446 HAL_RX_TYPE_SU, 447 HAL_RX_TYPE_MU_MIMO, 448 HAL_RX_TYPE_MU_OFDMA, 449 HAL_RX_TYPE_MU_OFDMA_MIMO, 450 }; 451 452 /** 453 * enum 454 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 455 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decoded in HAL 456 * @HAL_RX_MON_PPDU_RESET: Not PPDU start and end TLV 457 */ 458 enum { 459 HAL_RX_MON_PPDU_START = 0, 460 HAL_RX_MON_PPDU_END, 461 HAL_RX_MON_PPDU_RESET, 462 }; 463 464 /* struct hal_rx_ppdu_common_info - common ppdu info 465 * @ppdu_id - ppdu id number 466 * @ppdu_timestamp - timestamp at ppdu received 467 * @mpdu_cnt_fcs_ok - mpdu count in ppdu with fcs ok 468 * @mpdu_cnt_fcs_err - mpdu count in ppdu with fcs err 469 * @mpdu_fcs_ok_bitmap - fcs ok mpdu count in ppdu bitmap 470 * @last_ppdu_id - last received ppdu id 471 * @mpdu_cnt - total mpdu count 472 * @num_users - num users 473 */ 474 struct hal_rx_ppdu_common_info { 475 uint32_t ppdu_id; 476 uint32_t ppdu_timestamp; 477 uint32_t mpdu_cnt_fcs_ok; 478 uint32_t mpdu_cnt_fcs_err; 479 uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 480 uint32_t last_ppdu_id; 481 uint32_t mpdu_cnt; 482 uint8_t num_users; 483 }; 484 485 /** 486 * struct hal_rx_msdu_payload_info - msdu payload info 487 * @first_msdu_payload: pointer to first msdu payload 488 * @payload_len: payload len 489 */ 490 struct hal_rx_msdu_payload_info { 491 uint8_t *first_msdu_payload; 492 uint32_t payload_len; 493 }; 494 495 /** 496 * struct hal_rx_nac_info - struct for neighbour info 497 * @fc_valid: flag indicate if it has valid frame control information 498 * @frame_control: frame control from each MPDU 499 * @to_ds_flag: flag indicate to_ds bit 500 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 501 * @mac_addr2: mac address2 in wh 502 * @mcast_bcast: multicast/broadcast 503 */ 504 struct hal_rx_nac_info { 505 uint8_t fc_valid; 506 uint16_t frame_control; 507 uint8_t to_ds_flag; 508 uint8_t mac_addr2_valid; 509 uint8_t mac_addr2[QDF_MAC_ADDR_SIZE]; 510 uint8_t mcast_bcast; 511 }; 512 513 /** 514 * struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs 515 * @cce_metadata: cached CCE metadata value received in the MSDU_END TLV 516 * @is_flow_idx_timeout: flag to indicate if flow search timeout occurred 517 * @is_flow_idx_invalid: flag to indicate if flow idx is valid or not 518 * @fse_metadata: cached FSE metadata value received in the MSDU END TLV 519 * @flow_idx: flow idx matched in FSE received in the MSDU END TLV 520 */ 521 struct hal_rx_ppdu_msdu_info { 522 uint16_t cce_metadata; 523 bool is_flow_idx_timeout; 524 bool is_flow_idx_invalid; 525 uint32_t fse_metadata; 526 uint32_t flow_idx; 527 }; 528 529 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 530 /** 531 * struct hal_rx_ppdu_cfr_user_info - struct for storing peer info extracted 532 * from HW TLVs, this will be used for correlating CFR data with multiple peers 533 * in MU PPDUs 534 * 535 * @peer_macaddr: macaddr of the peer 536 * @ast_index: AST index of the peer 537 */ 538 struct hal_rx_ppdu_cfr_user_info { 539 uint8_t peer_macaddr[QDF_MAC_ADDR_SIZE]; 540 uint32_t ast_index; 541 }; 542 543 /** 544 * struct hal_rx_ppdu_cfr_info - struct for storing ppdu info extracted from HW 545 * TLVs, this will be used for CFR correlation 546 * 547 * @bb_captured_channel : Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 548 * sent to PHY, SW checks it to correlate current PPDU TLVs with uploaded 549 * channel information. 550 * 551 * @bb_captured_timeout : Set by RxPCU to indicate channel capture condition is 552 * met, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due to AST delay, 553 * which means the rx_frame_falling edge to FREEZE TLV ready time exceeds 554 * the threshold time defined by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 555 * Bb_captured_reason is still valid in this case. 556 * 557 * @rx_location_info_valid: Indicates whether CFR DMA address in the PPDU TLV 558 * is valid 559 * <enum 0 rx_location_info_is_not_valid> 560 * <enum 1 rx_location_info_is_valid> 561 * <legal all> 562 * 563 * @bb_captured_reason : Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL 564 * TLV to here for FW usage. Valid when bb_captured_channel or 565 * bb_captured_timeout is set. 566 * <enum 0 freeze_reason_TM> 567 * <enum 1 freeze_reason_FTM> 568 * <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 569 * <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 570 * <enum 4 freeze_reason_NDPA_NDP> 571 * <enum 5 freeze_reason_ALL_PACKET> 572 * <legal 0-5> 573 * 574 * @rtt_che_buffer_pointer_low32 : The low 32 bits of the 40 bits pointer to 575 * external RTT channel information buffer 576 * 577 * @rtt_che_buffer_pointer_high8 : The high 8 bits of the 40 bits pointer to 578 * external RTT channel information buffer 579 * 580 * @chan_capture_status : capture status reported by ucode 581 * a. CAPTURE_IDLE: FW has disabled "REPETITIVE_CHE_CAPTURE_CTRL" 582 * b. CAPTURE_BUSY: previous PPDU’s channel capture upload DMA ongoing. (Note 583 * that this upload is triggered after receiving freeze_channel_capture TLV 584 * after last PPDU is rx) 585 * c. CAPTURE_ACTIVE: channel capture is enabled and no previous channel 586 * capture ongoing 587 * d. CAPTURE_NO_BUFFER: next buffer in IPC ring not available 588 * 589 * @cfr_user_info: Peer mac for upto 4 MU users 590 * 591 * @rtt_cfo_measurement : raw cfo data extracted from hardware, which is 14 bit 592 * signed number. The first bit used for sign representation and 13 bits for 593 * fractional part. 594 * 595 * @agc_gain_info0: Chain 0 & chain 1 agc gain information reported by PHY 596 * 597 * @agc_gain_info1: Chain 2 & chain 3 agc gain information reported by PHY 598 * 599 * @agc_gain_info2: Chain 4 & chain 5 agc gain information reported by PHY 600 * 601 * @agc_gain_info3: Chain 6 & chain 7 agc gain information reported by PHY 602 * 603 * @rx_start_ts: Rx packet timestamp, the time the first L-STF ADC sample 604 * arrived at Rx antenna. 605 * 606 * @mcs_rate: Indicates the mcs/rate in which packet is received. 607 * If HT, 608 * 0-7: MCS0-MCS7 609 * If VHT, 610 * 0-9: MCS0 to MCS9 611 * If HE, 612 * 0-11: MCS0 to MCS11, 613 * 12-13: 4096QAM, 614 * 14-15: reserved 615 * If Legacy, 616 * 0: 48 Mbps 617 * 1: 24 Mbps 618 * 2: 12 Mbps 619 * 3: 6 Mbps 620 * 4: 54 Mbps 621 * 5: 36 Mbps 622 * 6: 18 Mbps 623 * 7: 9 Mbps 624 * 625 * @gi_type: Indicates the gaurd interval. 626 * 0: 0.8 us 627 * 1: 0.4 us 628 * 2: 1.6 us 629 * 3: 3.2 us 630 */ 631 struct hal_rx_ppdu_cfr_info { 632 bool bb_captured_channel; 633 bool bb_captured_timeout; 634 uint8_t bb_captured_reason; 635 bool rx_location_info_valid; 636 uint8_t chan_capture_status; 637 uint8_t rtt_che_buffer_pointer_high8; 638 uint32_t rtt_che_buffer_pointer_low32; 639 struct hal_rx_ppdu_cfr_user_info cfr_user_info[HAL_MAX_UL_MU_USERS]; 640 int16_t rtt_cfo_measurement; 641 uint32_t agc_gain_info0; 642 uint32_t agc_gain_info1; 643 uint32_t agc_gain_info2; 644 uint32_t agc_gain_info3; 645 uint32_t rx_start_ts; 646 uint32_t mcs_rate; 647 uint32_t gi_type; 648 }; 649 #else 650 struct hal_rx_ppdu_cfr_info {}; 651 #endif 652 653 struct mon_rx_info { 654 uint8_t qos_control_info_valid; 655 uint16_t qos_control; 656 uint8_t mac_addr1_valid; 657 uint8_t mac_addr1[QDF_MAC_ADDR_SIZE]; 658 uint32_t user_id; 659 }; 660 661 struct mon_rx_user_info { 662 uint16_t qos_control; 663 uint8_t qos_control_info_valid; 664 }; 665 666 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 667 struct hal_rx_frm_type_info { 668 uint32_t rx_mgmt_cnt; 669 uint32_t rx_ctrl_cnt; 670 uint32_t rx_data_cnt; 671 }; 672 #else 673 struct hal_rx_frm_type_info {}; 674 #endif 675 676 struct hal_rx_ppdu_info { 677 struct hal_rx_ppdu_common_info com_info; 678 struct mon_rx_status rx_status; 679 struct mon_rx_user_status rx_user_status[HAL_MAX_UL_MU_USERS]; 680 struct mon_rx_info rx_info; 681 struct mon_rx_user_info rx_user_info[HAL_MAX_UL_MU_USERS]; 682 struct hal_rx_msdu_payload_info msdu_info; 683 struct hal_rx_msdu_payload_info fcs_ok_msdu_info; 684 struct hal_rx_nac_info nac_info; 685 /* status ring PPDU start and end state */ 686 uint32_t rx_state; 687 /* MU user id for status ring TLV */ 688 uint32_t user_id; 689 /* MPDU/MSDU truncated to 128 bytes header start addr in status skb */ 690 unsigned char *data; 691 /* MPDU/MSDU truncated to 128 bytes header real length */ 692 uint32_t hdr_len; 693 /* MPDU FCS error */ 694 bool fcs_err; 695 /* Id to indicate how to process mpdu */ 696 uint8_t sw_frame_group_id; 697 struct hal_rx_ppdu_msdu_info rx_msdu_info[HAL_MAX_UL_MU_USERS]; 698 /* fcs passed mpdu count in rx monitor status buffer */ 699 uint8_t fcs_ok_cnt; 700 /* fcs error mpdu count in rx monitor status buffer */ 701 uint8_t fcs_err_cnt; 702 /* MPDU FCS passed */ 703 bool is_fcs_passed; 704 /* first msdu payload for all mpdus in rx monitor status buffer */ 705 struct hal_rx_msdu_payload_info ppdu_msdu_info[HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER]; 706 /* evm info */ 707 struct hal_rx_su_evm_info evm_info; 708 /** 709 * Will be used to store ppdu info extracted from HW TLVs, 710 * and for CFR correlation as well 711 */ 712 struct hal_rx_ppdu_cfr_info cfr_info; 713 /* per frame type counts */ 714 struct hal_rx_frm_type_info frm_type_info; 715 }; 716 717 static inline uint32_t 718 hal_get_rx_status_buf_size(void) { 719 /* RX status buffer size is hard coded for now */ 720 return 2048; 721 } 722 723 static inline uint8_t* 724 hal_rx_status_get_next_tlv(uint8_t *rx_tlv) { 725 uint32_t tlv_len, tlv_tag; 726 727 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 728 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 729 730 /* The actual length of PPDU_END is the combined length of many PHY 731 * TLVs that follow. Skip the TLV header and 732 * rx_rxpcu_classification_overview that follows the header to get to 733 * next TLV. 734 */ 735 if (tlv_tag == WIFIRX_PPDU_END_E) 736 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 737 738 return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len + 739 HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3))); 740 } 741 742 /** 743 * hal_rx_proc_phyrx_other_receive_info_tlv() 744 * - process other receive info TLV 745 * @rx_tlv_hdr: pointer to TLV header 746 * @ppdu_info: pointer to ppdu_info 747 * 748 * Return: None 749 */ 750 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 751 void *rx_tlv_hdr, 752 struct hal_rx_ppdu_info 753 *ppdu_info) 754 { 755 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 756 (void *)ppdu_info); 757 } 758 759 /** 760 * hal_rx_status_get_tlv_info() - process receive info TLV 761 * @rx_tlv_hdr: pointer to TLV header 762 * @ppdu_info: pointer to ppdu_info 763 * @hal_soc: HAL soc handle 764 * @nbuf: PPDU status netowrk buffer 765 * 766 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 767 */ 768 static inline uint32_t 769 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 770 hal_soc_handle_t hal_soc_hdl, 771 qdf_nbuf_t nbuf) 772 { 773 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 774 775 return hal_soc->ops->hal_rx_status_get_tlv_info( 776 rx_tlv_hdr, 777 ppdu_info, 778 hal_soc_hdl, 779 nbuf); 780 } 781 782 static inline 783 uint32_t hal_get_rx_status_done_tlv_size(hal_soc_handle_t hal_soc_hdl) 784 { 785 return HAL_RX_TLV32_HDR_SIZE; 786 } 787 788 static inline QDF_STATUS 789 hal_get_rx_status_done(uint8_t *rx_tlv) 790 { 791 uint32_t tlv_tag; 792 793 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 794 795 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 796 return QDF_STATUS_SUCCESS; 797 else 798 return QDF_STATUS_E_EMPTY; 799 } 800 801 static inline QDF_STATUS 802 hal_clear_rx_status_done(uint8_t *rx_tlv) 803 { 804 *(uint32_t *)rx_tlv = 0; 805 return QDF_STATUS_SUCCESS; 806 } 807 #endif 808