1 /* 2 * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_API_MON_H_ 20 #define _HAL_API_MON_H_ 21 22 #include "qdf_types.h" 23 #include "hal_internal.h" 24 #include <target_type.h> 25 26 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 27 #define HAL_RX_LSB(block, field) block##_##field##_LSB 28 #define HAL_RX_MASk(block, field) block##_##field##_MASK 29 30 #define HAL_RX_GET(_ptr, block, field) \ 31 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 32 HAL_RX_MASk(block, field)) >> \ 33 HAL_RX_LSB(block, field)) 34 35 #define HAL_RX_PHY_DATA_RADAR 0x01 36 #define HAL_SU_MU_CODING_LDPC 0x01 37 38 #define HAL_RX_FCS_LEN (4) 39 #define KEY_EXTIV 0x20 40 41 #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000 42 #define HAL_RX_USER_TLV32_TYPE_LSB 1 43 #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE 44 45 #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000 46 #define HAL_RX_USER_TLV32_LEN_LSB 10 47 #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00 48 49 #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000 50 #define HAL_RX_USER_TLV32_USERID_LSB 26 51 #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000 52 53 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 54 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 55 56 #define HAL_RX_TLV32_HDR_SIZE 4 57 58 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 59 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 60 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 61 HAL_RX_USER_TLV32_TYPE_LSB) 62 63 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 64 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 65 HAL_RX_USER_TLV32_LEN_MASK) >> \ 66 HAL_RX_USER_TLV32_LEN_LSB) 67 68 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 69 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 70 HAL_RX_USER_TLV32_USERID_MASK) >> \ 71 HAL_RX_USER_TLV32_USERID_LSB) 72 73 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 74 #define HAL_TLV_STATUS_PPDU_DONE 1 75 #define HAL_TLV_STATUS_BUF_DONE 2 76 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 77 78 79 #define HAL_MAX_UL_MU_USERS 8 80 81 #define HAL_RX_PKT_TYPE_11A 0 82 #define HAL_RX_PKT_TYPE_11B 1 83 #define HAL_RX_PKT_TYPE_11N 2 84 #define HAL_RX_PKT_TYPE_11AC 3 85 #define HAL_RX_PKT_TYPE_11AX 4 86 87 #define HAL_RX_RECEPTION_TYPE_SU 0 88 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 89 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 90 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 91 92 /* Multiply rate by 2 to avoid float point 93 * and get rate in units of 500kbps 94 */ 95 #define HAL_11B_RATE_0MCS 11*2 96 #define HAL_11B_RATE_1MCS 5.5*2 97 #define HAL_11B_RATE_2MCS 2*2 98 #define HAL_11B_RATE_3MCS 1*2 99 #define HAL_11B_RATE_4MCS 11*2 100 #define HAL_11B_RATE_5MCS 5.5*2 101 #define HAL_11B_RATE_6MCS 2*2 102 103 #define HAL_11A_RATE_0MCS 48*2 104 #define HAL_11A_RATE_1MCS 24*2 105 #define HAL_11A_RATE_2MCS 12*2 106 #define HAL_11A_RATE_3MCS 6*2 107 #define HAL_11A_RATE_4MCS 54*2 108 #define HAL_11A_RATE_5MCS 36*2 109 #define HAL_11A_RATE_6MCS 18*2 110 #define HAL_11A_RATE_7MCS 9*2 111 112 #define HAL_LEGACY_MCS0 0 113 #define HAL_LEGACY_MCS1 1 114 #define HAL_LEGACY_MCS2 2 115 #define HAL_LEGACY_MCS3 3 116 #define HAL_LEGACY_MCS4 4 117 #define HAL_LEGACY_MCS5 5 118 #define HAL_LEGACY_MCS6 6 119 #define HAL_LEGACY_MCS7 7 120 121 #define HE_GI_0_8 0 122 #define HE_GI_1_6 1 123 #define HE_GI_3_2 2 124 #define HE_GI_0_4 3 125 126 #define HT_SGI_PRESENT 0x80 127 128 #define HE_LTF_1_X 1 129 #define HE_LTF_2_X 2 130 #define HE_LTF_4_X 3 131 #define HE_LTF_UNKNOWN 0 132 #define VHT_SIG_SU_NSS_MASK 0x7 133 #define HT_SIG_SU_NSS_SHIFT 0x3 134 135 #define HAL_TID_INVALID 31 136 #define HAL_AST_IDX_INVALID 0xFFFF 137 138 #ifdef GET_MSDU_AGGREGATION 139 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 140 {\ 141 struct rx_msdu_end *rx_msdu_end;\ 142 bool first_msdu, last_msdu; \ 143 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 144 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 145 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 146 if (first_msdu && last_msdu)\ 147 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 148 else\ 149 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 150 } \ 151 152 #else 153 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 154 #endif 155 156 #define HAL_MAC_ADDR_LEN 6 157 158 enum { 159 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 160 HAL_HW_RX_DECAP_FORMAT_NWIFI, 161 HAL_HW_RX_DECAP_FORMAT_ETH2, 162 HAL_HW_RX_DECAP_FORMAT_8023, 163 }; 164 165 enum { 166 DP_PPDU_STATUS_START, 167 DP_PPDU_STATUS_DONE, 168 }; 169 170 static inline 171 uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void) 172 { 173 /* return the HW_RX_DESC size */ 174 return sizeof(struct rx_pkt_tlvs); 175 } 176 177 static inline 178 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 179 { 180 return data; 181 } 182 183 static inline 184 uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr) 185 { 186 struct rx_attention *rx_attn; 187 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 188 189 rx_attn = &rx_desc->attn_tlv.rx_attn; 190 191 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 192 } 193 194 static inline 195 uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr) 196 { 197 struct rx_attention *rx_attn; 198 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 199 200 rx_attn = &rx_desc->attn_tlv.rx_attn; 201 202 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 203 } 204 205 static inline 206 uint32_t 207 HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) { 208 struct rx_msdu_start *rx_msdu_start; 209 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 210 211 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 212 213 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 214 } 215 216 static inline 217 uint8_t * 218 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 219 uint8_t *rx_pkt_hdr; 220 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 221 222 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 223 224 return rx_pkt_hdr; 225 } 226 227 /* 228 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 229 * start TLV of Hardware TLV descriptor 230 * @hw_desc_addr: Hardware desciptor address 231 * 232 * Return: bool: if TLV tag match 233 */ 234 static inline 235 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 236 { 237 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 238 uint32_t tlv_tag; 239 240 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 241 &rx_desc->mpdu_start_tlv); 242 243 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 244 } 245 246 static inline 247 uint32_t HAL_RX_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr) 248 { 249 struct rx_mpdu_info *rx_mpdu_info; 250 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 251 252 rx_mpdu_info = 253 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 254 255 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 256 } 257 258 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 259 static inline 260 uint32_t hal_rx_desc_is_first_msdu(void *hw_desc_addr) 261 { 262 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 263 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 264 265 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 266 } 267 268 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 269 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 270 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 271 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 272 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 273 274 #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \ 275 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 276 (((struct reo_entrance_ring *)reo_ent_desc) \ 277 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 278 279 #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \ 280 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 281 (((struct reo_entrance_ring *)reo_ent_desc) \ 282 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 283 284 #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \ 285 (HAL_RX_BUF_COOKIE_GET(& \ 286 (((struct reo_entrance_ring *)reo_ent_desc) \ 287 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 288 289 /** 290 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 291 * cookie from the REO entrance ring element 292 * 293 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 294 * the current descriptor 295 * @ buf_info: structure to return the buffer information 296 * @ msdu_cnt: pointer to msdu count in MPDU 297 * Return: void 298 */ 299 static inline 300 void hal_rx_reo_ent_buf_paddr_get(void *rx_desc, 301 struct hal_buf_info *buf_info, 302 void **pp_buf_addr_info, 303 uint32_t *msdu_cnt 304 ) 305 { 306 struct reo_entrance_ring *reo_ent_ring = 307 (struct reo_entrance_ring *)rx_desc; 308 struct buffer_addr_info *buf_addr_info; 309 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 310 uint32_t loop_cnt; 311 312 rx_mpdu_desc_info_details = 313 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 314 315 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 316 RX_MPDU_DESC_INFO_0, MSDU_COUNT); 317 318 loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT); 319 320 buf_addr_info = 321 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 322 323 buf_info->paddr = 324 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 325 ((uint64_t) 326 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 327 328 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 329 330 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 331 "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 332 __func__, __LINE__, reo_ent_ring, buf_addr_info, 333 (unsigned long long)buf_info->paddr, loop_cnt); 334 335 *pp_buf_addr_info = (void *)buf_addr_info; 336 } 337 338 static inline 339 void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 340 struct hal_buf_info *buf_info, void **pp_buf_addr_info) 341 { 342 struct rx_msdu_link *msdu_link = 343 (struct rx_msdu_link *)rx_msdu_link_desc; 344 struct buffer_addr_info *buf_addr_info; 345 346 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 347 348 buf_info->paddr = 349 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 350 ((uint64_t) 351 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 352 353 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 354 355 *pp_buf_addr_info = (void *)buf_addr_info; 356 } 357 358 /** 359 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 360 * 361 * @ soc : HAL version of the SOC pointer 362 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 363 * @ buf_addr_info : void pointer to the buffer_addr_info 364 * 365 * Return: void 366 */ 367 368 static inline void hal_rx_mon_msdu_link_desc_set(struct hal_soc *soc, 369 void *src_srng_desc, void *buf_addr_info) 370 { 371 struct buffer_addr_info *wbm_srng_buffer_addr_info = 372 (struct buffer_addr_info *)src_srng_desc; 373 uint64_t paddr; 374 struct buffer_addr_info *p_buffer_addr_info = 375 (struct buffer_addr_info *)buf_addr_info; 376 377 paddr = 378 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 379 ((uint64_t) 380 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 381 382 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 383 "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 384 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 385 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 386 387 /* Structure copy !!! */ 388 *wbm_srng_buffer_addr_info = 389 *((struct buffer_addr_info *)buf_addr_info); 390 } 391 392 static inline 393 uint32 hal_get_rx_msdu_link_desc_size(void) 394 { 395 return sizeof(struct rx_msdu_link); 396 } 397 398 enum { 399 HAL_PKT_TYPE_OFDM = 0, 400 HAL_PKT_TYPE_CCK, 401 HAL_PKT_TYPE_HT, 402 HAL_PKT_TYPE_VHT, 403 HAL_PKT_TYPE_HE, 404 }; 405 406 enum { 407 HAL_SGI_0_8_US, 408 HAL_SGI_0_4_US, 409 HAL_SGI_1_6_US, 410 HAL_SGI_3_2_US, 411 }; 412 413 enum { 414 HAL_FULL_RX_BW_20, 415 HAL_FULL_RX_BW_40, 416 HAL_FULL_RX_BW_80, 417 HAL_FULL_RX_BW_160, 418 }; 419 420 enum { 421 HAL_RX_TYPE_SU, 422 HAL_RX_TYPE_MU_MIMO, 423 HAL_RX_TYPE_MU_OFDMA, 424 HAL_RX_TYPE_MU_OFDMA_MIMO, 425 }; 426 427 /** 428 * enum 429 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 430 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL 431 */ 432 enum { 433 HAL_RX_MON_PPDU_START = 0, 434 HAL_RX_MON_PPDU_END, 435 }; 436 437 struct hal_rx_ppdu_user_info { 438 439 }; 440 441 struct hal_rx_ppdu_common_info { 442 uint32_t ppdu_id; 443 uint32_t ppdu_timestamp; 444 uint32_t mpdu_cnt_fcs_ok; 445 uint32_t mpdu_cnt_fcs_err; 446 }; 447 448 struct hal_rx_msdu_payload_info { 449 uint8_t *first_msdu_payload; 450 uint32_t payload_len; 451 }; 452 453 /** 454 * struct hal_rx_nac_info - struct for neighbour info 455 * @fc_valid: flag indicate if it has valid frame control information 456 * @to_ds_flag: flag indicate to_ds bit 457 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 458 * @mac_addr2: mac address2 in wh 459 */ 460 struct hal_rx_nac_info { 461 uint8_t fc_valid; 462 uint8_t to_ds_flag; 463 uint8_t mac_addr2_valid; 464 uint8_t mac_addr2[HAL_MAC_ADDR_LEN]; 465 }; 466 467 struct hal_rx_ppdu_info { 468 struct hal_rx_ppdu_common_info com_info; 469 struct hal_rx_ppdu_user_info user_info[HAL_MAX_UL_MU_USERS]; 470 struct mon_rx_status rx_status; 471 struct hal_rx_msdu_payload_info msdu_info; 472 struct hal_rx_nac_info nac_info; 473 /* status ring PPDU start and end state */ 474 uint32_t rx_state; 475 }; 476 477 static inline uint32_t 478 hal_get_rx_status_buf_size(void) { 479 /* RX status buffer size is hard coded for now */ 480 return 2048; 481 } 482 483 static inline uint8_t* 484 hal_rx_status_get_next_tlv(uint8_t *rx_tlv) { 485 uint32_t tlv_len, tlv_tag; 486 487 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 488 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 489 490 /* The actual length of PPDU_END is the combined length of many PHY 491 * TLVs that follow. Skip the TLV header and 492 * rx_rxpcu_classification_overview that follows the header to get to 493 * next TLV. 494 */ 495 if (tlv_tag == WIFIRX_PPDU_END_E) 496 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 497 498 return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len + 499 HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3))); 500 } 501 502 /** 503 * hal_rx_proc_phyrx_other_receive_info_tlv() 504 * - process other receive info TLV 505 * @rx_tlv_hdr: pointer to TLV header 506 * @ppdu_info: pointer to ppdu_info 507 * 508 * Return: None 509 */ 510 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 511 void *rx_tlv_hdr, 512 struct hal_rx_ppdu_info 513 *ppdu_info) 514 { 515 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 516 (void *)ppdu_info); 517 } 518 519 /** 520 * hal_rx_status_get_tlv_info() - process receive info TLV 521 * @rx_tlv_hdr: pointer to TLV header 522 * @ppdu_info: pointer to ppdu_info 523 * 524 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 525 */ 526 static inline uint32_t 527 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 528 struct hal_soc *hal_soc) 529 { 530 return hal_soc->ops->hal_rx_status_get_tlv_info(rx_tlv_hdr, 531 ppdu_info, hal_soc); 532 } 533 534 static inline 535 uint32_t hal_get_rx_status_done_tlv_size(void *hal_soc) 536 { 537 return HAL_RX_TLV32_HDR_SIZE; 538 } 539 540 static inline QDF_STATUS 541 hal_get_rx_status_done(uint8_t *rx_tlv) 542 { 543 uint32_t tlv_tag; 544 545 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 546 547 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 548 return QDF_STATUS_SUCCESS; 549 else 550 return QDF_STATUS_E_EMPTY; 551 } 552 553 static inline QDF_STATUS 554 hal_clear_rx_status_done(uint8_t *rx_tlv) 555 { 556 *(uint32_t *)rx_tlv = 0; 557 return QDF_STATUS_SUCCESS; 558 } 559 560 #endif 561