1 /* 2 * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_API_MON_H_ 20 #define _HAL_API_MON_H_ 21 22 #include "qdf_types.h" 23 #include "hal_internal.h" 24 #include <target_type.h> 25 26 #define HAL_RX_PHY_DATA_RADAR 0x01 27 #define HAL_SU_MU_CODING_LDPC 0x01 28 29 #define HAL_RX_FCS_LEN (4) 30 #define KEY_EXTIV 0x20 31 32 #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000 33 #define HAL_RX_USER_TLV32_TYPE_LSB 1 34 #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE 35 36 #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000 37 #define HAL_RX_USER_TLV32_LEN_LSB 10 38 #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00 39 40 #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000 41 #define HAL_RX_USER_TLV32_USERID_LSB 26 42 #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000 43 44 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 45 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 46 47 #define HAL_RX_TLV32_HDR_SIZE 4 48 49 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 50 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 51 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 52 HAL_RX_USER_TLV32_TYPE_LSB) 53 54 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 55 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 56 HAL_RX_USER_TLV32_LEN_MASK) >> \ 57 HAL_RX_USER_TLV32_LEN_LSB) 58 59 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 60 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 61 HAL_RX_USER_TLV32_USERID_MASK) >> \ 62 HAL_RX_USER_TLV32_USERID_LSB) 63 64 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 65 #define HAL_TLV_STATUS_PPDU_DONE 1 66 #define HAL_TLV_STATUS_BUF_DONE 2 67 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 68 #define HAL_TLV_STATUS_PPDU_START 4 69 #define HAL_TLV_STATUS_HEADER 5 70 #define HAL_TLV_STATUS_MPDU_END 6 71 #define HAL_TLV_STATUS_MSDU_START 7 72 #define HAL_TLV_STATUS_MSDU_END 8 73 74 #define HAL_MAX_UL_MU_USERS 37 75 76 #define HAL_RX_PKT_TYPE_11A 0 77 #define HAL_RX_PKT_TYPE_11B 1 78 #define HAL_RX_PKT_TYPE_11N 2 79 #define HAL_RX_PKT_TYPE_11AC 3 80 #define HAL_RX_PKT_TYPE_11AX 4 81 82 #define HAL_RX_RECEPTION_TYPE_SU 0 83 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 84 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 85 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 86 87 /* Multiply rate by 2 to avoid float point 88 * and get rate in units of 500kbps 89 */ 90 #define HAL_11B_RATE_0MCS 11*2 91 #define HAL_11B_RATE_1MCS 5.5*2 92 #define HAL_11B_RATE_2MCS 2*2 93 #define HAL_11B_RATE_3MCS 1*2 94 #define HAL_11B_RATE_4MCS 11*2 95 #define HAL_11B_RATE_5MCS 5.5*2 96 #define HAL_11B_RATE_6MCS 2*2 97 98 #define HAL_11A_RATE_0MCS 48*2 99 #define HAL_11A_RATE_1MCS 24*2 100 #define HAL_11A_RATE_2MCS 12*2 101 #define HAL_11A_RATE_3MCS 6*2 102 #define HAL_11A_RATE_4MCS 54*2 103 #define HAL_11A_RATE_5MCS 36*2 104 #define HAL_11A_RATE_6MCS 18*2 105 #define HAL_11A_RATE_7MCS 9*2 106 107 #define HAL_LEGACY_MCS0 0 108 #define HAL_LEGACY_MCS1 1 109 #define HAL_LEGACY_MCS2 2 110 #define HAL_LEGACY_MCS3 3 111 #define HAL_LEGACY_MCS4 4 112 #define HAL_LEGACY_MCS5 5 113 #define HAL_LEGACY_MCS6 6 114 #define HAL_LEGACY_MCS7 7 115 116 #define HE_GI_0_8 0 117 #define HE_GI_0_4 1 118 #define HE_GI_1_6 2 119 #define HE_GI_3_2 3 120 121 #define HT_SGI_PRESENT 0x80 122 123 #define HE_LTF_1_X 0 124 #define HE_LTF_2_X 1 125 #define HE_LTF_4_X 2 126 #define HE_LTF_UNKNOWN 3 127 #define VHT_SIG_SU_NSS_MASK 0x7 128 #define HT_SIG_SU_NSS_SHIFT 0x3 129 130 #define HAL_TID_INVALID 31 131 #define HAL_AST_IDX_INVALID 0xFFFF 132 133 #ifdef GET_MSDU_AGGREGATION 134 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 135 {\ 136 struct rx_msdu_end *rx_msdu_end;\ 137 bool first_msdu, last_msdu; \ 138 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 139 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 140 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 141 if (first_msdu && last_msdu)\ 142 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 143 else\ 144 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 145 } \ 146 147 #else 148 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 149 #endif 150 151 /* Max MPDUs per status buffer */ 152 #define HAL_RX_MAX_MPDU 256 153 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 154 155 /* Max pilot count */ 156 #define HAL_RX_MAX_SU_EVM_COUNT 32 157 158 /* 159 * Struct hal_rx_su_evm_info - SU evm info 160 * @number_of_symbols: number of symbols 161 * @nss_count: nss count 162 * @pilot_count: pilot count 163 * @pilot_evm: Array of pilot evm values 164 */ 165 struct hal_rx_su_evm_info { 166 uint32_t number_of_symbols; 167 uint8_t nss_count; 168 uint8_t pilot_count; 169 uint32_t pilot_evm[HAL_RX_MAX_SU_EVM_COUNT]; 170 }; 171 172 enum { 173 DP_PPDU_STATUS_START, 174 DP_PPDU_STATUS_DONE, 175 }; 176 177 static inline 178 uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void) 179 { 180 /* return the HW_RX_DESC size */ 181 return sizeof(struct rx_pkt_tlvs); 182 } 183 184 static inline 185 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 186 { 187 return data; 188 } 189 190 static inline 191 uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr) 192 { 193 struct rx_attention *rx_attn; 194 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 195 196 rx_attn = &rx_desc->attn_tlv.rx_attn; 197 198 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 199 } 200 201 static inline 202 uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr) 203 { 204 struct rx_attention *rx_attn; 205 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 206 207 rx_attn = &rx_desc->attn_tlv.rx_attn; 208 209 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 210 } 211 212 /* 213 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 214 * start TLV of Hardware TLV descriptor 215 * @hw_desc_addr: Hardware desciptor address 216 * 217 * Return: bool: if TLV tag match 218 */ 219 static inline 220 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 221 { 222 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 223 uint32_t tlv_tag; 224 225 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 226 &rx_desc->mpdu_start_tlv); 227 228 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 229 } 230 231 232 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 233 234 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 235 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 236 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 237 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 238 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 239 240 #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \ 241 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 242 (((struct reo_entrance_ring *)reo_ent_desc) \ 243 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 244 245 #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \ 246 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 247 (((struct reo_entrance_ring *)reo_ent_desc) \ 248 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 249 250 #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \ 251 (HAL_RX_BUF_COOKIE_GET(& \ 252 (((struct reo_entrance_ring *)reo_ent_desc) \ 253 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info))) 254 255 /** 256 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and 257 * cookie from the REO entrance ring element 258 * 259 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 260 * the current descriptor 261 * @ buf_info: structure to return the buffer information 262 * @ msdu_cnt: pointer to msdu count in MPDU 263 * Return: void 264 */ 265 static inline 266 void hal_rx_reo_ent_buf_paddr_get(hal_rxdma_desc_t rx_desc, 267 struct hal_buf_info *buf_info, 268 void **pp_buf_addr_info, 269 uint32_t *msdu_cnt 270 ) 271 { 272 struct reo_entrance_ring *reo_ent_ring = 273 (struct reo_entrance_ring *)rx_desc; 274 struct buffer_addr_info *buf_addr_info; 275 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 276 uint32_t loop_cnt; 277 278 rx_mpdu_desc_info_details = 279 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 280 281 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 282 RX_MPDU_DESC_INFO_0, MSDU_COUNT); 283 284 loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT); 285 286 buf_addr_info = 287 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 288 289 buf_info->paddr = 290 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 291 ((uint64_t) 292 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 293 294 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 295 296 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 297 "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 298 __func__, __LINE__, reo_ent_ring, buf_addr_info, 299 (unsigned long long)buf_info->paddr, loop_cnt); 300 301 *pp_buf_addr_info = (void *)buf_addr_info; 302 } 303 304 static inline 305 void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 306 struct hal_buf_info *buf_info, void **pp_buf_addr_info) 307 { 308 struct rx_msdu_link *msdu_link = 309 (struct rx_msdu_link *)rx_msdu_link_desc; 310 struct buffer_addr_info *buf_addr_info; 311 312 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 313 314 buf_info->paddr = 315 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 316 ((uint64_t) 317 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 318 319 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 320 321 *pp_buf_addr_info = (void *)buf_addr_info; 322 } 323 324 /** 325 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 326 * 327 * @ soc : HAL version of the SOC pointer 328 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 329 * @ buf_addr_info : void pointer to the buffer_addr_info 330 * 331 * Return: void 332 */ 333 334 static inline 335 void hal_rx_mon_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 336 void *src_srng_desc, 337 void *buf_addr_info) 338 { 339 struct buffer_addr_info *wbm_srng_buffer_addr_info = 340 (struct buffer_addr_info *)src_srng_desc; 341 uint64_t paddr; 342 struct buffer_addr_info *p_buffer_addr_info = 343 (struct buffer_addr_info *)buf_addr_info; 344 345 paddr = 346 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 347 ((uint64_t) 348 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 349 350 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 351 "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 352 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 353 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 354 355 /* Structure copy !!! */ 356 *wbm_srng_buffer_addr_info = 357 *((struct buffer_addr_info *)buf_addr_info); 358 } 359 360 static inline 361 uint32 hal_get_rx_msdu_link_desc_size(void) 362 { 363 return sizeof(struct rx_msdu_link); 364 } 365 366 enum { 367 HAL_PKT_TYPE_OFDM = 0, 368 HAL_PKT_TYPE_CCK, 369 HAL_PKT_TYPE_HT, 370 HAL_PKT_TYPE_VHT, 371 HAL_PKT_TYPE_HE, 372 }; 373 374 enum { 375 HAL_SGI_0_8_US, 376 HAL_SGI_0_4_US, 377 HAL_SGI_1_6_US, 378 HAL_SGI_3_2_US, 379 }; 380 381 enum { 382 HAL_FULL_RX_BW_20, 383 HAL_FULL_RX_BW_40, 384 HAL_FULL_RX_BW_80, 385 HAL_FULL_RX_BW_160, 386 }; 387 388 enum { 389 HAL_RX_TYPE_SU, 390 HAL_RX_TYPE_MU_MIMO, 391 HAL_RX_TYPE_MU_OFDMA, 392 HAL_RX_TYPE_MU_OFDMA_MIMO, 393 }; 394 395 /** 396 * enum 397 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 398 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL 399 */ 400 enum { 401 HAL_RX_MON_PPDU_START = 0, 402 HAL_RX_MON_PPDU_END, 403 }; 404 405 /* struct hal_rx_ppdu_common_info - common ppdu info 406 * @ppdu_id - ppdu id number 407 * @ppdu_timestamp - timestamp at ppdu received 408 * @mpdu_cnt_fcs_ok - mpdu count in ppdu with fcs ok 409 * @mpdu_cnt_fcs_err - mpdu count in ppdu with fcs err 410 * @mpdu_fcs_ok_bitmap - fcs ok mpdu count in ppdu bitmap 411 * @last_ppdu_id - last received ppdu id 412 * @mpdu_cnt - total mpdu count 413 * @num_users - num users 414 */ 415 struct hal_rx_ppdu_common_info { 416 uint32_t ppdu_id; 417 uint32_t ppdu_timestamp; 418 uint32_t mpdu_cnt_fcs_ok; 419 uint32_t mpdu_cnt_fcs_err; 420 uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 421 uint32_t last_ppdu_id; 422 uint32_t mpdu_cnt; 423 uint8_t num_users; 424 }; 425 426 /** 427 * struct hal_rx_msdu_payload_info - msdu payload info 428 * @first_msdu_payload: pointer to first msdu payload 429 * @payload_len: payload len 430 * @nbuf: status network buffer to which msdu belongs to 431 */ 432 struct hal_rx_msdu_payload_info { 433 uint8_t *first_msdu_payload; 434 uint32_t payload_len; 435 qdf_nbuf_t nbuf; 436 }; 437 438 /** 439 * struct hal_rx_nac_info - struct for neighbour info 440 * @fc_valid: flag indicate if it has valid frame control information 441 * @frame_control: frame control from each MPDU 442 * @to_ds_flag: flag indicate to_ds bit 443 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 444 * @mac_addr2: mac address2 in wh 445 * @mcast_bcast: multicast/broadcast 446 */ 447 struct hal_rx_nac_info { 448 uint8_t fc_valid; 449 uint16_t frame_control; 450 uint8_t to_ds_flag; 451 uint8_t mac_addr2_valid; 452 uint8_t mac_addr2[QDF_MAC_ADDR_SIZE]; 453 uint8_t mcast_bcast; 454 }; 455 456 /** 457 * struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs 458 * @cce_metadata: cached CCE metadata value received in the MSDU_END TLV 459 * @is_flow_idx_timeout: flag to indicate if flow search timeout occurred 460 * @is_flow_idx_invalid: flag to indicate if flow idx is valid or not 461 * @fse_metadata: cached FSE metadata value received in the MSDU END TLV 462 * @flow_idx: flow idx matched in FSE received in the MSDU END TLV 463 */ 464 struct hal_rx_ppdu_msdu_info { 465 uint16_t cce_metadata; 466 bool is_flow_idx_timeout; 467 bool is_flow_idx_invalid; 468 uint32_t fse_metadata; 469 uint32_t flow_idx; 470 }; 471 472 struct hal_rx_ppdu_info { 473 struct hal_rx_ppdu_common_info com_info; 474 struct mon_rx_status rx_status; 475 struct mon_rx_user_status rx_user_status[HAL_MAX_UL_MU_USERS]; 476 struct hal_rx_msdu_payload_info msdu_info; 477 struct hal_rx_msdu_payload_info fcs_ok_msdu_info; 478 struct hal_rx_nac_info nac_info; 479 /* status ring PPDU start and end state */ 480 uint32_t rx_state; 481 /* MU user id for status ring TLV */ 482 uint32_t user_id; 483 /* MPDU/MSDU truncated to 128 bytes header start addr in status skb */ 484 unsigned char *data; 485 /* MPDU/MSDU truncated to 128 bytes header real length */ 486 uint32_t hdr_len; 487 /* MPDU FCS error */ 488 bool fcs_err; 489 struct hal_rx_ppdu_msdu_info rx_msdu_info[HAL_MAX_UL_MU_USERS]; 490 /* first msdu payload for all mpdus in ppdu */ 491 struct hal_rx_msdu_payload_info ppdu_msdu_info[HAL_RX_MAX_MPDU]; 492 /* evm info */ 493 struct hal_rx_su_evm_info evm_info; 494 }; 495 496 static inline uint32_t 497 hal_get_rx_status_buf_size(void) { 498 /* RX status buffer size is hard coded for now */ 499 return 2048; 500 } 501 502 static inline uint8_t* 503 hal_rx_status_get_next_tlv(uint8_t *rx_tlv) { 504 uint32_t tlv_len, tlv_tag; 505 506 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 507 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 508 509 /* The actual length of PPDU_END is the combined length of many PHY 510 * TLVs that follow. Skip the TLV header and 511 * rx_rxpcu_classification_overview that follows the header to get to 512 * next TLV. 513 */ 514 if (tlv_tag == WIFIRX_PPDU_END_E) 515 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 516 517 return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len + 518 HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3))); 519 } 520 521 /** 522 * hal_rx_proc_phyrx_other_receive_info_tlv() 523 * - process other receive info TLV 524 * @rx_tlv_hdr: pointer to TLV header 525 * @ppdu_info: pointer to ppdu_info 526 * 527 * Return: None 528 */ 529 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 530 void *rx_tlv_hdr, 531 struct hal_rx_ppdu_info 532 *ppdu_info) 533 { 534 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 535 (void *)ppdu_info); 536 } 537 538 /** 539 * hal_rx_status_get_tlv_info() - process receive info TLV 540 * @rx_tlv_hdr: pointer to TLV header 541 * @ppdu_info: pointer to ppdu_info 542 * @hal_soc: HAL soc handle 543 * @nbuf: PPDU status netowrk buffer 544 * 545 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 546 */ 547 static inline uint32_t 548 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 549 hal_soc_handle_t hal_soc_hdl, 550 qdf_nbuf_t nbuf) 551 { 552 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 553 554 return hal_soc->ops->hal_rx_status_get_tlv_info( 555 rx_tlv_hdr, 556 ppdu_info, 557 hal_soc_hdl, 558 nbuf); 559 } 560 561 static inline 562 uint32_t hal_get_rx_status_done_tlv_size(hal_soc_handle_t hal_soc_hdl) 563 { 564 return HAL_RX_TLV32_HDR_SIZE; 565 } 566 567 static inline QDF_STATUS 568 hal_get_rx_status_done(uint8_t *rx_tlv) 569 { 570 uint32_t tlv_tag; 571 572 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 573 574 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 575 return QDF_STATUS_SUCCESS; 576 else 577 return QDF_STATUS_E_EMPTY; 578 } 579 580 static inline QDF_STATUS 581 hal_clear_rx_status_done(uint8_t *rx_tlv) 582 { 583 *(uint32_t *)rx_tlv = 0; 584 return QDF_STATUS_SUCCESS; 585 } 586 587 #endif 588