1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_API_H_ 20 #define _HAL_API_H_ 21 22 #include "qdf_types.h" 23 #include "qdf_util.h" 24 #include "hal_internal.h" 25 26 #define MAX_UNWINDOWED_ADDRESS 0x80000 27 #ifdef QCA_WIFI_QCA6390 28 #define WINDOW_ENABLE_BIT 0x40000000 29 #else 30 #define WINDOW_ENABLE_BIT 0x80000000 31 #endif 32 #define WINDOW_REG_ADDRESS 0x310C 33 #define WINDOW_SHIFT 19 34 #define WINDOW_VALUE_MASK 0x3F 35 #define WINDOW_START MAX_UNWINDOWED_ADDRESS 36 #define WINDOW_RANGE_MASK 0x7FFFF 37 38 static inline void hal_select_window(struct hal_soc *hal_soc, uint32_t offset) 39 { 40 uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK; 41 if (window != hal_soc->register_window) { 42 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 43 WINDOW_ENABLE_BIT | window); 44 hal_soc->register_window = window; 45 } 46 } 47 48 /** 49 * note1: WINDOW_RANGE_MASK = (1 << WINDOW_SHIFT) -1 50 * note2: 1 << WINDOW_SHIFT = MAX_UNWINDOWED_ADDRESS 51 * note3: WINDOW_VALUE_MASK = big enough that trying to write past that window 52 * would be a bug 53 */ 54 static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset, 55 uint32_t value) 56 { 57 58 if (!hal_soc->use_register_windowing || 59 offset < MAX_UNWINDOWED_ADDRESS) { 60 qdf_iowrite32(hal_soc->dev_base_addr + offset, value); 61 } else { 62 qdf_spin_lock_irqsave(&hal_soc->register_access_lock); 63 hal_select_window(hal_soc, offset); 64 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START + 65 (offset & WINDOW_RANGE_MASK), value); 66 qdf_spin_unlock_irqrestore(&hal_soc->register_access_lock); 67 } 68 } 69 70 /** 71 * hal_write_address_32_mb - write a value to a register 72 * 73 */ 74 static inline void hal_write_address_32_mb(struct hal_soc *hal_soc, 75 void __iomem *addr, uint32_t value) 76 { 77 uint32_t offset; 78 79 if (!hal_soc->use_register_windowing) 80 return qdf_iowrite32(addr, value); 81 82 offset = addr - hal_soc->dev_base_addr; 83 hal_write32_mb(hal_soc, offset, value); 84 } 85 86 static inline uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset) 87 { 88 uint32_t ret; 89 90 if (!hal_soc->use_register_windowing || 91 offset < MAX_UNWINDOWED_ADDRESS) { 92 return qdf_ioread32(hal_soc->dev_base_addr + offset); 93 } 94 95 qdf_spin_lock_irqsave(&hal_soc->register_access_lock); 96 hal_select_window(hal_soc, offset); 97 ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START + 98 (offset & WINDOW_RANGE_MASK)); 99 qdf_spin_unlock_irqrestore(&hal_soc->register_access_lock); 100 101 return ret; 102 } 103 104 #include "hif_io32.h" 105 106 /** 107 * hal_attach - Initialize HAL layer 108 * @hif_handle: Opaque HIF handle 109 * @qdf_dev: QDF device 110 * 111 * Return: Opaque HAL SOC handle 112 * NULL on failure (if given ring is not available) 113 * 114 * This function should be called as part of HIF initialization (for accessing 115 * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle() 116 */ 117 extern void *hal_attach(void *hif_handle, qdf_device_t qdf_dev); 118 119 /** 120 * hal_detach - Detach HAL layer 121 * @hal_soc: HAL SOC handle 122 * 123 * This function should be called as part of HIF detach 124 * 125 */ 126 extern void hal_detach(void *hal_soc); 127 128 /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */ 129 enum hal_ring_type { 130 REO_DST, 131 REO_EXCEPTION, 132 REO_REINJECT, 133 REO_CMD, 134 REO_STATUS, 135 TCL_DATA, 136 TCL_CMD, 137 TCL_STATUS, 138 CE_SRC, 139 CE_DST, 140 CE_DST_STATUS, 141 WBM_IDLE_LINK, 142 SW2WBM_RELEASE, 143 WBM2SW_RELEASE, 144 RXDMA_BUF, 145 RXDMA_DST, 146 RXDMA_MONITOR_BUF, 147 RXDMA_MONITOR_STATUS, 148 RXDMA_MONITOR_DST, 149 RXDMA_MONITOR_DESC, 150 DIR_BUF_RX_DMA_SRC, 151 #ifdef WLAN_FEATURE_CIF_CFR 152 WIFI_POS_SRC, 153 #endif 154 MAX_RING_TYPES 155 }; 156 157 #define HAL_SRNG_LMAC_RING 0x80000000 158 /* SRNG flags passed in hal_srng_params.flags */ 159 #define HAL_SRNG_MSI_SWAP 0x00000008 160 #define HAL_SRNG_RING_PTR_SWAP 0x00000010 161 #define HAL_SRNG_DATA_TLV_SWAP 0x00000020 162 #define HAL_SRNG_LOW_THRES_INTR_ENABLE 0x00010000 163 #define HAL_SRNG_MSI_INTR 0x00020000 164 165 #define PN_SIZE_24 0 166 #define PN_SIZE_48 1 167 #define PN_SIZE_128 2 168 169 /** 170 * hal_srng_get_entrysize - Returns size of ring entry in bytes. Should be 171 * used by callers for calculating the size of memory to be allocated before 172 * calling hal_srng_setup to setup the ring 173 * 174 * @hal_soc: Opaque HAL SOC handle 175 * @ring_type: one of the types from hal_ring_type 176 * 177 */ 178 extern uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type); 179 180 /** 181 * hal_srng_max_entries - Returns maximum possible number of ring entries 182 * @hal_soc: Opaque HAL SOC handle 183 * @ring_type: one of the types from hal_ring_type 184 * 185 * Return: Maximum number of entries for the given ring_type 186 */ 187 uint32_t hal_srng_max_entries(void *hal_soc, int ring_type); 188 189 /** 190 * hal_srng_dump - Dump ring status 191 * @srng: hal srng pointer 192 */ 193 void hal_srng_dump(struct hal_srng *srng); 194 195 /** 196 * hal_srng_get_dir - Returns the direction of the ring 197 * @hal_soc: Opaque HAL SOC handle 198 * @ring_type: one of the types from hal_ring_type 199 * 200 * Return: Ring direction 201 */ 202 enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type); 203 204 /* HAL memory information */ 205 struct hal_mem_info { 206 /* dev base virutal addr */ 207 void *dev_base_addr; 208 /* dev base physical addr */ 209 void *dev_base_paddr; 210 /* Remote virtual pointer memory for HW/FW updates */ 211 void *shadow_rdptr_mem_vaddr; 212 /* Remote physical pointer memory for HW/FW updates */ 213 void *shadow_rdptr_mem_paddr; 214 /* Shared memory for ring pointer updates from host to FW */ 215 void *shadow_wrptr_mem_vaddr; 216 /* Shared physical memory for ring pointer updates from host to FW */ 217 void *shadow_wrptr_mem_paddr; 218 }; 219 220 /* SRNG parameters to be passed to hal_srng_setup */ 221 struct hal_srng_params { 222 /* Physical base address of the ring */ 223 qdf_dma_addr_t ring_base_paddr; 224 /* Virtual base address of the ring */ 225 void *ring_base_vaddr; 226 /* Number of entries in ring */ 227 uint32_t num_entries; 228 /* max transfer length */ 229 uint16_t max_buffer_length; 230 /* MSI Address */ 231 qdf_dma_addr_t msi_addr; 232 /* MSI data */ 233 uint32_t msi_data; 234 /* Interrupt timer threshold – in micro seconds */ 235 uint32_t intr_timer_thres_us; 236 /* Interrupt batch counter threshold – in number of ring entries */ 237 uint32_t intr_batch_cntr_thres_entries; 238 /* Low threshold – in number of ring entries 239 * (valid for src rings only) 240 */ 241 uint32_t low_threshold; 242 /* Misc flags */ 243 uint32_t flags; 244 /* Unique ring id */ 245 uint8_t ring_id; 246 /* Source or Destination ring */ 247 enum hal_srng_dir ring_dir; 248 /* Size of ring entry */ 249 uint32_t entry_size; 250 /* hw register base address */ 251 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 252 }; 253 254 /* hal_construct_shadow_config() - initialize the shadow registers for dp rings 255 * @hal_soc: hal handle 256 * 257 * Return: QDF_STATUS_OK on success 258 */ 259 extern QDF_STATUS hal_construct_shadow_config(void *hal_soc); 260 261 /* hal_set_one_shadow_config() - add a config for the specified ring 262 * @hal_soc: hal handle 263 * @ring_type: ring type 264 * @ring_num: ring num 265 * 266 * The ring type and ring num uniquely specify the ring. After this call, 267 * the hp/tp will be added as the next entry int the shadow register 268 * configuration table. The hal code will use the shadow register address 269 * in place of the hp/tp address. 270 * 271 * This function is exposed, so that the CE module can skip configuring shadow 272 * registers for unused ring and rings assigned to the firmware. 273 * 274 * Return: QDF_STATUS_OK on success 275 */ 276 extern QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type, 277 int ring_num); 278 /** 279 * hal_get_shadow_config() - retrieve the config table 280 * @hal_soc: hal handle 281 * @shadow_config: will point to the table after 282 * @num_shadow_registers_configured: will contain the number of valid entries 283 */ 284 extern void hal_get_shadow_config(void *hal_soc, 285 struct pld_shadow_reg_v2_cfg **shadow_config, 286 int *num_shadow_registers_configured); 287 /** 288 * hal_srng_setup - Initialize HW SRNG ring. 289 * 290 * @hal_soc: Opaque HAL SOC handle 291 * @ring_type: one of the types from hal_ring_type 292 * @ring_num: Ring number if there are multiple rings of 293 * same type (staring from 0) 294 * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings 295 * @ring_params: SRNG ring params in hal_srng_params structure. 296 297 * Callers are expected to allocate contiguous ring memory of size 298 * 'num_entries * entry_size' bytes and pass the physical and virtual base 299 * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in hal_srng_params 300 * structure. Ring base address should be 8 byte aligned and size of each ring 301 * entry should be queried using the API hal_srng_get_entrysize 302 * 303 * Return: Opaque pointer to ring on success 304 * NULL on failure (if given ring is not available) 305 */ 306 extern void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num, 307 int mac_id, struct hal_srng_params *ring_params); 308 309 /* Remapping ids of REO rings */ 310 #define REO_REMAP_TCL 0 311 #define REO_REMAP_SW1 1 312 #define REO_REMAP_SW2 2 313 #define REO_REMAP_SW3 3 314 #define REO_REMAP_SW4 4 315 #define REO_REMAP_RELEASE 5 316 #define REO_REMAP_FW 6 317 #define REO_REMAP_UNUSED 7 318 319 /* 320 * currently this macro only works for IX0 since all the rings we are remapping 321 * can be remapped from HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0 322 */ 323 #define HAL_REO_REMAP_VAL(_ORIGINAL_DEST, _NEW_DEST) \ 324 HAL_REO_REMAP_VAL_(_ORIGINAL_DEST, _NEW_DEST) 325 /* allow the destination macros to be expanded */ 326 #define HAL_REO_REMAP_VAL_(_ORIGINAL_DEST, _NEW_DEST) \ 327 (_NEW_DEST << \ 328 (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_ ## \ 329 _ORIGINAL_DEST ## _SHFT)) 330 331 /** 332 * hal_reo_remap_IX0 - Remap REO ring destination 333 * @hal: HAL SOC handle 334 * @remap_val: Remap value 335 */ 336 extern void hal_reo_remap_IX0(struct hal_soc *hal, uint32_t remap_val); 337 338 /** 339 * hal_srng_set_hp_paddr() - Set physical address to dest SRNG head pointer 340 * @sring: sring pointer 341 * @paddr: physical address 342 */ 343 extern void hal_srng_dst_set_hp_paddr(struct hal_srng *sring, uint64_t paddr); 344 345 /** 346 * hal_srng_dst_init_hp() - Initilaize head pointer with cached head pointer 347 * @srng: sring pointer 348 * @vaddr: virtual address 349 */ 350 extern void hal_srng_dst_init_hp(struct hal_srng *srng, uint32_t *vaddr); 351 352 /** 353 * hal_srng_cleanup - Deinitialize HW SRNG ring. 354 * @hal_soc: Opaque HAL SOC handle 355 * @hal_srng: Opaque HAL SRNG pointer 356 */ 357 extern void hal_srng_cleanup(void *hal_soc, void *hal_srng); 358 359 static inline bool hal_srng_initialized(void *hal_ring) 360 { 361 struct hal_srng *srng = (struct hal_srng *)hal_ring; 362 363 return !!srng->initialized; 364 } 365 366 /** 367 * hal_srng_access_start_unlocked - Start ring access (unlocked). Should use 368 * hal_srng_access_start if locked access is required 369 * 370 * @hal_soc: Opaque HAL SOC handle 371 * @hal_ring: Ring pointer (Source or Destination ring) 372 * 373 * Return: 0 on success; error on failire 374 */ 375 static inline int hal_srng_access_start_unlocked(void *hal_soc, void *hal_ring) 376 { 377 struct hal_srng *srng = (struct hal_srng *)hal_ring; 378 379 if (srng->ring_dir == HAL_SRNG_SRC_RING) 380 srng->u.src_ring.cached_tp = 381 *(volatile uint32_t *)(srng->u.src_ring.tp_addr); 382 else 383 srng->u.dst_ring.cached_hp = 384 *(volatile uint32_t *)(srng->u.dst_ring.hp_addr); 385 386 return 0; 387 } 388 389 /** 390 * hal_srng_access_start - Start (locked) ring access 391 * 392 * @hal_soc: Opaque HAL SOC handle 393 * @hal_ring: Ring pointer (Source or Destination ring) 394 * 395 * Return: 0 on success; error on failire 396 */ 397 static inline int hal_srng_access_start(void *hal_soc, void *hal_ring) 398 { 399 struct hal_srng *srng = (struct hal_srng *)hal_ring; 400 401 SRNG_LOCK(&(srng->lock)); 402 403 return hal_srng_access_start_unlocked(hal_soc, hal_ring); 404 } 405 406 /** 407 * hal_srng_dst_get_next - Get next entry from a destination ring and move 408 * cached tail pointer 409 * 410 * @hal_soc: Opaque HAL SOC handle 411 * @hal_ring: Destination ring pointer 412 * 413 * Return: Opaque pointer for next ring entry; NULL on failire 414 */ 415 static inline void *hal_srng_dst_get_next(void *hal_soc, void *hal_ring) 416 { 417 struct hal_srng *srng = (struct hal_srng *)hal_ring; 418 uint32_t *desc; 419 420 if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp) { 421 desc = &(srng->ring_base_vaddr[srng->u.dst_ring.tp]); 422 /* TODO: Using % is expensive, but we have to do this since 423 * size of some SRNG rings is not power of 2 (due to descriptor 424 * sizes). Need to create separate API for rings used 425 * per-packet, with sizes power of 2 (TCL2SW, REO2SW, 426 * SW2RXDMA and CE rings) 427 */ 428 srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size) % 429 srng->ring_size; 430 431 return (void *)desc; 432 } 433 434 return NULL; 435 } 436 437 /** 438 * hal_srng_dst_get_next_hp - Get next entry from a destination ring and move 439 * cached head pointer 440 * 441 * @hal_soc: Opaque HAL SOC handle 442 * @hal_ring: Destination ring pointer 443 * 444 * Return: Opaque pointer for next ring entry; NULL on failire 445 */ 446 static inline void *hal_srng_dst_get_next_hp(void *hal_soc, void *hal_ring) 447 { 448 struct hal_srng *srng = (struct hal_srng *)hal_ring; 449 uint32_t *desc; 450 /* TODO: Using % is expensive, but we have to do this since 451 * size of some SRNG rings is not power of 2 (due to descriptor 452 * sizes). Need to create separate API for rings used 453 * per-packet, with sizes power of 2 (TCL2SW, REO2SW, 454 * SW2RXDMA and CE rings) 455 */ 456 uint32_t next_hp = (srng->u.dst_ring.cached_hp + srng->entry_size) % 457 srng->ring_size; 458 459 if (next_hp != srng->u.dst_ring.tp) { 460 desc = &(srng->ring_base_vaddr[srng->u.dst_ring.cached_hp]); 461 srng->u.dst_ring.cached_hp = next_hp; 462 return (void *)desc; 463 } 464 465 return NULL; 466 } 467 468 /** 469 * hal_srng_dst_peek - Get next entry from a ring without moving tail pointer. 470 * hal_srng_dst_get_next should be called subsequently to move the tail pointer 471 * TODO: See if we need an optimized version of get_next that doesn't check for 472 * loop_cnt 473 * 474 * @hal_soc: Opaque HAL SOC handle 475 * @hal_ring: Destination ring pointer 476 * 477 * Return: Opaque pointer for next ring entry; NULL on failire 478 */ 479 static inline void *hal_srng_dst_peek(void *hal_soc, void *hal_ring) 480 { 481 struct hal_srng *srng = (struct hal_srng *)hal_ring; 482 483 if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp) 484 return (void *)(&(srng->ring_base_vaddr[srng->u.dst_ring.tp])); 485 486 return NULL; 487 } 488 489 /** 490 * hal_srng_dst_num_valid - Returns number of valid entries (to be processed 491 * by SW) in destination ring 492 * 493 * @hal_soc: Opaque HAL SOC handle 494 * @hal_ring: Destination ring pointer 495 * @sync_hw_ptr: Sync cached head pointer with HW 496 * 497 */ 498 static inline uint32_t hal_srng_dst_num_valid(void *hal_soc, void *hal_ring, 499 int sync_hw_ptr) 500 { 501 struct hal_srng *srng = (struct hal_srng *)hal_ring; 502 uint32_t hp; 503 uint32_t tp = srng->u.dst_ring.tp; 504 505 if (sync_hw_ptr) { 506 hp = *(srng->u.dst_ring.hp_addr); 507 srng->u.dst_ring.cached_hp = hp; 508 } else { 509 hp = srng->u.dst_ring.cached_hp; 510 } 511 512 if (hp >= tp) 513 return (hp - tp) / srng->entry_size; 514 else 515 return (srng->ring_size - tp + hp) / srng->entry_size; 516 } 517 518 /** 519 * hal_srng_src_reap_next - Reap next entry from a source ring and move reap 520 * pointer. This can be used to release any buffers associated with completed 521 * ring entries. Note that this should not be used for posting new descriptor 522 * entries. Posting of new entries should be done only using 523 * hal_srng_src_get_next_reaped when this function is used for reaping. 524 * 525 * @hal_soc: Opaque HAL SOC handle 526 * @hal_ring: Source ring pointer 527 * 528 * Return: Opaque pointer for next ring entry; NULL on failire 529 */ 530 static inline void *hal_srng_src_reap_next(void *hal_soc, void *hal_ring) 531 { 532 struct hal_srng *srng = (struct hal_srng *)hal_ring; 533 uint32_t *desc; 534 535 /* TODO: Using % is expensive, but we have to do this since 536 * size of some SRNG rings is not power of 2 (due to descriptor 537 * sizes). Need to create separate API for rings used 538 * per-packet, with sizes power of 2 (TCL2SW, REO2SW, 539 * SW2RXDMA and CE rings) 540 */ 541 uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) % 542 srng->ring_size; 543 544 if (next_reap_hp != srng->u.src_ring.cached_tp) { 545 desc = &(srng->ring_base_vaddr[next_reap_hp]); 546 srng->u.src_ring.reap_hp = next_reap_hp; 547 return (void *)desc; 548 } 549 550 return NULL; 551 } 552 553 /** 554 * hal_srng_src_get_next_reaped - Get next entry from a source ring that is 555 * already reaped using hal_srng_src_reap_next, for posting new entries to 556 * the ring 557 * 558 * @hal_soc: Opaque HAL SOC handle 559 * @hal_ring: Source ring pointer 560 * 561 * Return: Opaque pointer for next (reaped) source ring entry; NULL on failire 562 */ 563 static inline void *hal_srng_src_get_next_reaped(void *hal_soc, void *hal_ring) 564 { 565 struct hal_srng *srng = (struct hal_srng *)hal_ring; 566 uint32_t *desc; 567 568 if (srng->u.src_ring.hp != srng->u.src_ring.reap_hp) { 569 desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]); 570 srng->u.src_ring.hp = (srng->u.src_ring.hp + srng->entry_size) % 571 srng->ring_size; 572 573 return (void *)desc; 574 } 575 576 return NULL; 577 } 578 579 /** 580 * hal_srng_src_pending_reap_next - Reap next entry from a source ring and 581 * move reap pointer. This API is used in detach path to release any buffers 582 * associated with ring entries which are pending reap. 583 * 584 * @hal_soc: Opaque HAL SOC handle 585 * @hal_ring: Source ring pointer 586 * 587 * Return: Opaque pointer for next ring entry; NULL on failire 588 */ 589 static inline void *hal_srng_src_pending_reap_next(void *hal_soc, void *hal_ring) 590 { 591 struct hal_srng *srng = (struct hal_srng *)hal_ring; 592 uint32_t *desc; 593 594 uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) % 595 srng->ring_size; 596 597 if (next_reap_hp != srng->u.src_ring.hp) { 598 desc = &(srng->ring_base_vaddr[next_reap_hp]); 599 srng->u.src_ring.reap_hp = next_reap_hp; 600 return (void *)desc; 601 } 602 603 return NULL; 604 } 605 606 /** 607 * hal_srng_src_done_val - 608 * 609 * @hal_soc: Opaque HAL SOC handle 610 * @hal_ring: Source ring pointer 611 * 612 * Return: Opaque pointer for next ring entry; NULL on failire 613 */ 614 static inline uint32_t hal_srng_src_done_val(void *hal_soc, void *hal_ring) 615 { 616 struct hal_srng *srng = (struct hal_srng *)hal_ring; 617 /* TODO: Using % is expensive, but we have to do this since 618 * size of some SRNG rings is not power of 2 (due to descriptor 619 * sizes). Need to create separate API for rings used 620 * per-packet, with sizes power of 2 (TCL2SW, REO2SW, 621 * SW2RXDMA and CE rings) 622 */ 623 uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) % 624 srng->ring_size; 625 626 if (next_reap_hp == srng->u.src_ring.cached_tp) 627 return 0; 628 629 if (srng->u.src_ring.cached_tp > next_reap_hp) 630 return (srng->u.src_ring.cached_tp - next_reap_hp) / 631 srng->entry_size; 632 else 633 return ((srng->ring_size - next_reap_hp) + 634 srng->u.src_ring.cached_tp) / srng->entry_size; 635 } 636 637 /** 638 * hal_api_get_tphp - Get head and tail pointer location for any ring 639 * @hal_soc: Opaque HAL SOC handle 640 * @hal_ring: Source ring pointer 641 * @tailp: Tail Pointer 642 * @headp: Head Pointer 643 * 644 * Return: Update tail pointer and head pointer in arguments. 645 */ 646 static inline void hal_api_get_tphp(void *hal_soc, void *hal_ring, 647 uint32_t *tailp, uint32_t *headp) 648 { 649 struct hal_srng *srng = (struct hal_srng *)hal_ring; 650 651 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 652 *headp = srng->u.src_ring.hp / srng->entry_size; 653 *tailp = *(srng->u.src_ring.tp_addr) / srng->entry_size; 654 } else { 655 *tailp = srng->u.dst_ring.tp / srng->entry_size; 656 *headp = *(srng->u.dst_ring.hp_addr) / srng->entry_size; 657 } 658 } 659 660 /** 661 * hal_srng_src_get_next - Get next entry from a source ring and move cached tail pointer 662 * 663 * @hal_soc: Opaque HAL SOC handle 664 * @hal_ring: Source ring pointer 665 * 666 * Return: Opaque pointer for next ring entry; NULL on failire 667 */ 668 static inline void *hal_srng_src_get_next(void *hal_soc, void *hal_ring) 669 { 670 struct hal_srng *srng = (struct hal_srng *)hal_ring; 671 uint32_t *desc; 672 /* TODO: Using % is expensive, but we have to do this since 673 * size of some SRNG rings is not power of 2 (due to descriptor 674 * sizes). Need to create separate API for rings used 675 * per-packet, with sizes power of 2 (TCL2SW, REO2SW, 676 * SW2RXDMA and CE rings) 677 */ 678 uint32_t next_hp = (srng->u.src_ring.hp + srng->entry_size) % 679 srng->ring_size; 680 681 if (next_hp != srng->u.src_ring.cached_tp) { 682 desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]); 683 srng->u.src_ring.hp = next_hp; 684 /* TODO: Since reap function is not used by all rings, we can 685 * remove the following update of reap_hp in this function 686 * if we can ensure that only hal_srng_src_get_next_reaped 687 * is used for the rings requiring reap functionality 688 */ 689 srng->u.src_ring.reap_hp = next_hp; 690 return (void *)desc; 691 } 692 693 return NULL; 694 } 695 696 /** 697 * hal_srng_src_peek - Get next entry from a ring without moving head pointer. 698 * hal_srng_src_get_next should be called subsequently to move the head pointer 699 * 700 * @hal_soc: Opaque HAL SOC handle 701 * @hal_ring: Source ring pointer 702 * 703 * Return: Opaque pointer for next ring entry; NULL on failire 704 */ 705 static inline void *hal_srng_src_peek(void *hal_soc, void *hal_ring) 706 { 707 struct hal_srng *srng = (struct hal_srng *)hal_ring; 708 uint32_t *desc; 709 710 /* TODO: Using % is expensive, but we have to do this since 711 * size of some SRNG rings is not power of 2 (due to descriptor 712 * sizes). Need to create separate API for rings used 713 * per-packet, with sizes power of 2 (TCL2SW, REO2SW, 714 * SW2RXDMA and CE rings) 715 */ 716 if (((srng->u.src_ring.hp + srng->entry_size) % 717 srng->ring_size) != srng->u.src_ring.cached_tp) { 718 desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]); 719 return (void *)desc; 720 } 721 722 return NULL; 723 } 724 725 /** 726 * hal_srng_src_num_avail - Returns number of available entries in src ring 727 * 728 * @hal_soc: Opaque HAL SOC handle 729 * @hal_ring: Source ring pointer 730 * @sync_hw_ptr: Sync cached tail pointer with HW 731 * 732 */ 733 static inline uint32_t hal_srng_src_num_avail(void *hal_soc, 734 void *hal_ring, int sync_hw_ptr) 735 { 736 struct hal_srng *srng = (struct hal_srng *)hal_ring; 737 uint32_t tp; 738 uint32_t hp = srng->u.src_ring.hp; 739 740 if (sync_hw_ptr) { 741 tp = *(srng->u.src_ring.tp_addr); 742 srng->u.src_ring.cached_tp = tp; 743 } else { 744 tp = srng->u.src_ring.cached_tp; 745 } 746 747 if (tp > hp) 748 return ((tp - hp) / srng->entry_size) - 1; 749 else 750 return ((srng->ring_size - hp + tp) / srng->entry_size) - 1; 751 } 752 753 /** 754 * hal_srng_access_end_unlocked - End ring access (unlocked) - update cached 755 * ring head/tail pointers to HW. 756 * This should be used only if hal_srng_access_start_unlocked to start ring 757 * access 758 * 759 * @hal_soc: Opaque HAL SOC handle 760 * @hal_ring: Ring pointer (Source or Destination ring) 761 * 762 * Return: 0 on success; error on failire 763 */ 764 static inline void hal_srng_access_end_unlocked(void *hal_soc, void *hal_ring) 765 { 766 struct hal_srng *srng = (struct hal_srng *)hal_ring; 767 768 /* TODO: See if we need a write memory barrier here */ 769 if (srng->flags & HAL_SRNG_LMAC_RING) { 770 /* For LMAC rings, ring pointer updates are done through FW and 771 * hence written to a shared memory location that is read by FW 772 */ 773 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 774 *(srng->u.src_ring.hp_addr) = srng->u.src_ring.hp; 775 } else { 776 *(srng->u.dst_ring.tp_addr) = srng->u.dst_ring.tp; 777 } 778 } else { 779 if (srng->ring_dir == HAL_SRNG_SRC_RING) 780 hal_write_address_32_mb(hal_soc, 781 srng->u.src_ring.hp_addr, 782 srng->u.src_ring.hp); 783 else 784 hal_write_address_32_mb(hal_soc, 785 srng->u.dst_ring.tp_addr, 786 srng->u.dst_ring.tp); 787 } 788 } 789 790 /** 791 * hal_srng_access_end - Unlock ring access and update cached ring head/tail 792 * pointers to HW 793 * This should be used only if hal_srng_access_start to start ring access 794 * 795 * @hal_soc: Opaque HAL SOC handle 796 * @hal_ring: Ring pointer (Source or Destination ring) 797 * 798 * Return: 0 on success; error on failire 799 */ 800 static inline void hal_srng_access_end(void *hal_soc, void *hal_ring) 801 { 802 struct hal_srng *srng = (struct hal_srng *)hal_ring; 803 804 hal_srng_access_end_unlocked(hal_soc, hal_ring); 805 SRNG_UNLOCK(&(srng->lock)); 806 } 807 808 /** 809 * hal_srng_access_end_reap - Unlock ring access 810 * This should be used only if hal_srng_access_start to start ring access 811 * and should be used only while reaping SRC ring completions 812 * 813 * @hal_soc: Opaque HAL SOC handle 814 * @hal_ring: Ring pointer (Source or Destination ring) 815 * 816 * Return: 0 on success; error on failire 817 */ 818 static inline void hal_srng_access_end_reap(void *hal_soc, void *hal_ring) 819 { 820 struct hal_srng *srng = (struct hal_srng *)hal_ring; 821 822 SRNG_UNLOCK(&(srng->lock)); 823 } 824 825 /* TODO: Check if the following definitions is available in HW headers */ 826 #define WBM_IDLE_SCATTER_BUF_SIZE 32704 827 #define NUM_MPDUS_PER_LINK_DESC 6 828 #define NUM_MSDUS_PER_LINK_DESC 7 829 #define REO_QUEUE_DESC_ALIGN 128 830 831 #define LINK_DESC_ALIGN 128 832 833 #define ADDRESS_MATCH_TAG_VAL 0x5 834 /* Number of mpdu link pointers is 9 in case of TX_MPDU_QUEUE_HEAD and 14 in 835 * of TX_MPDU_QUEUE_EXT. We are defining a common average count here 836 */ 837 #define NUM_MPDU_LINKS_PER_QUEUE_DESC 12 838 839 /* TODO: Check with HW team on the scatter buffer size supported. As per WBM 840 * MLD, scatter_buffer_size in IDLE_LIST_CONTROL register is 9 bits and size 841 * should be specified in 16 word units. But the number of bits defined for 842 * this field in HW header files is 5. 843 */ 844 #define WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE 8 845 846 847 /** 848 * hal_idle_list_scatter_buf_size - Get the size of each scatter buffer 849 * in an idle list 850 * 851 * @hal_soc: Opaque HAL SOC handle 852 * 853 */ 854 static inline uint32_t hal_idle_list_scatter_buf_size(void *hal_soc) 855 { 856 return WBM_IDLE_SCATTER_BUF_SIZE; 857 } 858 859 /** 860 * hal_get_link_desc_size - Get the size of each link descriptor 861 * 862 * @hal_soc: Opaque HAL SOC handle 863 * 864 */ 865 static inline uint32_t hal_get_link_desc_size(struct hal_soc *hal_soc) 866 { 867 if (!hal_soc || !hal_soc->ops) { 868 qdf_print("Error: Invalid ops\n"); 869 QDF_BUG(0); 870 return -EINVAL; 871 } 872 if (!hal_soc->ops->hal_get_link_desc_size) { 873 qdf_print("Error: Invalid function pointer\n"); 874 QDF_BUG(0); 875 return -EINVAL; 876 } 877 return hal_soc->ops->hal_get_link_desc_size(); 878 } 879 880 /** 881 * hal_get_link_desc_align - Get the required start address alignment for 882 * link descriptors 883 * 884 * @hal_soc: Opaque HAL SOC handle 885 * 886 */ 887 static inline uint32_t hal_get_link_desc_align(void *hal_soc) 888 { 889 return LINK_DESC_ALIGN; 890 } 891 892 /** 893 * hal_num_mpdus_per_link_desc - Get number of mpdus each link desc can hold 894 * 895 * @hal_soc: Opaque HAL SOC handle 896 * 897 */ 898 static inline uint32_t hal_num_mpdus_per_link_desc(void *hal_soc) 899 { 900 return NUM_MPDUS_PER_LINK_DESC; 901 } 902 903 /** 904 * hal_num_msdus_per_link_desc - Get number of msdus each link desc can hold 905 * 906 * @hal_soc: Opaque HAL SOC handle 907 * 908 */ 909 static inline uint32_t hal_num_msdus_per_link_desc(void *hal_soc) 910 { 911 return NUM_MSDUS_PER_LINK_DESC; 912 } 913 914 /** 915 * hal_num_mpdu_links_per_queue_desc - Get number of mpdu links each queue 916 * descriptor can hold 917 * 918 * @hal_soc: Opaque HAL SOC handle 919 * 920 */ 921 static inline uint32_t hal_num_mpdu_links_per_queue_desc(void *hal_soc) 922 { 923 return NUM_MPDU_LINKS_PER_QUEUE_DESC; 924 } 925 926 /** 927 * hal_idle_list_scatter_buf_num_entries - Get the number of link desc entries 928 * that the given buffer size 929 * 930 * @hal_soc: Opaque HAL SOC handle 931 * @scatter_buf_size: Size of scatter buffer 932 * 933 */ 934 static inline uint32_t hal_idle_scatter_buf_num_entries(void *hal_soc, 935 uint32_t scatter_buf_size) 936 { 937 return (scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 938 hal_srng_get_entrysize(hal_soc, WBM_IDLE_LINK); 939 } 940 941 /** 942 * hal_idle_list_num_scatter_bufs - Get the number of sctater buffer 943 * each given buffer size 944 * 945 * @hal_soc: Opaque HAL SOC handle 946 * @total_mem: size of memory to be scattered 947 * @scatter_buf_size: Size of scatter buffer 948 * 949 */ 950 static inline uint32_t hal_idle_list_num_scatter_bufs(void *hal_soc, 951 uint32_t total_mem, uint32_t scatter_buf_size) 952 { 953 uint8_t rem = (total_mem % (scatter_buf_size - 954 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)) ? 1 : 0; 955 956 uint32_t num_scatter_bufs = (total_mem / (scatter_buf_size - 957 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)) + rem; 958 959 return num_scatter_bufs; 960 } 961 962 /* REO parameters to be passed to hal_reo_setup */ 963 struct hal_reo_params { 964 /** rx hash steering enabled or disabled */ 965 bool rx_hash_enabled; 966 /** reo remap 1 register */ 967 uint32_t remap1; 968 /** reo remap 2 register */ 969 uint32_t remap2; 970 /** fragment destination ring */ 971 uint8_t frag_dst_ring; 972 /** padding */ 973 uint8_t padding[3]; 974 }; 975 976 977 enum hal_pn_type { 978 HAL_PN_NONE, 979 HAL_PN_WPA, 980 HAL_PN_WAPI_EVEN, 981 HAL_PN_WAPI_UNEVEN, 982 }; 983 984 #define HAL_RX_MAX_BA_WINDOW 256 985 986 /** 987 * hal_get_reo_qdesc_align - Get start address alignment for reo 988 * queue descriptors 989 * 990 * @hal_soc: Opaque HAL SOC handle 991 * 992 */ 993 static inline uint32_t hal_get_reo_qdesc_align(void *hal_soc) 994 { 995 return REO_QUEUE_DESC_ALIGN; 996 } 997 998 /** 999 * hal_reo_qdesc_setup - Setup HW REO queue descriptor 1000 * 1001 * @hal_soc: Opaque HAL SOC handle 1002 * @ba_window_size: BlockAck window size 1003 * @start_seq: Starting sequence number 1004 * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory 1005 * @hw_qdesc_paddr: Physical address of REO queue descriptor memory 1006 * @pn_type: PN type (one of the types defined in 'enum hal_pn_type') 1007 * 1008 */ 1009 extern void hal_reo_qdesc_setup(void *hal_soc, int tid, uint32_t ba_window_size, 1010 uint32_t start_seq, void *hw_qdesc_vaddr, qdf_dma_addr_t hw_qdesc_paddr, 1011 int pn_type); 1012 1013 /** 1014 * hal_srng_get_hp_addr - Get head pointer physical address 1015 * 1016 * @hal_soc: Opaque HAL SOC handle 1017 * @hal_ring: Ring pointer (Source or Destination ring) 1018 * 1019 */ 1020 static inline qdf_dma_addr_t hal_srng_get_hp_addr(void *hal_soc, void *hal_ring) 1021 { 1022 struct hal_srng *srng = (struct hal_srng *)hal_ring; 1023 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1024 1025 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1026 return hal->shadow_wrptr_mem_paddr + 1027 ((unsigned long)(srng->u.src_ring.hp_addr) - 1028 (unsigned long)(hal->shadow_wrptr_mem_vaddr)); 1029 } else { 1030 return hal->shadow_rdptr_mem_paddr + 1031 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1032 (unsigned long)(hal->shadow_rdptr_mem_vaddr)); 1033 } 1034 } 1035 1036 /** 1037 * hal_srng_get_tp_addr - Get tail pointer physical address 1038 * 1039 * @hal_soc: Opaque HAL SOC handle 1040 * @hal_ring: Ring pointer (Source or Destination ring) 1041 * 1042 */ 1043 static inline qdf_dma_addr_t hal_srng_get_tp_addr(void *hal_soc, void *hal_ring) 1044 { 1045 struct hal_srng *srng = (struct hal_srng *)hal_ring; 1046 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1047 1048 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1049 return hal->shadow_rdptr_mem_paddr + 1050 ((unsigned long)(srng->u.src_ring.tp_addr) - 1051 (unsigned long)(hal->shadow_rdptr_mem_vaddr)); 1052 } else { 1053 return hal->shadow_wrptr_mem_paddr + 1054 ((unsigned long)(srng->u.dst_ring.tp_addr) - 1055 (unsigned long)(hal->shadow_wrptr_mem_vaddr)); 1056 } 1057 } 1058 1059 /** 1060 * hal_get_srng_params - Retrieve SRNG parameters for a given ring from HAL 1061 * 1062 * @hal_soc: Opaque HAL SOC handle 1063 * @hal_ring: Ring pointer (Source or Destination ring) 1064 * @ring_params: SRNG parameters will be returned through this structure 1065 */ 1066 extern void hal_get_srng_params(void *hal_soc, void *hal_ring, 1067 struct hal_srng_params *ring_params); 1068 1069 /** 1070 * hal_mem_info - Retrieve hal memory base address 1071 * 1072 * @hal_soc: Opaque HAL SOC handle 1073 * @mem: pointer to structure to be updated with hal mem info 1074 */ 1075 extern void hal_get_meminfo(void *hal_soc,struct hal_mem_info *mem ); 1076 1077 /** 1078 * hal_get_target_type - Return target type 1079 * 1080 * @hal_soc: Opaque HAL SOC handle 1081 */ 1082 uint32_t hal_get_target_type(struct hal_soc *hal); 1083 1084 /** 1085 * hal_get_ba_aging_timeout - Retrieve BA aging timeout 1086 * 1087 * @hal_soc: Opaque HAL SOC handle 1088 * @ac: Access category 1089 * @value: timeout duration in millisec 1090 */ 1091 void hal_get_ba_aging_timeout(void *hal_soc, uint8_t ac, 1092 uint32_t *value); 1093 /** 1094 * hal_set_aging_timeout - Set BA aging timeout 1095 * 1096 * @hal_soc: Opaque HAL SOC handle 1097 * @ac: Access category in millisec 1098 * @value: timeout duration value 1099 */ 1100 void hal_set_ba_aging_timeout(void *hal_soc, uint8_t ac, 1101 uint32_t value); 1102 /** 1103 * hal_srng_dst_hw_init - Private function to initialize SRNG 1104 * destination ring HW 1105 * @hal_soc: HAL SOC handle 1106 * @srng: SRNG ring pointer 1107 */ 1108 static inline void hal_srng_dst_hw_init(struct hal_soc *hal, 1109 struct hal_srng *srng) 1110 { 1111 hal->ops->hal_srng_dst_hw_init(hal, srng); 1112 } 1113 1114 /** 1115 * hal_srng_src_hw_init - Private function to initialize SRNG 1116 * source ring HW 1117 * @hal_soc: HAL SOC handle 1118 * @srng: SRNG ring pointer 1119 */ 1120 static inline void hal_srng_src_hw_init(struct hal_soc *hal, 1121 struct hal_srng *srng) 1122 { 1123 hal->ops->hal_srng_src_hw_init(hal, srng); 1124 } 1125 1126 /** 1127 * hal_reo_setup - Initialize HW REO block 1128 * 1129 * @hal_soc: Opaque HAL SOC handle 1130 * @reo_params: parameters needed by HAL for REO config 1131 */ 1132 static inline void hal_reo_setup(void *halsoc, 1133 void *reoparams) 1134 { 1135 struct hal_soc *hal_soc = (struct hal_soc *)halsoc; 1136 1137 hal_soc->ops->hal_reo_setup(halsoc, reoparams); 1138 } 1139 1140 /** 1141 * hal_setup_link_idle_list - Setup scattered idle list using the 1142 * buffer list provided 1143 * 1144 * @hal_soc: Opaque HAL SOC handle 1145 * @scatter_bufs_base_paddr: Array of physical base addresses 1146 * @scatter_bufs_base_vaddr: Array of virtual base addresses 1147 * @num_scatter_bufs: Number of scatter buffers in the above lists 1148 * @scatter_buf_size: Size of each scatter buffer 1149 * @last_buf_end_offset: Offset to the last entry 1150 * @num_entries: Total entries of all scatter bufs 1151 * 1152 */ 1153 static inline void hal_setup_link_idle_list(void *halsoc, 1154 qdf_dma_addr_t scatter_bufs_base_paddr[], 1155 void *scatter_bufs_base_vaddr[], uint32_t num_scatter_bufs, 1156 uint32_t scatter_buf_size, uint32_t last_buf_end_offset, 1157 uint32_t num_entries) 1158 { 1159 struct hal_soc *hal_soc = (struct hal_soc *)halsoc; 1160 1161 hal_soc->ops->hal_setup_link_idle_list(halsoc, scatter_bufs_base_paddr, 1162 scatter_bufs_base_vaddr, num_scatter_bufs, 1163 scatter_buf_size, last_buf_end_offset, 1164 num_entries); 1165 1166 } 1167 #endif /* _HAL_APIH_ */ 1168