1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_BE_TX_H_ 21 #define _HAL_BE_TX_H_ 22 23 #include "hal_be_hw_headers.h" 24 #include "hal_tx.h" 25 26 /* Number of TX banks reserved i.e, will not be used by host driver. */ 27 /* MAX_TCL_BANK reserved for FW use */ 28 #define HAL_TX_NUM_RESERVED_BANKS 1 29 30 /* 31 * Number of Priority to TID mapping 32 */ 33 #define HAL_BE_TX_MAP0_PRI2TID_MAX 10 34 #define HAL_BE_TX_MAP1_PRI2TID_MAX 6 35 36 enum hal_be_tx_ret_buf_manager { 37 HAL_BE_WBM_SW0_BM_ID = 5, 38 HAL_BE_WBM_SW1_BM_ID = 6, 39 HAL_BE_WBM_SW2_BM_ID = 7, 40 HAL_BE_WBM_SW3_BM_ID = 8, 41 HAL_BE_WBM_SW4_BM_ID = 9, 42 HAL_BE_WBM_SW5_BM_ID = 10, 43 HAL_BE_WBM_SW6_BM_ID = 11, 44 }; 45 46 enum hal_tx_mcast_ctrl { 47 /* mcast traffic exceptioned to FW 48 * valid only for AP VAP default for AP 49 */ 50 HAL_TX_MCAST_CTRL_FW_EXCEPTION = 0, 51 /* mcast traffic dropped in TCL*/ 52 HAL_TX_MCAST_CTRL_DROP, 53 /* MEC notification are enabled 54 * valid only for client VAP 55 */ 56 HAL_TX_MCAST_CTRL_MEC_NOTIFY, 57 /* no special routing for mcast 58 * valid for client vap when index search is enabled 59 */ 60 HAL_TX_MCAST_CTRL_NO_SPECIAL, 61 }; 62 63 /* enum hal_tx_notify_frame_type - TX notify frame type 64 * @NO_TX_NOTIFY: Not a notify frame 65 * @TX_HARD_NOTIFY: Hard notify TX frame 66 * @TX_SOFT_NOTIFY_E: Soft Notify Tx frame 67 * @TX_SEMI_HARD_NOTIFY_E: Semi Hard notify TX frame 68 */ 69 enum hal_tx_notify_frame_type { 70 NO_TX_NOTIFY = 0, 71 TX_HARD_NOTIFY = 1, 72 TX_SOFT_NOTIFY_E = 2, 73 TX_SEMI_HARD_NOTIFY_E = 3 74 }; 75 76 /*--------------------------------------------------------------------------- 77 * Structures 78 * --------------------------------------------------------------------------- 79 */ 80 /** 81 * struct hal_tx_bank_config - SW config bank params 82 * @epd: EPD indication flag 83 * @encap_type: encapsulation type 84 * @encrypt_type: encrypt type 85 * @src_buffer_swap: big-endia switch for packet buffer 86 * @link_meta_swap: big-endian switch for link metadata 87 * @index_lookup_enable: Enabel index lookup 88 * @addrx_en: Address-X search 89 * @addry_en: Address-Y search 90 * @mesh_enable:mesh enable flag 91 * @vdev_id_check_en: vdev id check 92 * @pmac_id: mac id 93 * @mcast_pkt_ctrl: mulitcast packet control 94 * @val: value representing bank config 95 */ 96 union hal_tx_bank_config { 97 struct { 98 uint32_t epd:1, 99 encap_type:2, 100 encrypt_type:4, 101 src_buffer_swap:1, 102 link_meta_swap:1, 103 index_lookup_enable:1, 104 addrx_en:1, 105 addry_en:1, 106 mesh_enable:2, 107 vdev_id_check_en:1, 108 pmac_id:2, 109 mcast_pkt_ctrl:2, 110 dscp_tid_map_id:6, 111 reserved:7; 112 }; 113 uint32_t val; 114 }; 115 116 /** 117 * struct hal_tx_cmn_config_ppe - SW config exception related parameters 118 * @drop_prec_err - Exception drop_prec errors. 119 * @fake_mac_hdr - Exception fake mac header. 120 * @cpu_code_inv - Exception cpu code invalid. 121 * @data_buff_err - Exception buffer length/offset erorors. 122 * @l3_l4_err - Exception m3_l4 checksum errors 123 * @data_offset_max - Maximum data offset allowed. 124 * @data_len_max - Maximum data length allowed. 125 */ 126 union hal_tx_cmn_config_ppe { 127 struct { 128 uint32_t drop_prec_err:1, 129 fake_mac_hdr:1, 130 cpu_code_inv:1, 131 data_buff_err:1, 132 l3_l4_err:1, 133 data_offset_max:12, 134 data_len_max:14; 135 }; 136 uint32_t val; 137 }; 138 139 /** 140 * hal_tx_ppe_vp_config - SW config PPE VP table 141 * @vp_num - Virtual port number 142 * @pmac_id - Lmac ID 143 * @bank_id: Bank ID correspondig to this I/F. 144 * @vdev_id: VDEV ID of the I/F. 145 * @search_idx_reg_num: Register number of this SI. 146 * @use_ppe_int_pri: Use the PPE INT_PRI to TID table 147 * @to_fw: Use FW 148 * @drop_prec_enable: Enable precendance drop. 149 */ 150 union hal_tx_ppe_vp_config { 151 struct { 152 uint32_t vp_num:8, 153 pmac_id:2, 154 bank_id:6, 155 vdev_id:8, 156 search_idx_reg_num:3, 157 use_ppe_int_pri:1, 158 to_fw:1, 159 drop_prec_enable:1; 160 }; 161 uint32_t val; 162 }; 163 164 /** 165 * hal_tx_cmn_ppe_idx_map_config: Use ppe index mapping table 166 * @search_idx: Search index 167 * @cache_set: Cache set number 168 */ 169 union hal_tx_ppe_idx_map_config { 170 struct { 171 uint32_t search_idx:20, 172 cache_set:4; 173 }; 174 uint32_t val; 175 }; 176 177 /** 178 * hal_tx_ppe_pri2tid_map0_config : Configure ppe INT_PRI to tid map 179 * @int_pri0: INT_PRI_0 180 * @int_pri1: INT_PRI_1 181 * @int_pri2: INT_PRI_2 182 * @int_pri3: INT_PRI_3 183 * @int_pri4: INT_PRI_4 184 * @int_pri5: INT_PRI_5 185 * @int_pri6: INT_PRI_6 186 * @int_pri7: INT_PRI_7 187 * @int_pri8: INT_PRI_8 188 * @int_pri9: INT_PRI_9 189 */ 190 union hal_tx_ppe_pri2tid_map0_config { 191 struct { 192 uint32_t int_pri0:3, 193 int_pri1:3, 194 int_pri2:3, 195 int_pri3:3, 196 int_pri4:3, 197 int_pri5:3, 198 int_pri6:3, 199 int_pri7:3, 200 int_pri8:3, 201 int_pri9:3; 202 }; 203 uint32_t val; 204 }; 205 206 /** 207 * hal_tx_ppe_pri2tid_map1_config : Configure ppe INT_PRI to tid map 208 * @int_pri0: INT_PRI_10 209 * @int_pri1: INT_PRI_11 210 * @int_pri2: INT_PRI_12 211 * @int_pri3: INT_PRI_13 212 * @int_pri4: INT_PRI_14 213 * @int_pri5: INT_PRI_15 214 */ 215 union hal_tx_ppe_pri2tid_map1_config { 216 struct { 217 uint32_t int_pri10:3, 218 int_pri11:3, 219 int_pri12:3, 220 int_pri13:3, 221 int_pri14:3, 222 int_pri15:3; 223 }; 224 uint32_t val; 225 }; 226 227 /*--------------------------------------------------------------------------- 228 * Function declarations and documentation 229 * --------------------------------------------------------------------------- 230 */ 231 232 /*--------------------------------------------------------------------------- 233 * TCL Descriptor accessor APIs 234 *--------------------------------------------------------------------------- 235 */ 236 237 /** 238 * hal_tx_desc_set_tx_notify_frame - Set TX notify_frame field in Tx desc 239 * @desc: Handle to Tx Descriptor 240 * @val: Value to be set 241 * 242 * Return: None 243 */ 244 static inline void hal_tx_desc_set_tx_notify_frame(void *desc, 245 uint8_t val) 246 { 247 HAL_SET_FLD(desc, TCL_DATA_CMD, TX_NOTIFY_FRAME) |= 248 HAL_TX_SM(TCL_DATA_CMD, TX_NOTIFY_FRAME, val); 249 } 250 251 /** 252 * hal_tx_desc_set_flow_override_enable - Set flow_override_enable field 253 * @desc: Handle to Tx Descriptor 254 * @val: Value to be set 255 * 256 * Return: None 257 */ 258 static inline void hal_tx_desc_set_flow_override_enable(void *desc, 259 uint8_t val) 260 { 261 HAL_SET_FLD(desc, TCL_DATA_CMD, FLOW_OVERRIDE_ENABLE) |= 262 HAL_TX_SM(TCL_DATA_CMD, FLOW_OVERRIDE_ENABLE, val); 263 } 264 265 /** 266 * hal_tx_desc_set_flow_override - Set flow_override field in TX desc 267 * @desc: Handle to Tx Descriptor 268 * @val: Value to be set 269 * 270 * Return: None 271 */ 272 static inline void hal_tx_desc_set_flow_override(void *desc, 273 uint8_t val) 274 { 275 HAL_SET_FLD(desc, TCL_DATA_CMD, FLOW_OVERRIDE) |= 276 HAL_TX_SM(TCL_DATA_CMD, FLOW_OVERRIDE, val); 277 } 278 279 /** 280 * hal_tx_desc_set_who_classify_info_sel - Set who_classify_info_sel field 281 * @desc: Handle to Tx Descriptor 282 * @val: Value to be set 283 * 284 * Return: None 285 */ 286 static inline void hal_tx_desc_set_who_classify_info_sel(void *desc, 287 uint8_t val) 288 { 289 HAL_SET_FLD(desc, TCL_DATA_CMD, WHO_CLASSIFY_INFO_SEL) |= 290 HAL_TX_SM(TCL_DATA_CMD, WHO_CLASSIFY_INFO_SEL, val); 291 } 292 293 /** 294 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 295 * @desc: Handle to Tx Descriptor 296 * @data_length: MSDU length in case of direct descriptor. 297 * Length of link extension descriptor in case of Link extension 298 * descriptor.Includes the length of Metadata 299 * Return: None 300 */ 301 static inline void hal_tx_desc_set_buf_length(void *desc, 302 uint16_t data_length) 303 { 304 HAL_SET_FLD(desc, TCL_DATA_CMD, DATA_LENGTH) |= 305 HAL_TX_SM(TCL_DATA_CMD, DATA_LENGTH, data_length); 306 } 307 308 /** 309 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 310 * @desc: Handle to Tx Descriptor 311 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 312 * 313 * Return: void 314 */ 315 static inline void hal_tx_desc_set_buf_offset(void *desc, 316 uint8_t offset) 317 { 318 HAL_SET_FLD(desc, TCL_DATA_CMD, PACKET_OFFSET) |= 319 HAL_TX_SM(TCL_DATA_CMD, PACKET_OFFSET, offset); 320 } 321 322 /** 323 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 324 * Tx Descriptor for MSDU_buffer type 325 * @desc: Handle to Tx Descriptor 326 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 327 * 328 * Return: void 329 */ 330 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 331 uint8_t en) 332 { 333 HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |= 334 (HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV4_CHECKSUM_EN, en) | 335 HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV6_CHECKSUM_EN, en) | 336 HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV4_CHECKSUM_EN, en) | 337 HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV6_CHECKSUM_EN, en)); 338 } 339 340 /** 341 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 342 * Tx Descriptor for MSDU_buffer type 343 * @desc: Handle to Tx Descriptor 344 * @checksum_en_flags: ipv4 checksum enable flags 345 * 346 * Return: void 347 */ 348 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 349 uint8_t en) 350 { 351 HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |= 352 HAL_TX_SM(TCL_DATA_CMD, IPV4_CHECKSUM_EN, en); 353 } 354 355 /** 356 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 357 * @desc:Handle to Tx Descriptor 358 * @metadata: Metadata to be sent to Firmware 359 * 360 * Return: void 361 */ 362 static inline void hal_tx_desc_set_fw_metadata(void *desc, 363 uint16_t metadata) 364 { 365 HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_NUMBER) |= 366 HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_NUMBER, metadata); 367 } 368 369 /** 370 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 371 * @desc:Handle to Tx Descriptor 372 * @to_fw: if set, Forward packet to FW along with classification result 373 * 374 * Return: void 375 */ 376 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 377 { 378 HAL_SET_FLD(desc, TCL_DATA_CMD, TO_FW) |= 379 HAL_TX_SM(TCL_DATA_CMD, TO_FW, to_fw); 380 } 381 382 /** 383 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 384 * frame) to be used for Tx Frame 385 * @desc: Handle to Tx Descriptor 386 * @hlos_tid: HLOS TID 387 * 388 * Return: void 389 */ 390 static inline void hal_tx_desc_set_hlos_tid(void *desc, 391 uint8_t hlos_tid) 392 { 393 HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID) |= 394 HAL_TX_SM(TCL_DATA_CMD, HLOS_TID, hlos_tid); 395 396 HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID_OVERWRITE) |= 397 HAL_TX_SM(TCL_DATA_CMD, HLOS_TID_OVERWRITE, 1); 398 } 399 400 /** 401 * hal_tx_desc_sync - Commit the descriptor to Hardware 402 * @hal_tx_des_cached: Cached descriptor that software maintains 403 * @hw_desc: Hardware descriptor to be updated 404 */ 405 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 406 void *hw_desc) 407 { 408 qdf_mem_copy(hw_desc, hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES); 409 } 410 411 /** 412 * hal_tx_desc_set_vdev_id - set vdev id to the descriptor to Hardware 413 * @hal_tx_des_cached: Cached descriptor that software maintains 414 * @vdev_id: vdev id 415 */ 416 static inline void hal_tx_desc_set_vdev_id(void *desc, uint8_t vdev_id) 417 { 418 HAL_SET_FLD(desc, TCL_DATA_CMD, VDEV_ID) |= 419 HAL_TX_SM(TCL_DATA_CMD, VDEV_ID, vdev_id); 420 } 421 422 /** 423 * hal_tx_desc_set_bank_id - set bank id to the descriptor to Hardware 424 * @hal_tx_des_cached: Cached descriptor that software maintains 425 * @bank_id: bank id 426 */ 427 static inline void hal_tx_desc_set_bank_id(void *desc, uint8_t bank_id) 428 { 429 HAL_SET_FLD(desc, TCL_DATA_CMD, BANK_ID) |= 430 HAL_TX_SM(TCL_DATA_CMD, BANK_ID, bank_id); 431 } 432 433 /** 434 * hal_tx_desc_set_tcl_cmd_type - set tcl command type to the descriptor 435 * to Hardware 436 * @hal_tx_des_cached: Cached descriptor that software maintains 437 * @tcl_cmd_type: tcl command type 438 */ 439 static inline void 440 hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type) 441 { 442 HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_TYPE) |= 443 HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_TYPE, tcl_cmd_type); 444 } 445 446 /** 447 * hal_tx_desc_set_lmac_id_be - set lmac id to the descriptor to Hardware 448 * @hal_soc_hdl: hal soc handle 449 * @hal_tx_des_cached: Cached descriptor that software maintains 450 * @lmac_id: lmac id 451 */ 452 static inline void 453 hal_tx_desc_set_lmac_id_be(hal_soc_handle_t hal_soc_hdl, void *desc, 454 uint8_t lmac_id) 455 { 456 HAL_SET_FLD(desc, TCL_DATA_CMD, PMAC_ID) |= 457 HAL_TX_SM(TCL_DATA_CMD, PMAC_ID, lmac_id); 458 } 459 460 /** 461 * hal_tx_desc_set_search_index_be - set search index to the 462 * descriptor to Hardware 463 * @hal_soc_hdl: hal soc handle 464 * @hal_tx_des_cached: Cached descriptor that software maintains 465 * @search_index: search index 466 */ 467 static inline void 468 hal_tx_desc_set_search_index_be(hal_soc_handle_t hal_soc_hdl, void *desc, 469 uint32_t search_index) 470 { 471 HAL_SET_FLD(desc, TCL_DATA_CMD, SEARCH_INDEX) |= 472 HAL_TX_SM(TCL_DATA_CMD, SEARCH_INDEX, search_index); 473 } 474 475 /** 476 * hal_tx_desc_set_cache_set_num - set cache set num to the 477 * descriptor to Hardware 478 * @hal_soc_hdl: hal soc handle 479 * @hal_tx_des_cached: Cached descriptor that software maintains 480 * @cache_num: cache number 481 */ 482 static inline void 483 hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, void *desc, 484 uint8_t cache_num) 485 { 486 HAL_SET_FLD(desc, TCL_DATA_CMD, CACHE_SET_NUM) |= 487 HAL_TX_SM(TCL_DATA_CMD, CACHE_SET_NUM, cache_num); 488 } 489 490 /*--------------------------------------------------------------------------- 491 * WBM Descriptor accessor APIs for Tx completions 492 * --------------------------------------------------------------------------- 493 */ 494 495 /** 496 * hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring 497 * 498 * Return: BM ID for first tx completion ring 499 */ 500 static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void) 501 { 502 return HAL_BE_WBM_SW0_BM_ID; 503 } 504 505 /** 506 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 507 * @hal_desc: completion ring descriptor pointer 508 * 509 * This function will tx descriptor id, cookie, within hardware completion 510 * descriptor. For cases when cookie conversion is disabled, the sw_cookie 511 * is present in the 2nd DWORD. 512 * 513 * Return: cookie 514 */ 515 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 516 { 517 uint32_t comp_desc = 518 *(uint32_t *)(((uint8_t *)hal_desc) + 519 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET); 520 521 /* Cookie is placed on 2nd word */ 522 return (comp_desc & BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK) >> 523 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB; 524 } 525 526 /** 527 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 528 * @hal_desc: completion ring descriptor pointer 529 * 530 * This function will get buffer physical address within hardware completion 531 * descriptor 532 * 533 * Return: Buffer physical address 534 */ 535 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 536 { 537 uint32_t paddr_lo; 538 uint32_t paddr_hi; 539 540 paddr_lo = *(uint32_t *)(((uint8_t *)hal_desc) + 541 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET); 542 543 paddr_hi = *(uint32_t *)(((uint8_t *)hal_desc) + 544 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET); 545 546 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) >> 547 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB; 548 549 return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32)); 550 } 551 552 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 553 /* HW set dowrd-2 bit30 to 1 if HW CC is done */ 554 #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_OFFSET 0x8 555 #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_MASK 0x40000000 556 #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_LSB 0x1E 557 /** 558 * hal_tx_comp_get_cookie_convert_done() - Get cookie conversion done flag 559 * @hal_desc: completion ring descriptor pointer 560 * 561 * This function will get the bit value that indicate HW cookie 562 * conversion done or not 563 * 564 * Return: 1 - HW cookie conversion done, 0 - not 565 */ 566 static inline uint8_t hal_tx_comp_get_cookie_convert_done(void *hal_desc) 567 { 568 return HAL_TX_DESC_GET(hal_desc, HAL_WBM2SW_COMPLETION_RING_TX, 569 CC_DONE); 570 } 571 #endif 572 573 /** 574 * hal_tx_comp_get_desc_va() - Get Desc virtual address within completion Desc 575 * @hal_desc: completion ring descriptor pointer 576 * 577 * This function will get the TX Desc virtual address 578 * 579 * Return: TX desc virtual address 580 */ 581 static inline uintptr_t hal_tx_comp_get_desc_va(void *hal_desc) 582 { 583 uint64_t va_from_desc; 584 585 va_from_desc = HAL_TX_DESC_GET(hal_desc, 586 WBM2SW_COMPLETION_RING_TX, 587 BUFFER_VIRT_ADDR_31_0) | 588 (((uint64_t)HAL_TX_DESC_GET( 589 hal_desc, 590 WBM2SW_COMPLETION_RING_TX, 591 BUFFER_VIRT_ADDR_63_32)) << 32); 592 593 return (uintptr_t)va_from_desc; 594 } 595 596 /*--------------------------------------------------------------------------- 597 * TX BANK register accessor APIs 598 * --------------------------------------------------------------------------- 599 */ 600 601 /** 602 * hal_tx_get_num_tcl_banks() - Get number of banks for target 603 * 604 * Return: None 605 */ 606 static inline uint8_t 607 hal_tx_get_num_tcl_banks(hal_soc_handle_t hal_soc_hdl) 608 { 609 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 610 int hal_banks = 0; 611 612 if (hal_soc->ops->hal_tx_get_num_tcl_banks) { 613 hal_banks = hal_soc->ops->hal_tx_get_num_tcl_banks(); 614 hal_banks -= HAL_TX_NUM_RESERVED_BANKS; 615 hal_banks = (hal_banks < 0) ? 0 : hal_banks; 616 } 617 618 return hal_banks; 619 } 620 621 /** 622 * hal_tx_populate_bank_register() - populate the bank register with 623 * the software configs. 624 * @soc: HAL soc handle 625 * @config: bank config 626 * @bank_id: bank id to be configured 627 * 628 * Returns: None 629 */ 630 static inline void 631 hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl, 632 union hal_tx_bank_config *config, 633 uint8_t bank_id) 634 { 635 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 636 637 hal_soc->ops->hal_tx_populate_bank_register(hal_soc_hdl, config, 638 bank_id); 639 } 640 641 #ifdef DP_TX_IMPLICIT_RBM_MAPPING 642 643 #define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK 644 #define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT 645 646 #define RBM_PPE2TCL_OFFSET \ 647 (HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2) 648 #define RBM_TCL_CMD_CREDIT_OFFSET \ 649 (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2) 650 651 /** 652 * hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id 653 * @hal_soc: HAL SoC context 654 * @hal_ring_hdl: Source ring pointer 655 * @rbm_id: return buffer manager ring id 656 * 657 * Return: void 658 */ 659 static inline void 660 hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl, 661 hal_ring_handle_t hal_ring_hdl, 662 uint8_t rbm_id) 663 { 664 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 665 666 hal_soc->ops->hal_tx_config_rbm_mapping_be(hal_soc_hdl, hal_ring_hdl, 667 rbm_id); 668 } 669 #else 670 static inline void 671 hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl, 672 hal_ring_handle_t hal_ring_hdl, 673 uint8_t rbm_id) 674 { 675 } 676 #endif 677 678 /** 679 * hal_tx_desc_set_buf_addr_be - Fill Buffer Address information in Tx Desc 680 * @desc: Handle to Tx Descriptor 681 * @paddr: Physical Address 682 * @pool_id: Return Buffer Manager ID 683 * @desc_id: Descriptor ID 684 * @type: 0 - Address points to a MSDU buffer 685 * 1 - Address points to MSDU extension descriptor 686 * 687 * Return: void 688 */ 689 #ifdef DP_TX_IMPLICIT_RBM_MAPPING 690 static inline void 691 hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc, 692 dma_addr_t paddr, uint8_t rbm_id, 693 uint32_t desc_id, uint8_t type) 694 { 695 /* Set buffer_addr_info.buffer_addr_31_0 */ 696 HAL_SET_FLD(desc, TCL_DATA_CMD, 697 BUF_ADDR_INFO_BUFFER_ADDR_31_0) = 698 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr); 699 700 /* Set buffer_addr_info.buffer_addr_39_32 */ 701 HAL_SET_FLD(desc, TCL_DATA_CMD, 702 BUF_ADDR_INFO_BUFFER_ADDR_39_32) |= 703 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32, 704 (((uint64_t)paddr) >> 32)); 705 706 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 707 HAL_SET_FLD(desc, TCL_DATA_CMD, 708 BUF_ADDR_INFO_SW_BUFFER_COOKIE) |= 709 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE, 710 desc_id); 711 712 /* Set Buffer or Ext Descriptor Type */ 713 HAL_SET_FLD(desc, TCL_DATA_CMD, 714 BUF_OR_EXT_DESC_TYPE) |= 715 HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type); 716 } 717 #else 718 static inline void 719 hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc, 720 dma_addr_t paddr, uint8_t rbm_id, 721 uint32_t desc_id, uint8_t type) 722 { 723 /* Set buffer_addr_info.buffer_addr_31_0 */ 724 HAL_SET_FLD(desc, TCL_DATA_CMD, 725 BUF_ADDR_INFO_BUFFER_ADDR_31_0) = 726 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr); 727 728 /* Set buffer_addr_info.buffer_addr_39_32 */ 729 HAL_SET_FLD(desc, TCL_DATA_CMD, 730 BUF_ADDR_INFO_BUFFER_ADDR_39_32) |= 731 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32, 732 (((uint64_t)paddr) >> 32)); 733 734 /* Set buffer_addr_info.return_buffer_manager = rbm id */ 735 HAL_SET_FLD(desc, TCL_DATA_CMD, 736 BUF_ADDR_INFO_RETURN_BUFFER_MANAGER) |= 737 HAL_TX_SM(TCL_DATA_CMD, 738 BUF_ADDR_INFO_RETURN_BUFFER_MANAGER, rbm_id); 739 740 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 741 HAL_SET_FLD(desc, TCL_DATA_CMD, 742 BUF_ADDR_INFO_SW_BUFFER_COOKIE) |= 743 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE, 744 desc_id); 745 746 /* Set Buffer or Ext Descriptor Type */ 747 HAL_SET_FLD(desc, TCL_DATA_CMD, 748 BUF_OR_EXT_DESC_TYPE) |= 749 HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type); 750 } 751 #endif 752 753 /** 754 * hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing 755 * @hal_soc: HAL SoC context 756 * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM 757 * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW 758 * 759 * Return: void 760 */ 761 #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK 762 static inline void 763 hal_tx_vdev_mismatch_routing_set(hal_soc_handle_t hal_soc_hdl, 764 enum hal_tx_vdev_mismatch_notify config) 765 { 766 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 767 768 hal_soc->ops->hal_tx_vdev_mismatch_routing_set(hal_soc_hdl, config); 769 } 770 #else 771 static inline void 772 hal_tx_vdev_mismatch_routing_set(hal_soc_handle_t hal_soc_hdl, 773 enum hal_tx_vdev_mismatch_notify config) 774 { 775 } 776 #endif 777 778 /** 779 * hal_tx_mcast_mlo_reinject_routing_set - set MLO multicast reinject routing 780 * @hal_soc: HAL SoC context 781 * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW 782 * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM 783 * 784 * Return: void 785 */ 786 #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \ 787 defined(WLAN_MCAST_MLO) 788 static inline void 789 hal_tx_mcast_mlo_reinject_routing_set( 790 hal_soc_handle_t hal_soc_hdl, 791 enum hal_tx_mcast_mlo_reinject_notify config) 792 { 793 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 794 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set(hal_soc_hdl, 795 config); 796 } 797 #else 798 static inline void 799 hal_tx_mcast_mlo_reinject_routing_set( 800 hal_soc_handle_t hal_soc_hdl, 801 enum hal_tx_mcast_mlo_reinject_notify config) 802 { 803 } 804 #endif 805 806 /* 807 * hal_tx_get_num_ppe_vp_tbl_entries() - Get the total number of VP table 808 * @hal_soc: HAL SoC Context 809 * 810 * Return: Total number of entries. 811 */ 812 static inline 813 uint32_t hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_handle_t hal_soc_hdl) 814 { 815 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 816 817 return hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_hdl); 818 } 819 820 /** 821 * hal_tx_set_ppe_cmn_cfg()- Set the PPE common config 822 * @hal_soc: HAL SoC context 823 * @cmn_cfg: HAL PPE VP common config 824 * 825 * Return: void 826 */ 827 static inline void 828 hal_tx_set_ppe_cmn_cfg(hal_soc_handle_t hal_soc_hdl, 829 union hal_tx_cmn_config_ppe *cmn_cfg) 830 { 831 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 832 833 hal_soc->ops->hal_tx_set_ppe_cmn_cfg(hal_soc_hdl, cmn_cfg); 834 } 835 836 /** 837 * hal_tx_populate_ppe_vp_entry - Populate ppe VP entry 838 * @hal_soc: HAL SoC context 839 * @vp_cfg: HAL PPE VP config 840 * @ppe_vp_idx: PPE VP index 841 * 842 * Return: void 843 */ 844 static inline void 845 hal_tx_populate_ppe_vp_entry(hal_soc_handle_t hal_soc_hdl, 846 union hal_tx_ppe_vp_config *vp_cfg, 847 int ppe_vp_idx) 848 { 849 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 850 851 hal_soc->ops->hal_tx_set_ppe_vp_entry(hal_soc_hdl, vp_cfg, ppe_vp_idx); 852 } 853 854 /** 855 * hal_tx_set_int_pri2id - Set the prit2tid table. 856 * @hal_soc: HAL SoC context 857 * @pri2tid: Reference to SW INT_PRI to TID table 858 * 859 * Return: void 860 */ 861 static inline void 862 hal_tx_set_int_pri2tid(hal_soc_handle_t hal_soc_hdl, 863 uint32_t val, uint8_t map_no) 864 { 865 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 866 867 hal_soc->ops->hal_tx_set_ppe_pri2tid(hal_soc_hdl, val, map_no); 868 } 869 870 /** 871 * hal_tx_update_int_pri2id - Populate the prit2tid table. 872 * @hal_soc: HAL SoC context 873 * @pri: INT_PRI value 874 * @tid: Wi-Fi TID 875 * 876 * Return: void 877 */ 878 static inline void 879 hal_tx_update_int_pri2tid(hal_soc_handle_t hal_soc_hdl, 880 uint8_t pri, uint8_t tid) 881 { 882 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 883 884 hal_soc->ops->hal_tx_update_ppe_pri2tid(hal_soc_hdl, pri, tid); 885 } 886 887 /** 888 * hal_tx_dump_ppe_vp_entry - Dump the PPE VP entry 889 * @hal_soc_hdl: HAL SoC context 890 * 891 * Return: void 892 */ 893 static inline void 894 hal_tx_dump_ppe_vp_entry(hal_soc_handle_t hal_soc_hdl) 895 { 896 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 897 898 hal_soc->ops->hal_tx_dump_ppe_vp_entry(hal_soc_hdl); 899 } 900 901 /** 902 * hal_tx_enable_pri2tid_map- Enable the priority to tid mapping 903 * @hal_soc_hdl: HAL SoC context 904 * @val: True/False value 905 * 906 * Return: void 907 */ 908 static inline void 909 hal_tx_enable_pri2tid_map(hal_soc_handle_t hal_soc_hdl, bool val, 910 uint8_t ppe_vp_idx) 911 { 912 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 913 914 hal_soc->ops->hal_tx_enable_pri2tid_map(hal_soc_hdl, val, 915 ppe_vp_idx); 916 } 917 918 #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT 919 static inline void 920 hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl, 921 uint8_t vdev_id, uint8_t mcast_ctrl_val) 922 { 923 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 924 925 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set(hal_soc_hdl, vdev_id, 926 mcast_ctrl_val); 927 } 928 #else 929 static inline void 930 hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl, 931 uint8_t vdev_id, uint8_t mcast_ctrl_val) 932 { 933 } 934 #endif 935 #endif /* _HAL_BE_TX_H_ */ 936