1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_BE_TX_H_ 21 #define _HAL_BE_TX_H_ 22 23 #include "hal_be_hw_headers.h" 24 #include "hal_tx.h" 25 26 /* Number of TX banks reserved i.e, will not be used by host driver. */ 27 /* MAX_TCL_BANK reserved for FW use */ 28 #define HAL_TX_NUM_RESERVED_BANKS 1 29 30 /* 31 * Number of Priority to TID mapping 32 */ 33 #define HAL_BE_TX_MAP0_PRI2TID_MAX 10 34 #define HAL_BE_TX_MAP1_PRI2TID_MAX 6 35 36 enum hal_be_tx_ret_buf_manager { 37 HAL_BE_WBM_SW0_BM_ID = 5, 38 HAL_BE_WBM_SW1_BM_ID = 6, 39 HAL_BE_WBM_SW2_BM_ID = 7, 40 HAL_BE_WBM_SW3_BM_ID = 8, 41 HAL_BE_WBM_SW4_BM_ID = 9, 42 HAL_BE_WBM_SW5_BM_ID = 10, 43 HAL_BE_WBM_SW6_BM_ID = 11, 44 }; 45 46 enum hal_tx_mcast_ctrl { 47 /* mcast traffic exceptioned to FW 48 * valid only for AP VAP default for AP 49 */ 50 HAL_TX_MCAST_CTRL_FW_EXCEPTION = 0, 51 /* mcast traffic dropped in TCL*/ 52 HAL_TX_MCAST_CTRL_DROP, 53 /* MEC notification are enabled 54 * valid only for client VAP 55 */ 56 HAL_TX_MCAST_CTRL_MEC_NOTIFY, 57 /* no special routing for mcast 58 * valid for client vap when index search is enabled 59 */ 60 HAL_TX_MCAST_CTRL_NO_SPECIAL, 61 }; 62 63 /* enum hal_tx_notify_frame_type - TX notify frame type 64 * @NO_TX_NOTIFY: Not a notify frame 65 * @TX_HARD_NOTIFY: Hard notify TX frame 66 * @TX_SOFT_NOTIFY_E: Soft Notify Tx frame 67 * @TX_SEMI_HARD_NOTIFY_E: Semi Hard notify TX frame 68 */ 69 enum hal_tx_notify_frame_type { 70 NO_TX_NOTIFY = 0, 71 TX_HARD_NOTIFY = 1, 72 TX_SOFT_NOTIFY_E = 2, 73 TX_SEMI_HARD_NOTIFY_E = 3 74 }; 75 76 /*--------------------------------------------------------------------------- 77 * Structures 78 * --------------------------------------------------------------------------- 79 */ 80 /** 81 * struct hal_tx_bank_config - SW config bank params 82 * @epd: EPD indication flag 83 * @encap_type: encapsulation type 84 * @encrypt_type: encrypt type 85 * @src_buffer_swap: big-endia switch for packet buffer 86 * @link_meta_swap: big-endian switch for link metadata 87 * @index_lookup_enable: Enable index lookup 88 * @addrx_en: Address-X search 89 * @addry_en: Address-Y search 90 * @mesh_enable:mesh enable flag 91 * @vdev_id_check_en: vdev id check 92 * @pmac_id: mac id 93 * @mcast_pkt_ctrl: mulitcast packet control 94 * @val: value representing bank config 95 */ 96 union hal_tx_bank_config { 97 struct { 98 uint32_t epd:1, 99 encap_type:2, 100 encrypt_type:4, 101 src_buffer_swap:1, 102 link_meta_swap:1, 103 index_lookup_enable:1, 104 addrx_en:1, 105 addry_en:1, 106 mesh_enable:2, 107 vdev_id_check_en:1, 108 pmac_id:2, 109 mcast_pkt_ctrl:2, 110 dscp_tid_map_id:6, 111 reserved:7; 112 }; 113 uint32_t val; 114 }; 115 116 /** 117 * struct hal_tx_cmn_config_ppe - SW config exception related parameters 118 * @drop_prec_err - Exception drop_prec errors. 119 * @fake_mac_hdr - Exception fake mac header. 120 * @cpu_code_inv - Exception cpu code invalid. 121 * @data_buff_err - Exception buffer length/offset erorors. 122 * @l3_l4_err - Exception m3_l4 checksum errors 123 * @data_offset_max - Maximum data offset allowed. 124 * @data_len_max - Maximum data length allowed. 125 */ 126 union hal_tx_cmn_config_ppe { 127 struct { 128 uint32_t drop_prec_err:1, 129 fake_mac_hdr:1, 130 cpu_code_inv:1, 131 data_buff_err:1, 132 l3_l4_err:1, 133 data_offset_max:12, 134 data_len_max:14; 135 }; 136 uint32_t val; 137 }; 138 139 /** 140 * hal_tx_ppe_vp_config - SW config PPE VP table 141 * @vp_num - Virtual port number 142 * @pmac_id - Lmac ID 143 * @bank_id: Bank ID corresponding to this I/F. 144 * @vdev_id: VDEV ID of the I/F. 145 * @search_idx_reg_num: Register number of this SI. 146 * @use_ppe_int_pri: Use the PPE INT_PRI to TID table 147 * @to_fw: Use FW 148 * @drop_prec_enable: Enable precedence drop. 149 */ 150 union hal_tx_ppe_vp_config { 151 struct { 152 uint32_t vp_num:8, 153 pmac_id:2, 154 bank_id:6, 155 vdev_id:8, 156 search_idx_reg_num:3, 157 use_ppe_int_pri:1, 158 to_fw:1, 159 drop_prec_enable:1; 160 }; 161 uint32_t val; 162 }; 163 164 /** 165 * hal_tx_cmn_ppe_idx_map_config: Use ppe index mapping table 166 * @search_idx: Search index 167 * @cache_set: Cache set number 168 */ 169 union hal_tx_ppe_idx_map_config { 170 struct { 171 uint32_t search_idx:20, 172 cache_set:4; 173 }; 174 uint32_t val; 175 }; 176 177 /** 178 * hal_tx_ppe_pri2tid_map0_config : Configure ppe INT_PRI to tid map 179 * @int_pri0: INT_PRI_0 180 * @int_pri1: INT_PRI_1 181 * @int_pri2: INT_PRI_2 182 * @int_pri3: INT_PRI_3 183 * @int_pri4: INT_PRI_4 184 * @int_pri5: INT_PRI_5 185 * @int_pri6: INT_PRI_6 186 * @int_pri7: INT_PRI_7 187 * @int_pri8: INT_PRI_8 188 * @int_pri9: INT_PRI_9 189 */ 190 union hal_tx_ppe_pri2tid_map0_config { 191 struct { 192 uint32_t int_pri0:3, 193 int_pri1:3, 194 int_pri2:3, 195 int_pri3:3, 196 int_pri4:3, 197 int_pri5:3, 198 int_pri6:3, 199 int_pri7:3, 200 int_pri8:3, 201 int_pri9:3; 202 }; 203 uint32_t val; 204 }; 205 206 /** 207 * hal_tx_ppe_pri2tid_map1_config : Configure ppe INT_PRI to tid map 208 * @int_pri0: INT_PRI_10 209 * @int_pri1: INT_PRI_11 210 * @int_pri2: INT_PRI_12 211 * @int_pri3: INT_PRI_13 212 * @int_pri4: INT_PRI_14 213 * @int_pri5: INT_PRI_15 214 */ 215 union hal_tx_ppe_pri2tid_map1_config { 216 struct { 217 uint32_t int_pri10:3, 218 int_pri11:3, 219 int_pri12:3, 220 int_pri13:3, 221 int_pri14:3, 222 int_pri15:3; 223 }; 224 uint32_t val; 225 }; 226 227 /*--------------------------------------------------------------------------- 228 * Function declarations and documentation 229 * --------------------------------------------------------------------------- 230 */ 231 232 /*--------------------------------------------------------------------------- 233 * TCL Descriptor accessor APIs 234 *--------------------------------------------------------------------------- 235 */ 236 237 /** 238 * hal_tx_desc_set_tx_notify_frame - Set TX notify_frame field in Tx desc 239 * @desc: Handle to Tx Descriptor 240 * @val: Value to be set 241 * 242 * Return: None 243 */ 244 static inline void hal_tx_desc_set_tx_notify_frame(void *desc, 245 uint8_t val) 246 { 247 HAL_SET_FLD(desc, TCL_DATA_CMD, TX_NOTIFY_FRAME) |= 248 HAL_TX_SM(TCL_DATA_CMD, TX_NOTIFY_FRAME, val); 249 } 250 251 /** 252 * hal_tx_desc_set_flow_override_enable - Set flow_override_enable field 253 * @desc: Handle to Tx Descriptor 254 * @val: Value to be set 255 * 256 * Return: None 257 */ 258 static inline void hal_tx_desc_set_flow_override_enable(void *desc, 259 uint8_t val) 260 { 261 HAL_SET_FLD(desc, TCL_DATA_CMD, FLOW_OVERRIDE_ENABLE) |= 262 HAL_TX_SM(TCL_DATA_CMD, FLOW_OVERRIDE_ENABLE, val); 263 } 264 265 /** 266 * hal_tx_desc_set_flow_override - Set flow_override field in TX desc 267 * @desc: Handle to Tx Descriptor 268 * @val: Value to be set 269 * 270 * Return: None 271 */ 272 static inline void hal_tx_desc_set_flow_override(void *desc, 273 uint8_t val) 274 { 275 HAL_SET_FLD(desc, TCL_DATA_CMD, FLOW_OVERRIDE) |= 276 HAL_TX_SM(TCL_DATA_CMD, FLOW_OVERRIDE, val); 277 } 278 279 /** 280 * hal_tx_desc_set_who_classify_info_sel - Set who_classify_info_sel field 281 * @desc: Handle to Tx Descriptor 282 * @val: Value to be set 283 * 284 * Return: None 285 */ 286 static inline void hal_tx_desc_set_who_classify_info_sel(void *desc, 287 uint8_t val) 288 { 289 HAL_SET_FLD(desc, TCL_DATA_CMD, WHO_CLASSIFY_INFO_SEL) |= 290 HAL_TX_SM(TCL_DATA_CMD, WHO_CLASSIFY_INFO_SEL, val); 291 } 292 293 /** 294 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 295 * @desc: Handle to Tx Descriptor 296 * @data_length: MSDU length in case of direct descriptor. 297 * Length of link extension descriptor in case of Link extension 298 * descriptor.Includes the length of Metadata 299 * Return: None 300 */ 301 static inline void hal_tx_desc_set_buf_length(void *desc, 302 uint16_t data_length) 303 { 304 HAL_SET_FLD(desc, TCL_DATA_CMD, DATA_LENGTH) |= 305 HAL_TX_SM(TCL_DATA_CMD, DATA_LENGTH, data_length); 306 } 307 308 /** 309 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 310 * @desc: Handle to Tx Descriptor 311 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 312 * 313 * Return: void 314 */ 315 static inline void hal_tx_desc_set_buf_offset(void *desc, 316 uint8_t offset) 317 { 318 HAL_SET_FLD(desc, TCL_DATA_CMD, PACKET_OFFSET) |= 319 HAL_TX_SM(TCL_DATA_CMD, PACKET_OFFSET, offset); 320 } 321 322 /** 323 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 324 * Tx Descriptor for MSDU_buffer type 325 * @desc: Handle to Tx Descriptor 326 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 327 * 328 * Return: void 329 */ 330 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 331 uint8_t en) 332 { 333 HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |= 334 (HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV4_CHECKSUM_EN, en) | 335 HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV6_CHECKSUM_EN, en) | 336 HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV4_CHECKSUM_EN, en) | 337 HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV6_CHECKSUM_EN, en)); 338 } 339 340 /** 341 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 342 * Tx Descriptor for MSDU_buffer type 343 * @desc: Handle to Tx Descriptor 344 * @checksum_en_flags: ipv4 checksum enable flags 345 * 346 * Return: void 347 */ 348 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 349 uint8_t en) 350 { 351 HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |= 352 HAL_TX_SM(TCL_DATA_CMD, IPV4_CHECKSUM_EN, en); 353 } 354 355 /** 356 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 357 * @desc:Handle to Tx Descriptor 358 * @metadata: Metadata to be sent to Firmware 359 * 360 * Return: void 361 */ 362 static inline void hal_tx_desc_set_fw_metadata(void *desc, 363 uint16_t metadata) 364 { 365 HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_NUMBER) |= 366 HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_NUMBER, metadata); 367 } 368 369 /** 370 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 371 * @desc:Handle to Tx Descriptor 372 * @to_fw: if set, Forward packet to FW along with classification result 373 * 374 * Return: void 375 */ 376 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 377 { 378 HAL_SET_FLD(desc, TCL_DATA_CMD, TO_FW) |= 379 HAL_TX_SM(TCL_DATA_CMD, TO_FW, to_fw); 380 } 381 382 /** 383 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 384 * frame) to be used for Tx Frame 385 * @desc: Handle to Tx Descriptor 386 * @hlos_tid: HLOS TID 387 * 388 * Return: void 389 */ 390 static inline void hal_tx_desc_set_hlos_tid(void *desc, 391 uint8_t hlos_tid) 392 { 393 HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID) |= 394 HAL_TX_SM(TCL_DATA_CMD, HLOS_TID, hlos_tid); 395 396 HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID_OVERWRITE) |= 397 HAL_TX_SM(TCL_DATA_CMD, HLOS_TID_OVERWRITE, 1); 398 } 399 400 /** 401 * hal_tx_desc_sync - Commit the descriptor to Hardware 402 * @hal_tx_des_cached: Cached descriptor that software maintains 403 * @hw_desc: Hardware descriptor to be updated 404 */ 405 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 406 void *hw_desc, uint8_t num_bytes) 407 { 408 qdf_mem_copy(hw_desc, hal_tx_desc_cached, num_bytes); 409 } 410 411 /** 412 * hal_tx_desc_set_vdev_id - set vdev id to the descriptor to Hardware 413 * @hal_tx_des_cached: Cached descriptor that software maintains 414 * @vdev_id: vdev id 415 */ 416 static inline void hal_tx_desc_set_vdev_id(void *desc, uint8_t vdev_id) 417 { 418 HAL_SET_FLD(desc, TCL_DATA_CMD, VDEV_ID) |= 419 HAL_TX_SM(TCL_DATA_CMD, VDEV_ID, vdev_id); 420 } 421 422 /** 423 * hal_tx_desc_set_bank_id - set bank id to the descriptor to Hardware 424 * @hal_tx_des_cached: Cached descriptor that software maintains 425 * @bank_id: bank id 426 */ 427 static inline void hal_tx_desc_set_bank_id(void *desc, uint8_t bank_id) 428 { 429 HAL_SET_FLD(desc, TCL_DATA_CMD, BANK_ID) |= 430 HAL_TX_SM(TCL_DATA_CMD, BANK_ID, bank_id); 431 } 432 433 /** 434 * hal_tx_desc_set_tcl_cmd_type - set tcl command type to the descriptor 435 * to Hardware 436 * @hal_tx_des_cached: Cached descriptor that software maintains 437 * @tcl_cmd_type: tcl command type 438 */ 439 static inline void 440 hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type) 441 { 442 HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_TYPE) |= 443 HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_TYPE, tcl_cmd_type); 444 } 445 446 /** 447 * hal_tx_desc_set_lmac_id_be - set lmac id to the descriptor to Hardware 448 * @hal_soc_hdl: hal soc handle 449 * @hal_tx_des_cached: Cached descriptor that software maintains 450 * @lmac_id: lmac id 451 */ 452 static inline void 453 hal_tx_desc_set_lmac_id_be(hal_soc_handle_t hal_soc_hdl, void *desc, 454 uint8_t lmac_id) 455 { 456 HAL_SET_FLD(desc, TCL_DATA_CMD, PMAC_ID) |= 457 HAL_TX_SM(TCL_DATA_CMD, PMAC_ID, lmac_id); 458 } 459 460 /** 461 * hal_tx_desc_set_search_index_be - set search index to the 462 * descriptor to Hardware 463 * @hal_soc_hdl: hal soc handle 464 * @hal_tx_des_cached: Cached descriptor that software maintains 465 * @search_index: search index 466 */ 467 static inline void 468 hal_tx_desc_set_search_index_be(hal_soc_handle_t hal_soc_hdl, void *desc, 469 uint32_t search_index) 470 { 471 HAL_SET_FLD(desc, TCL_DATA_CMD, SEARCH_INDEX) |= 472 HAL_TX_SM(TCL_DATA_CMD, SEARCH_INDEX, search_index); 473 } 474 475 /** 476 * hal_tx_desc_set_cache_set_num - set cache set num to the 477 * descriptor to Hardware 478 * @hal_soc_hdl: hal soc handle 479 * @hal_tx_des_cached: Cached descriptor that software maintains 480 * @cache_num: cache number 481 */ 482 static inline void 483 hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, void *desc, 484 uint8_t cache_num) 485 { 486 HAL_SET_FLD(desc, TCL_DATA_CMD, CACHE_SET_NUM) |= 487 HAL_TX_SM(TCL_DATA_CMD, CACHE_SET_NUM, cache_num); 488 } 489 490 /** 491 * hal_tx_desc_set_lookup_override_num - set lookup override num 492 * to the descriptor to Hardware 493 * @hal_soc_hdl: hal soc handle 494 * @hal_tx_des_cached: Cached descriptor that software maintains 495 * @cache_num: set numbernumber 496 */ 497 static inline void 498 hal_tx_desc_set_index_lookup_override(hal_soc_handle_t hal_soc_hdl, 499 void *desc, uint8_t num) 500 { 501 HAL_SET_FLD(desc, TCL_DATA_CMD, INDEX_LOOKUP_OVERRIDE) |= 502 HAL_TX_SM(TCL_DATA_CMD, INDEX_LOOKUP_OVERRIDE, num); 503 } 504 505 /*--------------------------------------------------------------------------- 506 * WBM Descriptor accessor APIs for Tx completions 507 * --------------------------------------------------------------------------- 508 */ 509 510 /** 511 * hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring 512 * 513 * Return: BM ID for first tx completion ring 514 */ 515 static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void) 516 { 517 return HAL_BE_WBM_SW0_BM_ID; 518 } 519 520 /** 521 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 522 * @hal_desc: completion ring descriptor pointer 523 * 524 * This function will tx descriptor id, cookie, within hardware completion 525 * descriptor. For cases when cookie conversion is disabled, the sw_cookie 526 * is present in the 2nd DWORD. 527 * 528 * Return: cookie 529 */ 530 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 531 { 532 uint32_t comp_desc = 533 *(uint32_t *)(((uint8_t *)hal_desc) + 534 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET); 535 536 /* Cookie is placed on 2nd word */ 537 return (comp_desc & BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK) >> 538 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB; 539 } 540 541 /** 542 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 543 * @hal_desc: completion ring descriptor pointer 544 * 545 * This function will get buffer physical address within hardware completion 546 * descriptor 547 * 548 * Return: Buffer physical address 549 */ 550 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 551 { 552 uint32_t paddr_lo; 553 uint32_t paddr_hi; 554 555 paddr_lo = *(uint32_t *)(((uint8_t *)hal_desc) + 556 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET); 557 558 paddr_hi = *(uint32_t *)(((uint8_t *)hal_desc) + 559 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET); 560 561 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) >> 562 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB; 563 564 return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32)); 565 } 566 567 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 568 /* HW set dowrd-2 bit30 to 1 if HW CC is done */ 569 #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_OFFSET 0x8 570 #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_MASK 0x40000000 571 #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_LSB 0x1E 572 /** 573 * hal_tx_comp_get_cookie_convert_done() - Get cookie conversion done flag 574 * @hal_desc: completion ring descriptor pointer 575 * 576 * This function will get the bit value that indicate HW cookie 577 * conversion done or not 578 * 579 * Return: 1 - HW cookie conversion done, 0 - not 580 */ 581 static inline uint8_t hal_tx_comp_get_cookie_convert_done(void *hal_desc) 582 { 583 return HAL_TX_DESC_GET(hal_desc, HAL_WBM2SW_COMPLETION_RING_TX, 584 CC_DONE); 585 } 586 #endif 587 588 /** 589 * hal_tx_comp_set_desc_va_63_32() - Set bit 32~63 value for 64 bit VA 590 * @hal_desc: completion ring descriptor pointer 591 * @val: value to be set 592 * 593 * Return: None 594 */ 595 static inline void hal_tx_comp_set_desc_va_63_32(void *hal_desc, uint32_t val) 596 { 597 HAL_SET_FLD(hal_desc, 598 WBM2SW_COMPLETION_RING_TX, 599 BUFFER_VIRT_ADDR_63_32) = val; 600 } 601 602 /** 603 * hal_tx_comp_get_desc_va() - Get Desc virtual address within completion Desc 604 * @hal_desc: completion ring descriptor pointer 605 * 606 * This function will get the TX Desc virtual address 607 * 608 * Return: TX desc virtual address 609 */ 610 static inline uint64_t hal_tx_comp_get_desc_va(void *hal_desc) 611 { 612 uint64_t va_from_desc; 613 614 va_from_desc = HAL_TX_DESC_GET(hal_desc, 615 WBM2SW_COMPLETION_RING_TX, 616 BUFFER_VIRT_ADDR_31_0) | 617 (((uint64_t)HAL_TX_DESC_GET( 618 hal_desc, 619 WBM2SW_COMPLETION_RING_TX, 620 BUFFER_VIRT_ADDR_63_32)) << 32); 621 622 return va_from_desc; 623 } 624 625 /*--------------------------------------------------------------------------- 626 * TX BANK register accessor APIs 627 * --------------------------------------------------------------------------- 628 */ 629 630 /** 631 * hal_tx_get_num_tcl_banks() - Get number of banks for target 632 * 633 * Return: None 634 */ 635 static inline uint8_t 636 hal_tx_get_num_tcl_banks(hal_soc_handle_t hal_soc_hdl) 637 { 638 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 639 int hal_banks = 0; 640 641 if (hal_soc->ops->hal_tx_get_num_tcl_banks) { 642 hal_banks = hal_soc->ops->hal_tx_get_num_tcl_banks(); 643 hal_banks -= HAL_TX_NUM_RESERVED_BANKS; 644 hal_banks = (hal_banks < 0) ? 0 : hal_banks; 645 } 646 647 return hal_banks; 648 } 649 650 /** 651 * hal_tx_populate_bank_register() - populate the bank register with 652 * the software configs. 653 * @soc: HAL soc handle 654 * @config: bank config 655 * @bank_id: bank id to be configured 656 * 657 * Returns: None 658 */ 659 static inline void 660 hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl, 661 union hal_tx_bank_config *config, 662 uint8_t bank_id) 663 { 664 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 665 666 hal_soc->ops->hal_tx_populate_bank_register(hal_soc_hdl, config, 667 bank_id); 668 } 669 670 #ifdef DP_TX_IMPLICIT_RBM_MAPPING 671 672 #define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK 673 #define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT 674 675 #define RBM_PPE2TCL_OFFSET \ 676 (HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2) 677 #define RBM_TCL_CMD_CREDIT_OFFSET \ 678 (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2) 679 680 /** 681 * hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id 682 * @hal_soc: HAL SoC context 683 * @hal_ring_hdl: Source ring pointer 684 * @rbm_id: return buffer manager ring id 685 * 686 * Return: void 687 */ 688 static inline void 689 hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl, 690 hal_ring_handle_t hal_ring_hdl, 691 uint8_t rbm_id) 692 { 693 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 694 695 hal_soc->ops->hal_tx_config_rbm_mapping_be(hal_soc_hdl, hal_ring_hdl, 696 rbm_id); 697 } 698 #else 699 static inline void 700 hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl, 701 hal_ring_handle_t hal_ring_hdl, 702 uint8_t rbm_id) 703 { 704 } 705 #endif 706 707 /** 708 * hal_tx_desc_set_buf_addr_be - Fill Buffer Address information in Tx Desc 709 * @desc: Handle to Tx Descriptor 710 * @paddr: Physical Address 711 * @pool_id: Return Buffer Manager ID 712 * @desc_id: Descriptor ID 713 * @type: 0 - Address points to a MSDU buffer 714 * 1 - Address points to MSDU extension descriptor 715 * 716 * Return: void 717 */ 718 #ifdef DP_TX_IMPLICIT_RBM_MAPPING 719 static inline void 720 hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc, 721 dma_addr_t paddr, uint8_t rbm_id, 722 uint32_t desc_id, uint8_t type) 723 { 724 /* Set buffer_addr_info.buffer_addr_31_0 */ 725 HAL_SET_FLD(desc, TCL_DATA_CMD, 726 BUF_ADDR_INFO_BUFFER_ADDR_31_0) = 727 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr); 728 729 /* Set buffer_addr_info.buffer_addr_39_32 */ 730 HAL_SET_FLD(desc, TCL_DATA_CMD, 731 BUF_ADDR_INFO_BUFFER_ADDR_39_32) |= 732 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32, 733 (((uint64_t)paddr) >> 32)); 734 735 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 736 HAL_SET_FLD(desc, TCL_DATA_CMD, 737 BUF_ADDR_INFO_SW_BUFFER_COOKIE) |= 738 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE, 739 desc_id); 740 741 /* Set Buffer or Ext Descriptor Type */ 742 HAL_SET_FLD(desc, TCL_DATA_CMD, 743 BUF_OR_EXT_DESC_TYPE) |= 744 HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type); 745 } 746 #else 747 static inline void 748 hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc, 749 dma_addr_t paddr, uint8_t rbm_id, 750 uint32_t desc_id, uint8_t type) 751 { 752 /* Set buffer_addr_info.buffer_addr_31_0 */ 753 HAL_SET_FLD(desc, TCL_DATA_CMD, 754 BUF_ADDR_INFO_BUFFER_ADDR_31_0) = 755 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr); 756 757 /* Set buffer_addr_info.buffer_addr_39_32 */ 758 HAL_SET_FLD(desc, TCL_DATA_CMD, 759 BUF_ADDR_INFO_BUFFER_ADDR_39_32) |= 760 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32, 761 (((uint64_t)paddr) >> 32)); 762 763 /* Set buffer_addr_info.return_buffer_manager = rbm id */ 764 HAL_SET_FLD(desc, TCL_DATA_CMD, 765 BUF_ADDR_INFO_RETURN_BUFFER_MANAGER) |= 766 HAL_TX_SM(TCL_DATA_CMD, 767 BUF_ADDR_INFO_RETURN_BUFFER_MANAGER, rbm_id); 768 769 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 770 HAL_SET_FLD(desc, TCL_DATA_CMD, 771 BUF_ADDR_INFO_SW_BUFFER_COOKIE) |= 772 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE, 773 desc_id); 774 775 /* Set Buffer or Ext Descriptor Type */ 776 HAL_SET_FLD(desc, TCL_DATA_CMD, 777 BUF_OR_EXT_DESC_TYPE) |= 778 HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type); 779 } 780 #endif 781 782 /** 783 * hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing 784 * @hal_soc: HAL SoC context 785 * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM 786 * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW 787 * 788 * Return: void 789 */ 790 #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK 791 static inline void 792 hal_tx_vdev_mismatch_routing_set(hal_soc_handle_t hal_soc_hdl, 793 enum hal_tx_vdev_mismatch_notify config) 794 { 795 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 796 797 hal_soc->ops->hal_tx_vdev_mismatch_routing_set(hal_soc_hdl, config); 798 } 799 #else 800 static inline void 801 hal_tx_vdev_mismatch_routing_set(hal_soc_handle_t hal_soc_hdl, 802 enum hal_tx_vdev_mismatch_notify config) 803 { 804 } 805 #endif 806 807 /** 808 * hal_tx_mcast_mlo_reinject_routing_set - set MLO multicast reinject routing 809 * @hal_soc: HAL SoC context 810 * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW 811 * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM 812 * 813 * Return: void 814 */ 815 #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \ 816 defined(WLAN_MCAST_MLO) 817 static inline void 818 hal_tx_mcast_mlo_reinject_routing_set( 819 hal_soc_handle_t hal_soc_hdl, 820 enum hal_tx_mcast_mlo_reinject_notify config) 821 { 822 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 823 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set(hal_soc_hdl, 824 config); 825 } 826 #else 827 static inline void 828 hal_tx_mcast_mlo_reinject_routing_set( 829 hal_soc_handle_t hal_soc_hdl, 830 enum hal_tx_mcast_mlo_reinject_notify config) 831 { 832 } 833 #endif 834 835 /* 836 * hal_reo_config_reo2ppe_dest_info() - Configure reo2ppe dest info 837 * @hal_soc_hdl: HAL SoC Context 838 * 839 * Return: None. 840 */ 841 static inline 842 void hal_reo_config_reo2ppe_dest_info(hal_soc_handle_t hal_soc_hdl) 843 { 844 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 845 846 if (hal_soc->ops->hal_reo_config_reo2ppe_dest_info) 847 hal_soc->ops->hal_reo_config_reo2ppe_dest_info(hal_soc_hdl); 848 } 849 850 /* 851 * hal_tx_get_num_ppe_vp_tbl_entries() - Get the total number of VP table 852 * @hal_soc: HAL SoC Context 853 * 854 * Return: Total number of entries. 855 */ 856 static inline 857 uint32_t hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_handle_t hal_soc_hdl) 858 { 859 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 860 861 return hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_hdl); 862 } 863 864 /** 865 * hal_tx_set_ppe_cmn_cfg()- Set the PPE common config 866 * @hal_soc: HAL SoC context 867 * @cmn_cfg: HAL PPE VP common config 868 * 869 * Return: void 870 */ 871 static inline void 872 hal_tx_set_ppe_cmn_cfg(hal_soc_handle_t hal_soc_hdl, 873 union hal_tx_cmn_config_ppe *cmn_cfg) 874 { 875 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 876 877 hal_soc->ops->hal_tx_set_ppe_cmn_cfg(hal_soc_hdl, cmn_cfg); 878 } 879 880 /** 881 * hal_tx_populate_ppe_vp_entry - Populate ppe VP entry 882 * @hal_soc: HAL SoC context 883 * @vp_cfg: HAL PPE VP config 884 * @ppe_vp_idx: PPE VP index 885 * 886 * Return: void 887 */ 888 static inline void 889 hal_tx_populate_ppe_vp_entry(hal_soc_handle_t hal_soc_hdl, 890 union hal_tx_ppe_vp_config *vp_cfg, 891 int ppe_vp_idx) 892 { 893 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 894 895 hal_soc->ops->hal_tx_set_ppe_vp_entry(hal_soc_hdl, vp_cfg, ppe_vp_idx); 896 } 897 898 /** 899 * hal_ppeds_cfg_ast_override_map_reg - Set ppe index mapping table value 900 * @hal_soc: HAL SoC context 901 * @reg_idx: index into the table 902 * @ppeds_astoveride_map: HAL PPE INDEX MAPPING config 903 * 904 * Return: void 905 */ 906 static inline void 907 hal_ppeds_cfg_ast_override_map_reg(hal_soc_handle_t hal_soc_hdl, 908 uint8_t reg_idx, union hal_tx_ppe_idx_map_config *ppeds_astoveride_map) 909 { 910 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 911 912 hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg(hal_soc_hdl, reg_idx, 913 ppeds_astoveride_map); 914 } 915 916 /** 917 * hal_tx_set_int_pri2id - Set the prit2tid table. 918 * @hal_soc: HAL SoC context 919 * @pri2tid: Reference to SW INT_PRI to TID table 920 * 921 * Return: void 922 */ 923 static inline void 924 hal_tx_set_int_pri2tid(hal_soc_handle_t hal_soc_hdl, 925 uint32_t val, uint8_t map_no) 926 { 927 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 928 929 hal_soc->ops->hal_tx_set_ppe_pri2tid(hal_soc_hdl, val, map_no); 930 } 931 932 /** 933 * hal_tx_update_int_pri2id - Populate the prit2tid table. 934 * @hal_soc: HAL SoC context 935 * @pri: INT_PRI value 936 * @tid: Wi-Fi TID 937 * 938 * Return: void 939 */ 940 static inline void 941 hal_tx_update_int_pri2tid(hal_soc_handle_t hal_soc_hdl, 942 uint8_t pri, uint8_t tid) 943 { 944 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 945 946 hal_soc->ops->hal_tx_update_ppe_pri2tid(hal_soc_hdl, pri, tid); 947 } 948 949 /** 950 * hal_tx_dump_ppe_vp_entry - Dump the PPE VP entry 951 * @hal_soc_hdl: HAL SoC context 952 * 953 * Return: void 954 */ 955 static inline void 956 hal_tx_dump_ppe_vp_entry(hal_soc_handle_t hal_soc_hdl) 957 { 958 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 959 960 hal_soc->ops->hal_tx_dump_ppe_vp_entry(hal_soc_hdl); 961 } 962 963 /** 964 * hal_tx_enable_pri2tid_map- Enable the priority to tid mapping 965 * @hal_soc_hdl: HAL SoC context 966 * @val: True/False value 967 * 968 * Return: void 969 */ 970 static inline void 971 hal_tx_enable_pri2tid_map(hal_soc_handle_t hal_soc_hdl, bool val, 972 uint8_t ppe_vp_idx) 973 { 974 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 975 976 hal_soc->ops->hal_tx_enable_pri2tid_map(hal_soc_hdl, val, 977 ppe_vp_idx); 978 } 979 980 #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT 981 static inline void 982 hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl, 983 uint8_t vdev_id, uint8_t mcast_ctrl_val) 984 { 985 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 986 987 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set(hal_soc_hdl, vdev_id, 988 mcast_ctrl_val); 989 } 990 #else 991 static inline void 992 hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl, 993 uint8_t vdev_id, uint8_t mcast_ctrl_val) 994 { 995 } 996 #endif 997 #endif /* _HAL_BE_TX_H_ */ 998