1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_BE_TX_H_ 20 #define _HAL_BE_TX_H_ 21 22 #include "hal_be_hw_headers.h" 23 #include "hal_tx.h" 24 25 /* Number of TX banks reserved i.e, will not be used by host driver. */ 26 /* MAX_TCL_BANK reserved for FW use */ 27 #define HAL_TX_NUM_RESERVED_BANKS 1 28 29 enum hal_be_tx_ret_buf_manager { 30 HAL_BE_WBM_SW0_BM_ID = 5, 31 HAL_BE_WBM_SW1_BM_ID = 6, 32 HAL_BE_WBM_SW2_BM_ID = 7, 33 HAL_BE_WBM_SW3_BM_ID = 8, 34 HAL_BE_WBM_SW4_BM_ID = 9, 35 HAL_BE_WBM_SW5_BM_ID = 10, 36 HAL_BE_WBM_SW6_BM_ID = 11, 37 }; 38 39 enum hal_tx_mcast_ctrl { 40 /* mcast traffic exceptioned to FW 41 * valid only for AP VAP default for AP 42 */ 43 HAL_TX_MCAST_CTRL_FW_EXCEPTION = 0, 44 /* mcast traffic dropped in TCL*/ 45 HAL_TX_MCAST_CTRL_DROP, 46 /* MEC notification are enabled 47 * valid only for client VAP 48 */ 49 HAL_TX_MCAST_CTRL_MEC_NOTIFY, 50 /* no special routing for mcast 51 * valid for client vap when index search is enabled 52 */ 53 HAL_TX_MCAST_CTRL_NO_SPECIAL, 54 }; 55 56 /*--------------------------------------------------------------------------- 57 * Structures 58 * --------------------------------------------------------------------------- 59 */ 60 /** 61 * struct hal_tx_bank_config - SW config bank params 62 * @epd: EPD indication flag 63 * @encap_type: encapsulation type 64 * @encrypt_type: encrypt type 65 * @src_buffer_swap: big-endia switch for packet buffer 66 * @link_meta_swap: big-endian switch for link metadata 67 * @index_lookup_enable: Enabel index lookup 68 * @addrx_en: Address-X search 69 * @addry_en: Address-Y search 70 * @mesh_enable:mesh enable flag 71 * @vdev_id_check_en: vdev id check 72 * @pmac_id: mac id 73 * @mcast_pkt_ctrl: mulitcast packet control 74 * @val: value representing bank config 75 */ 76 union hal_tx_bank_config { 77 struct { 78 uint32_t epd:1, 79 encap_type:2, 80 encrypt_type:4, 81 src_buffer_swap:1, 82 link_meta_swap:1, 83 index_lookup_enable:1, 84 addrx_en:1, 85 addry_en:1, 86 mesh_enable:2, 87 vdev_id_check_en:1, 88 pmac_id:2, 89 mcast_pkt_ctrl:2, 90 dscp_tid_map_id:6, 91 reserved:7; 92 }; 93 uint32_t val; 94 }; 95 96 /*--------------------------------------------------------------------------- 97 * Function declarations and documentation 98 * --------------------------------------------------------------------------- 99 */ 100 101 /*--------------------------------------------------------------------------- 102 * TCL Descriptor accessor APIs 103 *--------------------------------------------------------------------------- 104 */ 105 106 /** 107 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 108 * @desc: Handle to Tx Descriptor 109 * @data_length: MSDU length in case of direct descriptor. 110 * Length of link extension descriptor in case of Link extension 111 * descriptor.Includes the length of Metadata 112 * Return: None 113 */ 114 static inline void hal_tx_desc_set_buf_length(void *desc, 115 uint16_t data_length) 116 { 117 HAL_SET_FLD(desc, TCL_DATA_CMD, DATA_LENGTH) |= 118 HAL_TX_SM(TCL_DATA_CMD, DATA_LENGTH, data_length); 119 } 120 121 /** 122 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 123 * @desc: Handle to Tx Descriptor 124 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 125 * 126 * Return: void 127 */ 128 static inline void hal_tx_desc_set_buf_offset(void *desc, 129 uint8_t offset) 130 { 131 HAL_SET_FLD(desc, TCL_DATA_CMD, PACKET_OFFSET) |= 132 HAL_TX_SM(TCL_DATA_CMD, PACKET_OFFSET, offset); 133 } 134 135 /** 136 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 137 * Tx Descriptor for MSDU_buffer type 138 * @desc: Handle to Tx Descriptor 139 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 140 * 141 * Return: void 142 */ 143 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 144 uint8_t en) 145 { 146 HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |= 147 (HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV4_CHECKSUM_EN, en) | 148 HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV6_CHECKSUM_EN, en) | 149 HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV4_CHECKSUM_EN, en) | 150 HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV6_CHECKSUM_EN, en)); 151 } 152 153 /** 154 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 155 * Tx Descriptor for MSDU_buffer type 156 * @desc: Handle to Tx Descriptor 157 * @checksum_en_flags: ipv4 checksum enable flags 158 * 159 * Return: void 160 */ 161 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 162 uint8_t en) 163 { 164 HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |= 165 HAL_TX_SM(TCL_DATA_CMD, IPV4_CHECKSUM_EN, en); 166 } 167 168 /** 169 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 170 * @desc:Handle to Tx Descriptor 171 * @metadata: Metadata to be sent to Firmware 172 * 173 * Return: void 174 */ 175 static inline void hal_tx_desc_set_fw_metadata(void *desc, 176 uint16_t metadata) 177 { 178 HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_NUMBER) |= 179 HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_NUMBER, metadata); 180 } 181 182 /** 183 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 184 * @desc:Handle to Tx Descriptor 185 * @to_fw: if set, Forward packet to FW along with classification result 186 * 187 * Return: void 188 */ 189 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 190 { 191 HAL_SET_FLD(desc, TCL_DATA_CMD, TO_FW) |= 192 HAL_TX_SM(TCL_DATA_CMD, TO_FW, to_fw); 193 } 194 195 /** 196 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 197 * frame) to be used for Tx Frame 198 * @desc: Handle to Tx Descriptor 199 * @hlos_tid: HLOS TID 200 * 201 * Return: void 202 */ 203 static inline void hal_tx_desc_set_hlos_tid(void *desc, 204 uint8_t hlos_tid) 205 { 206 HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID) |= 207 HAL_TX_SM(TCL_DATA_CMD, HLOS_TID, hlos_tid); 208 209 HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID_OVERWRITE) |= 210 HAL_TX_SM(TCL_DATA_CMD, HLOS_TID_OVERWRITE, 1); 211 } 212 213 /** 214 * hal_tx_desc_sync - Commit the descriptor to Hardware 215 * @hal_tx_des_cached: Cached descriptor that software maintains 216 * @hw_desc: Hardware descriptor to be updated 217 */ 218 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 219 void *hw_desc) 220 { 221 qdf_mem_copy(hw_desc, hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES); 222 } 223 224 /** 225 * hal_tx_desc_set_vdev_id - set vdev id to the descriptor to Hardware 226 * @hal_tx_des_cached: Cached descriptor that software maintains 227 * @vdev_id: vdev id 228 */ 229 static inline void hal_tx_desc_set_vdev_id(void *desc, uint8_t vdev_id) 230 { 231 HAL_SET_FLD(desc, TCL_DATA_CMD, VDEV_ID) |= 232 HAL_TX_SM(TCL_DATA_CMD, VDEV_ID, vdev_id); 233 } 234 235 /** 236 * hal_tx_desc_set_bank_id - set bank id to the descriptor to Hardware 237 * @hal_tx_des_cached: Cached descriptor that software maintains 238 * @bank_id: bank id 239 */ 240 static inline void hal_tx_desc_set_bank_id(void *desc, uint8_t bank_id) 241 { 242 HAL_SET_FLD(desc, TCL_DATA_CMD, BANK_ID) |= 243 HAL_TX_SM(TCL_DATA_CMD, BANK_ID, bank_id); 244 } 245 246 /** 247 * hal_tx_desc_set_tcl_cmd_type - set tcl command type to the descriptor 248 * to Hardware 249 * @hal_tx_des_cached: Cached descriptor that software maintains 250 * @tcl_cmd_type: tcl command type 251 */ 252 static inline void 253 hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type) 254 { 255 HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_TYPE) |= 256 HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_TYPE, tcl_cmd_type); 257 } 258 259 /** 260 * hal_tx_desc_set_lmac_id_be - set lmac id to the descriptor to Hardware 261 * @hal_soc_hdl: hal soc handle 262 * @hal_tx_des_cached: Cached descriptor that software maintains 263 * @lmac_id: lmac id 264 */ 265 static inline void 266 hal_tx_desc_set_lmac_id_be(hal_soc_handle_t hal_soc_hdl, void *desc, 267 uint8_t lmac_id) 268 { 269 HAL_SET_FLD(desc, TCL_DATA_CMD, PMAC_ID) |= 270 HAL_TX_SM(TCL_DATA_CMD, PMAC_ID, lmac_id); 271 } 272 273 /** 274 * hal_tx_desc_set_search_index_be - set search index to the 275 * descriptor to Hardware 276 * @hal_soc_hdl: hal soc handle 277 * @hal_tx_des_cached: Cached descriptor that software maintains 278 * @search_index: search index 279 */ 280 static inline void 281 hal_tx_desc_set_search_index_be(hal_soc_handle_t hal_soc_hdl, void *desc, 282 uint32_t search_index) 283 { 284 HAL_SET_FLD(desc, TCL_DATA_CMD, SEARCH_INDEX) |= 285 HAL_TX_SM(TCL_DATA_CMD, SEARCH_INDEX, search_index); 286 } 287 288 /** 289 * hal_tx_desc_set_cache_set_num - set cache set num to the 290 * descriptor to Hardware 291 * @hal_soc_hdl: hal soc handle 292 * @hal_tx_des_cached: Cached descriptor that software maintains 293 * @cache_num: cache number 294 */ 295 static inline void 296 hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, void *desc, 297 uint8_t cache_num) 298 { 299 HAL_SET_FLD(desc, TCL_DATA_CMD, CACHE_SET_NUM) |= 300 HAL_TX_SM(TCL_DATA_CMD, CACHE_SET_NUM, cache_num); 301 } 302 303 /*--------------------------------------------------------------------------- 304 * WBM Descriptor accessor APIs for Tx completions 305 * --------------------------------------------------------------------------- 306 */ 307 308 /** 309 * hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring 310 * 311 * Return: BM ID for first tx completion ring 312 */ 313 static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void) 314 { 315 return HAL_BE_WBM_SW0_BM_ID; 316 } 317 318 /** 319 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 320 * @hal_desc: completion ring descriptor pointer 321 * 322 * This function will tx descriptor id, cookie, within hardware completion 323 * descriptor. For cases when cookie conversion is disabled, the sw_cookie 324 * is present in the 2nd DWORD. 325 * 326 * Return: cookie 327 */ 328 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 329 { 330 uint32_t comp_desc = 331 *(uint32_t *)(((uint8_t *)hal_desc) + 332 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET); 333 334 /* Cookie is placed on 2nd word */ 335 return (comp_desc & BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK) >> 336 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB; 337 } 338 339 /** 340 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 341 * @hal_desc: completion ring descriptor pointer 342 * 343 * This function will get buffer physical address within hardware completion 344 * descriptor 345 * 346 * Return: Buffer physical address 347 */ 348 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 349 { 350 uint32_t paddr_lo; 351 uint32_t paddr_hi; 352 353 paddr_lo = *(uint32_t *)(((uint8_t *)hal_desc) + 354 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET); 355 356 paddr_hi = *(uint32_t *)(((uint8_t *)hal_desc) + 357 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET); 358 359 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) >> 360 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB; 361 362 return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32)); 363 } 364 365 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 366 /* HW set dowrd-2 bit30 to 1 if HW CC is done */ 367 #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_OFFSET 0x8 368 #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_MASK 0x40000000 369 #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_LSB 0x1E 370 /** 371 * hal_tx_comp_get_cookie_convert_done() - Get cookie conversion done flag 372 * @hal_desc: completion ring descriptor pointer 373 * 374 * This function will get the bit value that indicate HW cookie 375 * conversion done or not 376 * 377 * Return: 1 - HW cookie conversion done, 0 - not 378 */ 379 static inline uint8_t hal_tx_comp_get_cookie_convert_done(void *hal_desc) 380 { 381 return HAL_TX_DESC_GET(hal_desc, HAL_WBM2SW_COMPLETION_RING_TX, 382 CC_DONE); 383 } 384 #endif 385 386 /** 387 * hal_tx_comp_get_desc_va() - Get Desc virtual address within completion Desc 388 * @hal_desc: completion ring descriptor pointer 389 * 390 * This function will get the TX Desc virtual address 391 * 392 * Return: TX desc virtual address 393 */ 394 static inline uintptr_t hal_tx_comp_get_desc_va(void *hal_desc) 395 { 396 uint64_t va_from_desc; 397 398 va_from_desc = HAL_TX_DESC_GET(hal_desc, 399 WBM2SW_COMPLETION_RING_TX, 400 BUFFER_VIRT_ADDR_31_0) | 401 (((uint64_t)HAL_TX_DESC_GET( 402 hal_desc, 403 WBM2SW_COMPLETION_RING_TX, 404 BUFFER_VIRT_ADDR_63_32)) << 32); 405 406 return (uintptr_t)va_from_desc; 407 } 408 409 /*--------------------------------------------------------------------------- 410 * TX BANK register accessor APIs 411 * --------------------------------------------------------------------------- 412 */ 413 414 /** 415 * hal_tx_get_num_tcl_banks() - Get number of banks for target 416 * 417 * Return: None 418 */ 419 static inline uint8_t 420 hal_tx_get_num_tcl_banks(hal_soc_handle_t hal_soc_hdl) 421 { 422 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 423 int hal_banks = 0; 424 425 if (hal_soc->ops->hal_tx_get_num_tcl_banks) { 426 hal_banks = hal_soc->ops->hal_tx_get_num_tcl_banks(); 427 hal_banks -= HAL_TX_NUM_RESERVED_BANKS; 428 hal_banks = (hal_banks < 0) ? 0 : hal_banks; 429 } 430 431 return hal_banks; 432 } 433 434 /** 435 * hal_tx_populate_bank_register() - populate the bank register with 436 * the software configs. 437 * @soc: HAL soc handle 438 * @config: bank config 439 * @bank_id: bank id to be configured 440 * 441 * Returns: None 442 */ 443 #ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT 444 static inline void 445 hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl, 446 union hal_tx_bank_config *config, 447 uint8_t bank_id) 448 { 449 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 450 uint32_t reg_addr, reg_val = 0; 451 452 reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE, 453 bank_id); 454 455 reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT); 456 reg_val |= (config->encap_type << 457 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT); 458 reg_val |= (config->encrypt_type << 459 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT); 460 reg_val |= (config->src_buffer_swap << 461 HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT); 462 reg_val |= (config->link_meta_swap << 463 HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT); 464 reg_val |= (config->index_lookup_enable << 465 HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT); 466 reg_val |= (config->addrx_en << 467 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT); 468 reg_val |= (config->addry_en << 469 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT); 470 reg_val |= (config->mesh_enable << 471 HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT); 472 reg_val |= (config->vdev_id_check_en << 473 HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT); 474 reg_val |= (config->pmac_id << 475 HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT); 476 reg_val |= (config->mcast_pkt_ctrl << 477 HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT); 478 479 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 480 } 481 #else 482 static inline void 483 hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl, 484 union hal_tx_bank_config *config, 485 uint8_t bank_id) 486 { 487 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 488 uint32_t reg_addr, reg_val = 0; 489 490 reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE, 491 bank_id); 492 493 reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT); 494 reg_val |= (config->encap_type << 495 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT); 496 reg_val |= (config->encrypt_type << 497 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT); 498 reg_val |= (config->src_buffer_swap << 499 HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT); 500 reg_val |= (config->link_meta_swap << 501 HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT); 502 reg_val |= (config->index_lookup_enable << 503 HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT); 504 reg_val |= (config->addrx_en << 505 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT); 506 reg_val |= (config->addry_en << 507 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT); 508 reg_val |= (config->mesh_enable << 509 HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT); 510 reg_val |= (config->vdev_id_check_en << 511 HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT); 512 reg_val |= (config->pmac_id << 513 HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT); 514 reg_val |= (config->mcast_pkt_ctrl << 515 HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT); 516 517 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 518 } 519 #endif 520 521 #ifdef DP_TX_IMPLICIT_RBM_MAPPING 522 523 #define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK 524 #define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT 525 526 #define RBM_PPE2TCL_OFFSET \ 527 (HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2) 528 #define RBM_TCL_CMD_CREDIT_OFFSET \ 529 (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2) 530 531 /** 532 * hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id 533 * @hal_soc: HAL SoC context 534 * @hal_ring_hdl: Source ring pointer 535 * @rbm_id: return buffer manager ring id 536 * 537 * Return: void 538 */ 539 static inline void 540 hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl, 541 hal_ring_handle_t hal_ring_hdl, 542 uint8_t rbm_id) 543 { 544 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 545 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 546 uint32_t reg_addr = 0; 547 uint32_t reg_val = 0; 548 uint32_t val = 0; 549 uint8_t ring_num; 550 enum hal_ring_type ring_type; 551 552 ring_type = srng->ring_type; 553 ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id; 554 ring_num = srng->ring_id - ring_num; 555 556 reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE); 557 558 if (ring_type == PPE2TCL) 559 ring_num = ring_num + RBM_PPE2TCL_OFFSET; 560 else if (ring_type == TCL_CMD_CREDIT) 561 ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET; 562 563 /* get current value stored in register address */ 564 val = HAL_REG_READ(hal_soc, reg_addr); 565 566 /* mask out other stored value */ 567 val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num))); 568 569 reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) << 570 (RBM_MAPPING_SHFT * ring_num)); 571 572 /* write rbm mapped value to register address */ 573 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 574 } 575 #else 576 static inline void 577 hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl, 578 hal_ring_handle_t hal_ring_hdl, 579 uint8_t rbm_id) 580 { 581 } 582 #endif 583 584 /** 585 * hal_tx_desc_set_buf_addr_be - Fill Buffer Address information in Tx Desc 586 * @desc: Handle to Tx Descriptor 587 * @paddr: Physical Address 588 * @pool_id: Return Buffer Manager ID 589 * @desc_id: Descriptor ID 590 * @type: 0 - Address points to a MSDU buffer 591 * 1 - Address points to MSDU extension descriptor 592 * 593 * Return: void 594 */ 595 static inline void 596 hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc, 597 dma_addr_t paddr, uint8_t rbm_id, 598 uint32_t desc_id, uint8_t type) 599 { 600 /* Set buffer_addr_info.buffer_addr_31_0 */ 601 HAL_SET_FLD(desc, TCL_DATA_CMD, 602 BUF_ADDR_INFO_BUFFER_ADDR_31_0) = 603 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr); 604 605 /* Set buffer_addr_info.buffer_addr_39_32 */ 606 HAL_SET_FLD(desc, TCL_DATA_CMD, 607 BUF_ADDR_INFO_BUFFER_ADDR_39_32) |= 608 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32, 609 (((uint64_t)paddr) >> 32)); 610 611 /* Set buffer_addr_info.return_buffer_manager = rbm id */ 612 HAL_SET_FLD(desc, TCL_DATA_CMD, 613 BUF_ADDR_INFO_RETURN_BUFFER_MANAGER) |= 614 HAL_TX_SM(TCL_DATA_CMD, 615 BUF_ADDR_INFO_RETURN_BUFFER_MANAGER, rbm_id); 616 617 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 618 HAL_SET_FLD(desc, TCL_DATA_CMD, 619 BUF_ADDR_INFO_SW_BUFFER_COOKIE) |= 620 HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE, 621 desc_id); 622 623 /* Set Buffer or Ext Descriptor Type */ 624 HAL_SET_FLD(desc, TCL_DATA_CMD, 625 BUF_OR_EXT_DESC_TYPE) |= 626 HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type); 627 } 628 629 #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT 630 631 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4) 632 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF) 633 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3 634 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2 635 636 /** 637 * hal_tx_vdev_mcast_ctrl_set - set mcast_ctrl value 638 * @hal_soc: HAL SoC context 639 * @mcast_ctrl_val: mcast ctrl value for this VAP 640 * 641 * Return: void 642 */ 643 static inline void 644 hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl, 645 uint8_t vdev_id, 646 uint8_t mcast_ctrl_val) 647 { 648 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 649 uint32_t reg_addr, reg_val = 0; 650 uint32_t val; 651 uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id); 652 uint8_t index_in_reg = 653 HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id); 654 655 reg_addr = 656 HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE, 657 reg_idx); 658 659 val = HAL_REG_READ(hal_soc, reg_addr); 660 661 /* mask out other stored value */ 662 val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK << 663 (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg))); 664 665 reg_val = val | 666 ((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) << 667 (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)); 668 669 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 670 } 671 #else 672 static inline void 673 hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl, 674 uint8_t vdev_id, 675 uint8_t mcast_ctrl_val) 676 { 677 } 678 #endif 679 #endif /* _HAL_BE_TX_H_ */ 680