1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_BE_RX_TLV_H_ 21 #define _HAL_BE_RX_TLV_H_ 22 23 #include "hal_api_mon.h" 24 25 /* 26 * Structures & Macros to obtain fields from the TLV's in the Rx packet 27 * pre-header. 28 */ 29 30 #define HAL_RX_BE_PKT_HDR_TLV_LEN 112 31 32 struct rx_pkt_hdr_tlv { 33 uint64_t tag; /* 8 B */ 34 uint64_t phy_ppdu_id; /* 8 B */ 35 char rx_pkt_hdr[HAL_RX_BE_PKT_HDR_TLV_LEN]; /* 112 B */ 36 }; 37 38 #ifdef CONFIG_WORD_BASED_TLV 39 #ifndef BIG_ENDIAN_HOST 40 struct rx_msdu_end_compact { 41 uint32_t sa_sw_peer_id : 16, 42 sa_idx_timeout : 1, 43 da_idx_timeout : 1, 44 to_ds : 1, 45 tid : 4, 46 sa_is_valid : 1, 47 da_is_valid : 1, 48 da_is_mcbc : 1, 49 l3_header_padding : 2, 50 first_msdu : 1, 51 last_msdu : 1, 52 fr_ds : 1, 53 ip_chksum_fail_copy : 1; 54 uint32_t sa_idx : 16, 55 da_idx_or_sw_peer_id : 16; 56 uint32_t msdu_drop : 1, 57 reo_destination_indication : 5, 58 flow_idx : 20, 59 use_ppe : 1, 60 mesh_sta : 2, 61 vlan_ctag_stripped : 1, 62 vlan_stag_stripped : 1, 63 fragment_flag : 1; 64 uint32_t fse_metadata : 32; 65 uint32_t cce_metadata : 16, 66 tcp_udp_chksum : 16; 67 uint32_t aggregation_count : 8, 68 flow_aggregation_continuation : 1, 69 fisa_timeout : 1, 70 tcp_udp_chksum_fail_copy : 1, 71 msdu_limit_error : 1, 72 flow_idx_timeout : 1, 73 flow_idx_invalid : 1, 74 cce_match : 1, 75 amsdu_parser_error : 1, 76 cumulative_ip_length : 16; 77 uint32_t key_id_octet : 8, 78 reserved_8a : 24; 79 uint32_t reserved_9a : 6, 80 service_code : 9, 81 priority_valid : 1, 82 intra_bss : 1, 83 dest_chip_id : 2, 84 multicast_echo : 1, 85 wds_learning_event : 1, 86 wds_roaming_event : 1, 87 wds_keep_alive_event : 1, 88 reserved_9b : 9; 89 uint32_t msdu_length : 14, 90 stbc : 1, 91 ipsec_esp : 1, 92 l3_offset : 7, 93 ipsec_ah : 1, 94 l4_offset : 8; 95 uint32_t msdu_number : 8, 96 decap_format : 2, 97 ipv4_proto : 1, 98 ipv6_proto : 1, 99 tcp_proto : 1, 100 udp_proto : 1, 101 ip_frag : 1, 102 tcp_only_ack : 1, 103 da_is_bcast_mcast : 1, 104 toeplitz_hash_sel : 2, 105 ip_fixed_header_valid : 1, 106 ip_extn_header_valid : 1, 107 tcp_udp_header_valid : 1, 108 mesh_control_present : 1, 109 ldpc : 1, 110 ip4_protocol_ip6_next_header : 8; 111 uint32_t vlan_ctag_ci : 16, 112 vlan_stag_ci : 16; 113 uint32_t peer_meta_data : 32; 114 uint32_t user_rssi : 8, 115 pkt_type : 4, 116 sgi : 2, 117 rate_mcs : 4, 118 receive_bandwidth : 3, 119 reception_type : 3, 120 mimo_ss_bitmap : 7, 121 msdu_done_copy : 1; 122 uint32_t flow_id_toeplitz : 32; 123 uint32_t ppdu_start_timestamp_63_32; 124 uint32_t sw_phy_meta_data : 32; 125 uint32_t first_mpdu : 1, 126 reserved_16a : 1, 127 mcast_bcast : 1, 128 ast_index_not_found : 1, 129 ast_index_timeout : 1, 130 power_mgmt : 1, 131 non_qos : 1, 132 null_data : 1, 133 mgmt_type : 1, 134 ctrl_type : 1, 135 more_data : 1, 136 eosp : 1, 137 a_msdu_error : 1, 138 reserved_16b : 1, 139 order : 1, 140 wifi_parser_error : 1, 141 overflow_err : 1, 142 msdu_length_err : 1, 143 tcp_udp_chksum_fail : 1, 144 ip_chksum_fail : 1, 145 sa_idx_invalid : 1, 146 da_idx_invalid : 1, 147 amsdu_addr_mismatch : 1, 148 rx_in_tx_decrypt_byp : 1, 149 encrypt_required : 1, 150 directed : 1, 151 buffer_fragment : 1, 152 mpdu_length_err : 1, 153 tkip_mic_err : 1, 154 decrypt_err : 1, 155 unencrypted_frame_err : 1, 156 fcs_err : 1; 157 uint32_t reserved_17a : 10, 158 decrypt_status_code : 3, 159 rx_bitmap_not_updated : 1, 160 reserved_17b : 17, 161 msdu_done : 1; 162 }; 163 164 struct rx_mpdu_start_compact { 165 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 166 receive_queue_number : 16, 167 pre_delim_err_warning : 1, 168 first_delim_err : 1, 169 reserved_0 : 6; 170 uint32_t pn_31_0 : 32; 171 uint32_t pn_63_32 : 32; 172 uint32_t pn_95_64 : 32; 173 uint32_t ast_index : 16, 174 sw_peer_id : 16; 175 uint32_t mpdu_frame_control_valid : 1, 176 mpdu_duration_valid : 1, 177 mac_addr_ad1_valid : 1, 178 mac_addr_ad2_valid : 1, 179 mac_addr_ad3_valid : 1, 180 mac_addr_ad4_valid : 1, 181 mpdu_sequence_control_valid : 1, 182 mpdu_qos_control_valid : 1, 183 mpdu_ht_control_valid : 1, 184 frame_encryption_info_valid : 1, 185 mpdu_fragment_number : 4, 186 more_fragment_flag : 1, 187 reserved_7a : 1, 188 fr_ds : 1, 189 to_ds : 1, 190 encrypted : 1, 191 mpdu_retry : 1, 192 mpdu_sequence_number : 12; 193 uint32_t mpdu_frame_control_field : 16, 194 mpdu_duration_field : 16; 195 uint32_t mac_addr_ad1_31_0 : 32; 196 uint32_t mac_addr_ad1_47_32 : 16, 197 mac_addr_ad2_15_0 : 16; 198 uint32_t mac_addr_ad2_47_16 : 32; 199 uint32_t mac_addr_ad3_31_0 : 32; 200 uint32_t mac_addr_ad3_47_32 : 16, 201 mpdu_sequence_control_field : 16; 202 }; 203 #else 204 struct rx_msdu_end_compact { 205 uint32_t ip_chksum_fail_copy : 1, 206 fr_ds : 1, 207 last_msdu : 1, 208 first_msdu : 1, 209 l3_header_padding : 2, 210 da_is_mcbc : 1, 211 da_is_valid : 1, 212 sa_is_valid : 1, 213 tid : 4, 214 to_ds : 1, 215 da_idx_timeout : 1, 216 sa_idx_timeout : 1, 217 sa_sw_peer_id : 16; 218 uint32_t da_idx_or_sw_peer_id : 16, 219 sa_idx : 16; 220 uint32_t fragment_flag : 1, 221 vlan_stag_stripped : 1, 222 vlan_ctag_stripped : 1, 223 mesh_sta : 2, 224 use_ppe : 1, 225 flow_idx : 20, 226 reo_destination_indication : 5, 227 msdu_drop : 1; 228 uint32_t fse_metadata : 32; 229 uint32_t tcp_udp_chksum : 16, 230 cce_metadata : 16; 231 uint32_t cumulative_ip_length : 16, 232 amsdu_parser_error : 1, 233 cce_match : 1, 234 flow_idx_invalid : 1, 235 flow_idx_timeout : 1, 236 msdu_limit_error : 1, 237 tcp_udp_chksum_fail_copy : 1, 238 fisa_timeout : 1, 239 flow_aggregation_continuation : 1, 240 aggregation_count : 8; 241 uint32_t reserved_8a : 24, 242 key_id_octet : 8; 243 uint32_t reserved_9b : 9, 244 wds_keep_alive_event : 1, 245 wds_roaming_event : 1, 246 wds_learning_event : 1, 247 multicast_echo : 1, 248 dest_chip_id : 2, 249 intra_bss : 1, 250 priority_valid : 1, 251 service_code : 9, 252 reserved_9a : 6; 253 uint32_t l4_offset : 8, 254 ipsec_ah : 1, 255 l3_offset : 7, 256 ipsec_esp : 1, 257 stbc : 1, 258 msdu_length : 14; 259 uint32_t ip4_protocol_ip6_next_header : 8, 260 ldpc : 1, 261 mesh_control_present : 1, 262 tcp_udp_header_valid : 1, 263 ip_extn_header_valid : 1, 264 ip_fixed_header_valid : 1, 265 toeplitz_hash_sel : 2, 266 da_is_bcast_mcast : 1, 267 tcp_only_ack : 1, 268 ip_frag : 1, 269 udp_proto : 1, 270 tcp_proto : 1, 271 ipv6_proto : 1, 272 ipv4_proto : 1, 273 decap_format : 2, 274 msdu_number : 8; 275 uint32_t vlan_stag_ci : 16, 276 vlan_ctag_ci : 16; 277 uint32_t peer_meta_data : 32; 278 uint32_t msdu_done_copy : 1, 279 mimo_ss_bitmap : 7, 280 reception_type : 3, 281 receive_bandwidth : 3, 282 rate_mcs : 4, 283 sgi : 2, 284 pkt_type : 4, 285 user_rssi : 8; 286 uint32_t flow_id_toeplitz : 32; 287 uint32_t ppdu_start_timestamp_63_32; 288 uint32_t sw_phy_meta_data : 32; 289 uint32_t fcs_err : 1, 290 unencrypted_frame_err : 1, 291 decrypt_err : 1, 292 tkip_mic_err : 1, 293 mpdu_length_err : 1, 294 buffer_fragment : 1, 295 directed : 1, 296 encrypt_required : 1, 297 rx_in_tx_decrypt_byp : 1, 298 amsdu_addr_mismatch : 1, 299 da_idx_invalid : 1, 300 sa_idx_invalid : 1, 301 ip_chksum_fail : 1, 302 tcp_udp_chksum_fail : 1, 303 msdu_length_err : 1, 304 overflow_err : 1, 305 wifi_parser_error : 1, 306 order : 1, 307 reserved_16b : 1, 308 a_msdu_error : 1, 309 eosp : 1, 310 more_data : 1, 311 ctrl_type : 1, 312 mgmt_type : 1, 313 null_data : 1, 314 non_qos : 1, 315 power_mgmt : 1, 316 ast_index_timeout : 1, 317 ast_index_not_found : 1, 318 mcast_bcast : 1, 319 reserved_16a : 1, 320 first_mpdu : 1; 321 uint32_t msdu_done : 1, 322 reserved_17b : 17, 323 rx_bitmap_not_updated : 1, 324 decrypt_status_code : 3, 325 reserved_17a : 10; 326 }; 327 328 struct rx_mpdu_start_compact { 329 uint32_t reserved_0 : 6, 330 first_delim_err : 1, 331 pre_delim_err_warning : 1, 332 receive_queue_number : 16, 333 rx_reo_queue_desc_addr_39_32 : 8; 334 uint32_t pn_31_0 : 32; 335 uint32_t pn_63_32 : 32; 336 uint32_t pn_95_64 : 32; 337 uint32_t sw_peer_id : 16, 338 ast_index : 16; 339 uint32_t mpdu_sequence_number : 12, 340 mpdu_retry : 1, 341 encrypted : 1, 342 to_ds : 1, 343 fr_ds : 1, 344 reserved_7a : 1, 345 more_fragment_flag : 1, 346 mpdu_fragment_number : 4, 347 frame_encryption_info_valid : 1, 348 mpdu_ht_control_valid : 1, 349 mpdu_qos_control_valid : 1, 350 mpdu_sequence_control_valid : 1, 351 mac_addr_ad4_valid : 1, 352 mac_addr_ad3_valid : 1, 353 mac_addr_ad2_valid : 1, 354 mac_addr_ad1_valid : 1, 355 mpdu_duration_valid : 1, 356 mpdu_frame_control_valid : 1; 357 uint32_t mpdu_duration_field : 16, 358 mpdu_frame_control_field : 16, 359 uint32_t mac_addr_ad1_31_0 : 32; 360 uint32_t mac_addr_ad2_15_0 : 16, 361 mac_addr_ad1_47_32 : 16; 362 uint32_t mac_addr_ad2_47_16 : 32; 363 uint32_t mac_addr_ad3_31_0 : 32; 364 uint32_t mpdu_sequence_control_field : 16, 365 mac_addr_ad3_47_32 : 16; 366 }; 367 #endif 368 #define RX_BE_PADDING0_BYTES 4 369 370 typedef struct rx_mpdu_start_compact hal_rx_mpdu_start_t; 371 typedef struct rx_msdu_end_compact hal_rx_msdu_end_t; 372 373 struct rx_mpdu_start_tlv { 374 hal_rx_mpdu_start_t rx_mpdu_start; 375 }; 376 377 struct rx_msdu_end_tlv { 378 uint64_t tag; /* 8 B */ 379 hal_rx_msdu_end_t rx_msdu_end; 380 }; 381 382 struct rx_pkt_tlvs { 383 struct rx_msdu_end_tlv msdu_end_tlv; /* 80 bytes */ 384 struct rx_mpdu_start_tlv mpdu_start_tlv; /* 48 bytes */ 385 }; 386 387 #define HAL_RX_MSDU_END(_rx_pkt_tlv) \ 388 (((struct rx_pkt_tlvs *)_rx_pkt_tlv)->msdu_end_tlv.rx_msdu_end) 389 390 #define HAL_RX_MPDU_START(_rx_pkt_tlv) \ 391 (((struct rx_pkt_tlvs *)_rx_pkt_tlv)->mpdu_start_tlv. \ 392 rx_mpdu_start) 393 394 #define HAL_RX_TLV_TID_GET(_rx_pkt_tlv) \ 395 HAL_RX_MSDU_END(_rx_pkt_tlv).tid 396 397 #define HAL_RX_TLV_FIRST_MPDU_GET(_rx_pkt_tlv) \ 398 HAL_RX_MSDU_END(_rx_pkt_tlv).first_mpdu 399 #else /* CONFIG_WORD_BASED_TLV */ 400 typedef struct rx_mpdu_start hal_rx_mpdu_start_t; 401 typedef struct rx_msdu_end hal_rx_msdu_end_t; 402 403 #define RX_BE_PADDING0_BYTES 8 404 /* 405 * Each RX descriptor TLV is preceded by 1 QWORD "tag" 406 */ 407 408 #ifndef CONFIG_NO_TLV_TAGS 409 struct rx_mpdu_start_tlv { 410 uint64_t tag; /* 8 B */ 411 hal_rx_mpdu_start_t rx_mpdu_start; 412 }; 413 414 struct rx_msdu_end_tlv { 415 uint64_t tag; /* 8 B */ 416 hal_rx_msdu_end_t rx_msdu_end; 417 }; 418 419 struct rx_pkt_tlvs { 420 struct rx_msdu_end_tlv msdu_end_tlv; /* 120 bytes */ 421 uint8_t rx_padding0[RX_BE_PADDING0_BYTES]; /* 8 bytes */ 422 struct rx_mpdu_start_tlv mpdu_start_tlv; /* 120 bytes */ 423 #ifndef NO_RX_PKT_HDR_TLV 424 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 425 #endif 426 }; 427 428 #else 429 struct rx_mpdu_start_tlv { 430 hal_rx_mpdu_start_t rx_mpdu_start; 431 }; 432 433 struct rx_msdu_end_tlv { 434 hal_rx_msdu_end_t rx_msdu_end; 435 }; 436 437 struct rx_pkt_tlvs { 438 struct rx_msdu_end_tlv msdu_end_tlv; /* 128 bytes */ 439 struct rx_mpdu_start_tlv mpdu_start_tlv; /* 120 bytes */ 440 uint8_t rx_padding0[RX_BE_PADDING0_BYTES]; /* 8 bytes */ 441 #ifndef NO_RX_PKT_HDR_TLV 442 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 443 #endif 444 }; 445 #endif /*CONFIG_NO_TLV_TAGS */ 446 447 #define HAL_RX_MSDU_END(_rx_pkt_tlv) \ 448 (((struct rx_pkt_tlvs *)_rx_pkt_tlv)->msdu_end_tlv.rx_msdu_end) 449 450 #define HAL_RX_MPDU_START(_rx_pkt_tlv) \ 451 (((struct rx_pkt_tlvs *)_rx_pkt_tlv)->mpdu_start_tlv. \ 452 rx_mpdu_start.rx_mpdu_info_details) 453 454 #define HAL_RX_REO_QUEUE_DESC_ADDR_31_0_GET(_rx_pkt_tlv) \ 455 HAL_RX_MPDU_START(_rx_pkt_tlv).rx_reo_queue_desc_addr_31_0 456 457 #define HAL_RX_TLV_AMPDU_FLAG_GET(_rx_pkt_tlv) \ 458 HAL_RX_MPDU_START(_rx_pkt_tlv).ampdu_flag 459 460 #define HAL_RX_TLV_MPDU_PN_127_96_GET(_rx_pkt_tlv) \ 461 HAL_RX_MPDU_START(_rx_pkt_tlv).pn_127_96 462 463 #define HAL_RX_TLV_TID_GET(_rx_pkt_tlv) \ 464 HAL_RX_MPDU_START(_rx_pkt_tlv).tid 465 466 #define HAL_RX_TLV_FIRST_MPDU_GET(_rx_pkt_tlv) \ 467 HAL_RX_MPDU_START(_rx_pkt_tlv).first_mpdu 468 469 #define HAL_RX_TLV_L3_TYPE_GET(_rx_pkt_tlv) \ 470 HAL_RX_MSDU_END(_rx_pkt_tlv).l3_type 471 472 #define HAL_RX_GET_PPDU_ID(_rx_pkt_tlv) \ 473 HAL_RX_MPDU_START(_rx_pkt_tlv).phy_ppdu_id 474 475 #define HAL_RX_TLV_PHY_PPDU_ID_GET(_rx_pkt_tlv) \ 476 HAL_RX_MSDU_END(_rx_pkt_tlv).phy_ppdu_id 477 478 #define HAL_RX_GET_FILTER_CATEGORY(_rx_pkt_tlv) \ 479 HAL_RX_MPDU_START(_rx_pkt_tlv).rxpcu_mpdu_filter_in_category 480 481 #define HAL_RX_TLV_SW_FRAME_GROUP_ID_GET(_rx_pkt_tlv) \ 482 HAL_RX_MPDU_START(_rx_pkt_tlv).sw_frame_group_id 483 484 #endif /* CONFIG_WORD_BASED_TLV */ 485 486 /** 487 * struct rx_mon_pkt_tlvs - RX packet data structure for DEST ring in the 488 * monitor mode. 489 * @msdu_end_tlv: MSDU end TLV 490 * @rx_padding0: Padding bytes 491 * @mpdu_start_tlv: MPDU start TLV 492 * @pkt_hdr_tlv: 802.11 packet header TLV 493 */ 494 struct rx_mon_pkt_tlvs { 495 struct rx_msdu_end_tlv msdu_end_tlv; /* 128B + sizeof(tag) */ 496 uint8_t rx_padding0[RX_BE_PADDING0_BYTES]; /* 8B */ 497 struct rx_mpdu_start_tlv mpdu_start_tlv; /* 120B + sizeof(tag) */ 498 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 120B + sizeof(tag) */ 499 }; 500 501 #define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs) 502 #define SIZE_OF_MON_DATA_RX_TLV sizeof(struct rx_mon_pkt_tlvs) 503 504 #define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV 505 #define MON_RX_PKT_TLVS_LEN SIZE_OF_MON_DATA_RX_TLV 506 507 #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field) 508 509 #define HAL_RX_TLV_MSDU_DONE_GET(_rx_pkt_tlv) \ 510 HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done 511 512 #define HAL_RX_TLV_DECAP_FORMAT_GET(_rx_pkt_tlv) \ 513 HAL_RX_MSDU_END(_rx_pkt_tlv).decap_format 514 515 #ifdef RECEIVE_OFFLOAD 516 #define HAL_RX_TLV_GET_TCP_PURE_ACK(_rx_pkt_tlv) \ 517 HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_only_ack 518 519 #define HAL_RX_TLV_GET_TCP_PROTO(_rx_pkt_tlv) \ 520 HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_proto 521 522 #define HAL_RX_TLV_GET_UDP_PROTO(_rx_pkt_tlv) \ 523 HAL_RX_MSDU_END(_rx_pkt_tlv).udp_proto 524 525 #define HAL_RX_TLV_GET_IPV6(_rx_pkt_tlv) \ 526 HAL_RX_MSDU_END(_rx_pkt_tlv).ipv6_proto 527 528 #define HAL_RX_TLV_GET_IP_OFFSET(_rx_pkt_tlv) \ 529 HAL_RX_MSDU_END(_rx_pkt_tlv).l3_offset 530 531 #define HAL_RX_TLV_GET_TCP_OFFSET(_rx_pkt_tlv) \ 532 HAL_RX_MSDU_END(_rx_pkt_tlv).l4_offset 533 #endif /* RECEIVE_OFFLOAD */ 534 535 #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(_rx_pkt_tlv) \ 536 HAL_RX_MSDU_END(_rx_pkt_tlv).flow_id_toeplitz 537 538 #define HAL_RX_TLV_MSDU_LEN_GET(_rx_pkt_tlv) \ 539 HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_length 540 541 #define HAL_RX_TLV_CCE_MATCH_GET(_rx_pkt_tlv) \ 542 HAL_RX_MSDU_END(_rx_pkt_tlv).cce_match 543 544 #define HAL_RX_TLV_BW_GET(_rx_pkt_tlv) \ 545 HAL_RX_MSDU_END(_rx_pkt_tlv).receive_bandwidth 546 547 #define HAL_RX_TLV_FLOWID_TOEPLITZ_GET(_rx_pkt_tlv) \ 548 HAL_RX_MSDU_END(_rx_pkt_tlv).flow_id_toeplitz 549 550 #define HAL_RX_TLV_SGI_GET(_rx_pkt_tlv) \ 551 HAL_RX_MSDU_END(_rx_pkt_tlv).sgi 552 553 #define HAL_RX_TLV_RATE_MCS_GET(_rx_pkt_tlv) \ 554 HAL_RX_MSDU_END(_rx_pkt_tlv).rate_mcs 555 556 #define HAL_RX_TLV_DECRYPT_STATUS_GET(_rx_pkt_tlv) \ 557 HAL_RX_MSDU_END(_rx_pkt_tlv).decrypt_status_code 558 559 #define HAL_RX_TLV_RSSI_GET(_rx_pkt_tlv) \ 560 HAL_RX_MSDU_END(_rx_pkt_tlv).user_rssi 561 562 #define HAL_RX_TLV_FREQ_GET(_rx_pkt_tlv) \ 563 HAL_RX_MSDU_END(_rx_pkt_tlv).sw_phy_meta_data 564 565 #define HAL_RX_TLV_PKT_TYPE_GET(_rx_pkt_tlv) \ 566 HAL_RX_MSDU_END(_rx_pkt_tlv).pkt_type 567 568 #define HAL_RX_TLV_DECRYPT_ERR_GET(_rx_pkt_tlv) \ 569 HAL_RX_MSDU_END(_rx_pkt_tlv).decrypt_err 570 571 #define HAL_RX_TLV_MIC_ERR_GET(_rx_pkt_tlv) \ 572 HAL_RX_MSDU_END(_rx_pkt_tlv).tkip_mic_err 573 574 #define HAL_RX_TLV_MIMO_SS_BITMAP(_rx_pkt_tlv)\ 575 HAL_RX_MSDU_END(_rx_pkt_tlv).mimo_ss_bitmap 576 577 #define HAL_RX_TLV_ANT_SIGNAL_DB_GET(_rx_pkt_tlv) \ 578 HAL_RX_MSDU_END(_rx_pkt_tlv).user_rssi 579 580 #define HAL_RX_TLV_STBC_GET(_rx_pkt_tlv) \ 581 HAL_RX_MSDU_END(_rx_pkt_tlv).stbc 582 583 #define HAL_RX_TLV_RECEPTION_TYPE_GET(_rx_pkt_tlv) \ 584 HAL_RX_MSDU_END(_rx_pkt_tlv).reception_type 585 586 #define HAL_RX_TLV_IP_CSUM_FAIL_GET(_rx_pkt_tlv) \ 587 HAL_RX_MSDU_END(_rx_pkt_tlv).ip_chksum_fail 588 589 #define HAL_RX_TLV_TCP_UDP_CSUM_FAIL_GET(_rx_pkt_tlv) \ 590 HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_udp_chksum_fail 591 592 #define HAL_RX_TLV_MPDU_LEN_ERR_GET(_rx_pkt_tlv) \ 593 HAL_RX_MSDU_END(_rx_pkt_tlv).mpdu_length_err 594 595 #define HAL_RX_TLV_MPDU_FCS_ERR_GET(_rx_pkt_tlv) \ 596 HAL_RX_MSDU_END(_rx_pkt_tlv).fcs_err 597 598 #define HAL_RX_TLV_IS_MCAST_GET(_rx_pkt_tlv) \ 599 HAL_RX_MSDU_END(_rx_pkt_tlv).mcast_bcast 600 601 #ifdef RECEIVE_OFFLOAD 602 /** 603 * LRO information needed from the TLVs 604 */ 605 #define HAL_RX_TLV_GET_LRO_ELIGIBLE(_rx_pkt_tlv) \ 606 HAL_RX_MSDU_END(_rx_pkt_tlv).lro_eligible 607 608 #define HAL_RX_TLV_GET_TCP_ACK(_rx_pkt_tlv) \ 609 HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_ack_number 610 611 #define HAL_RX_TLV_GET_TCP_SEQ(_rx_pkt_tlv) \ 612 HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_seq_number 613 614 #define HAL_RX_TLV_GET_TCP_WIN(_rx_pkt_tlv) \ 615 HAL_RX_MSDU_END(_rx_pkt_tlv).window_size 616 #endif 617 618 #define HAL_RX_TLV_L3_TYPE_GET(_rx_pkt_tlv) \ 619 HAL_RX_MSDU_END(_rx_pkt_tlv).l3_type 620 621 #ifdef RX_MSDU_END_PEER_META_DATA_OFFSET 622 #define HAL_RX_TLV_MSDU_PEER_META_DATA_GET(_rx_pkt_tlv) \ 623 HAL_RX_MSDU_END(_rx_pkt_tlv).peer_meta_data 624 #endif 625 626 #define HAL_RX_TLV_PEER_META_DATA_GET(_rx_pkt_tlv) \ 627 HAL_RX_MPDU_START(_rx_pkt_tlv).peer_meta_data 628 629 #define HAL_RX_TLV_KEYID_OCTET_GET(_rx_pkt_tlv) \ 630 HAL_RX_MSDU_END(_rx_pkt_tlv).key_id_octet 631 632 #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(_rx_pkt_tlv) \ 633 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_sequence_number 634 635 #define HAL_RX_TLV_SA_SW_PEER_ID_GET(_rx_pkt_tlv) \ 636 HAL_RX_MSDU_END(_rx_pkt_tlv).sa_sw_peer_id 637 638 #define HAL_RX_TLV_L3_HEADER_PADDING_GET(_rx_pkt_tlv) \ 639 HAL_RX_MSDU_END(_rx_pkt_tlv).l3_header_padding 640 641 #define HAL_RX_TLV_SA_IDX_GET(_rx_pkt_tlv) \ 642 HAL_RX_MSDU_END(_rx_pkt_tlv).sa_idx 643 644 #define HAL_RX_TLV_DA_IDX_GET(_rx_pkt_tlv) \ 645 HAL_RX_MSDU_END(_rx_pkt_tlv).da_idx_or_sw_peer_id 646 647 #define HAL_RX_TLV_FIRST_MSDU_GET(_rx_pkt_tlv) \ 648 HAL_RX_MSDU_END(_rx_pkt_tlv).first_msdu 649 650 #define HAL_RX_TLV_LAST_MSDU_GET(_rx_pkt_tlv) \ 651 HAL_RX_MSDU_END(_rx_pkt_tlv).last_msdu 652 653 #define HAL_RX_TLV_DA_IS_MCBC_GET(_rx_pkt_tlv) \ 654 HAL_RX_MSDU_END(_rx_pkt_tlv).da_is_mcbc 655 656 #define HAL_RX_TLV_IS_TKIP_MIC_ERR_GET(_rx_pkt_tlv) \ 657 HAL_RX_MSDU_END(_rx_pkt_tlv).tkip_mic_err 658 659 #define HAL_RX_TLV_SA_IS_VALID_GET(_rx_pkt_tlv) \ 660 HAL_RX_MSDU_END(_rx_pkt_tlv).sa_is_valid 661 662 #define HAL_RX_TLV_MPDU_ENCRYPTION_INFO_VALID(_rx_pkt_tlv) \ 663 HAL_RX_MPDU_START(_rx_pkt_tlv).frame_encryption_info_valid 664 665 #define HAL_RX_TLV_MPDU_PN_31_0_GET(_rx_pkt_tlv) \ 666 HAL_RX_MPDU_START(_rx_pkt_tlv).pn_31_0 667 668 #define HAL_RX_TLV_MPDU_PN_63_32_GET(_rx_pkt_tlv) \ 669 HAL_RX_MPDU_START(_rx_pkt_tlv).pn_63_32 670 671 #define HAL_RX_TLV_MPDU_PN_95_64_GET(_rx_pkt_tlv) \ 672 HAL_RX_MPDU_START(_rx_pkt_tlv).pn_95_64 673 674 #define HAL_RX_TLV_DA_IS_VALID_GET(_rx_pkt_tlv) \ 675 HAL_RX_MSDU_END(_rx_pkt_tlv).da_is_valid 676 677 #define HAL_RX_TLV_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_pkt_tlv) \ 678 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad4_valid 679 680 #define HAL_RX_TLV_SW_PEER_ID_GET(_rx_pkt_tlv) \ 681 HAL_RX_MPDU_START(_rx_pkt_tlv).sw_peer_id 682 683 #define HAL_RX_TLV_MPDU_GET_TODS(_rx_pkt_tlv) \ 684 HAL_RX_MPDU_START(_rx_pkt_tlv).to_ds 685 686 #define HAL_RX_TLV_MPDU_GET_FROMDS(_rx_pkt_tlv) \ 687 HAL_RX_MPDU_START(_rx_pkt_tlv).fr_ds 688 689 #define HAL_RX_TLV_MPDU_GET_FRAME_CONTROL_VALID(_rx_pkt_tlv) \ 690 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_frame_control_valid 691 692 #define HAL_RX_TLV_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_pkt_tlv) \ 693 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad1_valid 694 695 #define HAL_RX_TLV_MPDU_AD1_31_0_GET(_rx_pkt_tlv) \ 696 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad1_31_0 697 698 #define HAL_RX_TLV_MPDU_AD1_47_32_GET(_rx_pkt_tlv) \ 699 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad1_47_32 700 701 #define HAL_RX_TLV_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_pkt_tlv) \ 702 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad2_valid 703 704 #define HAL_RX_TLV_MPDU_AD2_15_0_GET(_rx_pkt_tlv) \ 705 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad2_15_0 706 707 #define HAL_RX_TLV_MPDU_AD2_47_16_GET(_rx_pkt_tlv) \ 708 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad2_47_16 709 710 #define HAL_RX_TLV_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_pkt_tlv) \ 711 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad3_valid 712 713 #define HAL_RX_TLV_MPDU_AD3_31_0_GET(_rx_pkt_tlv) \ 714 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad3_31_0 715 716 #define HAL_RX_TLV_MPDU_AD3_47_32_GET(_rx_pkt_tlv) \ 717 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad3_47_32 718 719 #define HAL_RX_TLV_MPDU_AD4_31_0_GET(_rx_pkt_tlv) \ 720 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad4_31_0 721 722 #define HAL_RX_TLV_MPDU_AD4_47_32_GET(_rx_pkt_tlv) \ 723 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad4_47_32 724 725 #define HAL_RX_TLV_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_pkt_tlv) \ 726 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_sequence_control_valid 727 728 #define HAL_RX_TLV_MPDU_QOS_CONTROL_VALID_GET(_rx_pkt_tlv) \ 729 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_qos_control_valid 730 731 #define HAL_RX_TLV_GET_FC_VALID(_rx_pkt_tlv) \ 732 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_frame_control_valid 733 734 #define HAL_RX_TLV_GET_TO_DS_FLAG(_rx_pkt_tlv) \ 735 HAL_RX_MPDU_START(_rx_pkt_tlv).to_ds 736 737 #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_pkt_tlv) \ 738 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_frame_control_field 739 740 #define HAL_RX_TLV_FLOW_IDX_GET(_rx_pkt_tlv) \ 741 HAL_RX_MSDU_END(_rx_pkt_tlv).flow_idx 742 743 #define HAL_RX_TLV_REO_DEST_IND_GET(_rx_pkt_tlv) \ 744 HAL_RX_MSDU_END(_rx_pkt_tlv).reo_destination_indication 745 746 #define HAL_RX_TLV_FLOW_IDX_INVALID_GET(_rx_pkt_tlv) \ 747 HAL_RX_MSDU_END(_rx_pkt_tlv).flow_idx_invalid 748 749 #define HAL_RX_TLV_FLOW_IDX_TIMEOUT_GET(_rx_pkt_tlv) \ 750 HAL_RX_MSDU_END(_rx_pkt_tlv).flow_idx_timeout 751 752 #define HAL_RX_TLV_FSE_METADATA_GET(_rx_pkt_tlv) \ 753 HAL_RX_MSDU_END(_rx_pkt_tlv).fse_metadata 754 755 #define HAL_RX_TLV_CCE_METADATA_GET(_rx_pkt_tlv) \ 756 HAL_RX_MSDU_END(_rx_pkt_tlv).cce_metadata 757 758 #define HAL_RX_TLV_DECRYPT_STATUS_GET(_rx_pkt_tlv) \ 759 HAL_RX_MSDU_END(_rx_pkt_tlv).decrypt_status_code 760 761 #define HAL_RX_TLV_GET_TCP_CHKSUM(_rx_pkt_tlv) \ 762 HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_udp_chksum 763 764 #define HAL_RX_TLV_GET_FLOW_AGGR_CONT(_rx_pkt_tlv) \ 765 HAL_RX_MSDU_END(_rx_pkt_tlv).flow_aggregation_continuation 766 767 #define HAL_RX_TLV_GET_FLOW_AGGR_COUNT(_rx_pkt_tlv) \ 768 HAL_RX_MSDU_END(_rx_pkt_tlv).aggregation_count 769 770 #define HAL_RX_TLV_GET_FISA_TIMEOUT(_rx_pkt_tlv) \ 771 HAL_RX_MSDU_END(_rx_pkt_tlv).fisa_timeout 772 773 #define HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(_rx_pkt_tlv) \ 774 HAL_RX_MSDU_END(_rx_pkt_tlv).cumulative_l4_checksum 775 776 #define HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(_rx_pkt_tlv) \ 777 HAL_RX_MSDU_END(_rx_pkt_tlv).cumulative_ip_length 778 779 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_pkt_tlv) \ 780 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_qos_control_valid 781 782 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_pkt_tlv) \ 783 HAL_RX_MSDU_END(_rx_pkt_tlv).sa_sw_peer_id 784 785 #define HAL_RX_REO_QUEUE_DESC_ADDR_39_32_GET(_rx_pkt_tlv) \ 786 HAL_RX_MPDU_START(_rx_pkt_tlv).rx_reo_queue_desc_addr_39_32 787 788 /* used by monitor mode for parsing from full TLV */ 789 #define HAL_RX_MON_GET_FC_VALID(_rx_mpdu_start) \ 790 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MPDU_FRAME_CONTROL_VALID) 791 792 #define HAL_RX_MON_GET_TO_DS_FLAG(_rx_mpdu_start) \ 793 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, TO_DS) 794 795 #define HAL_RX_MON_GET_MAC_ADDR2_VALID(_rx_mpdu_start) \ 796 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD2_VALID) 797 798 static inline 799 uint32_t hal_rx_tlv_decap_format_get_be(void *hw_desc_addr) 800 { 801 struct rx_pkt_tlvs *rx_pkt_tlvs = 802 (struct rx_pkt_tlvs *)hw_desc_addr; 803 804 return HAL_RX_TLV_DECAP_FORMAT_GET(rx_pkt_tlvs); 805 } 806 807 static inline uint32_t hal_rx_tlv_msdu_done_get_be(uint8_t *buf) 808 { 809 return HAL_RX_TLV_MSDU_DONE_GET(buf); 810 } 811 812 /* 813 * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention 814 * @buf: pointer to rx_pkt_tlvs 815 * 816 * return: uint32_t(first_msdu) 817 */ 818 static inline uint32_t hal_rx_tlv_first_mpdu_get_be(uint8_t *buf) 819 { 820 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 821 822 return HAL_RX_TLV_FIRST_MPDU_GET(rx_pkt_tlvs); 823 } 824 825 /* 826 * hal_rx_msdu_cce_match_get(): get CCE match bit 827 * from rx attention 828 * @buf: pointer to rx_pkt_tlvs 829 * Return: CCE match value 830 */ 831 static inline bool hal_rx_msdu_cce_match_get_be(uint8_t *buf) 832 { 833 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 834 835 return HAL_RX_TLV_CCE_MATCH_GET(rx_pkt_tlvs); 836 } 837 838 #ifdef RX_MSDU_END_PEER_META_DATA_OFFSET 839 /* 840 * Get peer_meta_data from RX_MSDU_END 841 */ 842 843 static inline uint32_t hal_rx_msdu_peer_meta_data_get_be(uint8_t *buf) 844 { 845 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 846 847 return HAL_RX_TLV_MSDU_PEER_META_DATA_GET(rx_pkt_tlvs); 848 } 849 #endif 850 851 /* 852 * hal_rx_mpdu_get_addr1_be(): API to check get address1 of the mpdu 853 * 854 * @buf: pointer to the start of RX PKT TLV headera 855 * @mac_addr: pointer to mac address 856 * Return: success/failure 857 */ 858 static inline QDF_STATUS hal_rx_mpdu_get_addr1_be(uint8_t *buf, 859 uint8_t *mac_addr) 860 { 861 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 862 struct __attribute__((__packed__)) hal_addr1 { 863 uint32_t ad1_31_0; 864 uint16_t ad1_47_32; 865 }; 866 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 867 uint32_t mac_addr_ad1_valid; 868 869 mac_addr_ad1_valid = HAL_RX_TLV_MPDU_MAC_ADDR_AD1_VALID_GET( 870 rx_pkt_tlvs); 871 872 if (mac_addr_ad1_valid) { 873 addr->ad1_31_0 = HAL_RX_TLV_MPDU_AD1_31_0_GET(rx_pkt_tlvs); 874 addr->ad1_47_32 = HAL_RX_TLV_MPDU_AD1_47_32_GET(rx_pkt_tlvs); 875 return QDF_STATUS_SUCCESS; 876 } 877 878 return QDF_STATUS_E_FAILURE; 879 } 880 881 #ifndef CONFIG_WORD_BASED_TLV 882 /** 883 * hal_rx_mpdu_info_ampdu_flag_get_be(): get ampdu flag bit 884 * from rx mpdu info 885 * @buf: pointer to rx_pkt_tlvs 886 * 887 * Return: ampdu flag 888 */ 889 static inline bool hal_rx_mpdu_info_ampdu_flag_get_be(uint8_t *buf) 890 { 891 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 892 893 return !!HAL_RX_TLV_AMPDU_FLAG_GET(rx_pkt_tlvs); 894 } 895 896 /** 897 * hal_rx_get_qdesc_addr_be(): API to get qdesc address of reo 898 * entrance ring desc 899 * 900 * @dst_ring_desc: reo dest ring descriptor (used for Lithium DP) 901 * @buf: pointer to the start of RX PKT TLV headers 902 * Return: qdesc address in reo destination ring buffer 903 */ 904 static inline uint64_t hal_rx_get_qdesc_addr_be(uint8_t *dst_ring_desc, 905 uint8_t *buf) 906 { 907 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 908 909 return (uint64_t)HAL_RX_REO_QUEUE_DESC_ADDR_31_0_GET(rx_pkt_tlvs); 910 } 911 912 /* 913 * @ hal_rx_print_pn_be: Prints the PN of rx packet. 914 * 915 * @ buf: rx_tlv_hdr of the received packet 916 * @ Return: void 917 */ 918 static inline void hal_rx_print_pn_be(uint8_t *buf) 919 { 920 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 921 922 uint32_t pn_31_0 = HAL_RX_TLV_MPDU_PN_31_0_GET(rx_pkt_tlvs); 923 uint32_t pn_63_32 = HAL_RX_TLV_MPDU_PN_63_32_GET(rx_pkt_tlvs); 924 uint32_t pn_95_64 = HAL_RX_TLV_MPDU_PN_95_64_GET(rx_pkt_tlvs); 925 uint32_t pn_127_96 = HAL_RX_TLV_MPDU_PN_127_96_GET(rx_pkt_tlvs); 926 927 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 928 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 929 } 930 931 static inline void hal_rx_tlv_get_pn_num_be(uint8_t *buf, uint64_t *pn_num) 932 { 933 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 934 935 pn_num[0] = HAL_RX_TLV_MPDU_PN_31_0_GET(pkt_tlvs); 936 pn_num[0] |= ((uint64_t)HAL_RX_TLV_MPDU_PN_63_32_GET(pkt_tlvs) << 32); 937 938 pn_num[1] = HAL_RX_TLV_MPDU_PN_95_64_GET(pkt_tlvs); 939 pn_num[1] |= ((uint64_t)HAL_RX_TLV_MPDU_PN_127_96_GET(pkt_tlvs) << 32); 940 } 941 942 /* 943 * hal_rx_mpdu_get_addr4_be(): API to get address4 of the mpdu 944 * in the packet 945 * 946 * @buf: pointer to the start of RX PKT TLV header 947 * @mac_addr: pointer to mac address 948 * Return: success/failure 949 */ 950 static inline QDF_STATUS hal_rx_mpdu_get_addr4_be(uint8_t *buf, 951 uint8_t *mac_addr) 952 { 953 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 954 struct __attribute__((__packed__)) hal_addr4 { 955 uint32_t ad4_31_0; 956 uint16_t ad4_47_32; 957 }; 958 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 959 uint32_t mac_addr_ad4_valid; 960 961 mac_addr_ad4_valid = HAL_RX_TLV_MPDU_MAC_ADDR_AD4_VALID_GET(pkt_tlvs); 962 963 if (mac_addr_ad4_valid) { 964 addr->ad4_31_0 = HAL_RX_TLV_MPDU_AD4_31_0_GET(pkt_tlvs); 965 addr->ad4_47_32 = HAL_RX_TLV_MPDU_AD4_47_32_GET(pkt_tlvs); 966 return QDF_STATUS_SUCCESS; 967 } 968 969 return QDF_STATUS_E_FAILURE; 970 } 971 972 /** 973 * hal_rx_priv_info_set_in_tlv_be(): Save the private info to 974 * the reserved bytes of rx_tlv_hdr 975 * @buf: start of rx_tlv_hdr 976 * @priv_data: hal_wbm_err_desc_info structure 977 * @len: length of the private data 978 * Return: void 979 */ 980 static inline void hal_rx_priv_info_set_in_tlv_be(uint8_t *buf, 981 uint8_t *priv_data, 982 uint32_t len) 983 { 984 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 985 uint32_t copy_len = (len > RX_BE_PADDING0_BYTES) ? 986 RX_BE_PADDING0_BYTES : len; 987 988 qdf_mem_copy(pkt_tlvs->rx_padding0, priv_data, copy_len); 989 } 990 991 /** 992 * hal_rx_priv_info_get_from_tlv_be(): retrieve the private data from 993 * the reserved bytes of rx_tlv_hdr. 994 * @buf: start of rx_tlv_hdr 995 * @priv_data: Handle to get the private data, output parameter. 996 * @len: length of the private data 997 * Return: void 998 */ 999 static inline void hal_rx_priv_info_get_from_tlv_be(uint8_t *buf, 1000 uint8_t *priv_data, 1001 uint32_t len) 1002 { 1003 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1004 uint32_t copy_len = (len > RX_BE_PADDING0_BYTES) ? 1005 RX_BE_PADDING0_BYTES : len; 1006 1007 qdf_mem_copy(priv_data, pkt_tlvs->rx_padding0, copy_len); 1008 } 1009 1010 /** 1011 * hal_rx_tlv_l3_type_get_be(): API to get the l3 type 1012 * from rx_msdu_start TLV 1013 * 1014 * @buf: pointer to the start of RX PKT TLV headers 1015 * Return: uint32_t(l3 type) 1016 */ 1017 static inline uint32_t hal_rx_tlv_l3_type_get_be(uint8_t *buf) 1018 { 1019 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1020 1021 return HAL_RX_TLV_L3_TYPE_GET(rx_pkt_tlvs); 1022 } 1023 1024 /** 1025 * hal_rx_hw_desc_get_ppduid_get_be(): retrieve ppdu id 1026 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1027 * @rxdma_dst_ring_desc: Rx HW descriptor 1028 * 1029 * Return: ppdu id 1030 */ 1031 static inline uint32_t 1032 hal_rx_hw_desc_get_ppduid_get_be(void *rx_tlv_hdr, void *rxdma_dst_ring_desc) 1033 { 1034 struct rx_pkt_tlvs *rx_pkt_tlvs = 1035 (struct rx_pkt_tlvs *)rx_tlv_hdr; 1036 1037 return HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs); 1038 } 1039 1040 /* 1041 * hal_rx_tlv_phy_ppdu_id_get(): get phy_ppdu_id value 1042 * from rx attention 1043 * @buf: pointer to rx_pkt_tlvs 1044 * 1045 * Return: phy_ppdu_id 1046 */ 1047 static inline uint16_t hal_rx_tlv_phy_ppdu_id_get_be(uint8_t *buf) 1048 { 1049 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1050 1051 return HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs); 1052 } 1053 1054 /* 1055 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 1056 * from rx attention 1057 * @buf: pointer to rx_pkt_tlvs 1058 * 1059 * Return: phy_ppdu_id 1060 */ 1061 static inline uint16_t hal_rx_attn_phy_ppdu_id_get_be(uint8_t *buf) 1062 { 1063 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1064 uint16_t phy_ppdu_id; 1065 1066 phy_ppdu_id = HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs); 1067 1068 return phy_ppdu_id; 1069 } 1070 1071 static inline uint32_t 1072 hal_rx_get_ppdu_id_be(uint8_t *buf) 1073 { 1074 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1075 1076 return HAL_RX_GET_PPDU_ID(rx_pkt_tlvs); 1077 } 1078 1079 /* 1080 * hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv 1081 * 1082 * @buf: rx_tlv_hdr of the received packet 1083 * @peer_mdata: peer meta data to be set. 1084 * Return: void 1085 */ 1086 static inline void 1087 hal_rx_mpdu_peer_meta_data_set_be(uint8_t *buf, uint32_t peer_mdata) 1088 { 1089 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1090 1091 HAL_RX_TLV_PEER_META_DATA_GET(rx_pkt_tlvs) = peer_mdata; 1092 } 1093 1094 /* 1095 * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START 1096 */ 1097 1098 static inline uint32_t hal_rx_mpdu_peer_meta_data_get_be(uint8_t *buf) 1099 { 1100 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1101 1102 return HAL_RX_TLV_PEER_META_DATA_GET(rx_pkt_tlvs); 1103 } 1104 1105 static inline uint8_t hal_rx_get_filter_category_be(uint8_t *buf) 1106 { 1107 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1108 1109 return HAL_RX_GET_FILTER_CATEGORY(rx_pkt_tlvs); 1110 } 1111 1112 /** 1113 * hal_rx_is_unicast_be: check packet is unicast frame or not. 1114 * 1115 * @ buf: pointer to rx pkt TLV. 1116 * Return: true on unicast. 1117 */ 1118 static inline bool hal_rx_is_unicast_be(uint8_t *buf) 1119 { 1120 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1121 uint32_t grp_id; 1122 1123 grp_id = HAL_RX_TLV_SW_FRAME_GROUP_ID_GET(rx_pkt_tlvs); 1124 1125 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1126 } 1127 1128 #else 1129 #define IS_ADDR_MULTICAST(_a) (*(_a) & 0x01) 1130 /** 1131 * hal_rx_is_unicast_be: check packet is unicast frame or not. 1132 * 1133 * @ buf: pointer to rx pkt TLV. 1134 * Return: true on unicast. 1135 */ 1136 static inline bool hal_rx_is_unicast_be(uint8_t *buf) 1137 { 1138 uint8_t mac[QDF_MAC_ADDR_SIZE] = {0}; 1139 1140 hal_rx_mpdu_get_addr1_be(buf, &mac[0]); 1141 1142 return !IS_ADDR_MULTICAST(mac); 1143 } 1144 1145 /** 1146 * hal_rx_priv_info_set_in_tlv_be(): Save the private info to 1147 * the reserved bytes of rx_tlv_hdr 1148 * @buf: start of rx_tlv_hdr 1149 * @priv_data: hal_wbm_err_desc_info structure 1150 * @len: length of the private data 1151 * Return: void 1152 */ 1153 static inline void hal_rx_priv_info_set_in_tlv_be(uint8_t *buf, 1154 uint8_t *priv_data, 1155 uint32_t len) 1156 { 1157 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1158 uint32_t copy_len = (len > RX_BE_PADDING0_BYTES) ? 1159 RX_BE_PADDING0_BYTES : len; 1160 1161 qdf_mem_copy(&(HAL_RX_MSDU_END(pkt_tlvs).ppdu_start_timestamp_63_32), 1162 priv_data, copy_len); 1163 } 1164 1165 /** 1166 * hal_rx_priv_info_get_from_tlv_be(): retrieve the private data from 1167 * the reserved bytes of rx_tlv_hdr. 1168 * @buf: start of rx_tlv_hdr 1169 * @priv_data: Handle to get the private data, output parameter. 1170 * @len: length of the private data 1171 * Return: void 1172 */ 1173 static inline void hal_rx_priv_info_get_from_tlv_be(uint8_t *buf, 1174 uint8_t *priv_data, 1175 uint32_t len) 1176 { 1177 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1178 uint32_t copy_len = (len > RX_BE_PADDING0_BYTES) ? 1179 RX_BE_PADDING0_BYTES : len; 1180 1181 qdf_mem_copy(priv_data, 1182 &(HAL_RX_MSDU_END(pkt_tlvs).ppdu_start_timestamp_63_32), 1183 copy_len); 1184 } 1185 1186 /* 1187 * @ hal_rx_print_pn_be: Prints the PN of rx packet. 1188 * 1189 * @ buf: rx_tlv_hdr of the received packet 1190 * @ Return: void 1191 */ 1192 static inline void hal_rx_print_pn_be(uint8_t *buf) 1193 { 1194 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1195 1196 uint32_t pn_31_0 = HAL_RX_TLV_MPDU_PN_31_0_GET(rx_pkt_tlvs); 1197 uint32_t pn_63_32 = HAL_RX_TLV_MPDU_PN_63_32_GET(rx_pkt_tlvs); 1198 uint32_t pn_95_64 = HAL_RX_TLV_MPDU_PN_95_64_GET(rx_pkt_tlvs); 1199 1200 hal_debug("PN number pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 1201 pn_95_64, pn_63_32, pn_31_0); 1202 } 1203 1204 static inline void hal_rx_tlv_get_pn_num_be(uint8_t *buf, uint64_t *pn_num) 1205 { 1206 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1207 1208 pn_num[0] = HAL_RX_TLV_MPDU_PN_31_0_GET(pkt_tlvs); 1209 pn_num[0] |= ((uint64_t)HAL_RX_TLV_MPDU_PN_63_32_GET(pkt_tlvs) << 32); 1210 1211 pn_num[1] = HAL_RX_TLV_MPDU_PN_95_64_GET(pkt_tlvs); 1212 } 1213 #endif 1214 1215 /** 1216 * hal_rx_tlv_msdu_len_get(): API to get the MSDU length 1217 * from rx_msdu_start TLV 1218 * 1219 * @ buf: pointer to the start of RX PKT TLV headers 1220 * Return: msdu length 1221 */ 1222 static inline uint32_t hal_rx_tlv_msdu_len_get_be(uint8_t *buf) 1223 { 1224 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1225 1226 return HAL_RX_TLV_MSDU_LEN_GET(rx_pkt_tlvs); 1227 } 1228 1229 /** 1230 * hal_rx_tlv_msdu_len_set(): API to set the MSDU length 1231 * from rx_msdu_start TLV 1232 * 1233 * @buf: pointer to the start of RX PKT TLV headers 1234 * @len: msdu length 1235 * 1236 * Return: none 1237 */ 1238 static inline void hal_rx_tlv_msdu_len_set_be(uint8_t *buf, uint32_t len) 1239 { 1240 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1241 1242 HAL_RX_TLV_MSDU_LEN_GET(rx_pkt_tlvs) = len; 1243 } 1244 1245 /* 1246 * hal_rx_tlv_bw_get(): API to get the Bandwidth 1247 * Interval from rx_msdu_start 1248 * 1249 * @buf: pointer to the start of RX PKT TLV header 1250 * Return: uint32_t(bw) 1251 */ 1252 static inline uint32_t hal_rx_tlv_bw_get_be(uint8_t *buf) 1253 { 1254 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1255 1256 return HAL_RX_TLV_BW_GET(rx_pkt_tlvs); 1257 } 1258 1259 /** 1260 * hal_rx_tlv_toeplitz_get: API to get the toeplitz hash 1261 * from rx_msdu_start TLV 1262 * 1263 * @ buf: pointer to the start of RX PKT TLV headers 1264 * Return: toeplitz hash 1265 */ 1266 static inline uint32_t hal_rx_tlv_toeplitz_get_be(uint8_t *buf) 1267 { 1268 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1269 1270 return HAL_RX_TLV_FLOWID_TOEPLITZ_GET(rx_pkt_tlvs); 1271 } 1272 1273 /** 1274 * hal_rx_tlv_msdu_sgi_get(): API to get the Short Guard 1275 * Interval from rx_msdu_start TLV 1276 * 1277 * @buf: pointer to the start of RX PKT TLV headers 1278 * Return: uint32_t(sgi) 1279 */ 1280 static inline uint32_t hal_rx_tlv_sgi_get_be(uint8_t *buf) 1281 { 1282 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1283 1284 return HAL_RX_TLV_SGI_GET(rx_pkt_tlvs); 1285 } 1286 1287 /** 1288 * hal_rx_tlv_msdu_rate_mcs_get(): API to get the MCS rate 1289 * from rx_msdu_start TLV 1290 * 1291 * @buf: pointer to the start of RX PKT TLV headers 1292 * Return: uint32_t(rate_mcs) 1293 */ 1294 static inline uint32_t hal_rx_tlv_rate_mcs_get_be(uint8_t *buf) 1295 { 1296 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1297 uint32_t rate_mcs; 1298 1299 rate_mcs = HAL_RX_TLV_RATE_MCS_GET(rx_pkt_tlvs); 1300 1301 return rate_mcs; 1302 } 1303 1304 /* 1305 * Get key index from RX_MSDU_END 1306 */ 1307 /* 1308 * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet 1309 * from rx_msdu_end 1310 * 1311 * @buf: pointer to the start of RX PKT TLV header 1312 * Return: uint32_t(key id) 1313 */ 1314 1315 static inline uint8_t hal_rx_msdu_get_keyid_be(uint8_t *buf) 1316 { 1317 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1318 uint32_t keyid_octet; 1319 1320 keyid_octet = HAL_RX_TLV_KEYID_OCTET_GET(rx_pkt_tlvs); 1321 1322 return keyid_octet & 0x3; 1323 } 1324 1325 /* 1326 * hal_rx_tlv_get_rssi(): API to get the rssi of received pkt 1327 * from rx_msdu_start 1328 * 1329 * @buf: pointer to the start of RX PKT TLV header 1330 * Return: uint32_t(rssi) 1331 */ 1332 1333 static inline uint32_t hal_rx_tlv_get_rssi_be(uint8_t *buf) 1334 { 1335 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1336 uint32_t rssi; 1337 1338 rssi = HAL_RX_TLV_RSSI_GET(rx_pkt_tlvs); 1339 1340 return rssi; 1341 } 1342 1343 /* 1344 * hal_rx_tlv_get_freq(): API to get the frequency of operating channel 1345 * from rx_msdu_start 1346 * 1347 * @buf: pointer to the start of RX PKT TLV header 1348 * Return: uint32_t(frequency) 1349 */ 1350 1351 static inline uint32_t hal_rx_tlv_get_freq_be(uint8_t *buf) 1352 { 1353 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1354 uint32_t freq; 1355 1356 freq = HAL_RX_TLV_FREQ_GET(rx_pkt_tlvs); 1357 1358 return freq; 1359 } 1360 1361 1362 /* 1363 * hal_rx_tlv_get_pkt_type(): API to get the pkt type 1364 * from rx_msdu_start 1365 * 1366 * @buf: pointer to the start of RX PKT TLV header 1367 * Return: uint32_t(pkt type) 1368 */ 1369 1370 static inline uint32_t hal_rx_tlv_get_pkt_type_be(uint8_t *buf) 1371 { 1372 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1373 uint32_t pkt_type; 1374 1375 pkt_type = HAL_RX_TLV_PKT_TYPE_GET(rx_pkt_tlvs); 1376 1377 return pkt_type; 1378 } 1379 1380 /******************************************************************************* 1381 * RX ERROR APIS 1382 ******************************************************************************/ 1383 1384 /** 1385 * hal_rx_tlv_decrypt_err_get(): API to get the Decrypt ERR 1386 * from rx_mpdu_end TLV 1387 * 1388 * @buf: pointer to the start of RX PKT TLV headers 1389 * Return: uint32_t(decrypt_err) 1390 */ 1391 static inline uint32_t hal_rx_tlv_decrypt_err_get_be(uint8_t *buf) 1392 { 1393 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1394 uint32_t decrypt_err; 1395 1396 decrypt_err = HAL_RX_TLV_DECRYPT_ERR_GET(rx_pkt_tlvs); 1397 1398 return decrypt_err; 1399 } 1400 1401 /** 1402 * hal_rx_tlv_mic_err_get(): API to get the MIC ERR 1403 * from rx_tlv TLV 1404 * 1405 * @buf: pointer to the start of RX PKT TLV headers 1406 * Return: uint32_t(mic_err) 1407 */ 1408 static inline uint32_t hal_rx_tlv_mic_err_get_be(uint8_t *buf) 1409 { 1410 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1411 uint32_t mic_err; 1412 1413 mic_err = HAL_RX_TLV_MIC_ERR_GET(rx_pkt_tlvs); 1414 1415 return mic_err; 1416 } 1417 1418 /** 1419 * hal_get_reo_ent_desc_qdesc_addr_be(): API to get qdesc address of reo 1420 * entrance ring desc 1421 * 1422 * @desc: reo entrance ring descriptor 1423 * Return: qdesc address 1424 */ 1425 static inline uint8_t *hal_get_reo_ent_desc_qdesc_addr_be(uint8_t *desc) 1426 { 1427 return desc + REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET; 1428 } 1429 1430 /** 1431 * hal_set_reo_ent_desc_reo_dest_ind_be(): API to set reo destination 1432 * indication of reo entrance ring desc 1433 * 1434 * @desc: reo ent ring descriptor 1435 * @dst_ind: reo destination indication value 1436 * Return: None 1437 */ 1438 static inline void 1439 hal_set_reo_ent_desc_reo_dest_ind_be(uint8_t *desc, uint32_t dst_ind) 1440 { 1441 HAL_RX_FLD_SET(desc, REO_ENTRANCE_RING, 1442 REO_DESTINATION_INDICATION, dst_ind); 1443 } 1444 1445 /** 1446 * hal_rx_mpdu_sequence_number_get() - Get mpdu sequence number 1447 * @buf: pointer to packet buffer 1448 * 1449 * Return: mpdu sequence 1450 */ 1451 static inline int hal_rx_mpdu_sequence_number_get_be(uint8_t *buf) 1452 { 1453 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1454 1455 return HAL_RX_MPDU_SEQUENCE_NUMBER_GET(rx_pkt_tlvs); 1456 } 1457 1458 /** 1459 * hal_rx_msdu_packet_metadata_get(): API to get the 1460 * msdu information from rx_msdu_end TLV 1461 * 1462 * @ buf: pointer to the start of RX PKT TLV headers 1463 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1464 */ 1465 static inline void 1466 hal_rx_msdu_packet_metadata_get_generic_be(uint8_t *buf, 1467 void *pkt_msdu_metadata) 1468 { 1469 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1470 struct hal_rx_msdu_metadata *msdu_metadata = 1471 (struct hal_rx_msdu_metadata *)pkt_msdu_metadata; 1472 1473 msdu_metadata->l3_hdr_pad = 1474 HAL_RX_TLV_L3_HEADER_PADDING_GET(rx_pkt_tlvs); 1475 msdu_metadata->sa_idx = HAL_RX_TLV_SA_IDX_GET(rx_pkt_tlvs); 1476 msdu_metadata->da_idx = HAL_RX_TLV_DA_IDX_GET(rx_pkt_tlvs); 1477 msdu_metadata->sa_sw_peer_id = 1478 HAL_RX_TLV_SA_SW_PEER_ID_GET(rx_pkt_tlvs); 1479 } 1480 1481 /* 1482 * hal_rx_msdu_start_nss_get_kiwi(): API to get the NSS 1483 * Interval from rx_msdu_start 1484 * 1485 * @buf: pointer to the start of RX PKT TLV header 1486 * Return: uint32_t(nss) 1487 */ 1488 static inline uint32_t hal_rx_tlv_nss_get_be(uint8_t *buf) 1489 { 1490 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1491 uint8_t mimo_ss_bitmap; 1492 1493 mimo_ss_bitmap = HAL_RX_TLV_MIMO_SS_BITMAP(rx_pkt_tlvs); 1494 1495 return qdf_get_hweight8(mimo_ss_bitmap); 1496 } 1497 1498 #ifdef GET_MSDU_AGGREGATION 1499 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 1500 {\ 1501 bool first_msdu, last_msdu; \ 1502 first_msdu = HAL_RX_TLV_FIRST_MSDU_GET(rx_desc);\ 1503 last_msdu = HAL_RX_TLV_LAST_MSDU_GET(rx_desc);\ 1504 if (first_msdu && last_msdu)\ 1505 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 1506 else\ 1507 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 1508 } \ 1509 1510 #define HAL_RX_SET_MSDU_AGGREGATION((rs_mpdu), (rs_ppdu))\ 1511 {\ 1512 if (rs_mpdu->rs_flags & IEEE80211_AMSDU_FLAG)\ 1513 rs_ppdu->rs_flags |= IEEE80211_AMSDU_FLAG;\ 1514 } \ 1515 1516 #else 1517 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 1518 #define HAL_RX_SET_MSDU_AGGREGATION(rs_mpdu, rs_ppdu) 1519 #endif 1520 1521 /** 1522 * hal_rx_mon_hw_desc_get_mpdu_status_be(): Retrieve MPDU status 1523 * 1524 * @ hw_desc_addr: Start address of Rx HW TLVs 1525 * @ rs: Status for monitor mode 1526 * 1527 * Return: void 1528 */ 1529 static inline void 1530 hal_rx_mon_hw_desc_get_mpdu_status_be(void *hw_desc_addr, 1531 struct mon_rx_status *rs) 1532 { 1533 uint32_t reg_value; 1534 struct rx_pkt_tlvs *rx_desc = 1535 (struct rx_pkt_tlvs *)hw_desc_addr; 1536 const uint32_t sgi_hw_to_cdp[] = { 1537 CDP_SGI_0_8_US, 1538 CDP_SGI_0_4_US, 1539 CDP_SGI_1_6_US, 1540 CDP_SGI_3_2_US, 1541 }; 1542 1543 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 1544 1545 rs->ant_signal_db = HAL_RX_TLV_ANT_SIGNAL_DB_GET(rx_desc); 1546 rs->is_stbc = HAL_RX_TLV_STBC_GET(rx_desc); 1547 1548 reg_value = HAL_RX_TLV_SGI_GET(rx_desc); 1549 rs->sgi = sgi_hw_to_cdp[reg_value]; 1550 1551 reg_value = HAL_RX_TLV_RECEPTION_TYPE_GET(rx_desc); 1552 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 1553 /* TODO: rs->beamformed should be set for SU beamforming also */ 1554 } 1555 1556 static inline uint32_t hal_rx_tlv_tid_get_be(uint8_t *buf) 1557 { 1558 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1559 uint32_t tid; 1560 1561 tid = HAL_RX_TLV_TID_GET(rx_pkt_tlvs); 1562 1563 return tid; 1564 } 1565 1566 /* 1567 * hal_rx_tlv_reception_type_get(): API to get the reception type 1568 * Interval from rx_msdu_start 1569 * 1570 * @buf: pointer to the start of RX PKT TLV header 1571 * Return: uint32_t(reception_type) 1572 */ 1573 static inline 1574 uint32_t hal_rx_tlv_reception_type_get_be(uint8_t *buf) 1575 { 1576 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1577 uint32_t reception_type; 1578 1579 reception_type = HAL_RX_TLV_RECEPTION_TYPE_GET(rx_pkt_tlvs); 1580 1581 return reception_type; 1582 } 1583 1584 /** 1585 * hal_rx_msdu_end_da_idx_get_be: API to get da_idx 1586 * from rx_msdu_end TLV 1587 * 1588 * @ buf: pointer to the start of RX PKT TLV headers 1589 * Return: da index 1590 */ 1591 static inline uint16_t hal_rx_msdu_end_da_idx_get_be(uint8_t *buf) 1592 { 1593 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1594 uint16_t da_idx; 1595 1596 da_idx = HAL_RX_TLV_DA_IDX_GET(rx_pkt_tlvs); 1597 1598 return da_idx; 1599 } 1600 1601 /** 1602 * hal_rx_get_rx_fragment_number_be(): Function to retrieve rx fragment number 1603 * 1604 * @nbuf: Network buffer 1605 * Returns: rx fragment number 1606 */ 1607 static inline 1608 uint8_t hal_rx_get_rx_fragment_number_be(uint8_t *buf) 1609 { 1610 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1611 1612 /* Return first 4 bits as fragment number */ 1613 return (HAL_RX_MPDU_SEQUENCE_NUMBER_GET(rx_pkt_tlvs) & 1614 DOT11_SEQ_FRAG_MASK); 1615 } 1616 1617 /** 1618 * hal_rx_msdu_end_da_is_mcbc_get_be(): API to check if pkt is MCBC 1619 * from rx_msdu_end TLV 1620 * 1621 * @ buf: pointer to the start of RX PKT TLV headers 1622 * Return: da_is_mcbc 1623 */ 1624 static inline uint8_t 1625 hal_rx_tlv_da_is_mcbc_get_be(uint8_t *buf) 1626 { 1627 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1628 1629 return HAL_RX_TLV_DA_IS_MCBC_GET(rx_pkt_tlvs); 1630 } 1631 1632 /** 1633 * hal_rx_tlv_is_tkip_mic_err_get_be(): API to get tkip Mic error 1634 * from rx_msdu_end TLV 1635 * 1636 * @ buf: pointer to the start of RX PKT TLV headers 1637 * Return: tkip_mic_err 1638 */ 1639 static inline uint8_t 1640 hal_rx_tlv_is_tkip_mic_err_get_be(uint8_t *buf) 1641 { 1642 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1643 1644 return HAL_RX_TLV_IS_TKIP_MIC_ERR_GET(rx_pkt_tlvs); 1645 } 1646 1647 /** 1648 * hal_rx_tlvd_sa_is_valid_get_be(): API to get the sa_is_valid bit from 1649 * rx_msdu_end TLV 1650 * 1651 * @ buf: pointer to the start of RX PKT TLV headers 1652 * Return: sa_is_valid bit 1653 */ 1654 static inline uint8_t 1655 hal_rx_tlv_sa_is_valid_get_be(uint8_t *buf) 1656 { 1657 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1658 uint8_t sa_is_valid; 1659 1660 sa_is_valid = HAL_RX_TLV_SA_IS_VALID_GET(rx_pkt_tlvs); 1661 1662 return sa_is_valid; 1663 } 1664 1665 /** 1666 * hal_rx_tlv_sa_idx_get_be(): API to get the sa_idx from rx_msdu_end TLV 1667 * 1668 * @ buf: pointer to the start of RX PKT TLV headers 1669 * Return: sa_idx (SA AST index) 1670 */ 1671 static inline 1672 uint16_t hal_rx_tlv_sa_idx_get_be(uint8_t *buf) 1673 { 1674 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1675 uint16_t sa_idx; 1676 1677 sa_idx = HAL_RX_TLV_SA_IDX_GET(rx_pkt_tlvs); 1678 1679 return sa_idx; 1680 } 1681 1682 /** 1683 * hal_rx_desc_is_first_msdu_be() - Check if first msdu 1684 * 1685 * @hal_soc_hdl: hal_soc handle 1686 * @hw_desc_addr: hardware descriptor address 1687 * 1688 * Return: 0 - success/ non-zero failure 1689 */ 1690 static inline uint32_t hal_rx_desc_is_first_msdu_be(void *hw_desc_addr) 1691 { 1692 struct rx_pkt_tlvs *rx_pkt_tlvs = 1693 (struct rx_pkt_tlvs *)hw_desc_addr; 1694 1695 return HAL_RX_TLV_FIRST_MSDU_GET(rx_pkt_tlvs); 1696 } 1697 1698 /** 1699 * hal_rx_tlv_l3_hdr_padding_get_be(): API to get the l3_header padding 1700 * from rx_msdu_end TLV 1701 * 1702 * @ buf: pointer to the start of RX PKT TLV headers 1703 * Return: number of l3 header padding bytes 1704 */ 1705 static inline uint32_t hal_rx_tlv_l3_hdr_padding_get_be(uint8_t *buf) 1706 { 1707 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1708 uint32_t l3_header_padding; 1709 1710 l3_header_padding = HAL_RX_TLV_L3_HEADER_PADDING_GET(rx_pkt_tlvs); 1711 1712 return l3_header_padding; 1713 } 1714 1715 /* 1716 * @ hal_rx_encryption_info_valid_be: Returns encryption type. 1717 * 1718 * @ buf: rx_tlv_hdr of the received packet 1719 * @ Return: encryption type 1720 */ 1721 static inline uint32_t hal_rx_encryption_info_valid_be(uint8_t *buf) 1722 { 1723 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1724 uint32_t encryption_info = 1725 HAL_RX_TLV_MPDU_ENCRYPTION_INFO_VALID(rx_pkt_tlvs); 1726 1727 return encryption_info; 1728 } 1729 1730 /** 1731 * hal_rx_tlv_first_msdu_get_be: API to get first msdu status 1732 * from rx_msdu_end TLV 1733 * 1734 * @ buf: pointer to the start of RX PKT TLV headers 1735 * Return: first_msdu 1736 */ 1737 static inline uint8_t hal_rx_tlv_first_msdu_get_be(uint8_t *buf) 1738 { 1739 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1740 uint8_t first_msdu; 1741 1742 first_msdu = HAL_RX_TLV_FIRST_MSDU_GET(rx_pkt_tlvs); 1743 1744 return first_msdu; 1745 } 1746 1747 /** 1748 * hal_rx_tlv_da_is_valid_get_be: API to check if da is valid 1749 * from rx_msdu_end TLV 1750 * 1751 * @ buf: pointer to the start of RX PKT TLV headers 1752 * Return: da_is_valid 1753 */ 1754 static inline uint8_t hal_rx_tlv_da_is_valid_get_be(uint8_t *buf) 1755 { 1756 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1757 uint8_t da_is_valid; 1758 1759 da_is_valid = HAL_RX_TLV_DA_IS_VALID_GET(rx_pkt_tlvs); 1760 1761 return da_is_valid; 1762 } 1763 1764 /** 1765 * hal_rx_tlv_last_msdu_get_be: API to get last msdu status 1766 * from rx_msdu_end TLV 1767 * 1768 * @ buf: pointer to the start of RX PKT TLV headers 1769 * Return: last_msdu 1770 */ 1771 static inline uint8_t hal_rx_tlv_last_msdu_get_be(uint8_t *buf) 1772 { 1773 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1774 uint8_t last_msdu; 1775 1776 last_msdu = HAL_RX_TLV_LAST_MSDU_GET(rx_pkt_tlvs); 1777 1778 return last_msdu; 1779 } 1780 1781 /* 1782 * hal_rx_get_mpdu_mac_ad4_valid_be(): Retrieves if mpdu 4th addr is valid 1783 * 1784 * @nbuf: Network buffer 1785 * Returns: value of mpdu 4th address valid field 1786 */ 1787 static inline bool hal_rx_get_mpdu_mac_ad4_valid_be(uint8_t *buf) 1788 { 1789 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1790 bool ad4_valid = 0; 1791 1792 ad4_valid = HAL_RX_TLV_MPDU_MAC_ADDR_AD4_VALID_GET(rx_pkt_tlvs); 1793 1794 return ad4_valid; 1795 } 1796 1797 /** 1798 * hal_rx_mpdu_start_sw_peer_id_get_be: Retrieve sw peer_id 1799 * @buf: network buffer 1800 * 1801 * Return: sw peer_id 1802 */ 1803 static inline uint32_t hal_rx_mpdu_start_sw_peer_id_get_be(uint8_t *buf) 1804 { 1805 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1806 1807 return HAL_RX_TLV_SW_PEER_ID_GET(rx_pkt_tlvs); 1808 } 1809 1810 /** 1811 * hal_rx_mpdu_get_to_ds_be(): API to get the tods info 1812 * from rx_mpdu_start 1813 * 1814 * @buf: pointer to the start of RX PKT TLV header 1815 * Return: uint32_t(to_ds) 1816 */ 1817 static inline uint32_t hal_rx_mpdu_get_to_ds_be(uint8_t *buf) 1818 { 1819 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1820 1821 return HAL_RX_TLV_MPDU_GET_TODS(rx_pkt_tlvs); 1822 } 1823 1824 /* 1825 * hal_rx_mpdu_get_fr_ds_be(): API to get the from ds info 1826 * from rx_mpdu_start 1827 * 1828 * @buf: pointer to the start of RX PKT TLV header 1829 * Return: uint32_t(fr_ds) 1830 */ 1831 static inline uint32_t hal_rx_mpdu_get_fr_ds_be(uint8_t *buf) 1832 { 1833 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1834 1835 return HAL_RX_TLV_MPDU_GET_FROMDS(rx_pkt_tlvs); 1836 } 1837 1838 /* 1839 * hal_rx_get_mpdu_frame_control_valid_be(): Retrieves mpdu 1840 * frame control valid 1841 * 1842 * @nbuf: Network buffer 1843 * Returns: value of frame control valid field 1844 */ 1845 static inline uint8_t hal_rx_get_mpdu_frame_control_valid_be(uint8_t *buf) 1846 { 1847 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1848 1849 return HAL_RX_TLV_MPDU_GET_FRAME_CONTROL_VALID(rx_pkt_tlvs); 1850 } 1851 1852 /* 1853 * hal_rx_mpdu_get_addr2_be(): API to check get address2 of the mpdu 1854 * in the packet 1855 * 1856 * @buf: pointer to the start of RX PKT TLV header 1857 * @mac_addr: pointer to mac address 1858 * Return: success/failure 1859 */ 1860 static inline QDF_STATUS hal_rx_mpdu_get_addr2_be(uint8_t *buf, 1861 uint8_t *mac_addr) 1862 { 1863 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1864 struct __attribute__((__packed__)) hal_addr2 { 1865 uint16_t ad2_15_0; 1866 uint32_t ad2_47_16; 1867 }; 1868 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 1869 uint32_t mac_addr_ad2_valid; 1870 1871 mac_addr_ad2_valid = HAL_RX_TLV_MPDU_MAC_ADDR_AD2_VALID_GET(rx_pkt_tlvs); 1872 1873 if (mac_addr_ad2_valid) { 1874 addr->ad2_15_0 = HAL_RX_TLV_MPDU_AD2_15_0_GET(rx_pkt_tlvs); 1875 addr->ad2_47_16 = HAL_RX_TLV_MPDU_AD2_47_16_GET(rx_pkt_tlvs); 1876 return QDF_STATUS_SUCCESS; 1877 } 1878 1879 return QDF_STATUS_E_FAILURE; 1880 } 1881 1882 /* 1883 * hal_rx_mpdu_get_addr3_be(): API to get address3 of the mpdu 1884 * in the packet 1885 * 1886 * @buf: pointer to the start of RX PKT TLV header 1887 * @mac_addr: pointer to mac address 1888 * Return: success/failure 1889 */ 1890 static inline QDF_STATUS hal_rx_mpdu_get_addr3_be(uint8_t *buf, 1891 uint8_t *mac_addr) 1892 { 1893 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1894 struct __attribute__((__packed__)) hal_addr3 { 1895 uint32_t ad3_31_0; 1896 uint16_t ad3_47_32; 1897 }; 1898 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 1899 uint32_t mac_addr_ad3_valid; 1900 1901 mac_addr_ad3_valid = HAL_RX_TLV_MPDU_MAC_ADDR_AD3_VALID_GET(rx_pkt_tlvs); 1902 1903 if (mac_addr_ad3_valid) { 1904 addr->ad3_31_0 = HAL_RX_TLV_MPDU_AD3_31_0_GET(rx_pkt_tlvs); 1905 addr->ad3_47_32 = HAL_RX_TLV_MPDU_AD3_47_32_GET(rx_pkt_tlvs); 1906 return QDF_STATUS_SUCCESS; 1907 } 1908 1909 return QDF_STATUS_E_FAILURE; 1910 } 1911 1912 /* 1913 * hal_rx_get_mpdu_sequence_control_valid_be(): Get mpdu 1914 * sequence control valid 1915 * 1916 * @nbuf: Network buffer 1917 * Returns: value of sequence control valid field 1918 */ 1919 static inline uint8_t hal_rx_get_mpdu_sequence_control_valid_be(uint8_t *buf) 1920 { 1921 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1922 1923 return HAL_RX_TLV_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_pkt_tlvs); 1924 } 1925 1926 /** 1927 * hal_rx_tid_get_be: get tid based on qos control valid. 1928 * @hal_soc_hdl: hal_soc handle 1929 * @ buf: pointer to rx pkt TLV. 1930 * 1931 * Return: tid 1932 */ 1933 static inline uint32_t hal_rx_tid_get_be(hal_soc_handle_t hal_soc_hdl, 1934 uint8_t *buf) 1935 { 1936 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1937 uint8_t qos_control_valid = 1938 HAL_RX_TLV_MPDU_QOS_CONTROL_VALID_GET(rx_pkt_tlvs); 1939 1940 if (qos_control_valid) 1941 return hal_rx_tlv_tid_get_be(buf); 1942 1943 return HAL_RX_NON_QOS_TID; 1944 } 1945 1946 static inline 1947 uint8_t hal_rx_get_fc_valid_be(uint8_t *buf) 1948 { 1949 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1950 1951 return HAL_RX_TLV_GET_FC_VALID(rx_pkt_tlvs); 1952 } 1953 1954 static inline uint8_t hal_rx_get_to_ds_flag_be(uint8_t *buf) 1955 { 1956 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1957 1958 return HAL_RX_TLV_GET_TO_DS_FLAG(rx_pkt_tlvs); 1959 } 1960 1961 static inline uint8_t hal_rx_get_mac_addr2_valid_be(uint8_t *buf) 1962 { 1963 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1964 1965 return HAL_RX_TLV_MPDU_MAC_ADDR_AD2_VALID_GET(rx_pkt_tlvs); 1966 } 1967 1968 /** 1969 * hal_rx_msdu_flow_idx_get_be: API to get flow index 1970 * from rx_msdu_end TLV 1971 * @buf: pointer to the start of RX PKT TLV headers 1972 * 1973 * Return: flow index value from MSDU END TLV 1974 */ 1975 static inline uint32_t hal_rx_msdu_flow_idx_get_be(uint8_t *buf) 1976 { 1977 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1978 1979 return HAL_RX_TLV_FLOW_IDX_GET(pkt_tlvs); 1980 } 1981 1982 /** 1983 * hal_rx_msdu_get_reo_destination_indication_be: API to get 1984 * reo_destination_indication from rx_msdu_end TLV 1985 * @buf: pointer to the start of RX PKT TLV headers 1986 * @reo_destination_indication: pointer to return value of 1987 * reo_destination_indication 1988 * 1989 * Return: none 1990 */ 1991 static inline void 1992 hal_rx_msdu_get_reo_destination_indication_be(uint8_t *buf, 1993 uint32_t *reo_destination_indication) 1994 { 1995 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1996 1997 *reo_destination_indication = HAL_RX_TLV_REO_DEST_IND_GET(pkt_tlvs); 1998 } 1999 2000 /** 2001 * hal_rx_msdu_flow_idx_invalid_be: API to get flow index invalid 2002 * from rx_msdu_end TLV 2003 * @buf: pointer to the start of RX PKT TLV headers 2004 * 2005 * Return: flow index invalid value from MSDU END TLV 2006 */ 2007 static inline bool hal_rx_msdu_flow_idx_invalid_be(uint8_t *buf) 2008 { 2009 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2010 2011 return HAL_RX_TLV_FLOW_IDX_INVALID_GET(pkt_tlvs); 2012 } 2013 2014 /** 2015 * hal_rx_msdu_flow_idx_timeout_be: API to get flow index timeout 2016 * from rx_msdu_end TLV 2017 * @buf: pointer to the start of RX PKT TLV headers 2018 * 2019 * Return: flow index timeout value from MSDU END TLV 2020 */ 2021 static inline bool hal_rx_msdu_flow_idx_timeout_be(uint8_t *buf) 2022 { 2023 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2024 2025 return HAL_RX_TLV_FLOW_IDX_TIMEOUT_GET(pkt_tlvs); 2026 } 2027 2028 /** 2029 * hal_rx_msdu_fse_metadata_get_be: API to get FSE metadata 2030 * from rx_msdu_end TLV 2031 * @buf: pointer to the start of RX PKT TLV headers 2032 * 2033 * Return: fse metadata value from MSDU END TLV 2034 */ 2035 static inline uint32_t hal_rx_msdu_fse_metadata_get_be(uint8_t *buf) 2036 { 2037 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2038 2039 return HAL_RX_TLV_FSE_METADATA_GET(pkt_tlvs); 2040 } 2041 2042 /** 2043 * hal_rx_msdu_cce_metadata_get_be: API to get CCE metadata 2044 * from rx_msdu_end TLV 2045 * @buf: pointer to the start of RX PKT TLV headers 2046 * 2047 * Return: cce_metadata 2048 */ 2049 static inline uint16_t 2050 hal_rx_msdu_cce_metadata_get_be(uint8_t *buf) 2051 { 2052 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2053 2054 return HAL_RX_TLV_CCE_METADATA_GET(pkt_tlvs); 2055 } 2056 2057 /** 2058 * hal_rx_msdu_get_flow_params_be: API to get flow index, flow index invalid 2059 * and flow index timeout from rx_msdu_end TLV 2060 * @buf: pointer to the start of RX PKT TLV headers 2061 * @flow_invalid: pointer to return value of flow_idx_valid 2062 * @flow_timeout: pointer to return value of flow_idx_timeout 2063 * @flow_index: pointer to return value of flow_idx 2064 * 2065 * Return: none 2066 */ 2067 static inline void 2068 hal_rx_msdu_get_flow_params_be(uint8_t *buf, 2069 bool *flow_invalid, 2070 bool *flow_timeout, 2071 uint32_t *flow_index) 2072 { 2073 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2074 2075 *flow_invalid = HAL_RX_TLV_FLOW_IDX_INVALID_GET(pkt_tlvs); 2076 *flow_timeout = HAL_RX_TLV_FLOW_IDX_TIMEOUT_GET(pkt_tlvs); 2077 *flow_index = HAL_RX_TLV_FLOW_IDX_GET(pkt_tlvs); 2078 } 2079 2080 /** 2081 * hal_rx_tlv_get_tcp_chksum_be() - API to get tcp checksum 2082 * @buf: rx_tlv_hdr 2083 * 2084 * Return: tcp checksum 2085 */ 2086 static inline uint16_t 2087 hal_rx_tlv_get_tcp_chksum_be(uint8_t *buf) 2088 { 2089 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2090 2091 return HAL_RX_TLV_GET_TCP_CHKSUM(rx_pkt_tlvs); 2092 } 2093 2094 /** 2095 * hal_rx_get_rx_sequence_be(): Function to retrieve rx sequence number 2096 * 2097 * @nbuf: Network buffer 2098 * Returns: rx sequence number 2099 */ 2100 static inline 2101 uint16_t hal_rx_get_rx_sequence_be(uint8_t *buf) 2102 { 2103 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2104 2105 return HAL_RX_MPDU_SEQUENCE_NUMBER_GET(rx_pkt_tlvs); 2106 } 2107 2108 #ifdef RECEIVE_OFFLOAD 2109 #ifdef QCA_WIFI_KIWI_V2 2110 static inline 2111 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_be(uint8_t *buf) 2112 { 2113 /* 2114 * cumulative l4 checksum is not supported in V2 and 2115 * cumulative_l4_checksum field is not present 2116 */ 2117 return 0; 2118 } 2119 #else 2120 /** 2121 * hal_rx_get_fisa_cumulative_l4_checksum_be() - Retrieve cumulative 2122 * checksum 2123 * @buf: buffer pointer 2124 * 2125 * Return: cumulative checksum 2126 */ 2127 static inline 2128 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_be(uint8_t *buf) 2129 { 2130 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2131 2132 return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(rx_pkt_tlvs); 2133 } 2134 #endif 2135 2136 /** 2137 * hal_rx_get_fisa_cumulative_ip_length_be() - Retrieve cumulative 2138 * ip length 2139 * @buf: buffer pointer 2140 * 2141 * Return: cumulative length 2142 */ 2143 static inline 2144 uint16_t hal_rx_get_fisa_cumulative_ip_length_be(uint8_t *buf) 2145 { 2146 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2147 2148 return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(rx_pkt_tlvs); 2149 } 2150 2151 /** 2152 * hal_rx_get_udp_proto_be() - Retrieve udp proto value 2153 * @buf: buffer 2154 * 2155 * Return: udp proto bit 2156 */ 2157 static inline 2158 bool hal_rx_get_udp_proto_be(uint8_t *buf) 2159 { 2160 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2161 2162 return HAL_RX_TLV_GET_UDP_PROTO(rx_pkt_tlvs); 2163 } 2164 #endif 2165 2166 /** 2167 * hal_rx_get_flow_agg_continuation_be() - retrieve flow agg 2168 * continuation 2169 * @buf: buffer 2170 * 2171 * Return: flow agg 2172 */ 2173 static inline 2174 bool hal_rx_get_flow_agg_continuation_be(uint8_t *buf) 2175 { 2176 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2177 2178 return HAL_RX_TLV_GET_FLOW_AGGR_CONT(rx_pkt_tlvs); 2179 } 2180 2181 /** 2182 * hal_rx_get_flow_agg_count_be()- Retrieve flow agg count 2183 * @buf: buffer 2184 * 2185 * Return: flow agg count 2186 */ 2187 static inline 2188 uint8_t hal_rx_get_flow_agg_count_be(uint8_t *buf) 2189 { 2190 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2191 2192 return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(rx_pkt_tlvs); 2193 } 2194 2195 /** 2196 * hal_rx_get_fisa_timeout_be() - Retrieve fisa timeout 2197 * @buf: buffer 2198 * 2199 * Return: fisa timeout 2200 */ 2201 static inline 2202 bool hal_rx_get_fisa_timeout_be(uint8_t *buf) 2203 { 2204 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2205 2206 return HAL_RX_TLV_GET_FISA_TIMEOUT(rx_pkt_tlvs); 2207 } 2208 2209 /** 2210 * hal_rx_mpdu_start_tlv_tag_valid_be () - API to check if RX_MPDU_START 2211 * tlv tag is valid 2212 * 2213 *@rx_tlv_hdr: start address of rx_pkt_tlvs 2214 * 2215 * Return: true if RX_MPDU_START is valid, else false. 2216 */ 2217 static inline uint8_t hal_rx_mpdu_start_tlv_tag_valid_be(void *rx_tlv_hdr) 2218 { 2219 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 2220 uint32_t tlv_tag; 2221 2222 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 2223 2224 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 2225 } 2226 2227 /** 2228 * hal_rx_msdu_end_offset_get_generic(): API to get the 2229 * msdu_end structure offset rx_pkt_tlv structure 2230 * 2231 * NOTE: API returns offset of msdu_end TLV from structure 2232 * rx_pkt_tlvs 2233 */ 2234 static inline uint32_t hal_rx_msdu_end_offset_get_generic(void) 2235 { 2236 return RX_PKT_TLV_OFFSET(msdu_end_tlv); 2237 } 2238 2239 /** 2240 * hal_rx_mpdu_start_offset_get_generic(): API to get the 2241 * mpdu_start structure offset rx_pkt_tlv structure 2242 * 2243 * NOTE: API returns offset of attn TLV from structure 2244 * rx_pkt_tlvs 2245 */ 2246 static inline uint32_t hal_rx_mpdu_start_offset_get_generic(void) 2247 { 2248 return RX_PKT_TLV_OFFSET(mpdu_start_tlv); 2249 } 2250 2251 #ifndef NO_RX_PKT_HDR_TLV 2252 static inline uint32_t hal_rx_pkt_tlv_offset_get_generic(void) 2253 { 2254 return RX_PKT_TLV_OFFSET(pkt_hdr_tlv); 2255 } 2256 #endif 2257 2258 #ifdef CONFIG_WORD_BASED_TLV 2259 #define MPDU_START_WMASK 0x074C 2260 #define MSDU_END_WMASK 0x13FC1 2261 2262 /** 2263 * hal_rx_mpdu_start_wmask_get_be(): API to get the mpdu_start_tlv word mask 2264 * 2265 * return: Word mask for MPDU start tlv 2266 */ 2267 static inline uint32_t hal_rx_mpdu_start_wmask_get_be(void) 2268 { 2269 return MPDU_START_WMASK; 2270 } 2271 2272 /** 2273 * hal_rx_msdu_end_wmask_get_be(): API to get the msdu_end_tlv word mask 2274 * 2275 * return: Word mask for MSDU end tlv 2276 */ 2277 static inline uint32_t hal_rx_msdu_end_wmask_get_be(void) 2278 { 2279 return MSDU_END_WMASK; 2280 } 2281 #endif 2282 2283 #ifdef RECEIVE_OFFLOAD 2284 static inline int 2285 hal_rx_tlv_get_offload_info_be(uint8_t *rx_tlv, 2286 struct hal_offload_info *offload_info) 2287 { 2288 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)rx_tlv; 2289 2290 offload_info->lro_eligible = HAL_RX_TLV_GET_LRO_ELIGIBLE(rx_pkt_tlvs); 2291 offload_info->flow_id = HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(rx_pkt_tlvs); 2292 offload_info->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_pkt_tlvs); 2293 offload_info->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_pkt_tlvs); 2294 2295 if (offload_info->tcp_proto) { 2296 offload_info->tcp_pure_ack = 2297 HAL_RX_TLV_GET_TCP_PURE_ACK(rx_pkt_tlvs); 2298 offload_info->tcp_offset = 2299 HAL_RX_TLV_GET_TCP_OFFSET(rx_pkt_tlvs); 2300 offload_info->tcp_win = HAL_RX_TLV_GET_TCP_WIN(rx_pkt_tlvs); 2301 offload_info->tcp_seq_num = HAL_RX_TLV_GET_TCP_SEQ(rx_pkt_tlvs); 2302 offload_info->tcp_ack_num = HAL_RX_TLV_GET_TCP_ACK(rx_pkt_tlvs); 2303 } 2304 return 0; 2305 } 2306 2307 static inline int hal_rx_get_proto_params_be(uint8_t *buf, void *proto_params) 2308 { 2309 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2310 struct hal_proto_params *param = 2311 (struct hal_proto_params *)proto_params; 2312 2313 param->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_pkt_tlvs); 2314 param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(rx_pkt_tlvs); 2315 param->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_pkt_tlvs); 2316 2317 return 0; 2318 } 2319 2320 static inline int hal_rx_get_l3_l4_offsets_be(uint8_t *buf, 2321 uint32_t *l3_hdr_offset, 2322 uint32_t *l4_hdr_offset) 2323 { 2324 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2325 2326 *l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(rx_pkt_tlvs); 2327 *l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_pkt_tlvs); 2328 2329 return 0; 2330 } 2331 #endif 2332 2333 /** 2334 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 2335 * from rx_msdu_start TLV 2336 * 2337 * @ buf: pointer to the start of RX PKT TLV headers 2338 * Return: msdu length 2339 */ 2340 static inline uint32_t hal_rx_msdu_start_msdu_len_get_be(uint8_t *buf) 2341 { 2342 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2343 uint32_t msdu_len; 2344 2345 msdu_len = HAL_RX_TLV_MSDU_LEN_GET(rx_pkt_tlvs); 2346 2347 return msdu_len; 2348 } 2349 2350 /** 2351 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2352 * 2353 * @nbuf: Network buffer 2354 * Returns: rx more fragment bit 2355 * 2356 */ 2357 static inline uint16_t hal_rx_get_frame_ctrl_field_be(uint8_t *buf) 2358 { 2359 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2360 uint16_t frame_ctrl = 0; 2361 2362 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_pkt_tlvs); 2363 2364 return frame_ctrl; 2365 } 2366 2367 /* 2368 * hal_rx_tlv_get_is_decrypted_be(): API to get the decrypt status of the 2369 * packet from msdu_end 2370 * 2371 * @buf: pointer to the start of RX PKT TLV header 2372 * Return: uint32_t(decryt status) 2373 */ 2374 static inline uint32_t hal_rx_tlv_get_is_decrypted_be(uint8_t *buf) 2375 { 2376 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2377 uint32_t is_decrypt = 0; 2378 uint32_t decrypt_status; 2379 2380 decrypt_status = HAL_RX_TLV_DECRYPT_STATUS_GET(rx_pkt_tlvs); 2381 2382 if (!decrypt_status) 2383 is_decrypt = 1; 2384 2385 return is_decrypt; 2386 } 2387 2388 #ifdef NO_RX_PKT_HDR_TLV 2389 /** 2390 * hal_rx_pkt_hdr_get_be(): API to get 80211 header 2391 * @buf: start of rx_pkt_tlv 2392 * 2393 * If NO_RX_PKT_HDR_TLV is enabled, then this API assume caller gives a raw 2394 * data, get 80211 header from packet data directly. 2395 * If NO_RX_PKT_HDR_TLV is disabled, then get it from rx_pkt_hdr_tlv in 2396 * rx_pkt_tlvs. 2397 * 2398 * Return: pointer to start of 80211 header 2399 */ 2400 static inline uint8_t *hal_rx_pkt_hdr_get_be(uint8_t *buf) 2401 { 2402 return buf + RX_PKT_TLVS_LEN; 2403 } 2404 #else 2405 static inline uint8_t *hal_rx_pkt_hdr_get_be(uint8_t *buf) 2406 { 2407 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2408 2409 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 2410 } 2411 #endif 2412 2413 /** 2414 * hal_rx_tlv_csum_err_get_be() - Get IP and tcp-udp checksum fail flag 2415 * @rx_tlv_hdr: start address of rx_tlv_hdr 2416 * @ip_csum_err: buffer to return ip_csum_fail flag 2417 * @tcp_udp_csum_fail: placeholder to return tcp-udp checksum fail flag 2418 * 2419 * Return: None 2420 */ 2421 static inline void 2422 hal_rx_tlv_csum_err_get_be(uint8_t *rx_tlv_hdr, uint32_t *ip_csum_err, 2423 uint32_t *tcp_udp_csum_err) 2424 { 2425 struct rx_pkt_tlvs *rx_pkt_tlvs = 2426 (struct rx_pkt_tlvs *)rx_tlv_hdr; 2427 2428 *ip_csum_err = HAL_RX_TLV_IP_CSUM_FAIL_GET(rx_pkt_tlvs); 2429 *tcp_udp_csum_err = HAL_RX_TLV_TCP_UDP_CSUM_FAIL_GET(rx_pkt_tlvs); 2430 } 2431 2432 static inline 2433 uint32_t hal_rx_tlv_mpdu_len_err_get_be(void *hw_desc_addr) 2434 { 2435 struct rx_pkt_tlvs *rx_pkt_tlvs = 2436 (struct rx_pkt_tlvs *)hw_desc_addr; 2437 2438 return HAL_RX_TLV_MPDU_LEN_ERR_GET(rx_pkt_tlvs); 2439 } 2440 2441 static inline 2442 uint32_t hal_rx_tlv_mpdu_fcs_err_get_be(void *hw_desc_addr) 2443 { 2444 struct rx_pkt_tlvs *rx_pkt_tlvs = 2445 (struct rx_pkt_tlvs *)hw_desc_addr; 2446 2447 return HAL_RX_TLV_MPDU_FCS_ERR_GET(rx_pkt_tlvs); 2448 } 2449 2450 /** 2451 * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit 2452 * 2453 * @nbuf: Network buffer 2454 * Returns: rx more fragment bit 2455 */ 2456 static inline 2457 uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) 2458 { 2459 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2460 uint16_t frame_ctrl = 0; 2461 2462 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(pkt_tlvs) >> 2463 DOT11_FC1_MORE_FRAG_OFFSET; 2464 2465 /* more fragment bit if at offset bit 4 */ 2466 return frame_ctrl; 2467 } 2468 2469 /* 2470 * hal_rx_msdu_is_wlan_mcast_generic_be(): Check if the buffer is for multicast 2471 * address 2472 * @nbuf: Network buffer 2473 * 2474 * Returns: flag to indicate whether the nbuf has MC/BC address 2475 */ 2476 static inline uint32_t hal_rx_msdu_is_wlan_mcast_generic_be(qdf_nbuf_t nbuf) 2477 { 2478 uint8_t *buf = qdf_nbuf_data(nbuf); 2479 2480 return HAL_RX_TLV_IS_MCAST_GET(buf);; 2481 } 2482 2483 /** 2484 * hal_rx_msdu_start_msdu_len_set_be(): API to set the MSDU length 2485 * from rx_msdu_start TLV 2486 * 2487 * @buf: pointer to the start of RX PKT TLV headers 2488 * @len: msdu length 2489 * 2490 * Return: none 2491 */ 2492 static inline void 2493 hal_rx_msdu_start_msdu_len_set_be(uint8_t *buf, uint32_t len) 2494 { 2495 HAL_RX_TLV_MSDU_LEN_GET(buf) = len; 2496 } 2497 2498 /** 2499 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_be(): 2500 * Retrieve qos control valid bit from the tlv. 2501 * @buf: pointer to rx pkt TLV. 2502 * 2503 * Return: qos control value. 2504 */ 2505 static inline uint32_t 2506 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be(uint8_t *buf) 2507 { 2508 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2509 2510 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(pkt_tlvs); 2511 } 2512 2513 /** 2514 * hal_rx_msdu_end_sa_sw_peer_id_get_be(): API to get the 2515 * sa_sw_peer_id from rx_msdu_end TLV 2516 * @buf: pointer to the start of RX PKT TLV headers 2517 * 2518 * Return: sa_sw_peer_id index 2519 */ 2520 static inline uint32_t 2521 hal_rx_msdu_end_sa_sw_peer_id_get_be(uint8_t *buf) 2522 { 2523 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2524 2525 hal_rx_msdu_end_t *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 2526 2527 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 2528 } 2529 #endif /* _HAL_BE_RX_TLV_H_ */ 2530