1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_BE_RX_TLV_H_ 21 #define _HAL_BE_RX_TLV_H_ 22 23 #include "hal_api_mon.h" 24 25 /* 26 * Structures & Macros to obtain fields from the TLV's in the Rx packet 27 * pre-header. 28 */ 29 30 #define HAL_RX_BE_PKT_HDR_TLV_LEN 112 31 32 struct rx_pkt_hdr_tlv { 33 uint64_t tag; /* 8 B */ 34 uint64_t phy_ppdu_id; /* 8 B */ 35 char rx_pkt_hdr[HAL_RX_BE_PKT_HDR_TLV_LEN]; /* 112 B */ 36 }; 37 38 #ifdef CONFIG_WORD_BASED_TLV 39 #ifndef BIG_ENDIAN_HOST 40 struct rx_msdu_end_compact { 41 uint32_t sa_sw_peer_id : 16, 42 sa_idx_timeout : 1, 43 da_idx_timeout : 1, 44 to_ds : 1, 45 tid : 4, 46 sa_is_valid : 1, 47 da_is_valid : 1, 48 da_is_mcbc : 1, 49 l3_header_padding : 2, 50 first_msdu : 1, 51 last_msdu : 1, 52 fr_ds : 1, 53 ip_chksum_fail_copy : 1; 54 uint32_t sa_idx : 16, 55 da_idx_or_sw_peer_id : 16; 56 uint32_t msdu_drop : 1, 57 reo_destination_indication : 5, 58 flow_idx : 20, 59 use_ppe : 1, 60 mesh_sta : 2, 61 vlan_ctag_stripped : 1, 62 vlan_stag_stripped : 1, 63 fragment_flag : 1; 64 uint32_t fse_metadata : 32; 65 uint32_t cce_metadata : 16, 66 tcp_udp_chksum : 16; 67 uint32_t aggregation_count : 8, 68 flow_aggregation_continuation : 1, 69 fisa_timeout : 1, 70 tcp_udp_chksum_fail_copy : 1, 71 msdu_limit_error : 1, 72 flow_idx_timeout : 1, 73 flow_idx_invalid : 1, 74 cce_match : 1, 75 amsdu_parser_error : 1, 76 cumulative_ip_length : 16; 77 uint32_t key_id_octet : 8, 78 reserved_8a : 24; 79 uint32_t reserved_9a : 6, 80 service_code : 9, 81 priority_valid : 1, 82 intra_bss : 1, 83 dest_chip_id : 2, 84 multicast_echo : 1, 85 wds_learning_event : 1, 86 wds_roaming_event : 1, 87 wds_keep_alive_event : 1, 88 dest_chip_pmac_id : 1, 89 reserved_9b : 8; 90 uint32_t msdu_length : 14, 91 stbc : 1, 92 ipsec_esp : 1, 93 l3_offset : 7, 94 ipsec_ah : 1, 95 l4_offset : 8; 96 uint32_t msdu_number : 8, 97 decap_format : 2, 98 ipv4_proto : 1, 99 ipv6_proto : 1, 100 tcp_proto : 1, 101 udp_proto : 1, 102 ip_frag : 1, 103 tcp_only_ack : 1, 104 da_is_bcast_mcast : 1, 105 toeplitz_hash_sel : 2, 106 ip_fixed_header_valid : 1, 107 ip_extn_header_valid : 1, 108 tcp_udp_header_valid : 1, 109 mesh_control_present : 1, 110 ldpc : 1, 111 ip4_protocol_ip6_next_header : 8; 112 uint32_t vlan_ctag_ci : 16, 113 vlan_stag_ci : 16; 114 uint32_t peer_meta_data : 32; 115 uint32_t user_rssi : 8, 116 pkt_type : 4, 117 sgi : 2, 118 rate_mcs : 4, 119 receive_bandwidth : 3, 120 reception_type : 3, 121 mimo_ss_bitmap : 7, 122 msdu_done_copy : 1; 123 uint32_t flow_id_toeplitz : 32; 124 uint32_t ppdu_start_timestamp_63_32; 125 uint32_t sw_phy_meta_data : 32; 126 uint32_t first_mpdu : 1, 127 reserved_16a : 1, 128 mcast_bcast : 1, 129 ast_index_not_found : 1, 130 ast_index_timeout : 1, 131 power_mgmt : 1, 132 non_qos : 1, 133 null_data : 1, 134 mgmt_type : 1, 135 ctrl_type : 1, 136 more_data : 1, 137 eosp : 1, 138 a_msdu_error : 1, 139 reserved_16b : 1, 140 order : 1, 141 wifi_parser_error : 1, 142 overflow_err : 1, 143 msdu_length_err : 1, 144 tcp_udp_chksum_fail : 1, 145 ip_chksum_fail : 1, 146 sa_idx_invalid : 1, 147 da_idx_invalid : 1, 148 amsdu_addr_mismatch : 1, 149 rx_in_tx_decrypt_byp : 1, 150 encrypt_required : 1, 151 directed : 1, 152 buffer_fragment : 1, 153 mpdu_length_err : 1, 154 tkip_mic_err : 1, 155 decrypt_err : 1, 156 unencrypted_frame_err : 1, 157 fcs_err : 1; 158 uint32_t reserved_17a : 10, 159 decrypt_status_code : 3, 160 rx_bitmap_not_updated : 1, 161 reserved_17b : 17, 162 msdu_done : 1; 163 }; 164 165 struct rx_mpdu_start_compact { 166 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 167 receive_queue_number : 16, 168 pre_delim_err_warning : 1, 169 first_delim_err : 1, 170 reserved_0 : 6; 171 uint32_t pn_31_0 : 32; 172 uint32_t pn_63_32 : 32; 173 uint32_t pn_95_64 : 32; 174 uint32_t ast_index : 16, 175 sw_peer_id : 16; 176 uint32_t mpdu_frame_control_valid : 1, 177 mpdu_duration_valid : 1, 178 mac_addr_ad1_valid : 1, 179 mac_addr_ad2_valid : 1, 180 mac_addr_ad3_valid : 1, 181 mac_addr_ad4_valid : 1, 182 mpdu_sequence_control_valid : 1, 183 mpdu_qos_control_valid : 1, 184 mpdu_ht_control_valid : 1, 185 frame_encryption_info_valid : 1, 186 mpdu_fragment_number : 4, 187 more_fragment_flag : 1, 188 reserved_7a : 1, 189 fr_ds : 1, 190 to_ds : 1, 191 encrypted : 1, 192 mpdu_retry : 1, 193 mpdu_sequence_number : 12; 194 uint32_t mpdu_frame_control_field : 16, 195 mpdu_duration_field : 16; 196 uint32_t mac_addr_ad1_31_0 : 32; 197 uint32_t mac_addr_ad1_47_32 : 16, 198 mac_addr_ad2_15_0 : 16; 199 uint32_t mac_addr_ad2_47_16 : 32; 200 uint32_t mac_addr_ad3_31_0 : 32; 201 uint32_t mac_addr_ad3_47_32 : 16, 202 mpdu_sequence_control_field : 16; 203 }; 204 #else 205 struct rx_msdu_end_compact { 206 uint32_t ip_chksum_fail_copy : 1, 207 fr_ds : 1, 208 last_msdu : 1, 209 first_msdu : 1, 210 l3_header_padding : 2, 211 da_is_mcbc : 1, 212 da_is_valid : 1, 213 sa_is_valid : 1, 214 tid : 4, 215 to_ds : 1, 216 da_idx_timeout : 1, 217 sa_idx_timeout : 1, 218 sa_sw_peer_id : 16; 219 uint32_t da_idx_or_sw_peer_id : 16, 220 sa_idx : 16; 221 uint32_t fragment_flag : 1, 222 vlan_stag_stripped : 1, 223 vlan_ctag_stripped : 1, 224 mesh_sta : 2, 225 use_ppe : 1, 226 flow_idx : 20, 227 reo_destination_indication : 5, 228 msdu_drop : 1; 229 uint32_t fse_metadata : 32; 230 uint32_t tcp_udp_chksum : 16, 231 cce_metadata : 16; 232 uint32_t cumulative_ip_length : 16, 233 amsdu_parser_error : 1, 234 cce_match : 1, 235 flow_idx_invalid : 1, 236 flow_idx_timeout : 1, 237 msdu_limit_error : 1, 238 tcp_udp_chksum_fail_copy : 1, 239 fisa_timeout : 1, 240 flow_aggregation_continuation : 1, 241 aggregation_count : 8; 242 uint32_t reserved_8a : 24, 243 key_id_octet : 8; 244 uint32_t reserved_9b : 8, 245 dest_chip_pmac_id : 1, 246 wds_keep_alive_event : 1, 247 wds_roaming_event : 1, 248 wds_learning_event : 1, 249 multicast_echo : 1, 250 dest_chip_id : 2, 251 intra_bss : 1, 252 priority_valid : 1, 253 service_code : 9, 254 reserved_9a : 6; 255 uint32_t l4_offset : 8, 256 ipsec_ah : 1, 257 l3_offset : 7, 258 ipsec_esp : 1, 259 stbc : 1, 260 msdu_length : 14; 261 uint32_t ip4_protocol_ip6_next_header : 8, 262 ldpc : 1, 263 mesh_control_present : 1, 264 tcp_udp_header_valid : 1, 265 ip_extn_header_valid : 1, 266 ip_fixed_header_valid : 1, 267 toeplitz_hash_sel : 2, 268 da_is_bcast_mcast : 1, 269 tcp_only_ack : 1, 270 ip_frag : 1, 271 udp_proto : 1, 272 tcp_proto : 1, 273 ipv6_proto : 1, 274 ipv4_proto : 1, 275 decap_format : 2, 276 msdu_number : 8; 277 uint32_t vlan_stag_ci : 16, 278 vlan_ctag_ci : 16; 279 uint32_t peer_meta_data : 32; 280 uint32_t msdu_done_copy : 1, 281 mimo_ss_bitmap : 7, 282 reception_type : 3, 283 receive_bandwidth : 3, 284 rate_mcs : 4, 285 sgi : 2, 286 pkt_type : 4, 287 user_rssi : 8; 288 uint32_t flow_id_toeplitz : 32; 289 uint32_t ppdu_start_timestamp_63_32; 290 uint32_t sw_phy_meta_data : 32; 291 uint32_t fcs_err : 1, 292 unencrypted_frame_err : 1, 293 decrypt_err : 1, 294 tkip_mic_err : 1, 295 mpdu_length_err : 1, 296 buffer_fragment : 1, 297 directed : 1, 298 encrypt_required : 1, 299 rx_in_tx_decrypt_byp : 1, 300 amsdu_addr_mismatch : 1, 301 da_idx_invalid : 1, 302 sa_idx_invalid : 1, 303 ip_chksum_fail : 1, 304 tcp_udp_chksum_fail : 1, 305 msdu_length_err : 1, 306 overflow_err : 1, 307 wifi_parser_error : 1, 308 order : 1, 309 reserved_16b : 1, 310 a_msdu_error : 1, 311 eosp : 1, 312 more_data : 1, 313 ctrl_type : 1, 314 mgmt_type : 1, 315 null_data : 1, 316 non_qos : 1, 317 power_mgmt : 1, 318 ast_index_timeout : 1, 319 ast_index_not_found : 1, 320 mcast_bcast : 1, 321 reserved_16a : 1, 322 first_mpdu : 1; 323 uint32_t msdu_done : 1, 324 reserved_17b : 17, 325 rx_bitmap_not_updated : 1, 326 decrypt_status_code : 3, 327 reserved_17a : 10; 328 }; 329 330 struct rx_mpdu_start_compact { 331 uint32_t reserved_0 : 6, 332 first_delim_err : 1, 333 pre_delim_err_warning : 1, 334 receive_queue_number : 16, 335 rx_reo_queue_desc_addr_39_32 : 8; 336 uint32_t pn_31_0 : 32; 337 uint32_t pn_63_32 : 32; 338 uint32_t pn_95_64 : 32; 339 uint32_t sw_peer_id : 16, 340 ast_index : 16; 341 uint32_t mpdu_sequence_number : 12, 342 mpdu_retry : 1, 343 encrypted : 1, 344 to_ds : 1, 345 fr_ds : 1, 346 reserved_7a : 1, 347 more_fragment_flag : 1, 348 mpdu_fragment_number : 4, 349 frame_encryption_info_valid : 1, 350 mpdu_ht_control_valid : 1, 351 mpdu_qos_control_valid : 1, 352 mpdu_sequence_control_valid : 1, 353 mac_addr_ad4_valid : 1, 354 mac_addr_ad3_valid : 1, 355 mac_addr_ad2_valid : 1, 356 mac_addr_ad1_valid : 1, 357 mpdu_duration_valid : 1, 358 mpdu_frame_control_valid : 1; 359 uint32_t mpdu_duration_field : 16, 360 mpdu_frame_control_field : 16; 361 uint32_t mac_addr_ad1_31_0 : 32; 362 uint32_t mac_addr_ad2_15_0 : 16, 363 mac_addr_ad1_47_32 : 16; 364 uint32_t mac_addr_ad2_47_16 : 32; 365 uint32_t mac_addr_ad3_31_0 : 32; 366 uint32_t mpdu_sequence_control_field : 16, 367 mac_addr_ad3_47_32 : 16; 368 }; 369 #endif 370 #define RX_BE_PADDING0_BYTES 4 371 372 typedef struct rx_mpdu_start_compact hal_rx_mpdu_start_t; 373 typedef struct rx_msdu_end_compact hal_rx_msdu_end_t; 374 375 struct rx_mpdu_start_tlv { 376 hal_rx_mpdu_start_t rx_mpdu_start; 377 }; 378 379 struct rx_msdu_end_tlv { 380 uint64_t tag; /* 8 B */ 381 hal_rx_msdu_end_t rx_msdu_end; 382 }; 383 384 struct rx_pkt_tlvs { 385 struct rx_msdu_end_tlv msdu_end_tlv; /* 80 bytes */ 386 struct rx_mpdu_start_tlv mpdu_start_tlv; /* 48 bytes */ 387 }; 388 389 #define HAL_RX_MSDU_END(_rx_pkt_tlv) \ 390 (((struct rx_pkt_tlvs *)_rx_pkt_tlv)->msdu_end_tlv.rx_msdu_end) 391 392 #define HAL_RX_MPDU_START(_rx_pkt_tlv) \ 393 (((struct rx_pkt_tlvs *)_rx_pkt_tlv)->mpdu_start_tlv. \ 394 rx_mpdu_start) 395 396 #define HAL_RX_TLV_TID_GET(_rx_pkt_tlv) \ 397 HAL_RX_MSDU_END(_rx_pkt_tlv).tid 398 399 #define HAL_RX_TLV_FIRST_MPDU_GET(_rx_pkt_tlv) \ 400 HAL_RX_MSDU_END(_rx_pkt_tlv).first_mpdu 401 #else /* CONFIG_WORD_BASED_TLV */ 402 typedef struct rx_mpdu_start hal_rx_mpdu_start_t; 403 typedef struct rx_msdu_end hal_rx_msdu_end_t; 404 405 #define RX_BE_PADDING0_BYTES 8 406 /* 407 * Each RX descriptor TLV is preceded by 1 QWORD "tag" 408 */ 409 410 #ifndef CONFIG_NO_TLV_TAGS 411 struct rx_mpdu_start_tlv { 412 uint64_t tag; /* 8 B */ 413 hal_rx_mpdu_start_t rx_mpdu_start; 414 }; 415 416 struct rx_msdu_end_tlv { 417 uint64_t tag; /* 8 B */ 418 hal_rx_msdu_end_t rx_msdu_end; 419 }; 420 421 struct rx_pkt_tlvs { 422 struct rx_msdu_end_tlv msdu_end_tlv; /* 136 bytes */ 423 uint8_t rx_padding0[RX_BE_PADDING0_BYTES]; /* 8 bytes */ 424 struct rx_mpdu_start_tlv mpdu_start_tlv; /* 128 bytes */ 425 #ifndef NO_RX_PKT_HDR_TLV 426 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 427 #endif 428 }; 429 430 #else 431 struct rx_mpdu_start_tlv { 432 hal_rx_mpdu_start_t rx_mpdu_start; 433 }; 434 435 struct rx_msdu_end_tlv { 436 hal_rx_msdu_end_t rx_msdu_end; 437 }; 438 439 struct rx_pkt_tlvs { 440 struct rx_msdu_end_tlv msdu_end_tlv; /* 128 bytes */ 441 struct rx_mpdu_start_tlv mpdu_start_tlv; /* 120 bytes */ 442 uint8_t rx_padding0[RX_BE_PADDING0_BYTES]; /* 8 bytes */ 443 #ifndef NO_RX_PKT_HDR_TLV 444 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 445 #endif 446 }; 447 #endif /*CONFIG_NO_TLV_TAGS */ 448 449 #define HAL_RX_MSDU_END(_rx_pkt_tlv) \ 450 (((struct rx_pkt_tlvs *)_rx_pkt_tlv)->msdu_end_tlv.rx_msdu_end) 451 452 #define HAL_RX_MPDU_START(_rx_pkt_tlv) \ 453 (((struct rx_pkt_tlvs *)_rx_pkt_tlv)->mpdu_start_tlv. \ 454 rx_mpdu_start.rx_mpdu_info_details) 455 456 #define HAL_RX_REO_QUEUE_DESC_ADDR_31_0_GET(_rx_pkt_tlv) \ 457 HAL_RX_MPDU_START(_rx_pkt_tlv).rx_reo_queue_desc_addr_31_0 458 459 #define HAL_RX_TLV_AMPDU_FLAG_GET(_rx_pkt_tlv) \ 460 HAL_RX_MPDU_START(_rx_pkt_tlv).ampdu_flag 461 462 #define HAL_RX_TLV_MPDU_PN_127_96_GET(_rx_pkt_tlv) \ 463 HAL_RX_MPDU_START(_rx_pkt_tlv).pn_127_96 464 465 #define HAL_RX_TLV_TID_GET(_rx_pkt_tlv) \ 466 HAL_RX_MPDU_START(_rx_pkt_tlv).tid 467 468 #define HAL_RX_TLV_FIRST_MPDU_GET(_rx_pkt_tlv) \ 469 HAL_RX_MPDU_START(_rx_pkt_tlv).first_mpdu 470 471 #define HAL_RX_TLV_L3_TYPE_GET(_rx_pkt_tlv) \ 472 HAL_RX_MSDU_END(_rx_pkt_tlv).l3_type 473 474 #define HAL_RX_GET_PPDU_ID(_rx_pkt_tlv) \ 475 HAL_RX_MPDU_START(_rx_pkt_tlv).phy_ppdu_id 476 477 #define HAL_RX_TLV_PHY_PPDU_ID_GET(_rx_pkt_tlv) \ 478 HAL_RX_MSDU_END(_rx_pkt_tlv).phy_ppdu_id 479 480 #define HAL_RX_GET_FILTER_CATEGORY(_rx_pkt_tlv) \ 481 HAL_RX_MPDU_START(_rx_pkt_tlv).rxpcu_mpdu_filter_in_category 482 483 #define HAL_RX_TLV_SW_FRAME_GROUP_ID_GET(_rx_pkt_tlv) \ 484 HAL_RX_MPDU_START(_rx_pkt_tlv).sw_frame_group_id 485 486 #endif /* CONFIG_WORD_BASED_TLV */ 487 488 /** 489 * struct rx_mon_pkt_tlvs - RX packet data structure for DEST ring in the 490 * monitor mode. 491 * @msdu_end_tlv: MSDU end TLV 492 * @rx_padding0: Padding bytes 493 * @mpdu_start_tlv: MPDU start TLV 494 * @pkt_hdr_tlv: 802.11 packet header TLV 495 */ 496 struct rx_mon_pkt_tlvs { 497 struct rx_msdu_end_tlv msdu_end_tlv; /* 128B + sizeof(tag) */ 498 uint8_t rx_padding0[RX_BE_PADDING0_BYTES]; /* 8B */ 499 struct rx_mpdu_start_tlv mpdu_start_tlv; /* 120B + sizeof(tag) */ 500 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 120B + sizeof(tag) */ 501 }; 502 503 #define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs) 504 #define SIZE_OF_MON_DATA_RX_TLV sizeof(struct rx_mon_pkt_tlvs) 505 506 #define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV 507 #define MON_RX_PKT_TLVS_LEN SIZE_OF_MON_DATA_RX_TLV 508 509 #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field) 510 511 #define HAL_RX_TLV_MSDU_DONE_GET(_rx_pkt_tlv) \ 512 HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done 513 514 #define HAL_RX_TLV_DECAP_FORMAT_GET(_rx_pkt_tlv) \ 515 HAL_RX_MSDU_END(_rx_pkt_tlv).decap_format 516 517 #ifdef RECEIVE_OFFLOAD 518 #define HAL_RX_TLV_GET_TCP_PURE_ACK(_rx_pkt_tlv) \ 519 HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_only_ack 520 521 #define HAL_RX_TLV_GET_TCP_PROTO(_rx_pkt_tlv) \ 522 HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_proto 523 524 #define HAL_RX_TLV_GET_UDP_PROTO(_rx_pkt_tlv) \ 525 HAL_RX_MSDU_END(_rx_pkt_tlv).udp_proto 526 527 #define HAL_RX_TLV_GET_IPV6(_rx_pkt_tlv) \ 528 HAL_RX_MSDU_END(_rx_pkt_tlv).ipv6_proto 529 530 #define HAL_RX_TLV_GET_IP_OFFSET(_rx_pkt_tlv) \ 531 HAL_RX_MSDU_END(_rx_pkt_tlv).l3_offset 532 533 #define HAL_RX_TLV_GET_TCP_OFFSET(_rx_pkt_tlv) \ 534 HAL_RX_MSDU_END(_rx_pkt_tlv).l4_offset 535 #endif /* RECEIVE_OFFLOAD */ 536 537 #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(_rx_pkt_tlv) \ 538 HAL_RX_MSDU_END(_rx_pkt_tlv).flow_id_toeplitz 539 540 #define HAL_RX_TLV_MSDU_LEN_GET(_rx_pkt_tlv) \ 541 HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_length 542 543 #define HAL_RX_TLV_CCE_MATCH_GET(_rx_pkt_tlv) \ 544 HAL_RX_MSDU_END(_rx_pkt_tlv).cce_match 545 546 #define HAL_RX_TLV_BW_GET(_rx_pkt_tlv) \ 547 HAL_RX_MSDU_END(_rx_pkt_tlv).receive_bandwidth 548 549 #define HAL_RX_TLV_FLOWID_TOEPLITZ_GET(_rx_pkt_tlv) \ 550 HAL_RX_MSDU_END(_rx_pkt_tlv).flow_id_toeplitz 551 552 #define HAL_RX_TLV_SGI_GET(_rx_pkt_tlv) \ 553 HAL_RX_MSDU_END(_rx_pkt_tlv).sgi 554 555 #define HAL_RX_TLV_RATE_MCS_GET(_rx_pkt_tlv) \ 556 HAL_RX_MSDU_END(_rx_pkt_tlv).rate_mcs 557 558 #define HAL_RX_TLV_DECRYPT_STATUS_GET(_rx_pkt_tlv) \ 559 HAL_RX_MSDU_END(_rx_pkt_tlv).decrypt_status_code 560 561 #define HAL_RX_TLV_RSSI_GET(_rx_pkt_tlv) \ 562 HAL_RX_MSDU_END(_rx_pkt_tlv).user_rssi 563 564 #define HAL_RX_TLV_FREQ_GET(_rx_pkt_tlv) \ 565 HAL_RX_MSDU_END(_rx_pkt_tlv).sw_phy_meta_data 566 567 #define HAL_RX_TLV_PKT_TYPE_GET(_rx_pkt_tlv) \ 568 HAL_RX_MSDU_END(_rx_pkt_tlv).pkt_type 569 570 #define HAL_RX_TLV_DECRYPT_ERR_GET(_rx_pkt_tlv) \ 571 HAL_RX_MSDU_END(_rx_pkt_tlv).decrypt_err 572 573 #define HAL_RX_TLV_MIC_ERR_GET(_rx_pkt_tlv) \ 574 HAL_RX_MSDU_END(_rx_pkt_tlv).tkip_mic_err 575 576 #define HAL_RX_TLV_MIMO_SS_BITMAP(_rx_pkt_tlv)\ 577 HAL_RX_MSDU_END(_rx_pkt_tlv).mimo_ss_bitmap 578 579 #define HAL_RX_TLV_ANT_SIGNAL_DB_GET(_rx_pkt_tlv) \ 580 HAL_RX_MSDU_END(_rx_pkt_tlv).user_rssi 581 582 #define HAL_RX_TLV_STBC_GET(_rx_pkt_tlv) \ 583 HAL_RX_MSDU_END(_rx_pkt_tlv).stbc 584 585 #define HAL_RX_TLV_RECEPTION_TYPE_GET(_rx_pkt_tlv) \ 586 HAL_RX_MSDU_END(_rx_pkt_tlv).reception_type 587 588 #define HAL_RX_TLV_IP_CSUM_FAIL_GET(_rx_pkt_tlv) \ 589 HAL_RX_MSDU_END(_rx_pkt_tlv).ip_chksum_fail 590 591 #define HAL_RX_TLV_TCP_UDP_CSUM_FAIL_GET(_rx_pkt_tlv) \ 592 HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_udp_chksum_fail 593 594 #define HAL_RX_TLV_MPDU_LEN_ERR_GET(_rx_pkt_tlv) \ 595 HAL_RX_MSDU_END(_rx_pkt_tlv).mpdu_length_err 596 597 #define HAL_RX_TLV_MPDU_FCS_ERR_GET(_rx_pkt_tlv) \ 598 HAL_RX_MSDU_END(_rx_pkt_tlv).fcs_err 599 600 #define HAL_RX_TLV_IS_MCAST_GET(_rx_pkt_tlv) \ 601 HAL_RX_MSDU_END(_rx_pkt_tlv).mcast_bcast 602 603 #ifdef RECEIVE_OFFLOAD 604 /** 605 * LRO information needed from the TLVs 606 */ 607 #define HAL_RX_TLV_GET_LRO_ELIGIBLE(_rx_pkt_tlv) \ 608 HAL_RX_MSDU_END(_rx_pkt_tlv).lro_eligible 609 610 #define HAL_RX_TLV_GET_TCP_ACK(_rx_pkt_tlv) \ 611 HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_ack_number 612 613 #define HAL_RX_TLV_GET_TCP_SEQ(_rx_pkt_tlv) \ 614 HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_seq_number 615 616 #define HAL_RX_TLV_GET_TCP_WIN(_rx_pkt_tlv) \ 617 HAL_RX_MSDU_END(_rx_pkt_tlv).window_size 618 #endif 619 620 #define HAL_RX_TLV_L3_TYPE_GET(_rx_pkt_tlv) \ 621 HAL_RX_MSDU_END(_rx_pkt_tlv).l3_type 622 623 #ifdef RX_MSDU_END_PEER_META_DATA_OFFSET 624 #define HAL_RX_TLV_MSDU_PEER_META_DATA_GET(_rx_pkt_tlv) \ 625 HAL_RX_MSDU_END(_rx_pkt_tlv).peer_meta_data 626 #endif 627 628 #define HAL_RX_TLV_PEER_META_DATA_GET(_rx_pkt_tlv) \ 629 HAL_RX_MPDU_START(_rx_pkt_tlv).peer_meta_data 630 631 #define HAL_RX_TLV_KEYID_OCTET_GET(_rx_pkt_tlv) \ 632 HAL_RX_MSDU_END(_rx_pkt_tlv).key_id_octet 633 634 #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(_rx_pkt_tlv) \ 635 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_sequence_number 636 637 #define HAL_RX_TLV_SA_SW_PEER_ID_GET(_rx_pkt_tlv) \ 638 HAL_RX_MSDU_END(_rx_pkt_tlv).sa_sw_peer_id 639 640 #define HAL_RX_TLV_L3_HEADER_PADDING_GET(_rx_pkt_tlv) \ 641 HAL_RX_MSDU_END(_rx_pkt_tlv).l3_header_padding 642 643 #define HAL_RX_TLV_SA_IDX_GET(_rx_pkt_tlv) \ 644 HAL_RX_MSDU_END(_rx_pkt_tlv).sa_idx 645 646 #define HAL_RX_TLV_DA_IDX_GET(_rx_pkt_tlv) \ 647 HAL_RX_MSDU_END(_rx_pkt_tlv).da_idx_or_sw_peer_id 648 649 #define HAL_RX_TLV_FIRST_MSDU_GET(_rx_pkt_tlv) \ 650 HAL_RX_MSDU_END(_rx_pkt_tlv).first_msdu 651 652 #define HAL_RX_TLV_LAST_MSDU_GET(_rx_pkt_tlv) \ 653 HAL_RX_MSDU_END(_rx_pkt_tlv).last_msdu 654 655 #define HAL_RX_TLV_DA_IS_MCBC_GET(_rx_pkt_tlv) \ 656 HAL_RX_MSDU_END(_rx_pkt_tlv).da_is_mcbc 657 658 #define HAL_RX_TLV_IS_TKIP_MIC_ERR_GET(_rx_pkt_tlv) \ 659 HAL_RX_MSDU_END(_rx_pkt_tlv).tkip_mic_err 660 661 #define HAL_RX_TLV_SA_IS_VALID_GET(_rx_pkt_tlv) \ 662 HAL_RX_MSDU_END(_rx_pkt_tlv).sa_is_valid 663 664 #define HAL_RX_TLV_MPDU_ENCRYPTION_INFO_VALID(_rx_pkt_tlv) \ 665 HAL_RX_MPDU_START(_rx_pkt_tlv).frame_encryption_info_valid 666 667 #define HAL_RX_TLV_MPDU_PN_31_0_GET(_rx_pkt_tlv) \ 668 HAL_RX_MPDU_START(_rx_pkt_tlv).pn_31_0 669 670 #define HAL_RX_TLV_MPDU_PN_63_32_GET(_rx_pkt_tlv) \ 671 HAL_RX_MPDU_START(_rx_pkt_tlv).pn_63_32 672 673 #define HAL_RX_TLV_MPDU_PN_95_64_GET(_rx_pkt_tlv) \ 674 HAL_RX_MPDU_START(_rx_pkt_tlv).pn_95_64 675 676 #define HAL_RX_TLV_DA_IS_VALID_GET(_rx_pkt_tlv) \ 677 HAL_RX_MSDU_END(_rx_pkt_tlv).da_is_valid 678 679 #define HAL_RX_TLV_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_pkt_tlv) \ 680 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad4_valid 681 682 #define HAL_RX_TLV_SW_PEER_ID_GET(_rx_pkt_tlv) \ 683 HAL_RX_MPDU_START(_rx_pkt_tlv).sw_peer_id 684 685 #define HAL_RX_TLV_MPDU_GET_TODS(_rx_pkt_tlv) \ 686 HAL_RX_MPDU_START(_rx_pkt_tlv).to_ds 687 688 #define HAL_RX_TLV_MPDU_GET_FROMDS(_rx_pkt_tlv) \ 689 HAL_RX_MPDU_START(_rx_pkt_tlv).fr_ds 690 691 #define HAL_RX_TLV_MPDU_GET_FRAME_CONTROL_VALID(_rx_pkt_tlv) \ 692 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_frame_control_valid 693 694 #define HAL_RX_TLV_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_pkt_tlv) \ 695 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad1_valid 696 697 #define HAL_RX_TLV_MPDU_AD1_31_0_GET(_rx_pkt_tlv) \ 698 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad1_31_0 699 700 #define HAL_RX_TLV_MPDU_AD1_47_32_GET(_rx_pkt_tlv) \ 701 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad1_47_32 702 703 #define HAL_RX_TLV_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_pkt_tlv) \ 704 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad2_valid 705 706 #define HAL_RX_TLV_MPDU_AD2_15_0_GET(_rx_pkt_tlv) \ 707 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad2_15_0 708 709 #define HAL_RX_TLV_MPDU_AD2_47_16_GET(_rx_pkt_tlv) \ 710 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad2_47_16 711 712 #define HAL_RX_TLV_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_pkt_tlv) \ 713 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad3_valid 714 715 #define HAL_RX_TLV_MPDU_AD3_31_0_GET(_rx_pkt_tlv) \ 716 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad3_31_0 717 718 #define HAL_RX_TLV_MPDU_AD3_47_32_GET(_rx_pkt_tlv) \ 719 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad3_47_32 720 721 #define HAL_RX_TLV_MPDU_AD4_31_0_GET(_rx_pkt_tlv) \ 722 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad4_31_0 723 724 #define HAL_RX_TLV_MPDU_AD4_47_32_GET(_rx_pkt_tlv) \ 725 HAL_RX_MPDU_START(_rx_pkt_tlv).mac_addr_ad4_47_32 726 727 #define HAL_RX_TLV_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_pkt_tlv) \ 728 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_sequence_control_valid 729 730 #define HAL_RX_TLV_MPDU_QOS_CONTROL_VALID_GET(_rx_pkt_tlv) \ 731 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_qos_control_valid 732 733 #define HAL_RX_TLV_GET_FC_VALID(_rx_pkt_tlv) \ 734 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_frame_control_valid 735 736 #define HAL_RX_TLV_GET_TO_DS_FLAG(_rx_pkt_tlv) \ 737 HAL_RX_MPDU_START(_rx_pkt_tlv).to_ds 738 739 #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_pkt_tlv) \ 740 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_frame_control_field 741 742 #define HAL_RX_TLV_FLOW_IDX_GET(_rx_pkt_tlv) \ 743 HAL_RX_MSDU_END(_rx_pkt_tlv).flow_idx 744 745 #define HAL_RX_TLV_REO_DEST_IND_GET(_rx_pkt_tlv) \ 746 HAL_RX_MSDU_END(_rx_pkt_tlv).reo_destination_indication 747 748 #define HAL_RX_TLV_FLOW_IDX_INVALID_GET(_rx_pkt_tlv) \ 749 HAL_RX_MSDU_END(_rx_pkt_tlv).flow_idx_invalid 750 751 #define HAL_RX_TLV_FLOW_IDX_TIMEOUT_GET(_rx_pkt_tlv) \ 752 HAL_RX_MSDU_END(_rx_pkt_tlv).flow_idx_timeout 753 754 #define HAL_RX_TLV_FSE_METADATA_GET(_rx_pkt_tlv) \ 755 HAL_RX_MSDU_END(_rx_pkt_tlv).fse_metadata 756 757 #define HAL_RX_TLV_CCE_METADATA_GET(_rx_pkt_tlv) \ 758 HAL_RX_MSDU_END(_rx_pkt_tlv).cce_metadata 759 760 #define HAL_RX_TLV_DECRYPT_STATUS_GET(_rx_pkt_tlv) \ 761 HAL_RX_MSDU_END(_rx_pkt_tlv).decrypt_status_code 762 763 #define HAL_RX_TLV_GET_TCP_CHKSUM(_rx_pkt_tlv) \ 764 HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_udp_chksum 765 766 #define HAL_RX_TLV_GET_FLOW_AGGR_CONT(_rx_pkt_tlv) \ 767 HAL_RX_MSDU_END(_rx_pkt_tlv).flow_aggregation_continuation 768 769 #define HAL_RX_TLV_GET_FLOW_AGGR_COUNT(_rx_pkt_tlv) \ 770 HAL_RX_MSDU_END(_rx_pkt_tlv).aggregation_count 771 772 #define HAL_RX_TLV_GET_FISA_TIMEOUT(_rx_pkt_tlv) \ 773 HAL_RX_MSDU_END(_rx_pkt_tlv).fisa_timeout 774 775 #define HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(_rx_pkt_tlv) \ 776 HAL_RX_MSDU_END(_rx_pkt_tlv).cumulative_l4_checksum 777 778 #define HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(_rx_pkt_tlv) \ 779 HAL_RX_MSDU_END(_rx_pkt_tlv).cumulative_ip_length 780 781 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_pkt_tlv) \ 782 HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_qos_control_valid 783 784 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_pkt_tlv) \ 785 HAL_RX_MSDU_END(_rx_pkt_tlv).sa_sw_peer_id 786 787 #define HAL_RX_REO_QUEUE_DESC_ADDR_39_32_GET(_rx_pkt_tlv) \ 788 HAL_RX_MPDU_START(_rx_pkt_tlv).rx_reo_queue_desc_addr_39_32 789 790 /* used by monitor mode for parsing from full TLV */ 791 #define HAL_RX_MON_GET_FC_VALID(_rx_mpdu_start) \ 792 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MPDU_FRAME_CONTROL_VALID) 793 794 #define HAL_RX_MON_GET_TO_DS_FLAG(_rx_mpdu_start) \ 795 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, TO_DS) 796 797 #define HAL_RX_MON_GET_MAC_ADDR2_VALID(_rx_mpdu_start) \ 798 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD2_VALID) 799 800 static inline 801 uint32_t hal_rx_tlv_decap_format_get_be(void *hw_desc_addr) 802 { 803 struct rx_pkt_tlvs *rx_pkt_tlvs = 804 (struct rx_pkt_tlvs *)hw_desc_addr; 805 806 return HAL_RX_TLV_DECAP_FORMAT_GET(rx_pkt_tlvs); 807 } 808 809 static inline uint32_t hal_rx_tlv_msdu_done_get_be(uint8_t *buf) 810 { 811 return HAL_RX_TLV_MSDU_DONE_GET(buf); 812 } 813 814 /* 815 * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention 816 * @buf: pointer to rx_pkt_tlvs 817 * 818 * return: uint32_t(first_msdu) 819 */ 820 static inline uint32_t hal_rx_tlv_first_mpdu_get_be(uint8_t *buf) 821 { 822 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 823 824 return HAL_RX_TLV_FIRST_MPDU_GET(rx_pkt_tlvs); 825 } 826 827 /* 828 * hal_rx_msdu_cce_match_get(): get CCE match bit 829 * from rx attention 830 * @buf: pointer to rx_pkt_tlvs 831 * Return: CCE match value 832 */ 833 static inline bool hal_rx_msdu_cce_match_get_be(uint8_t *buf) 834 { 835 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 836 837 return HAL_RX_TLV_CCE_MATCH_GET(rx_pkt_tlvs); 838 } 839 840 #ifdef RX_MSDU_END_PEER_META_DATA_OFFSET 841 /* 842 * Get peer_meta_data from RX_MSDU_END 843 */ 844 845 static inline uint32_t hal_rx_msdu_peer_meta_data_get_be(uint8_t *buf) 846 { 847 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 848 849 return HAL_RX_TLV_MSDU_PEER_META_DATA_GET(rx_pkt_tlvs); 850 } 851 #endif 852 853 /* 854 * hal_rx_mpdu_get_addr1_be(): API to check get address1 of the mpdu 855 * 856 * @buf: pointer to the start of RX PKT TLV headera 857 * @mac_addr: pointer to mac address 858 * Return: success/failure 859 */ 860 static inline QDF_STATUS hal_rx_mpdu_get_addr1_be(uint8_t *buf, 861 uint8_t *mac_addr) 862 { 863 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 864 struct __attribute__((__packed__)) hal_addr1 { 865 uint32_t ad1_31_0; 866 uint16_t ad1_47_32; 867 }; 868 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 869 uint32_t mac_addr_ad1_valid; 870 871 mac_addr_ad1_valid = HAL_RX_TLV_MPDU_MAC_ADDR_AD1_VALID_GET( 872 rx_pkt_tlvs); 873 874 if (mac_addr_ad1_valid) { 875 addr->ad1_31_0 = HAL_RX_TLV_MPDU_AD1_31_0_GET(rx_pkt_tlvs); 876 addr->ad1_47_32 = HAL_RX_TLV_MPDU_AD1_47_32_GET(rx_pkt_tlvs); 877 return QDF_STATUS_SUCCESS; 878 } 879 880 return QDF_STATUS_E_FAILURE; 881 } 882 883 #ifndef CONFIG_WORD_BASED_TLV 884 /** 885 * hal_rx_mpdu_info_ampdu_flag_get_be(): get ampdu flag bit 886 * from rx mpdu info 887 * @buf: pointer to rx_pkt_tlvs 888 * 889 * Return: ampdu flag 890 */ 891 static inline bool hal_rx_mpdu_info_ampdu_flag_get_be(uint8_t *buf) 892 { 893 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 894 895 return !!HAL_RX_TLV_AMPDU_FLAG_GET(rx_pkt_tlvs); 896 } 897 898 /** 899 * hal_rx_get_qdesc_addr_be(): API to get qdesc address of reo 900 * entrance ring desc 901 * 902 * @dst_ring_desc: reo dest ring descriptor (used for Lithium DP) 903 * @buf: pointer to the start of RX PKT TLV headers 904 * Return: qdesc address in reo destination ring buffer 905 */ 906 static inline uint64_t hal_rx_get_qdesc_addr_be(uint8_t *dst_ring_desc, 907 uint8_t *buf) 908 { 909 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 910 911 return (uint64_t)HAL_RX_REO_QUEUE_DESC_ADDR_31_0_GET(rx_pkt_tlvs); 912 } 913 914 /* 915 * @ hal_rx_print_pn_be: Prints the PN of rx packet. 916 * 917 * @ buf: rx_tlv_hdr of the received packet 918 * @ Return: void 919 */ 920 static inline void hal_rx_print_pn_be(uint8_t *buf) 921 { 922 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 923 924 uint32_t pn_31_0 = HAL_RX_TLV_MPDU_PN_31_0_GET(rx_pkt_tlvs); 925 uint32_t pn_63_32 = HAL_RX_TLV_MPDU_PN_63_32_GET(rx_pkt_tlvs); 926 uint32_t pn_95_64 = HAL_RX_TLV_MPDU_PN_95_64_GET(rx_pkt_tlvs); 927 uint32_t pn_127_96 = HAL_RX_TLV_MPDU_PN_127_96_GET(rx_pkt_tlvs); 928 929 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 930 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 931 } 932 933 static inline void hal_rx_tlv_get_pn_num_be(uint8_t *buf, uint64_t *pn_num) 934 { 935 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 936 937 pn_num[0] = HAL_RX_TLV_MPDU_PN_31_0_GET(pkt_tlvs); 938 pn_num[0] |= ((uint64_t)HAL_RX_TLV_MPDU_PN_63_32_GET(pkt_tlvs) << 32); 939 940 pn_num[1] = HAL_RX_TLV_MPDU_PN_95_64_GET(pkt_tlvs); 941 pn_num[1] |= ((uint64_t)HAL_RX_TLV_MPDU_PN_127_96_GET(pkt_tlvs) << 32); 942 } 943 944 /* 945 * hal_rx_mpdu_get_addr4_be(): API to get address4 of the mpdu 946 * in the packet 947 * 948 * @buf: pointer to the start of RX PKT TLV header 949 * @mac_addr: pointer to mac address 950 * Return: success/failure 951 */ 952 static inline QDF_STATUS hal_rx_mpdu_get_addr4_be(uint8_t *buf, 953 uint8_t *mac_addr) 954 { 955 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 956 struct __attribute__((__packed__)) hal_addr4 { 957 uint32_t ad4_31_0; 958 uint16_t ad4_47_32; 959 }; 960 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 961 uint32_t mac_addr_ad4_valid; 962 963 mac_addr_ad4_valid = HAL_RX_TLV_MPDU_MAC_ADDR_AD4_VALID_GET(pkt_tlvs); 964 965 if (mac_addr_ad4_valid) { 966 addr->ad4_31_0 = HAL_RX_TLV_MPDU_AD4_31_0_GET(pkt_tlvs); 967 addr->ad4_47_32 = HAL_RX_TLV_MPDU_AD4_47_32_GET(pkt_tlvs); 968 return QDF_STATUS_SUCCESS; 969 } 970 971 return QDF_STATUS_E_FAILURE; 972 } 973 974 /** 975 * hal_rx_priv_info_set_in_tlv_be(): Save the private info to 976 * the reserved bytes of rx_tlv_hdr 977 * @buf: start of rx_tlv_hdr 978 * @priv_data: hal_wbm_err_desc_info structure 979 * @len: length of the private data 980 * Return: void 981 */ 982 static inline void hal_rx_priv_info_set_in_tlv_be(uint8_t *buf, 983 uint8_t *priv_data, 984 uint32_t len) 985 { 986 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 987 uint32_t copy_len = (len > RX_BE_PADDING0_BYTES) ? 988 RX_BE_PADDING0_BYTES : len; 989 990 qdf_mem_copy(pkt_tlvs->rx_padding0, priv_data, copy_len); 991 } 992 993 /** 994 * hal_rx_priv_info_get_from_tlv_be(): retrieve the private data from 995 * the reserved bytes of rx_tlv_hdr. 996 * @buf: start of rx_tlv_hdr 997 * @priv_data: Handle to get the private data, output parameter. 998 * @len: length of the private data 999 * Return: void 1000 */ 1001 static inline void hal_rx_priv_info_get_from_tlv_be(uint8_t *buf, 1002 uint8_t *priv_data, 1003 uint32_t len) 1004 { 1005 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1006 uint32_t copy_len = (len > RX_BE_PADDING0_BYTES) ? 1007 RX_BE_PADDING0_BYTES : len; 1008 1009 qdf_mem_copy(priv_data, pkt_tlvs->rx_padding0, copy_len); 1010 } 1011 1012 /** 1013 * hal_rx_tlv_l3_type_get_be(): API to get the l3 type 1014 * from rx_msdu_start TLV 1015 * 1016 * @buf: pointer to the start of RX PKT TLV headers 1017 * Return: uint32_t(l3 type) 1018 */ 1019 static inline uint32_t hal_rx_tlv_l3_type_get_be(uint8_t *buf) 1020 { 1021 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1022 1023 return HAL_RX_TLV_L3_TYPE_GET(rx_pkt_tlvs); 1024 } 1025 1026 /** 1027 * hal_rx_hw_desc_get_ppduid_get_be(): retrieve ppdu id 1028 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1029 * @rxdma_dst_ring_desc: Rx HW descriptor 1030 * 1031 * Return: ppdu id 1032 */ 1033 static inline uint32_t 1034 hal_rx_hw_desc_get_ppduid_get_be(void *rx_tlv_hdr, void *rxdma_dst_ring_desc) 1035 { 1036 struct rx_pkt_tlvs *rx_pkt_tlvs = 1037 (struct rx_pkt_tlvs *)rx_tlv_hdr; 1038 1039 return HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs); 1040 } 1041 1042 /* 1043 * hal_rx_tlv_phy_ppdu_id_get(): get phy_ppdu_id value 1044 * from rx attention 1045 * @buf: pointer to rx_pkt_tlvs 1046 * 1047 * Return: phy_ppdu_id 1048 */ 1049 static inline uint16_t hal_rx_tlv_phy_ppdu_id_get_be(uint8_t *buf) 1050 { 1051 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1052 1053 return HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs); 1054 } 1055 1056 /* 1057 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 1058 * from rx attention 1059 * @buf: pointer to rx_pkt_tlvs 1060 * 1061 * Return: phy_ppdu_id 1062 */ 1063 static inline uint16_t hal_rx_attn_phy_ppdu_id_get_be(uint8_t *buf) 1064 { 1065 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1066 uint16_t phy_ppdu_id; 1067 1068 phy_ppdu_id = HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs); 1069 1070 return phy_ppdu_id; 1071 } 1072 1073 static inline uint32_t 1074 hal_rx_get_ppdu_id_be(uint8_t *buf) 1075 { 1076 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1077 1078 return HAL_RX_GET_PPDU_ID(rx_pkt_tlvs); 1079 } 1080 1081 /* 1082 * hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv 1083 * 1084 * @buf: rx_tlv_hdr of the received packet 1085 * @peer_mdata: peer meta data to be set. 1086 * Return: void 1087 */ 1088 static inline void 1089 hal_rx_mpdu_peer_meta_data_set_be(uint8_t *buf, uint32_t peer_mdata) 1090 { 1091 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1092 1093 HAL_RX_TLV_PEER_META_DATA_GET(rx_pkt_tlvs) = peer_mdata; 1094 } 1095 1096 /* 1097 * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START 1098 */ 1099 1100 static inline uint32_t hal_rx_mpdu_peer_meta_data_get_be(uint8_t *buf) 1101 { 1102 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1103 1104 return HAL_RX_TLV_PEER_META_DATA_GET(rx_pkt_tlvs); 1105 } 1106 1107 static inline uint8_t hal_rx_get_filter_category_be(uint8_t *buf) 1108 { 1109 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1110 1111 return HAL_RX_GET_FILTER_CATEGORY(rx_pkt_tlvs); 1112 } 1113 1114 /** 1115 * hal_rx_is_unicast_be: check packet is unicast frame or not. 1116 * 1117 * @ buf: pointer to rx pkt TLV. 1118 * Return: true on unicast. 1119 */ 1120 static inline bool hal_rx_is_unicast_be(uint8_t *buf) 1121 { 1122 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1123 uint32_t grp_id; 1124 1125 grp_id = HAL_RX_TLV_SW_FRAME_GROUP_ID_GET(rx_pkt_tlvs); 1126 1127 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1128 } 1129 1130 #else 1131 #define IS_ADDR_MULTICAST(_a) (*(_a) & 0x01) 1132 /** 1133 * hal_rx_is_unicast_be: check packet is unicast frame or not. 1134 * 1135 * @ buf: pointer to rx pkt TLV. 1136 * Return: true on unicast. 1137 */ 1138 static inline bool hal_rx_is_unicast_be(uint8_t *buf) 1139 { 1140 uint8_t mac[QDF_MAC_ADDR_SIZE] = {0}; 1141 1142 hal_rx_mpdu_get_addr1_be(buf, &mac[0]); 1143 1144 return !IS_ADDR_MULTICAST(mac); 1145 } 1146 1147 /** 1148 * hal_rx_priv_info_set_in_tlv_be(): Save the private info to 1149 * the reserved bytes of rx_tlv_hdr 1150 * @buf: start of rx_tlv_hdr 1151 * @priv_data: hal_wbm_err_desc_info structure 1152 * @len: length of the private data 1153 * Return: void 1154 */ 1155 static inline void hal_rx_priv_info_set_in_tlv_be(uint8_t *buf, 1156 uint8_t *priv_data, 1157 uint32_t len) 1158 { 1159 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1160 uint32_t copy_len = (len > RX_BE_PADDING0_BYTES) ? 1161 RX_BE_PADDING0_BYTES : len; 1162 1163 qdf_mem_copy(&(HAL_RX_MSDU_END(pkt_tlvs).ppdu_start_timestamp_63_32), 1164 priv_data, copy_len); 1165 } 1166 1167 /** 1168 * hal_rx_priv_info_get_from_tlv_be(): retrieve the private data from 1169 * the reserved bytes of rx_tlv_hdr. 1170 * @buf: start of rx_tlv_hdr 1171 * @priv_data: Handle to get the private data, output parameter. 1172 * @len: length of the private data 1173 * Return: void 1174 */ 1175 static inline void hal_rx_priv_info_get_from_tlv_be(uint8_t *buf, 1176 uint8_t *priv_data, 1177 uint32_t len) 1178 { 1179 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1180 uint32_t copy_len = (len > RX_BE_PADDING0_BYTES) ? 1181 RX_BE_PADDING0_BYTES : len; 1182 1183 qdf_mem_copy(priv_data, 1184 &(HAL_RX_MSDU_END(pkt_tlvs).ppdu_start_timestamp_63_32), 1185 copy_len); 1186 } 1187 1188 /* 1189 * @ hal_rx_print_pn_be: Prints the PN of rx packet. 1190 * 1191 * @ buf: rx_tlv_hdr of the received packet 1192 * @ Return: void 1193 */ 1194 static inline void hal_rx_print_pn_be(uint8_t *buf) 1195 { 1196 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1197 1198 uint32_t pn_31_0 = HAL_RX_TLV_MPDU_PN_31_0_GET(rx_pkt_tlvs); 1199 uint32_t pn_63_32 = HAL_RX_TLV_MPDU_PN_63_32_GET(rx_pkt_tlvs); 1200 uint32_t pn_95_64 = HAL_RX_TLV_MPDU_PN_95_64_GET(rx_pkt_tlvs); 1201 1202 hal_debug("PN number pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 1203 pn_95_64, pn_63_32, pn_31_0); 1204 } 1205 1206 static inline void hal_rx_tlv_get_pn_num_be(uint8_t *buf, uint64_t *pn_num) 1207 { 1208 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1209 1210 pn_num[0] = HAL_RX_TLV_MPDU_PN_31_0_GET(pkt_tlvs); 1211 pn_num[0] |= ((uint64_t)HAL_RX_TLV_MPDU_PN_63_32_GET(pkt_tlvs) << 32); 1212 1213 pn_num[1] = HAL_RX_TLV_MPDU_PN_95_64_GET(pkt_tlvs); 1214 } 1215 #endif 1216 1217 /** 1218 * hal_rx_tlv_msdu_len_get(): API to get the MSDU length 1219 * from rx_msdu_start TLV 1220 * 1221 * @ buf: pointer to the start of RX PKT TLV headers 1222 * Return: msdu length 1223 */ 1224 static inline uint32_t hal_rx_tlv_msdu_len_get_be(uint8_t *buf) 1225 { 1226 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1227 1228 return HAL_RX_TLV_MSDU_LEN_GET(rx_pkt_tlvs); 1229 } 1230 1231 /** 1232 * hal_rx_tlv_msdu_len_set(): API to set the MSDU length 1233 * from rx_msdu_start TLV 1234 * 1235 * @buf: pointer to the start of RX PKT TLV headers 1236 * @len: msdu length 1237 * 1238 * Return: none 1239 */ 1240 static inline void hal_rx_tlv_msdu_len_set_be(uint8_t *buf, uint32_t len) 1241 { 1242 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1243 1244 HAL_RX_TLV_MSDU_LEN_GET(rx_pkt_tlvs) = len; 1245 } 1246 1247 /* 1248 * hal_rx_tlv_bw_get(): API to get the Bandwidth 1249 * Interval from rx_msdu_start 1250 * 1251 * @buf: pointer to the start of RX PKT TLV header 1252 * Return: uint32_t(bw) 1253 */ 1254 static inline uint32_t hal_rx_tlv_bw_get_be(uint8_t *buf) 1255 { 1256 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1257 1258 return HAL_RX_TLV_BW_GET(rx_pkt_tlvs); 1259 } 1260 1261 /** 1262 * hal_rx_tlv_toeplitz_get: API to get the toeplitz hash 1263 * from rx_msdu_start TLV 1264 * 1265 * @ buf: pointer to the start of RX PKT TLV headers 1266 * Return: toeplitz hash 1267 */ 1268 static inline uint32_t hal_rx_tlv_toeplitz_get_be(uint8_t *buf) 1269 { 1270 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1271 1272 return HAL_RX_TLV_FLOWID_TOEPLITZ_GET(rx_pkt_tlvs); 1273 } 1274 1275 /** 1276 * hal_rx_tlv_msdu_sgi_get(): API to get the Short Guard 1277 * Interval from rx_msdu_start TLV 1278 * 1279 * @buf: pointer to the start of RX PKT TLV headers 1280 * Return: uint32_t(sgi) 1281 */ 1282 static inline uint32_t hal_rx_tlv_sgi_get_be(uint8_t *buf) 1283 { 1284 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1285 1286 return HAL_RX_TLV_SGI_GET(rx_pkt_tlvs); 1287 } 1288 1289 /** 1290 * hal_rx_tlv_msdu_rate_mcs_get(): API to get the MCS rate 1291 * from rx_msdu_start TLV 1292 * 1293 * @buf: pointer to the start of RX PKT TLV headers 1294 * Return: uint32_t(rate_mcs) 1295 */ 1296 static inline uint32_t hal_rx_tlv_rate_mcs_get_be(uint8_t *buf) 1297 { 1298 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1299 uint32_t rate_mcs; 1300 1301 rate_mcs = HAL_RX_TLV_RATE_MCS_GET(rx_pkt_tlvs); 1302 1303 return rate_mcs; 1304 } 1305 1306 /* 1307 * Get key index from RX_MSDU_END 1308 */ 1309 /* 1310 * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet 1311 * from rx_msdu_end 1312 * 1313 * @buf: pointer to the start of RX PKT TLV header 1314 * Return: uint32_t(key id) 1315 */ 1316 1317 static inline uint8_t hal_rx_msdu_get_keyid_be(uint8_t *buf) 1318 { 1319 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1320 uint32_t keyid_octet; 1321 1322 keyid_octet = HAL_RX_TLV_KEYID_OCTET_GET(rx_pkt_tlvs); 1323 1324 return keyid_octet & 0x3; 1325 } 1326 1327 /* 1328 * hal_rx_tlv_get_rssi(): API to get the rssi of received pkt 1329 * from rx_msdu_start 1330 * 1331 * @buf: pointer to the start of RX PKT TLV header 1332 * Return: uint32_t(rssi) 1333 */ 1334 1335 static inline uint32_t hal_rx_tlv_get_rssi_be(uint8_t *buf) 1336 { 1337 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1338 uint32_t rssi; 1339 1340 rssi = HAL_RX_TLV_RSSI_GET(rx_pkt_tlvs); 1341 1342 return rssi; 1343 } 1344 1345 /* 1346 * hal_rx_tlv_get_freq(): API to get the frequency of operating channel 1347 * from rx_msdu_start 1348 * 1349 * @buf: pointer to the start of RX PKT TLV header 1350 * Return: uint32_t(frequency) 1351 */ 1352 1353 static inline uint32_t hal_rx_tlv_get_freq_be(uint8_t *buf) 1354 { 1355 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1356 uint32_t freq; 1357 1358 freq = HAL_RX_TLV_FREQ_GET(rx_pkt_tlvs); 1359 1360 return freq; 1361 } 1362 1363 1364 /* 1365 * hal_rx_tlv_get_pkt_type(): API to get the pkt type 1366 * from rx_msdu_start 1367 * 1368 * @buf: pointer to the start of RX PKT TLV header 1369 * Return: uint32_t(pkt type) 1370 */ 1371 1372 static inline uint32_t hal_rx_tlv_get_pkt_type_be(uint8_t *buf) 1373 { 1374 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1375 uint32_t pkt_type; 1376 1377 pkt_type = HAL_RX_TLV_PKT_TYPE_GET(rx_pkt_tlvs); 1378 1379 return pkt_type; 1380 } 1381 1382 /******************************************************************************* 1383 * RX ERROR APIS 1384 ******************************************************************************/ 1385 1386 /** 1387 * hal_rx_tlv_decrypt_err_get(): API to get the Decrypt ERR 1388 * from rx_mpdu_end TLV 1389 * 1390 * @buf: pointer to the start of RX PKT TLV headers 1391 * Return: uint32_t(decrypt_err) 1392 */ 1393 static inline uint32_t hal_rx_tlv_decrypt_err_get_be(uint8_t *buf) 1394 { 1395 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1396 uint32_t decrypt_err; 1397 1398 decrypt_err = HAL_RX_TLV_DECRYPT_ERR_GET(rx_pkt_tlvs); 1399 1400 return decrypt_err; 1401 } 1402 1403 /** 1404 * hal_rx_tlv_mic_err_get(): API to get the MIC ERR 1405 * from rx_tlv TLV 1406 * 1407 * @buf: pointer to the start of RX PKT TLV headers 1408 * Return: uint32_t(mic_err) 1409 */ 1410 static inline uint32_t hal_rx_tlv_mic_err_get_be(uint8_t *buf) 1411 { 1412 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1413 uint32_t mic_err; 1414 1415 mic_err = HAL_RX_TLV_MIC_ERR_GET(rx_pkt_tlvs); 1416 1417 return mic_err; 1418 } 1419 1420 /** 1421 * hal_get_reo_ent_desc_qdesc_addr_be(): API to get qdesc address of reo 1422 * entrance ring desc 1423 * 1424 * @desc: reo entrance ring descriptor 1425 * Return: qdesc address 1426 */ 1427 static inline uint8_t *hal_get_reo_ent_desc_qdesc_addr_be(uint8_t *desc) 1428 { 1429 return desc + REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET; 1430 } 1431 1432 /** 1433 * hal_set_reo_ent_desc_reo_dest_ind_be(): API to set reo destination 1434 * indication of reo entrance ring desc 1435 * 1436 * @desc: reo ent ring descriptor 1437 * @dst_ind: reo destination indication value 1438 * Return: None 1439 */ 1440 static inline void 1441 hal_set_reo_ent_desc_reo_dest_ind_be(uint8_t *desc, uint32_t dst_ind) 1442 { 1443 HAL_RX_FLD_SET(desc, REO_ENTRANCE_RING, 1444 REO_DESTINATION_INDICATION, dst_ind); 1445 } 1446 1447 /** 1448 * hal_rx_mpdu_sequence_number_get() - Get mpdu sequence number 1449 * @buf: pointer to packet buffer 1450 * 1451 * Return: mpdu sequence 1452 */ 1453 static inline int hal_rx_mpdu_sequence_number_get_be(uint8_t *buf) 1454 { 1455 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1456 1457 return HAL_RX_MPDU_SEQUENCE_NUMBER_GET(rx_pkt_tlvs); 1458 } 1459 1460 /** 1461 * hal_rx_msdu_packet_metadata_get(): API to get the 1462 * msdu information from rx_msdu_end TLV 1463 * 1464 * @ buf: pointer to the start of RX PKT TLV headers 1465 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1466 */ 1467 static inline void 1468 hal_rx_msdu_packet_metadata_get_generic_be(uint8_t *buf, 1469 void *pkt_msdu_metadata) 1470 { 1471 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1472 struct hal_rx_msdu_metadata *msdu_metadata = 1473 (struct hal_rx_msdu_metadata *)pkt_msdu_metadata; 1474 1475 msdu_metadata->l3_hdr_pad = 1476 HAL_RX_TLV_L3_HEADER_PADDING_GET(rx_pkt_tlvs); 1477 msdu_metadata->sa_idx = HAL_RX_TLV_SA_IDX_GET(rx_pkt_tlvs); 1478 msdu_metadata->da_idx = HAL_RX_TLV_DA_IDX_GET(rx_pkt_tlvs); 1479 msdu_metadata->sa_sw_peer_id = 1480 HAL_RX_TLV_SA_SW_PEER_ID_GET(rx_pkt_tlvs); 1481 } 1482 1483 /* 1484 * hal_rx_msdu_start_nss_get_kiwi(): API to get the NSS 1485 * Interval from rx_msdu_start 1486 * 1487 * @buf: pointer to the start of RX PKT TLV header 1488 * Return: uint32_t(nss) 1489 */ 1490 static inline uint32_t hal_rx_tlv_nss_get_be(uint8_t *buf) 1491 { 1492 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1493 uint8_t mimo_ss_bitmap; 1494 1495 mimo_ss_bitmap = HAL_RX_TLV_MIMO_SS_BITMAP(rx_pkt_tlvs); 1496 1497 return qdf_get_hweight8(mimo_ss_bitmap); 1498 } 1499 1500 #ifdef GET_MSDU_AGGREGATION 1501 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 1502 {\ 1503 bool first_msdu, last_msdu; \ 1504 first_msdu = HAL_RX_TLV_FIRST_MSDU_GET(rx_desc);\ 1505 last_msdu = HAL_RX_TLV_LAST_MSDU_GET(rx_desc);\ 1506 if (first_msdu && last_msdu)\ 1507 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 1508 else\ 1509 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 1510 } \ 1511 1512 #define HAL_RX_SET_MSDU_AGGREGATION((rs_mpdu), (rs_ppdu))\ 1513 {\ 1514 if (rs_mpdu->rs_flags & IEEE80211_AMSDU_FLAG)\ 1515 rs_ppdu->rs_flags |= IEEE80211_AMSDU_FLAG;\ 1516 } \ 1517 1518 #else 1519 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 1520 #define HAL_RX_SET_MSDU_AGGREGATION(rs_mpdu, rs_ppdu) 1521 #endif 1522 1523 /** 1524 * hal_rx_mon_hw_desc_get_mpdu_status_be(): Retrieve MPDU status 1525 * 1526 * @ hw_desc_addr: Start address of Rx HW TLVs 1527 * @ rs: Status for monitor mode 1528 * 1529 * Return: void 1530 */ 1531 static inline void 1532 hal_rx_mon_hw_desc_get_mpdu_status_be(void *hw_desc_addr, 1533 struct mon_rx_status *rs) 1534 { 1535 uint32_t reg_value; 1536 struct rx_pkt_tlvs *rx_desc = 1537 (struct rx_pkt_tlvs *)hw_desc_addr; 1538 const uint32_t sgi_hw_to_cdp[] = { 1539 CDP_SGI_0_8_US, 1540 CDP_SGI_0_4_US, 1541 CDP_SGI_1_6_US, 1542 CDP_SGI_3_2_US, 1543 }; 1544 1545 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 1546 1547 rs->ant_signal_db = HAL_RX_TLV_ANT_SIGNAL_DB_GET(rx_desc); 1548 rs->is_stbc = HAL_RX_TLV_STBC_GET(rx_desc); 1549 1550 reg_value = HAL_RX_TLV_SGI_GET(rx_desc); 1551 rs->sgi = sgi_hw_to_cdp[reg_value]; 1552 1553 reg_value = HAL_RX_TLV_RECEPTION_TYPE_GET(rx_desc); 1554 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 1555 /* TODO: rs->beamformed should be set for SU beamforming also */ 1556 } 1557 1558 static inline uint32_t hal_rx_tlv_tid_get_be(uint8_t *buf) 1559 { 1560 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1561 uint32_t tid; 1562 1563 tid = HAL_RX_TLV_TID_GET(rx_pkt_tlvs); 1564 1565 return tid; 1566 } 1567 1568 /* 1569 * hal_rx_tlv_reception_type_get(): API to get the reception type 1570 * Interval from rx_msdu_start 1571 * 1572 * @buf: pointer to the start of RX PKT TLV header 1573 * Return: uint32_t(reception_type) 1574 */ 1575 static inline 1576 uint32_t hal_rx_tlv_reception_type_get_be(uint8_t *buf) 1577 { 1578 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1579 uint32_t reception_type; 1580 1581 reception_type = HAL_RX_TLV_RECEPTION_TYPE_GET(rx_pkt_tlvs); 1582 1583 return reception_type; 1584 } 1585 1586 /** 1587 * hal_rx_msdu_end_da_idx_get_be: API to get da_idx 1588 * from rx_msdu_end TLV 1589 * 1590 * @ buf: pointer to the start of RX PKT TLV headers 1591 * Return: da index 1592 */ 1593 static inline uint16_t hal_rx_msdu_end_da_idx_get_be(uint8_t *buf) 1594 { 1595 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1596 uint16_t da_idx; 1597 1598 da_idx = HAL_RX_TLV_DA_IDX_GET(rx_pkt_tlvs); 1599 1600 return da_idx; 1601 } 1602 1603 /** 1604 * hal_rx_get_rx_fragment_number_be(): Function to retrieve rx fragment number 1605 * 1606 * @nbuf: Network buffer 1607 * Returns: rx fragment number 1608 */ 1609 static inline 1610 uint8_t hal_rx_get_rx_fragment_number_be(uint8_t *buf) 1611 { 1612 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1613 1614 /* Return first 4 bits as fragment number */ 1615 return (HAL_RX_MPDU_SEQUENCE_NUMBER_GET(rx_pkt_tlvs) & 1616 DOT11_SEQ_FRAG_MASK); 1617 } 1618 1619 /** 1620 * hal_rx_msdu_end_da_is_mcbc_get_be(): API to check if pkt is MCBC 1621 * from rx_msdu_end TLV 1622 * 1623 * @ buf: pointer to the start of RX PKT TLV headers 1624 * Return: da_is_mcbc 1625 */ 1626 static inline uint8_t 1627 hal_rx_tlv_da_is_mcbc_get_be(uint8_t *buf) 1628 { 1629 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1630 1631 return HAL_RX_TLV_DA_IS_MCBC_GET(rx_pkt_tlvs); 1632 } 1633 1634 /** 1635 * hal_rx_tlv_is_tkip_mic_err_get_be(): API to get tkip Mic error 1636 * from rx_msdu_end TLV 1637 * 1638 * @ buf: pointer to the start of RX PKT TLV headers 1639 * Return: tkip_mic_err 1640 */ 1641 static inline uint8_t 1642 hal_rx_tlv_is_tkip_mic_err_get_be(uint8_t *buf) 1643 { 1644 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1645 1646 return HAL_RX_TLV_IS_TKIP_MIC_ERR_GET(rx_pkt_tlvs); 1647 } 1648 1649 /** 1650 * hal_rx_tlvd_sa_is_valid_get_be(): API to get the sa_is_valid bit from 1651 * rx_msdu_end TLV 1652 * 1653 * @ buf: pointer to the start of RX PKT TLV headers 1654 * Return: sa_is_valid bit 1655 */ 1656 static inline uint8_t 1657 hal_rx_tlv_sa_is_valid_get_be(uint8_t *buf) 1658 { 1659 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1660 uint8_t sa_is_valid; 1661 1662 sa_is_valid = HAL_RX_TLV_SA_IS_VALID_GET(rx_pkt_tlvs); 1663 1664 return sa_is_valid; 1665 } 1666 1667 /** 1668 * hal_rx_tlv_sa_idx_get_be(): API to get the sa_idx from rx_msdu_end TLV 1669 * 1670 * @ buf: pointer to the start of RX PKT TLV headers 1671 * Return: sa_idx (SA AST index) 1672 */ 1673 static inline 1674 uint16_t hal_rx_tlv_sa_idx_get_be(uint8_t *buf) 1675 { 1676 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1677 uint16_t sa_idx; 1678 1679 sa_idx = HAL_RX_TLV_SA_IDX_GET(rx_pkt_tlvs); 1680 1681 return sa_idx; 1682 } 1683 1684 /** 1685 * hal_rx_desc_is_first_msdu_be() - Check if first msdu 1686 * 1687 * @hal_soc_hdl: hal_soc handle 1688 * @hw_desc_addr: hardware descriptor address 1689 * 1690 * Return: 0 - success/ non-zero failure 1691 */ 1692 static inline uint32_t hal_rx_desc_is_first_msdu_be(void *hw_desc_addr) 1693 { 1694 struct rx_pkt_tlvs *rx_pkt_tlvs = 1695 (struct rx_pkt_tlvs *)hw_desc_addr; 1696 1697 return HAL_RX_TLV_FIRST_MSDU_GET(rx_pkt_tlvs); 1698 } 1699 1700 /** 1701 * hal_rx_tlv_l3_hdr_padding_get_be(): API to get the l3_header padding 1702 * from rx_msdu_end TLV 1703 * 1704 * @ buf: pointer to the start of RX PKT TLV headers 1705 * Return: number of l3 header padding bytes 1706 */ 1707 static inline uint32_t hal_rx_tlv_l3_hdr_padding_get_be(uint8_t *buf) 1708 { 1709 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1710 uint32_t l3_header_padding; 1711 1712 l3_header_padding = HAL_RX_TLV_L3_HEADER_PADDING_GET(rx_pkt_tlvs); 1713 1714 return l3_header_padding; 1715 } 1716 1717 /* 1718 * @ hal_rx_encryption_info_valid_be: Returns encryption type. 1719 * 1720 * @ buf: rx_tlv_hdr of the received packet 1721 * @ Return: encryption type 1722 */ 1723 static inline uint32_t hal_rx_encryption_info_valid_be(uint8_t *buf) 1724 { 1725 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1726 uint32_t encryption_info = 1727 HAL_RX_TLV_MPDU_ENCRYPTION_INFO_VALID(rx_pkt_tlvs); 1728 1729 return encryption_info; 1730 } 1731 1732 /** 1733 * hal_rx_tlv_first_msdu_get_be: API to get first msdu status 1734 * from rx_msdu_end TLV 1735 * 1736 * @ buf: pointer to the start of RX PKT TLV headers 1737 * Return: first_msdu 1738 */ 1739 static inline uint8_t hal_rx_tlv_first_msdu_get_be(uint8_t *buf) 1740 { 1741 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1742 uint8_t first_msdu; 1743 1744 first_msdu = HAL_RX_TLV_FIRST_MSDU_GET(rx_pkt_tlvs); 1745 1746 return first_msdu; 1747 } 1748 1749 /** 1750 * hal_rx_tlv_da_is_valid_get_be: API to check if da is valid 1751 * from rx_msdu_end TLV 1752 * 1753 * @ buf: pointer to the start of RX PKT TLV headers 1754 * Return: da_is_valid 1755 */ 1756 static inline uint8_t hal_rx_tlv_da_is_valid_get_be(uint8_t *buf) 1757 { 1758 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1759 uint8_t da_is_valid; 1760 1761 da_is_valid = HAL_RX_TLV_DA_IS_VALID_GET(rx_pkt_tlvs); 1762 1763 return da_is_valid; 1764 } 1765 1766 /** 1767 * hal_rx_tlv_last_msdu_get_be: API to get last msdu status 1768 * from rx_msdu_end TLV 1769 * 1770 * @ buf: pointer to the start of RX PKT TLV headers 1771 * Return: last_msdu 1772 */ 1773 static inline uint8_t hal_rx_tlv_last_msdu_get_be(uint8_t *buf) 1774 { 1775 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1776 uint8_t last_msdu; 1777 1778 last_msdu = HAL_RX_TLV_LAST_MSDU_GET(rx_pkt_tlvs); 1779 1780 return last_msdu; 1781 } 1782 1783 /* 1784 * hal_rx_get_mpdu_mac_ad4_valid_be(): Retrieves if mpdu 4th addr is valid 1785 * 1786 * @nbuf: Network buffer 1787 * Returns: value of mpdu 4th address valid field 1788 */ 1789 static inline bool hal_rx_get_mpdu_mac_ad4_valid_be(uint8_t *buf) 1790 { 1791 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1792 bool ad4_valid = 0; 1793 1794 ad4_valid = HAL_RX_TLV_MPDU_MAC_ADDR_AD4_VALID_GET(rx_pkt_tlvs); 1795 1796 return ad4_valid; 1797 } 1798 1799 /** 1800 * hal_rx_mpdu_start_sw_peer_id_get_be: Retrieve sw peer_id 1801 * @buf: network buffer 1802 * 1803 * Return: sw peer_id 1804 */ 1805 static inline uint32_t hal_rx_mpdu_start_sw_peer_id_get_be(uint8_t *buf) 1806 { 1807 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1808 1809 return HAL_RX_TLV_SW_PEER_ID_GET(rx_pkt_tlvs); 1810 } 1811 1812 /** 1813 * hal_rx_mpdu_get_to_ds_be(): API to get the tods info 1814 * from rx_mpdu_start 1815 * 1816 * @buf: pointer to the start of RX PKT TLV header 1817 * Return: uint32_t(to_ds) 1818 */ 1819 static inline uint32_t hal_rx_mpdu_get_to_ds_be(uint8_t *buf) 1820 { 1821 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1822 1823 return HAL_RX_TLV_MPDU_GET_TODS(rx_pkt_tlvs); 1824 } 1825 1826 /* 1827 * hal_rx_mpdu_get_fr_ds_be(): API to get the from ds info 1828 * from rx_mpdu_start 1829 * 1830 * @buf: pointer to the start of RX PKT TLV header 1831 * Return: uint32_t(fr_ds) 1832 */ 1833 static inline uint32_t hal_rx_mpdu_get_fr_ds_be(uint8_t *buf) 1834 { 1835 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1836 1837 return HAL_RX_TLV_MPDU_GET_FROMDS(rx_pkt_tlvs); 1838 } 1839 1840 /* 1841 * hal_rx_get_mpdu_frame_control_valid_be(): Retrieves mpdu 1842 * frame control valid 1843 * 1844 * @nbuf: Network buffer 1845 * Returns: value of frame control valid field 1846 */ 1847 static inline uint8_t hal_rx_get_mpdu_frame_control_valid_be(uint8_t *buf) 1848 { 1849 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1850 1851 return HAL_RX_TLV_MPDU_GET_FRAME_CONTROL_VALID(rx_pkt_tlvs); 1852 } 1853 1854 /* 1855 * hal_rx_mpdu_get_addr2_be(): API to check get address2 of the mpdu 1856 * in the packet 1857 * 1858 * @buf: pointer to the start of RX PKT TLV header 1859 * @mac_addr: pointer to mac address 1860 * Return: success/failure 1861 */ 1862 static inline QDF_STATUS hal_rx_mpdu_get_addr2_be(uint8_t *buf, 1863 uint8_t *mac_addr) 1864 { 1865 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1866 struct __attribute__((__packed__)) hal_addr2 { 1867 uint16_t ad2_15_0; 1868 uint32_t ad2_47_16; 1869 }; 1870 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 1871 uint32_t mac_addr_ad2_valid; 1872 1873 mac_addr_ad2_valid = HAL_RX_TLV_MPDU_MAC_ADDR_AD2_VALID_GET(rx_pkt_tlvs); 1874 1875 if (mac_addr_ad2_valid) { 1876 addr->ad2_15_0 = HAL_RX_TLV_MPDU_AD2_15_0_GET(rx_pkt_tlvs); 1877 addr->ad2_47_16 = HAL_RX_TLV_MPDU_AD2_47_16_GET(rx_pkt_tlvs); 1878 return QDF_STATUS_SUCCESS; 1879 } 1880 1881 return QDF_STATUS_E_FAILURE; 1882 } 1883 1884 /* 1885 * hal_rx_mpdu_get_addr3_be(): API to get address3 of the mpdu 1886 * in the packet 1887 * 1888 * @buf: pointer to the start of RX PKT TLV header 1889 * @mac_addr: pointer to mac address 1890 * Return: success/failure 1891 */ 1892 static inline QDF_STATUS hal_rx_mpdu_get_addr3_be(uint8_t *buf, 1893 uint8_t *mac_addr) 1894 { 1895 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1896 struct __attribute__((__packed__)) hal_addr3 { 1897 uint32_t ad3_31_0; 1898 uint16_t ad3_47_32; 1899 }; 1900 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 1901 uint32_t mac_addr_ad3_valid; 1902 1903 mac_addr_ad3_valid = HAL_RX_TLV_MPDU_MAC_ADDR_AD3_VALID_GET(rx_pkt_tlvs); 1904 1905 if (mac_addr_ad3_valid) { 1906 addr->ad3_31_0 = HAL_RX_TLV_MPDU_AD3_31_0_GET(rx_pkt_tlvs); 1907 addr->ad3_47_32 = HAL_RX_TLV_MPDU_AD3_47_32_GET(rx_pkt_tlvs); 1908 return QDF_STATUS_SUCCESS; 1909 } 1910 1911 return QDF_STATUS_E_FAILURE; 1912 } 1913 1914 /* 1915 * hal_rx_get_mpdu_sequence_control_valid_be(): Get mpdu 1916 * sequence control valid 1917 * 1918 * @nbuf: Network buffer 1919 * Returns: value of sequence control valid field 1920 */ 1921 static inline uint8_t hal_rx_get_mpdu_sequence_control_valid_be(uint8_t *buf) 1922 { 1923 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1924 1925 return HAL_RX_TLV_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_pkt_tlvs); 1926 } 1927 1928 /** 1929 * hal_rx_tid_get_be: get tid based on qos control valid. 1930 * @hal_soc_hdl: hal_soc handle 1931 * @ buf: pointer to rx pkt TLV. 1932 * 1933 * Return: tid 1934 */ 1935 static inline uint32_t hal_rx_tid_get_be(hal_soc_handle_t hal_soc_hdl, 1936 uint8_t *buf) 1937 { 1938 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1939 uint8_t qos_control_valid = 1940 HAL_RX_TLV_MPDU_QOS_CONTROL_VALID_GET(rx_pkt_tlvs); 1941 1942 if (qos_control_valid) 1943 return hal_rx_tlv_tid_get_be(buf); 1944 1945 return HAL_RX_NON_QOS_TID; 1946 } 1947 1948 static inline 1949 uint8_t hal_rx_get_fc_valid_be(uint8_t *buf) 1950 { 1951 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1952 1953 return HAL_RX_TLV_GET_FC_VALID(rx_pkt_tlvs); 1954 } 1955 1956 static inline uint8_t hal_rx_get_to_ds_flag_be(uint8_t *buf) 1957 { 1958 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1959 1960 return HAL_RX_TLV_GET_TO_DS_FLAG(rx_pkt_tlvs); 1961 } 1962 1963 static inline uint8_t hal_rx_get_mac_addr2_valid_be(uint8_t *buf) 1964 { 1965 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1966 1967 return HAL_RX_TLV_MPDU_MAC_ADDR_AD2_VALID_GET(rx_pkt_tlvs); 1968 } 1969 1970 /** 1971 * hal_rx_msdu_flow_idx_get_be: API to get flow index 1972 * from rx_msdu_end TLV 1973 * @buf: pointer to the start of RX PKT TLV headers 1974 * 1975 * Return: flow index value from MSDU END TLV 1976 */ 1977 static inline uint32_t hal_rx_msdu_flow_idx_get_be(uint8_t *buf) 1978 { 1979 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1980 1981 return HAL_RX_TLV_FLOW_IDX_GET(pkt_tlvs); 1982 } 1983 1984 /** 1985 * hal_rx_msdu_get_reo_destination_indication_be: API to get 1986 * reo_destination_indication from rx_msdu_end TLV 1987 * @buf: pointer to the start of RX PKT TLV headers 1988 * @reo_destination_indication: pointer to return value of 1989 * reo_destination_indication 1990 * 1991 * Return: none 1992 */ 1993 static inline void 1994 hal_rx_msdu_get_reo_destination_indication_be(uint8_t *buf, 1995 uint32_t *reo_destination_indication) 1996 { 1997 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1998 1999 *reo_destination_indication = HAL_RX_TLV_REO_DEST_IND_GET(pkt_tlvs); 2000 } 2001 2002 /** 2003 * hal_rx_msdu_flow_idx_invalid_be: API to get flow index invalid 2004 * from rx_msdu_end TLV 2005 * @buf: pointer to the start of RX PKT TLV headers 2006 * 2007 * Return: flow index invalid value from MSDU END TLV 2008 */ 2009 static inline bool hal_rx_msdu_flow_idx_invalid_be(uint8_t *buf) 2010 { 2011 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2012 2013 return HAL_RX_TLV_FLOW_IDX_INVALID_GET(pkt_tlvs); 2014 } 2015 2016 /** 2017 * hal_rx_msdu_flow_idx_timeout_be: API to get flow index timeout 2018 * from rx_msdu_end TLV 2019 * @buf: pointer to the start of RX PKT TLV headers 2020 * 2021 * Return: flow index timeout value from MSDU END TLV 2022 */ 2023 static inline bool hal_rx_msdu_flow_idx_timeout_be(uint8_t *buf) 2024 { 2025 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2026 2027 return HAL_RX_TLV_FLOW_IDX_TIMEOUT_GET(pkt_tlvs); 2028 } 2029 2030 /** 2031 * hal_rx_msdu_fse_metadata_get_be: API to get FSE metadata 2032 * from rx_msdu_end TLV 2033 * @buf: pointer to the start of RX PKT TLV headers 2034 * 2035 * Return: fse metadata value from MSDU END TLV 2036 */ 2037 static inline uint32_t hal_rx_msdu_fse_metadata_get_be(uint8_t *buf) 2038 { 2039 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2040 2041 return HAL_RX_TLV_FSE_METADATA_GET(pkt_tlvs); 2042 } 2043 2044 /** 2045 * hal_rx_msdu_cce_metadata_get_be: API to get CCE metadata 2046 * from rx_msdu_end TLV 2047 * @buf: pointer to the start of RX PKT TLV headers 2048 * 2049 * Return: cce_metadata 2050 */ 2051 static inline uint16_t 2052 hal_rx_msdu_cce_metadata_get_be(uint8_t *buf) 2053 { 2054 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2055 2056 return HAL_RX_TLV_CCE_METADATA_GET(pkt_tlvs); 2057 } 2058 2059 /** 2060 * hal_rx_msdu_get_flow_params_be: API to get flow index, flow index invalid 2061 * and flow index timeout from rx_msdu_end TLV 2062 * @buf: pointer to the start of RX PKT TLV headers 2063 * @flow_invalid: pointer to return value of flow_idx_valid 2064 * @flow_timeout: pointer to return value of flow_idx_timeout 2065 * @flow_index: pointer to return value of flow_idx 2066 * 2067 * Return: none 2068 */ 2069 static inline void 2070 hal_rx_msdu_get_flow_params_be(uint8_t *buf, 2071 bool *flow_invalid, 2072 bool *flow_timeout, 2073 uint32_t *flow_index) 2074 { 2075 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2076 2077 *flow_invalid = HAL_RX_TLV_FLOW_IDX_INVALID_GET(pkt_tlvs); 2078 *flow_timeout = HAL_RX_TLV_FLOW_IDX_TIMEOUT_GET(pkt_tlvs); 2079 *flow_index = HAL_RX_TLV_FLOW_IDX_GET(pkt_tlvs); 2080 } 2081 2082 /** 2083 * hal_rx_tlv_get_tcp_chksum_be() - API to get tcp checksum 2084 * @buf: rx_tlv_hdr 2085 * 2086 * Return: tcp checksum 2087 */ 2088 static inline uint16_t 2089 hal_rx_tlv_get_tcp_chksum_be(uint8_t *buf) 2090 { 2091 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2092 2093 return HAL_RX_TLV_GET_TCP_CHKSUM(rx_pkt_tlvs); 2094 } 2095 2096 /** 2097 * hal_rx_get_rx_sequence_be(): Function to retrieve rx sequence number 2098 * 2099 * @nbuf: Network buffer 2100 * Returns: rx sequence number 2101 */ 2102 static inline 2103 uint16_t hal_rx_get_rx_sequence_be(uint8_t *buf) 2104 { 2105 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2106 2107 return HAL_RX_MPDU_SEQUENCE_NUMBER_GET(rx_pkt_tlvs); 2108 } 2109 2110 #ifdef RECEIVE_OFFLOAD 2111 #ifdef QCA_WIFI_KIWI_V2 2112 static inline 2113 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_be(uint8_t *buf) 2114 { 2115 /* 2116 * cumulative l4 checksum is not supported in V2 and 2117 * cumulative_l4_checksum field is not present 2118 */ 2119 return 0; 2120 } 2121 #else 2122 /** 2123 * hal_rx_get_fisa_cumulative_l4_checksum_be() - Retrieve cumulative 2124 * checksum 2125 * @buf: buffer pointer 2126 * 2127 * Return: cumulative checksum 2128 */ 2129 static inline 2130 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_be(uint8_t *buf) 2131 { 2132 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2133 2134 return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(rx_pkt_tlvs); 2135 } 2136 #endif 2137 2138 /** 2139 * hal_rx_get_fisa_cumulative_ip_length_be() - Retrieve cumulative 2140 * ip length 2141 * @buf: buffer pointer 2142 * 2143 * Return: cumulative length 2144 */ 2145 static inline 2146 uint16_t hal_rx_get_fisa_cumulative_ip_length_be(uint8_t *buf) 2147 { 2148 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2149 2150 return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(rx_pkt_tlvs); 2151 } 2152 2153 /** 2154 * hal_rx_get_udp_proto_be() - Retrieve udp proto value 2155 * @buf: buffer 2156 * 2157 * Return: udp proto bit 2158 */ 2159 static inline 2160 bool hal_rx_get_udp_proto_be(uint8_t *buf) 2161 { 2162 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2163 2164 return HAL_RX_TLV_GET_UDP_PROTO(rx_pkt_tlvs); 2165 } 2166 #endif 2167 2168 /** 2169 * hal_rx_get_flow_agg_continuation_be() - retrieve flow agg 2170 * continuation 2171 * @buf: buffer 2172 * 2173 * Return: flow agg 2174 */ 2175 static inline 2176 bool hal_rx_get_flow_agg_continuation_be(uint8_t *buf) 2177 { 2178 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2179 2180 return HAL_RX_TLV_GET_FLOW_AGGR_CONT(rx_pkt_tlvs); 2181 } 2182 2183 /** 2184 * hal_rx_get_flow_agg_count_be()- Retrieve flow agg count 2185 * @buf: buffer 2186 * 2187 * Return: flow agg count 2188 */ 2189 static inline 2190 uint8_t hal_rx_get_flow_agg_count_be(uint8_t *buf) 2191 { 2192 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2193 2194 return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(rx_pkt_tlvs); 2195 } 2196 2197 /** 2198 * hal_rx_get_fisa_timeout_be() - Retrieve fisa timeout 2199 * @buf: buffer 2200 * 2201 * Return: fisa timeout 2202 */ 2203 static inline 2204 bool hal_rx_get_fisa_timeout_be(uint8_t *buf) 2205 { 2206 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2207 2208 return HAL_RX_TLV_GET_FISA_TIMEOUT(rx_pkt_tlvs); 2209 } 2210 2211 /** 2212 * hal_rx_mpdu_start_tlv_tag_valid_be () - API to check if RX_MPDU_START 2213 * tlv tag is valid 2214 * 2215 *@rx_tlv_hdr: start address of rx_pkt_tlvs 2216 * 2217 * Return: true if RX_MPDU_START is valid, else false. 2218 */ 2219 static inline uint8_t hal_rx_mpdu_start_tlv_tag_valid_be(void *rx_tlv_hdr) 2220 { 2221 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 2222 uint32_t tlv_tag; 2223 2224 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 2225 2226 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 2227 } 2228 2229 /** 2230 * hal_rx_msdu_end_offset_get_generic(): API to get the 2231 * msdu_end structure offset rx_pkt_tlv structure 2232 * 2233 * NOTE: API returns offset of msdu_end TLV from structure 2234 * rx_pkt_tlvs 2235 */ 2236 static inline uint32_t hal_rx_msdu_end_offset_get_generic(void) 2237 { 2238 return RX_PKT_TLV_OFFSET(msdu_end_tlv); 2239 } 2240 2241 /** 2242 * hal_rx_mpdu_start_offset_get_generic(): API to get the 2243 * mpdu_start structure offset rx_pkt_tlv structure 2244 * 2245 * NOTE: API returns offset of attn TLV from structure 2246 * rx_pkt_tlvs 2247 */ 2248 static inline uint32_t hal_rx_mpdu_start_offset_get_generic(void) 2249 { 2250 return RX_PKT_TLV_OFFSET(mpdu_start_tlv); 2251 } 2252 2253 #ifndef NO_RX_PKT_HDR_TLV 2254 static inline uint32_t hal_rx_pkt_tlv_offset_get_generic(void) 2255 { 2256 return RX_PKT_TLV_OFFSET(pkt_hdr_tlv); 2257 } 2258 #endif 2259 2260 #ifdef CONFIG_WORD_BASED_TLV 2261 #define MPDU_START_WMASK 0x074C 2262 #define MSDU_END_WMASK 0x13FC1 2263 2264 /** 2265 * hal_rx_mpdu_start_wmask_get_be(): API to get the mpdu_start_tlv word mask 2266 * 2267 * return: Word mask for MPDU start tlv 2268 */ 2269 static inline uint32_t hal_rx_mpdu_start_wmask_get_be(void) 2270 { 2271 return MPDU_START_WMASK; 2272 } 2273 2274 /** 2275 * hal_rx_msdu_end_wmask_get_be(): API to get the msdu_end_tlv word mask 2276 * 2277 * return: Word mask for MSDU end tlv 2278 */ 2279 static inline uint32_t hal_rx_msdu_end_wmask_get_be(void) 2280 { 2281 return MSDU_END_WMASK; 2282 } 2283 #endif 2284 2285 #ifdef RECEIVE_OFFLOAD 2286 static inline int 2287 hal_rx_tlv_get_offload_info_be(uint8_t *rx_tlv, 2288 struct hal_offload_info *offload_info) 2289 { 2290 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)rx_tlv; 2291 2292 offload_info->lro_eligible = HAL_RX_TLV_GET_LRO_ELIGIBLE(rx_pkt_tlvs); 2293 offload_info->flow_id = HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(rx_pkt_tlvs); 2294 offload_info->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_pkt_tlvs); 2295 offload_info->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_pkt_tlvs); 2296 2297 if (offload_info->tcp_proto) { 2298 offload_info->tcp_pure_ack = 2299 HAL_RX_TLV_GET_TCP_PURE_ACK(rx_pkt_tlvs); 2300 offload_info->tcp_offset = 2301 HAL_RX_TLV_GET_TCP_OFFSET(rx_pkt_tlvs); 2302 offload_info->tcp_win = HAL_RX_TLV_GET_TCP_WIN(rx_pkt_tlvs); 2303 offload_info->tcp_seq_num = HAL_RX_TLV_GET_TCP_SEQ(rx_pkt_tlvs); 2304 offload_info->tcp_ack_num = HAL_RX_TLV_GET_TCP_ACK(rx_pkt_tlvs); 2305 } 2306 return 0; 2307 } 2308 2309 static inline int hal_rx_get_proto_params_be(uint8_t *buf, void *proto_params) 2310 { 2311 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2312 struct hal_proto_params *param = 2313 (struct hal_proto_params *)proto_params; 2314 2315 param->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_pkt_tlvs); 2316 param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(rx_pkt_tlvs); 2317 param->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_pkt_tlvs); 2318 2319 return 0; 2320 } 2321 2322 static inline int hal_rx_get_l3_l4_offsets_be(uint8_t *buf, 2323 uint32_t *l3_hdr_offset, 2324 uint32_t *l4_hdr_offset) 2325 { 2326 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2327 2328 *l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(rx_pkt_tlvs); 2329 *l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_pkt_tlvs); 2330 2331 return 0; 2332 } 2333 #endif 2334 2335 /** 2336 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 2337 * from rx_msdu_start TLV 2338 * 2339 * @ buf: pointer to the start of RX PKT TLV headers 2340 * Return: msdu length 2341 */ 2342 static inline uint32_t hal_rx_msdu_start_msdu_len_get_be(uint8_t *buf) 2343 { 2344 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2345 uint32_t msdu_len; 2346 2347 msdu_len = HAL_RX_TLV_MSDU_LEN_GET(rx_pkt_tlvs); 2348 2349 return msdu_len; 2350 } 2351 2352 /** 2353 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2354 * 2355 * @nbuf: Network buffer 2356 * Returns: rx more fragment bit 2357 * 2358 */ 2359 static inline uint16_t hal_rx_get_frame_ctrl_field_be(uint8_t *buf) 2360 { 2361 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2362 uint16_t frame_ctrl = 0; 2363 2364 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_pkt_tlvs); 2365 2366 return frame_ctrl; 2367 } 2368 2369 /* 2370 * hal_rx_tlv_get_is_decrypted_be(): API to get the decrypt status of the 2371 * packet from msdu_end 2372 * 2373 * @buf: pointer to the start of RX PKT TLV header 2374 * Return: uint32_t(decryt status) 2375 */ 2376 static inline uint32_t hal_rx_tlv_get_is_decrypted_be(uint8_t *buf) 2377 { 2378 struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2379 uint32_t is_decrypt = 0; 2380 uint32_t decrypt_status; 2381 2382 decrypt_status = HAL_RX_TLV_DECRYPT_STATUS_GET(rx_pkt_tlvs); 2383 2384 if (!decrypt_status) 2385 is_decrypt = 1; 2386 2387 return is_decrypt; 2388 } 2389 2390 #ifdef NO_RX_PKT_HDR_TLV 2391 /** 2392 * hal_rx_pkt_hdr_get_be(): API to get 80211 header 2393 * @buf: start of rx_pkt_tlv 2394 * 2395 * If NO_RX_PKT_HDR_TLV is enabled, then this API assume caller gives a raw 2396 * data, get 80211 header from packet data directly. 2397 * If NO_RX_PKT_HDR_TLV is disabled, then get it from rx_pkt_hdr_tlv in 2398 * rx_pkt_tlvs. 2399 * 2400 * Return: pointer to start of 80211 header 2401 */ 2402 static inline uint8_t *hal_rx_pkt_hdr_get_be(uint8_t *buf) 2403 { 2404 return buf + RX_PKT_TLVS_LEN; 2405 } 2406 #else 2407 static inline uint8_t *hal_rx_pkt_hdr_get_be(uint8_t *buf) 2408 { 2409 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2410 2411 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 2412 } 2413 #endif 2414 2415 /** 2416 * hal_rx_tlv_csum_err_get_be() - Get IP and tcp-udp checksum fail flag 2417 * @rx_tlv_hdr: start address of rx_tlv_hdr 2418 * @ip_csum_err: buffer to return ip_csum_fail flag 2419 * @tcp_udp_csum_fail: placeholder to return tcp-udp checksum fail flag 2420 * 2421 * Return: None 2422 */ 2423 static inline void 2424 hal_rx_tlv_csum_err_get_be(uint8_t *rx_tlv_hdr, uint32_t *ip_csum_err, 2425 uint32_t *tcp_udp_csum_err) 2426 { 2427 struct rx_pkt_tlvs *rx_pkt_tlvs = 2428 (struct rx_pkt_tlvs *)rx_tlv_hdr; 2429 2430 *ip_csum_err = HAL_RX_TLV_IP_CSUM_FAIL_GET(rx_pkt_tlvs); 2431 *tcp_udp_csum_err = HAL_RX_TLV_TCP_UDP_CSUM_FAIL_GET(rx_pkt_tlvs); 2432 } 2433 2434 static inline 2435 uint32_t hal_rx_tlv_mpdu_len_err_get_be(void *hw_desc_addr) 2436 { 2437 struct rx_pkt_tlvs *rx_pkt_tlvs = 2438 (struct rx_pkt_tlvs *)hw_desc_addr; 2439 2440 return HAL_RX_TLV_MPDU_LEN_ERR_GET(rx_pkt_tlvs); 2441 } 2442 2443 static inline 2444 uint32_t hal_rx_tlv_mpdu_fcs_err_get_be(void *hw_desc_addr) 2445 { 2446 struct rx_pkt_tlvs *rx_pkt_tlvs = 2447 (struct rx_pkt_tlvs *)hw_desc_addr; 2448 2449 return HAL_RX_TLV_MPDU_FCS_ERR_GET(rx_pkt_tlvs); 2450 } 2451 2452 /** 2453 * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit 2454 * 2455 * @nbuf: Network buffer 2456 * Returns: rx more fragment bit 2457 */ 2458 static inline 2459 uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) 2460 { 2461 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2462 uint16_t frame_ctrl = 0; 2463 2464 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(pkt_tlvs) >> 2465 DOT11_FC1_MORE_FRAG_OFFSET; 2466 2467 /* more fragment bit if at offset bit 4 */ 2468 return frame_ctrl; 2469 } 2470 2471 /* 2472 * hal_rx_msdu_is_wlan_mcast_generic_be(): Check if the buffer is for multicast 2473 * address 2474 * @nbuf: Network buffer 2475 * 2476 * Returns: flag to indicate whether the nbuf has MC/BC address 2477 */ 2478 static inline uint32_t hal_rx_msdu_is_wlan_mcast_generic_be(qdf_nbuf_t nbuf) 2479 { 2480 uint8_t *buf = qdf_nbuf_data(nbuf); 2481 2482 return HAL_RX_TLV_IS_MCAST_GET(buf);; 2483 } 2484 2485 /** 2486 * hal_rx_msdu_start_msdu_len_set_be(): API to set the MSDU length 2487 * from rx_msdu_start TLV 2488 * 2489 * @buf: pointer to the start of RX PKT TLV headers 2490 * @len: msdu length 2491 * 2492 * Return: none 2493 */ 2494 static inline void 2495 hal_rx_msdu_start_msdu_len_set_be(uint8_t *buf, uint32_t len) 2496 { 2497 HAL_RX_TLV_MSDU_LEN_GET(buf) = len; 2498 } 2499 2500 /** 2501 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_be(): 2502 * Retrieve qos control valid bit from the tlv. 2503 * @buf: pointer to rx pkt TLV. 2504 * 2505 * Return: qos control value. 2506 */ 2507 static inline uint32_t 2508 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be(uint8_t *buf) 2509 { 2510 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2511 2512 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(pkt_tlvs); 2513 } 2514 2515 /** 2516 * hal_rx_msdu_end_sa_sw_peer_id_get_be(): API to get the 2517 * sa_sw_peer_id from rx_msdu_end TLV 2518 * @buf: pointer to the start of RX PKT TLV headers 2519 * 2520 * Return: sa_sw_peer_id index 2521 */ 2522 static inline uint32_t 2523 hal_rx_msdu_end_sa_sw_peer_id_get_be(uint8_t *buf) 2524 { 2525 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2526 2527 hal_rx_msdu_end_t *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 2528 2529 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 2530 } 2531 #endif /* _HAL_BE_RX_TLV_H_ */ 2532