1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_BE_RX_H_ 21 #define _HAL_BE_RX_H_ 22 23 #include "hal_be_hw_headers.h" 24 #include "hal_rx.h" 25 #include <wbm_release_ring_rx.h> 26 27 #define HAL_RX_DA_IDX_CHIP_ID_OFFSET 14 28 #define HAL_RX_DA_IDX_CHIP_ID_MASK 0x3 29 30 #define HAL_RX_DA_IDX_PEER_ID_MASK 0x3fff 31 #define HAL_RX_DA_IDX_ML_PEER_MASK 0x2000 32 33 /* 34 * macro to set the cookie into the rxdma ring entry 35 */ 36 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ 37 ((*(((unsigned int *)buff_addr_info) + \ 38 (BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 39 ~BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK); \ 40 ((*(((unsigned int *)buff_addr_info) + \ 41 (BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 42 (cookie << BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB) & \ 43 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK) 44 45 /* 46 * macro to set the manager into the rxdma ring entry 47 */ 48 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ 49 ((*(((unsigned int *)buff_addr_info) + \ 50 (BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ 51 ~BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK); \ 52 ((*(((unsigned int *)buff_addr_info) + \ 53 (BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ 54 (manager << BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB) & \ 55 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK) 56 57 #define HAL_RX_ERROR_STATUS_GET(reo_desc) \ 58 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 59 REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET)),\ 60 REO_DESTINATION_RING_REO_PUSH_REASON_MASK, \ 61 REO_DESTINATION_RING_REO_PUSH_REASON_LSB)) 62 63 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \ 64 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 65 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET)), \ 66 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK, \ 67 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB)) 68 69 #define HAL_RX_BUF_RBM_GET(buff_addr_info) \ 70 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 71 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET)),\ 72 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK, \ 73 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB)) 74 75 /* TODO: Convert the following structure fields accesseses to offsets */ 76 77 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \ 78 (HAL_RX_BUF_COOKIE_GET(& \ 79 (((struct reo_destination_ring *) \ 80 reo_desc)->buf_or_link_desc_addr_info))) 81 82 #define HAL_RX_MSDU_DESC_IP_CHKSUM_FAIL_GET(msdu_desc_info_ptr) \ 83 (_HAL_MS((*_OFFSET_TO_WORD_PTR((msdu_desc_info_ptr), \ 84 RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET)), \ 85 RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK, \ 86 RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB)) 87 88 #define HAL_RX_REO_IP_CHKSUM_FAIL_GET(ring_desc) \ 89 (HAL_RX_MSDU_DESC_IP_CHKSUM_FAIL_GET(& \ 90 ((struct reo_destination_ring *)ring_desc)->rx_msdu_desc_info_details)) 91 92 #define HAL_RX_MSDU_DESC_TCP_UDP_CHKSUM_FAIL_GET(msdu_desc_info_ptr) \ 93 (_HAL_MS((*_OFFSET_TO_WORD_PTR((msdu_desc_info_ptr), \ 94 RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ 95 RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK, \ 96 RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB)) 97 98 #define HAL_RX_REO_TCP_UDP_CHKSUM_FAIL_GET(ring_desc) \ 99 (HAL_RX_MSDU_DESC_TCP_UDP_CHKSUM_FAIL_GET(& \ 100 ((struct reo_destination_ring *)ring_desc)->rx_msdu_desc_info_details)) 101 102 #define HAL_RX_MSDU_DESC_AMPDU_FLAG_GET(mpdu_info_ptr) \ 103 (_HAL_MS((*_OFFSET_TO_WORD_PTR((mpdu_info_ptr), \ 104 RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET)), \ 105 RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK, \ 106 RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB)) 107 108 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \ 109 ((mpdu_info_ptr \ 110 [RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET >> 2] & \ 111 RX_MPDU_DESC_INFO_PEER_META_DATA_MASK) >> \ 112 RX_MPDU_DESC_INFO_PEER_META_DATA_LSB) 113 114 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \ 115 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET >> 2] & \ 116 RX_MPDU_DESC_INFO_MSDU_COUNT_MASK) >> \ 117 RX_MPDU_DESC_INFO_MSDU_COUNT_LSB) 118 119 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \ 120 (mpdu_info_ptr[RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET >> 2] & \ 121 RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK) 122 123 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \ 124 (mpdu_info_ptr[RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET >> 2] & \ 125 RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK) 126 127 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \ 128 (mpdu_info_ptr[RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET >> 2] & \ 129 RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK) 130 131 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \ 132 (mpdu_info_ptr[RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET >> 2] & \ 133 RX_MPDU_DESC_INFO_RAW_MPDU_MASK) 134 135 #define HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info_ptr) \ 136 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET >> 2] & \ 137 RX_MPDU_DESC_INFO_BAR_FRAME_MASK) >> \ 138 RX_MPDU_DESC_INFO_BAR_FRAME_LSB) 139 140 #define HAL_RX_MPDU_TID_GET(mpdu_info_ptr) \ 141 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_TID_OFFSET >> 2] & \ 142 RX_MPDU_DESC_INFO_TID_MASK) >> \ 143 RX_MPDU_DESC_INFO_TID_LSB) 144 145 #define HAL_RX_MPDU_MPDU_QOS_CONTROL_VALID_GET(mpdu_info_ptr) \ 146 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET >> 2] &\ 147 RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK) >> \ 148 RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB) 149 150 /* 151 * NOTE: None of the following _GET macros need a right 152 * shift by the corresponding _LSB. This is because, they are 153 * finally taken and "OR'ed" into a single word again. 154 */ 155 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \ 156 ((*(((uint32_t *)msdu_info_ptr) + \ 157 (RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET >> 2))) |= \ 158 ((val) << RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB) & \ 159 RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK) 160 161 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ 162 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 163 RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET)) & \ 164 RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK) 165 166 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \ 167 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 168 RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET)), \ 169 RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK, \ 170 RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB)) 171 172 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 173 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 174 RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET)) & \ 175 RX_MSDU_DESC_INFO_SA_IS_VALID_MASK) 176 177 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 178 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 179 RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET)) & \ 180 RX_MSDU_DESC_INFO_DA_IS_VALID_MASK) 181 182 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ 183 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 184 RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET)) & \ 185 RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK) 186 187 #define HAL_RX_MSDU_INTRA_BSS_FLAG_GET(msdu_info_ptr) \ 188 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 189 RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET)) & \ 190 RX_MSDU_DESC_INFO_INTRA_BSS_MASK) 191 192 #define HAL_RX_MSDU_DEST_CHIP_ID_GET(msdu_info_ptr) \ 193 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 194 RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET)) & \ 195 RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK) 196 197 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \ 198 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 199 RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET)), \ 200 RX_MPDU_INFO_ENCRYPT_TYPE_MASK, \ 201 RX_MPDU_INFO_ENCRYPT_TYPE_LSB)) 202 203 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \ 204 HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO, \ 205 _field, _val) 206 207 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \ 208 HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO, \ 209 _field, _val) 210 211 #define HAL_RX_MSDU_REO_DST_IND_SET(_msdu_ext_desc_info_ptr, _field, _val) \ 212 HAL_RX_FLD_SET(_msdu_ext_desc_info_ptr, RX_MSDU_EXT_DESC_INFO, \ 213 _field, _val) 214 215 #define HAL_RX_REO_MSDU_REO_DST_IND_GET(reo_desc) \ 216 (HAL_RX_MSDU_REO_DST_IND_GET(& \ 217 (((struct reo_destination_ring *) \ 218 reo_desc)->rx_msdu_desc_info_details))) 219 220 #define HAL_RX_DEST_CHIP_ID_GET(msdu_metadata) \ 221 (((msdu_metadata)->da_idx >> HAL_RX_DA_IDX_CHIP_ID_OFFSET) & \ 222 HAL_RX_DA_IDX_CHIP_ID_MASK) 223 224 #define HAL_RX_PEER_ID_GET(msdu_metadata) \ 225 (((msdu_metadata)->da_idx) & HAL_RX_DA_IDX_PEER_ID_MASK) 226 227 /** 228 * enum hal_be_rx_wbm_error_source: Indicates which module initiated the 229 * release of this buffer or descriptor 230 * 231 * @ HAL_BE_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 232 * @ HAL_BE_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 233 * @ HAL_BE_RX_WBM_ERR_SRC_FW_RX: FW released this buffer or descriptor from the 234 * RX path 235 * @ HAL_BE_RX_WBM_ERR_SRC_SW_RX: SW released this buffer or descriptor from the 236 * RX path 237 * @ HAL_BE_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 238 * @ HAL_BE_RX_WBM_ERR_SRC_FW_TX: FW released this buffer or descriptor from the 239 * RX path 240 * @ HAL_BE_RX_WBM_ERR_SRC_SW_TX: SW released this buffer or descriptor from the 241 * RX path 242 */ 243 enum hal_be_rx_wbm_error_source { 244 HAL_BE_RX_WBM_ERR_SRC_RXDMA = 0, 245 HAL_BE_RX_WBM_ERR_SRC_REO, 246 HAL_BE_RX_WBM_ERR_SRC_FW_RX, 247 HAL_BE_RX_WBM_ERR_SRC_SW_RX, 248 HAL_BE_RX_WBM_ERR_SRC_TQM, 249 HAL_BE_RX_WBM_ERR_SRC_FW_TX, 250 HAL_BE_RX_WBM_ERR_SRC_SW_TX, 251 }; 252 253 /** 254 * enum hal_be_wbm_release_dir - Direction of the buffer which was released to 255 * wbm. 256 * @HAL_BE_WBM_RELEASE_DIR_RX: Buffer released to WBM due to error 257 * @HAL_BE_WBM_RELEASE_DIR_TX: Buffer released to WBM from TX path 258 */ 259 enum hal_be_wbm_release_dir { 260 HAL_BE_WBM_RELEASE_DIR_RX, 261 HAL_BE_WBM_RELEASE_DIR_TX, 262 }; 263 264 static inline uint32_t hal_rx_get_mpdu_flags(uint32_t *mpdu_info) 265 { 266 uint32_t mpdu_flags = 0; 267 268 if (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info)) 269 mpdu_flags |= HAL_MPDU_F_FRAGMENT; 270 271 if (HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info)) 272 mpdu_flags |= HAL_MPDU_F_RETRY_BIT; 273 274 if (HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info)) 275 mpdu_flags |= HAL_MPDU_F_AMPDU_FLAG; 276 277 if (HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info)) 278 mpdu_flags |= HAL_MPDU_F_RAW_AMPDU; 279 280 if (HAL_RX_MPDU_MPDU_QOS_CONTROL_VALID_GET(mpdu_info)) 281 mpdu_flags |= HAL_MPDU_F_QOS_CONTROL_VALID; 282 283 return mpdu_flags; 284 } 285 286 /******************************************************************************* 287 * RX REO ERROR APIS 288 ******************************************************************************/ 289 290 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 291 (REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \ 292 REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK) >> \ 293 REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB) 294 295 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 296 (REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET >> 2))) & \ 297 REO_DESTINATION_RING_REO_ERROR_CODE_MASK) >> \ 298 REO_DESTINATION_RING_REO_ERROR_CODE_LSB) 299 300 /* 301 * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to 302 * REO entrance ring 303 * 304 * @ soc: HAL version of the SOC pointer 305 * @ pa: Physical address of the MSDU Link Descriptor 306 * @ cookie: SW cookie to get to the virtual address 307 * @ error_enabled_reo_q: Argument to determine whether this needs to go 308 * to the error enabled REO queue 309 * 310 * Return: void 311 */ 312 static inline void 313 hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, uint64_t pa, 314 uint32_t cookie, bool error_enabled_reo_q) 315 { 316 /* TODO */ 317 } 318 319 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 320 /* HW set dowrd-2 bit16 to 1 if HW CC is done */ 321 #define HAL_WBM2SW_COMPLETION_RING_RX_CC_DONE_OFFSET 0x8 322 #define HAL_WBM2SW_COMPLETION_RING_RX_CC_DONE_MASK 0x10000 323 #define HAL_WBM2SW_COMPLETION_RING_RX_CC_DONE_LSB 0x10 324 /** 325 * hal_rx_wbm_get_cookie_convert_done() - Get cookie conversion done flag 326 * @hal_desc: wbm Rx ring descriptor pointer 327 * 328 * This function will get the bit value that indicate HW cookie 329 * conversion done or not 330 * 331 * Return: 1 - HW cookie conversion done, 0 - not 332 */ 333 static inline uint8_t hal_rx_wbm_get_cookie_convert_done(void *hal_desc) 334 { 335 return HAL_RX_GET(hal_desc, HAL_WBM2SW_COMPLETION_RING_RX, 336 CC_DONE); 337 } 338 #endif 339 340 /** 341 * hal_rx_wbm_get_desc_va() - Get Desc virtual address within WBM Desc 342 * @hal_desc: RX WBM2SW ring descriptor pointer 343 * 344 * Return: RX descriptor virtual address 345 */ 346 static inline uintptr_t hal_rx_wbm_get_desc_va(void *hal_desc) 347 { 348 uint64_t va_from_desc; 349 350 va_from_desc = HAL_RX_GET(hal_desc, 351 WBM2SW_COMPLETION_RING_RX, 352 BUFFER_VIRT_ADDR_31_0) | 353 (((uint64_t)HAL_RX_GET(hal_desc, 354 WBM2SW_COMPLETION_RING_RX, 355 BUFFER_VIRT_ADDR_63_32)) << 32); 356 357 return (uintptr_t)va_from_desc; 358 } 359 360 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \ 361 (((*(((uint32_t *)wbm_desc) + \ 362 (WBM_RELEASE_RING_FIRST_MSDU_OFFSET >> 2))) & \ 363 WBM_RELEASE_RING_FIRST_MSDU_MASK) >> \ 364 WBM_RELEASE_RING_FIRST_MSDU_LSB) 365 366 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \ 367 (((*(((uint32_t *)wbm_desc) + \ 368 (WBM_RELEASE_RING_LAST_MSDU_OFFSET >> 2))) & \ 369 WBM_RELEASE_RING_LAST_MSDU_MASK) >> \ 370 WBM_RELEASE_RING_LAST_MSDU_LSB) 371 372 #define HAL_RX_WBM_BUF_ADDR_39_32_GET(wbm_desc) \ 373 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 374 (((struct wbm_release_ring_rx *) \ 375 wbm_desc)->released_buff_or_desc_addr_info))) 376 377 #define HAL_RX_WBM_BUF_ADDR_31_0_GET(wbm_desc) \ 378 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 379 (((struct wbm_release_ring_rx *) \ 380 wbm_desc)->released_buff_or_desc_addr_info))) 381 382 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \ 383 HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring_rx *) \ 384 wbm_desc)->released_buff_or_desc_addr_info) 385 386 #define HAL_RX_WBM_COMP_BUF_ADDR_31_0_GET(wbm_desc) \ 387 HAL_RX_GET(wbm_desc, WBM2SW_COMPLETION_RING_RX, BUFFER_PHYS_ADDR_31_0) 388 389 #define HAL_RX_WBM_COMP_BUF_ADDR_39_32_GET(wbm_desc) \ 390 HAL_RX_GET(wbm_desc, WBM2SW_COMPLETION_RING_RX, BUFFER_PHYS_ADDR_39_32) 391 392 #define HAL_RX_WBM_COMP_BUF_COOKIE_GET(wbm_desc) \ 393 HAL_RX_GET(wbm_desc, WBM2SW_COMPLETION_RING_RX, SW_BUFFER_COOKIE) 394 /** 395 * hal_rx_msdu_flags_get_be() - Get msdu flags from ring desc 396 * @msdu_desc_info_hdl: msdu desc info handle 397 * 398 * Return: msdu flags 399 */ 400 static inline 401 uint32_t hal_rx_msdu_flags_get_be(rx_msdu_desc_info_t msdu_desc_info_hdl) 402 { 403 struct rx_msdu_desc_info *msdu_desc_info = 404 (struct rx_msdu_desc_info *)msdu_desc_info_hdl; 405 uint32_t flags = 0; 406 407 if (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_desc_info)) 408 flags |= HAL_MSDU_F_FIRST_MSDU_IN_MPDU; 409 410 if (HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_desc_info)) 411 flags |= HAL_MSDU_F_LAST_MSDU_IN_MPDU; 412 413 if (HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_desc_info)) 414 flags |= HAL_MSDU_F_MSDU_CONTINUATION; 415 416 if (HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_desc_info)) 417 flags |= HAL_MSDU_F_SA_IS_VALID; 418 419 if (HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_desc_info)) 420 flags |= HAL_MSDU_F_DA_IS_VALID; 421 422 if (HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_desc_info)) 423 flags |= HAL_MSDU_F_DA_IS_MCBC; 424 425 if (HAL_RX_MSDU_INTRA_BSS_FLAG_GET(msdu_desc_info)) 426 flags |= HAL_MSDU_F_INTRA_BSS; 427 428 return flags; 429 } 430 431 static inline 432 void hal_rx_mpdu_desc_info_get_be(void *desc_addr, 433 void *mpdu_desc_info_hdl) 434 { 435 struct reo_destination_ring *reo_dst_ring; 436 struct hal_rx_mpdu_desc_info *mpdu_desc_info = 437 (struct hal_rx_mpdu_desc_info *)mpdu_desc_info_hdl; 438 uint32_t *mpdu_info; 439 440 reo_dst_ring = (struct reo_destination_ring *)desc_addr; 441 442 mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details; 443 444 mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 445 mpdu_desc_info->mpdu_flags = hal_rx_get_mpdu_flags(mpdu_info); 446 mpdu_desc_info->peer_meta_data = 447 HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info); 448 mpdu_desc_info->bar_frame = HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info); 449 mpdu_desc_info->tid = HAL_RX_MPDU_TID_GET(mpdu_info); 450 } 451 452 /* 453 *hal_rx_msdu_desc_info_get_be: Gets the flags related to MSDU descriptor. 454 *@desc_addr: REO ring descriptor addr 455 *@msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor 456 * 457 * Specifically flags needed are: first_msdu_in_mpdu, 458 * last_msdu_in_mpdu, msdu_continuation, sa_is_valid, 459 * sa_idx_timeout, da_is_valid, da_idx_timeout, da_is_MCBC 460 * 461 462 *Return: void 463 */ 464 static inline void 465 hal_rx_msdu_desc_info_get_be(void *desc_addr, 466 struct hal_rx_msdu_desc_info *msdu_desc_info) 467 { 468 struct reo_destination_ring *reo_dst_ring; 469 uint32_t *msdu_info; 470 471 reo_dst_ring = (struct reo_destination_ring *)desc_addr; 472 473 msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details; 474 msdu_desc_info->msdu_flags = 475 hal_rx_msdu_flags_get_be((struct rx_msdu_desc_info *)msdu_info); 476 msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info); 477 } 478 479 /** 480 * hal_rx_get_reo_desc_va() - Get Desc virtual address within REO Desc 481 * @reo_desc: REO2SW ring descriptor pointer 482 * 483 * Return: RX descriptor virtual address 484 */ 485 static inline uintptr_t hal_rx_get_reo_desc_va(void *reo_desc) 486 { 487 uint64_t va_from_desc; 488 489 va_from_desc = HAL_RX_GET(reo_desc, 490 REO_DESTINATION_RING, 491 BUFFER_VIRT_ADDR_31_0) | 492 (((uint64_t)HAL_RX_GET(reo_desc, 493 REO_DESTINATION_RING, 494 BUFFER_VIRT_ADDR_63_32)) << 32); 495 496 return (uintptr_t)va_from_desc; 497 } 498 499 /** 500 * hal_rx_sw_exception_get_be() - Get sw_exception bit value from REO Desc 501 * @reo_desc: REO2SW ring descriptor pointer 502 * 503 * sw_exception bit might not exist in reo destination ring descriptor 504 * for some chipset, so just restrict this function for BE only. 505 * 506 * Return: sw_exception bit value 507 */ 508 static inline uint8_t hal_rx_sw_exception_get_be(void *reo_desc) 509 { 510 return HAL_RX_GET(reo_desc, REO_DESTINATION_RING, SW_EXCEPTION); 511 } 512 #endif /* _HAL_BE_RX_H_ */ 513