1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_BE_RX_H_ 20 #define _HAL_BE_RX_H_ 21 22 #include "hal_be_hw_headers.h" 23 #include "hal_rx.h" 24 25 /* 26 * macro to set the cookie into the rxdma ring entry 27 */ 28 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ 29 ((*(((unsigned int *)buff_addr_info) + \ 30 (BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 31 ~BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK); \ 32 ((*(((unsigned int *)buff_addr_info) + \ 33 (BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 34 (cookie << BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB) & \ 35 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK) 36 37 /* 38 * macro to set the manager into the rxdma ring entry 39 */ 40 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ 41 ((*(((unsigned int *)buff_addr_info) + \ 42 (BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ 43 ~BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK); \ 44 ((*(((unsigned int *)buff_addr_info) + \ 45 (BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ 46 (manager << BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB) & \ 47 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK) 48 49 #define HAL_RX_ERROR_STATUS_GET(reo_desc) \ 50 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 51 REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET)),\ 52 REO_DESTINATION_RING_REO_PUSH_REASON_MASK, \ 53 REO_DESTINATION_RING_REO_PUSH_REASON_LSB)) 54 55 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \ 56 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 57 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET)), \ 58 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK, \ 59 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB)) 60 61 #define HAL_RX_BUF_RBM_GET(buff_addr_info) \ 62 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 63 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET)),\ 64 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK, \ 65 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB)) 66 67 /* TODO: Convert the following structure fields accesseses to offsets */ 68 69 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \ 70 (HAL_RX_BUF_COOKIE_GET(& \ 71 (((struct reo_destination_ring *) \ 72 reo_desc)->buf_or_link_desc_addr_info))) 73 74 #define HAL_RX_MSDU_DESC_IP_CHKSUM_FAIL_GET(msdu_desc_info_ptr) \ 75 (_HAL_MS((*_OFFSET_TO_WORD_PTR((msdu_desc_info_ptr), \ 76 RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET)), \ 77 RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK, \ 78 RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB)) 79 80 #define HAL_RX_REO_IP_CHKSUM_FAIL_GET(ring_desc) \ 81 (HAL_RX_MSDU_DESC_IP_CHKSUM_FAIL_GET(& \ 82 ((struct reo_destination_ring *)ring_desc)->rx_msdu_desc_info_details)) 83 84 #define HAL_RX_MSDU_DESC_TCP_UDP_CHKSUM_FAIL_GET(msdu_desc_info_ptr) \ 85 (_HAL_MS((*_OFFSET_TO_WORD_PTR((msdu_desc_info_ptr), \ 86 RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ 87 RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK, \ 88 RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB)) 89 90 #define HAL_RX_REO_TCP_UDP_CHKSUM_FAIL_GET(ring_desc) \ 91 (HAL_RX_MSDU_DESC_TCP_UDP_CHKSUM_FAIL_GET(& \ 92 ((struct reo_destination_ring *)ring_desc)->rx_msdu_desc_info_details)) 93 94 #define HAL_RX_MSDU_DESC_AMPDU_FLAG_GET(mpdu_info_ptr) \ 95 (_HAL_MS((*_OFFSET_TO_WORD_PTR((mpdu_info_ptr), \ 96 RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET)), \ 97 RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK, \ 98 RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB)) 99 100 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \ 101 ((mpdu_info_ptr \ 102 [RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET >> 2] & \ 103 RX_MPDU_DESC_INFO_PEER_META_DATA_MASK) >> \ 104 RX_MPDU_DESC_INFO_PEER_META_DATA_LSB) 105 106 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \ 107 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET >> 2] & \ 108 RX_MPDU_DESC_INFO_MSDU_COUNT_MASK) >> \ 109 RX_MPDU_DESC_INFO_MSDU_COUNT_LSB) 110 111 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \ 112 (mpdu_info_ptr[RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET >> 2] & \ 113 RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK) 114 115 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \ 116 (mpdu_info_ptr[RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET >> 2] & \ 117 RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK) 118 119 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \ 120 (mpdu_info_ptr[RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET >> 2] & \ 121 RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK) 122 123 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \ 124 (mpdu_info_ptr[RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET >> 2] & \ 125 RX_MPDU_DESC_INFO_RAW_MPDU_MASK) 126 127 #define HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info_ptr) \ 128 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET >> 2] & \ 129 RX_MPDU_DESC_INFO_BAR_FRAME_MASK) >> \ 130 RX_MPDU_DESC_INFO_BAR_FRAME_LSB) 131 132 /* 133 * NOTE: None of the following _GET macros need a right 134 * shift by the corresponding _LSB. This is because, they are 135 * finally taken and "OR'ed" into a single word again. 136 */ 137 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \ 138 ((*(((uint32_t *)msdu_info_ptr) + \ 139 (RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET >> 2))) |= \ 140 ((val) << RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB) & \ 141 RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK) 142 143 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ 144 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 145 RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET)) & \ 146 RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK) 147 148 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \ 149 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 150 RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET)), \ 151 RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK, \ 152 RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB)) 153 154 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 155 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 156 RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET)) & \ 157 RX_MSDU_DESC_INFO_SA_IS_VALID_MASK) 158 159 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 160 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 161 RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET)) & \ 162 RX_MSDU_DESC_INFO_DA_IS_VALID_MASK) 163 164 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ 165 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 166 RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET)) & \ 167 RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK) 168 169 #define HAL_RX_MSDU_INTRA_BSS_FLAG_GET(msdu_info_ptr) \ 170 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 171 RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET)) & \ 172 RX_MSDU_DESC_INFO_INTRA_BSS_MASK) 173 174 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \ 175 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 176 RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET)), \ 177 RX_MPDU_INFO_ENCRYPT_TYPE_MASK, \ 178 RX_MPDU_INFO_ENCRYPT_TYPE_LSB)) 179 180 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \ 181 HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO, \ 182 _field, _val) 183 184 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \ 185 HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO, \ 186 _field, _val) 187 188 #define HAL_RX_REO_MSDU_REO_DST_IND_GET(reo_desc) \ 189 (HAL_RX_MSDU_REO_DST_IND_GET(& \ 190 (((struct reo_destination_ring *) \ 191 reo_desc)->rx_msdu_desc_info_details))) 192 193 /** 194 * enum hal_be_rx_wbm_error_source: Indicates which module initiated the 195 * release of this buffer or descriptor 196 * 197 * @ HAL_BE_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 198 * @ HAL_BE_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 199 * @ HAL_BE_RX_WBM_ERR_SRC_FW_RX: FW released this buffer or descriptor from the 200 * RX path 201 * @ HAL_BE_RX_WBM_ERR_SRC_SW_RX: SW released this buffer or descriptor from the 202 * RX path 203 * @ HAL_BE_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 204 * @ HAL_BE_RX_WBM_ERR_SRC_FW_TX: FW released this buffer or descriptor from the 205 * RX path 206 * @ HAL_BE_RX_WBM_ERR_SRC_SW_TX: SW released this buffer or descriptor from the 207 * RX path 208 */ 209 enum hal_be_rx_wbm_error_source { 210 HAL_BE_RX_WBM_ERR_SRC_RXDMA = 0, 211 HAL_BE_RX_WBM_ERR_SRC_REO, 212 HAL_BE_RX_WBM_ERR_SRC_FW_RX, 213 HAL_BE_RX_WBM_ERR_SRC_SW_RX, 214 HAL_BE_RX_WBM_ERR_SRC_TQM, 215 HAL_BE_RX_WBM_ERR_SRC_FW_TX, 216 HAL_BE_RX_WBM_ERR_SRC_SW_TX, 217 }; 218 219 /** 220 * enum hal_be_wbm_release_dir - Direction of the buffer which was released to 221 * wbm. 222 * @HAL_BE_WBM_RELEASE_DIR_RX: Buffer released to WBM due to error 223 * @HAL_BE_WBM_RELEASE_DIR_TX: Buffer released to WBM from TX path 224 */ 225 enum hal_be_wbm_release_dir { 226 HAL_BE_WBM_RELEASE_DIR_RX, 227 HAL_BE_WBM_RELEASE_DIR_TX, 228 }; 229 230 static inline uint32_t hal_rx_get_mpdu_flags(uint32_t *mpdu_info) 231 { 232 uint32_t mpdu_flags = 0; 233 234 if (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info)) 235 mpdu_flags |= HAL_MPDU_F_FRAGMENT; 236 237 if (HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info)) 238 mpdu_flags |= HAL_MPDU_F_RETRY_BIT; 239 240 if (HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info)) 241 mpdu_flags |= HAL_MPDU_F_AMPDU_FLAG; 242 243 if (HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info)) 244 mpdu_flags |= HAL_MPDU_F_RAW_AMPDU; 245 246 return mpdu_flags; 247 } 248 249 /******************************************************************************* 250 * RX REO ERROR APIS 251 ******************************************************************************/ 252 253 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 254 (REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \ 255 REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK) >> \ 256 REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB) 257 258 #define HAL_RX_REO_QUEUE_NUMBER_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 259 (REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET >> 2))) & \ 260 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK) >> \ 261 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB) 262 263 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 264 (REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET >> 2))) & \ 265 REO_DESTINATION_RING_REO_ERROR_CODE_MASK) >> \ 266 REO_DESTINATION_RING_REO_ERROR_CODE_LSB) 267 268 /* 269 * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to 270 * REO entrance ring 271 * 272 * @ soc: HAL version of the SOC pointer 273 * @ pa: Physical address of the MSDU Link Descriptor 274 * @ cookie: SW cookie to get to the virtual address 275 * @ error_enabled_reo_q: Argument to determine whether this needs to go 276 * to the error enabled REO queue 277 * 278 * Return: void 279 */ 280 static inline void 281 hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, uint64_t pa, 282 uint32_t cookie, bool error_enabled_reo_q) 283 { 284 /* TODO */ 285 } 286 287 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 288 /* HW set dowrd-2 bit16 to 1 if HW CC is done */ 289 #define HAL_WBM2SW_COMPLETION_RING_RX_CC_DONE_OFFSET 0x8 290 #define HAL_WBM2SW_COMPLETION_RING_RX_CC_DONE_MASK 0x10000 291 #define HAL_WBM2SW_COMPLETION_RING_RX_CC_DONE_LSB 0x10 292 /** 293 * hal_rx_wbm_get_cookie_convert_done() - Get cookie conversion done flag 294 * @hal_desc: wbm Rx ring descriptor pointer 295 * 296 * This function will get the bit value that indicate HW cookie 297 * conversion done or not 298 * 299 * Return: 1 - HW cookie conversion done, 0 - not 300 */ 301 static inline uint8_t hal_rx_wbm_get_cookie_convert_done(void *hal_desc) 302 { 303 return HAL_RX_GET(hal_desc, HAL_WBM2SW_COMPLETION_RING_RX, 304 CC_DONE); 305 } 306 #endif 307 308 /** 309 * hal_rx_wbm_get_desc_va() - Get Desc virtual address within WBM Desc 310 * @hal_desc: RX WBM2SW ring descriptor pointer 311 * 312 * Return: RX descriptor virtual address 313 */ 314 static inline uintptr_t hal_rx_wbm_get_desc_va(void *hal_desc) 315 { 316 uint64_t va_from_desc; 317 318 va_from_desc = HAL_RX_GET(hal_desc, 319 WBM2SW_COMPLETION_RING_RX, 320 BUFFER_VIRT_ADDR_31_0) | 321 (((uint64_t)HAL_RX_GET(hal_desc, 322 WBM2SW_COMPLETION_RING_RX, 323 BUFFER_VIRT_ADDR_63_32)) << 32); 324 325 return (uintptr_t)va_from_desc; 326 } 327 328 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \ 329 (((*(((uint32_t *)wbm_desc) + \ 330 (WBM_RELEASE_RING_FIRST_MSDU_OFFSET >> 2))) & \ 331 WBM_RELEASE_RING_FIRST_MSDU_MASK) >> \ 332 WBM_RELEASE_RING_FIRST_MSDU_LSB) 333 334 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \ 335 (((*(((uint32_t *)wbm_desc) + \ 336 (WBM_RELEASE_RING_LAST_MSDU_OFFSET >> 2))) & \ 337 WBM_RELEASE_RING_LAST_MSDU_MASK) >> \ 338 WBM_RELEASE_RING_LAST_MSDU_LSB) 339 340 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \ 341 HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \ 342 wbm_desc)->released_buff_or_desc_addr_info) 343 344 /** 345 * hal_rx_msdu_flags_get_be() - Get msdu flags from ring desc 346 * @msdu_desc_info_hdl: msdu desc info handle 347 * 348 * Return: msdu flags 349 */ 350 static inline 351 uint32_t hal_rx_msdu_flags_get_be(rx_msdu_desc_info_t msdu_desc_info_hdl) 352 { 353 struct rx_msdu_desc_info *msdu_desc_info = 354 (struct rx_msdu_desc_info *)msdu_desc_info_hdl; 355 uint32_t flags = 0; 356 357 if (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_desc_info)) 358 flags |= HAL_MSDU_F_FIRST_MSDU_IN_MPDU; 359 360 if (HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_desc_info)) 361 flags |= HAL_MSDU_F_LAST_MSDU_IN_MPDU; 362 363 if (HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_desc_info)) 364 flags |= HAL_MSDU_F_MSDU_CONTINUATION; 365 366 if (HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_desc_info)) 367 flags |= HAL_MSDU_F_SA_IS_VALID; 368 369 if (HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_desc_info)) 370 flags |= HAL_MSDU_F_DA_IS_VALID; 371 372 if (HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_desc_info)) 373 flags |= HAL_MSDU_F_DA_IS_MCBC; 374 375 if (HAL_RX_MSDU_INTRA_BSS_FLAG_GET(msdu_desc_info)) 376 flags |= HAL_MSDU_F_INTRA_BSS; 377 378 return flags; 379 } 380 381 static inline 382 void hal_rx_mpdu_desc_info_get_be(void *desc_addr, 383 void *mpdu_desc_info_hdl) 384 { 385 struct reo_destination_ring *reo_dst_ring; 386 struct hal_rx_mpdu_desc_info *mpdu_desc_info = 387 (struct hal_rx_mpdu_desc_info *)mpdu_desc_info_hdl; 388 uint32_t *mpdu_info; 389 390 reo_dst_ring = (struct reo_destination_ring *)desc_addr; 391 392 mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details; 393 394 mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 395 mpdu_desc_info->mpdu_flags = hal_rx_get_mpdu_flags(mpdu_info); 396 mpdu_desc_info->peer_meta_data = 397 HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info); 398 mpdu_desc_info->bar_frame = HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info); 399 } 400 401 /* 402 *hal_rx_msdu_desc_info_get_be: Gets the flags related to MSDU descriptor. 403 *@desc_addr: REO ring descriptor addr 404 *@msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor 405 * 406 * Specifically flags needed are: first_msdu_in_mpdu, 407 * last_msdu_in_mpdu, msdu_continuation, sa_is_valid, 408 * sa_idx_timeout, da_is_valid, da_idx_timeout, da_is_MCBC 409 * 410 411 *Return: void 412 */ 413 static inline void 414 hal_rx_msdu_desc_info_get_be(void *desc_addr, 415 struct hal_rx_msdu_desc_info *msdu_desc_info) 416 { 417 struct reo_destination_ring *reo_dst_ring; 418 uint32_t *msdu_info; 419 420 reo_dst_ring = (struct reo_destination_ring *)desc_addr; 421 422 msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details; 423 msdu_desc_info->msdu_flags = 424 hal_rx_msdu_flags_get_be((struct rx_msdu_desc_info *)msdu_info); 425 msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info); 426 } 427 428 /** 429 * hal_rx_get_reo_desc_va() - Get Desc virtual address within REO Desc 430 * @reo_desc: REO2SW ring descriptor pointer 431 * 432 * Return: RX descriptor virtual address 433 */ 434 static inline uintptr_t hal_rx_get_reo_desc_va(void *reo_desc) 435 { 436 uint64_t va_from_desc; 437 438 va_from_desc = HAL_RX_GET(reo_desc, 439 REO_DESTINATION_RING, 440 BUFFER_VIRT_ADDR_31_0) | 441 (((uint64_t)HAL_RX_GET(reo_desc, 442 REO_DESTINATION_RING, 443 BUFFER_VIRT_ADDR_63_32)) << 32); 444 445 return (uintptr_t)va_from_desc; 446 } 447 448 #endif /* _HAL_BE_RX_H_ */ 449