1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_BE_GENERIC_API_H_ 21 #define _HAL_BE_GENERIC_API_H_ 22 23 #include <hal_be_hw_headers.h> 24 #include "hal_be_tx.h" 25 #include "hal_be_reo.h" 26 #include <hal_api_mon.h> 27 #include <hal_generic_api.h> 28 #include <hal_be_api_mon.h> 29 30 /** 31 * Debug macro to print the TLV header tag 32 */ 33 #define SHOW_DEFINED(x) do {} while (0) 34 35 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(CONFIG_SAWF) 36 static inline void 37 hal_tx_comp_get_buffer_timestamp_be(void *desc, 38 struct hal_tx_completion_status *ts) 39 { 40 ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 41 BUFFER_TIMESTAMP); 42 } 43 #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */ 44 static inline void 45 hal_tx_comp_get_buffer_timestamp_be(void *desc, 46 struct hal_tx_completion_status *ts) 47 { 48 } 49 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */ 50 51 /** 52 * hal_tx_comp_get_status() - TQM Release reason 53 * @hal_desc: completion ring Tx status 54 * 55 * This function will parse the WBM completion descriptor and populate in 56 * HAL structure 57 * 58 * Return: none 59 */ 60 static inline void 61 hal_tx_comp_get_status_generic_be(void *desc, void *ts1, 62 struct hal_soc *hal) 63 { 64 uint8_t rate_stats_valid = 0; 65 uint32_t rate_stats = 0; 66 struct hal_tx_completion_status *ts = 67 (struct hal_tx_completion_status *)ts1; 68 69 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 70 TQM_STATUS_NUMBER); 71 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 72 ACK_FRAME_RSSI); 73 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 74 FIRST_MSDU); 75 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 76 LAST_MSDU); 77 #if 0 78 // TODO - This has to be calculated form first and last msdu 79 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, 80 WBM2SW_COMPLETION_RING_TX, 81 MSDU_PART_OF_AMSDU); 82 #endif 83 84 ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 85 SW_PEER_ID); 86 ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID); 87 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 88 TRANSMIT_COUNT); 89 90 rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS); 91 92 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO, 93 TX_RATE_STATS_INFO_VALID, rate_stats); 94 95 ts->valid = rate_stats_valid; 96 97 if (rate_stats_valid) { 98 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW, 99 rate_stats); 100 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO, 101 TRANSMIT_PKT_TYPE, rate_stats); 102 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO, 103 TRANSMIT_STBC, rate_stats); 104 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC, 105 rate_stats); 106 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI, 107 rate_stats); 108 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS, 109 rate_stats); 110 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION, 111 rate_stats); 112 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU, 113 rate_stats); 114 } 115 116 ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc); 117 ts->status = hal_tx_comp_get_release_reason( 118 desc, 119 hal_soc_to_hal_soc_handle(hal)); 120 121 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 122 TX_RATE_STATS_INFO_TX_RATE_STATS); 123 hal_tx_comp_get_buffer_timestamp_be(desc, ts); 124 } 125 126 /** 127 * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table 128 * @soc: HAL SoC context 129 * @map: PCP-TID mapping table 130 * 131 * PCP are mapped to 8 TID values using TID values programmed 132 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 133 * The mapping register has TID mapping for 8 PCP values 134 * 135 * Return: none 136 */ 137 static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map) 138 { 139 uint32_t addr, value; 140 141 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 142 MAC_TCL_REG_REG_BASE); 143 144 value = (map[0] | 145 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 146 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 147 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 148 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 149 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 150 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 151 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 152 153 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 154 } 155 156 /** 157 * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with 158 * value received from user-space 159 * @soc: HAL SoC context 160 * @pcp: pcp value 161 * @tid : tid value 162 * 163 * Return: void 164 */ 165 static void 166 hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc, 167 uint8_t pcp, uint8_t tid) 168 { 169 uint32_t addr, value, regval; 170 171 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 172 MAC_TCL_REG_REG_BASE); 173 174 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 175 176 /* Read back previous PCP TID config and update 177 * with new config. 178 */ 179 regval = HAL_REG_READ(soc, addr); 180 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 181 regval |= value; 182 183 HAL_REG_WRITE(soc, addr, 184 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 185 } 186 187 /** 188 * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority 189 * @soc: HAL SoC context 190 * @val: priority value 191 * 192 * Return: void 193 */ 194 static 195 void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value) 196 { 197 uint32_t addr; 198 199 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 200 MAC_TCL_REG_REG_BASE); 201 202 HAL_REG_WRITE(soc, addr, 203 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 204 } 205 206 /** 207 * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size 208 * @rx_pkt_tlv_size: TLV size for regular RX packets 209 * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets 210 * 211 * Return: size of rx pkt tlv before the actual data 212 */ 213 static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size, 214 uint16_t *rx_mon_pkt_tlv_size) 215 { 216 *rx_pkt_tlv_size = RX_PKT_TLVS_LEN; 217 /* For now mon pkt tlv is same as rx pkt tlv */ 218 *rx_mon_pkt_tlv_size = RX_PKT_TLVS_LEN; 219 } 220 221 /** 222 * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST 223 * @fst: Pointer to the Rx Flow Search Table 224 * @hal_hash: HAL 5 tuple hash 225 * @tuple_info: 5-tuple info of the flow returned to the caller 226 * 227 * Return: Success/Failure 228 */ 229 static void * 230 hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash, 231 uint8_t *flow_tuple_info) 232 { 233 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 234 void *hal_fse = NULL; 235 struct hal_flow_tuple_info *tuple_info 236 = (struct hal_flow_tuple_info *)flow_tuple_info; 237 238 hal_fse = (uint8_t *)fst->base_vaddr + 239 (hal_hash * HAL_RX_FST_ENTRY_SIZE); 240 241 if (!hal_fse || !tuple_info) 242 return NULL; 243 244 if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY, VALID)) 245 return NULL; 246 247 tuple_info->src_ip_127_96 = 248 qdf_ntohl(HAL_GET_FLD(hal_fse, 249 RX_FLOW_SEARCH_ENTRY, 250 SRC_IP_127_96)); 251 tuple_info->src_ip_95_64 = 252 qdf_ntohl(HAL_GET_FLD(hal_fse, 253 RX_FLOW_SEARCH_ENTRY, 254 SRC_IP_95_64)); 255 tuple_info->src_ip_63_32 = 256 qdf_ntohl(HAL_GET_FLD(hal_fse, 257 RX_FLOW_SEARCH_ENTRY, 258 SRC_IP_63_32)); 259 tuple_info->src_ip_31_0 = 260 qdf_ntohl(HAL_GET_FLD(hal_fse, 261 RX_FLOW_SEARCH_ENTRY, 262 SRC_IP_31_0)); 263 tuple_info->dest_ip_127_96 = 264 qdf_ntohl(HAL_GET_FLD(hal_fse, 265 RX_FLOW_SEARCH_ENTRY, 266 DEST_IP_127_96)); 267 tuple_info->dest_ip_95_64 = 268 qdf_ntohl(HAL_GET_FLD(hal_fse, 269 RX_FLOW_SEARCH_ENTRY, 270 DEST_IP_95_64)); 271 tuple_info->dest_ip_63_32 = 272 qdf_ntohl(HAL_GET_FLD(hal_fse, 273 RX_FLOW_SEARCH_ENTRY, 274 DEST_IP_63_32)); 275 tuple_info->dest_ip_31_0 = 276 qdf_ntohl(HAL_GET_FLD(hal_fse, 277 RX_FLOW_SEARCH_ENTRY, 278 DEST_IP_31_0)); 279 tuple_info->dest_port = HAL_GET_FLD(hal_fse, 280 RX_FLOW_SEARCH_ENTRY, 281 DEST_PORT); 282 tuple_info->src_port = HAL_GET_FLD(hal_fse, 283 RX_FLOW_SEARCH_ENTRY, 284 SRC_PORT); 285 tuple_info->l4_protocol = HAL_GET_FLD(hal_fse, 286 RX_FLOW_SEARCH_ENTRY, 287 L4_PROTOCOL); 288 289 return hal_fse; 290 } 291 292 /** 293 * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST 294 * @fst: Pointer to the Rx Flow Search Table 295 * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST 296 * 297 * Return: Success/Failure 298 */ 299 static QDF_STATUS 300 hal_rx_flow_delete_entry_be(uint8_t *rx_fst, void *hal_rx_fse) 301 { 302 uint8_t *fse = (uint8_t *)hal_rx_fse; 303 304 if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID)) 305 return QDF_STATUS_E_NOENT; 306 307 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 308 309 return QDF_STATUS_SUCCESS; 310 } 311 312 /** 313 * hal_rx_fst_get_fse_size_be() - Retrieve the size of each entry in Rx FST 314 * 315 * Return: size of each entry/flow in Rx FST 316 */ 317 static inline uint32_t 318 hal_rx_fst_get_fse_size_be(void) 319 { 320 return HAL_RX_FST_ENTRY_SIZE; 321 } 322 323 /* 324 * TX MONITOR 325 */ 326 327 #ifdef QCA_MONITOR_2_0_SUPPORT 328 /** 329 * hal_txmon_is_mon_buf_addr_tlv_generic_be() - api to find mon buffer tlv 330 * @tx_tlv: pointer to TLV header 331 * 332 * Return: bool based on tlv tag matches monitor buffer address tlv 333 */ 334 static inline bool 335 hal_txmon_is_mon_buf_addr_tlv_generic_be(void *tx_tlv_hdr) 336 { 337 uint32_t tlv_tag; 338 339 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr); 340 341 if (WIFIMON_BUFFER_ADDR_E == tlv_tag) 342 return true; 343 344 return false; 345 } 346 347 /** 348 * hal_txmon_populate_packet_info_generic_be() - api to populate packet info 349 * @tx_tlv: pointer to TLV header 350 * @packet_info: place holder for packet info 351 * 352 * Return: Address to void 353 */ 354 static inline void 355 hal_txmon_populate_packet_info_generic_be(void *tx_tlv, void *packet_info) 356 { 357 struct hal_mon_packet_info *pkt_info; 358 struct mon_buffer_addr *addr = (struct mon_buffer_addr *)tx_tlv; 359 360 pkt_info = (struct hal_mon_packet_info *)packet_info; 361 pkt_info->sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) | 362 (addr->buffer_virt_addr_31_0)); 363 pkt_info->dma_length = addr->dma_length + 1; 364 pkt_info->msdu_continuation = addr->msdu_continuation; 365 pkt_info->truncated = addr->truncated; 366 } 367 368 #if defined(TX_MONITOR_WORD_MASK) 369 /** 370 * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv 371 * 372 * @tx_tlv: pointer to tx_fes_setup tlv header 373 * 374 * Return: number of users 375 */ 376 static inline uint8_t 377 hal_txmon_get_num_users(void *tx_tlv) 378 { 379 hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv; 380 381 return tx_fes_setup->number_of_users; 382 } 383 384 /** 385 * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv 386 * 387 * @tx_tlv: pointer to tx_fes_setup tlv header 388 * @ppdu_info: pointer to hal_tx_ppdu_info 389 * 390 * Return: void 391 */ 392 static inline void 393 hal_txmon_parse_tx_fes_setup(void *tx_tlv, 394 struct hal_tx_ppdu_info *tx_ppdu_info) 395 { 396 hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv; 397 398 tx_ppdu_info->num_users = tx_fes_setup->number_of_users; 399 if (tx_ppdu_info->num_users == 0) 400 tx_ppdu_info->num_users = 1; 401 tx_ppdu_info->ppdu_id = tx_fes_setup->schedule_id; 402 } 403 404 /** 405 * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv 406 * 407 * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header 408 * @data_status_info: pointer to data hal_tx_status_info 409 * @prot_status_info: pointer to protection hal_tx_status_info 410 * 411 * Return: void 412 */ 413 static inline void 414 hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv, 415 struct hal_tx_status_info *data_status_info, 416 struct hal_tx_status_info *prot_status_info) 417 { 418 } 419 420 /** 421 * hal_txmon_parse_peer_entry() - parse peer entry tlv 422 * 423 * @tx_tlv: pointer to peer_entry tlv header 424 * @user_id: user_id 425 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 426 * @tx_status_info: pointer to hal_tx_status_info 427 * 428 * Return: void 429 */ 430 static inline void 431 hal_txmon_parse_peer_entry(void *tx_tlv, 432 uint8_t user_id, 433 struct hal_tx_ppdu_info *tx_ppdu_info, 434 struct hal_tx_status_info *tx_status_info) 435 { 436 } 437 438 /** 439 * hal_txmon_parse_queue_exten() - parse queue exten tlv 440 * 441 * @tx_tlv: pointer to queue exten tlv header 442 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 443 * 444 * Return: void 445 */ 446 static inline void 447 hal_txmon_parse_queue_exten(void *tx_tlv, 448 struct hal_tx_ppdu_info *tx_ppdu_info) 449 { 450 } 451 452 /** 453 * hal_txmon_parse_mpdu_start() - parse mpdu start tlv 454 * 455 * @tx_tlv: pointer to mpdu start tlv header 456 * @user_id: user id 457 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 458 * 459 * Return: void 460 */ 461 static inline void 462 hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id, 463 struct hal_tx_ppdu_info *tx_ppdu_info) 464 { 465 } 466 467 #else 468 /** 469 * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv 470 * 471 * @tx_tlv: pointer to tx_fes_setup tlv header 472 * 473 * Return: number of users 474 */ 475 static inline uint8_t 476 hal_txmon_get_num_users(void *tx_tlv) 477 { 478 uint8_t num_users = HAL_TX_DESC_GET_64(tx_tlv, 479 TX_FES_SETUP, NUMBER_OF_USERS); 480 481 return num_users; 482 } 483 484 /** 485 * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv 486 * 487 * @tx_tlv: pointer to tx_fes_setup tlv header 488 * @ppdu_info: pointer to hal_tx_ppdu_info 489 * 490 * Return: void 491 */ 492 static inline void 493 hal_txmon_parse_tx_fes_setup(void *tx_tlv, 494 struct hal_tx_ppdu_info *tx_ppdu_info) 495 { 496 uint32_t num_users = 0; 497 uint32_t ppdu_id = 0; 498 499 num_users = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_SETUP, NUMBER_OF_USERS); 500 ppdu_id = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_SETUP, SCHEDULE_ID); 501 502 if (num_users == 0) 503 num_users = 1; 504 505 tx_ppdu_info->num_users = num_users; 506 tx_ppdu_info->ppdu_id = ppdu_id; 507 } 508 509 /** 510 * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv 511 * 512 * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header 513 * @data_status_info: pointer to data hal_tx_status_info 514 * @prot_status_info: pointer to protection hal_tx_status_info 515 * 516 * Return: void 517 */ 518 static inline void 519 hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv, 520 struct hal_tx_status_info *data_status_info, 521 struct hal_tx_status_info *prot_status_info) 522 { 523 prot_status_info->protection_addr = 524 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 525 USE_ADDRESS_FIELDS_FOR_PROTECTION); 526 /* protection frame address 1 */ 527 *(uint32_t *)&prot_status_info->addr1[0] = 528 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 529 PROTECTION_FRAME_AD1_31_0); 530 *(uint32_t *)&prot_status_info->addr1[4] = 531 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 532 PROTECTION_FRAME_AD1_47_32); 533 /* protection frame address 2 */ 534 *(uint32_t *)&prot_status_info->addr2[0] = 535 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 536 PROTECTION_FRAME_AD2_15_0); 537 *(uint32_t *)&prot_status_info->addr2[2] = 538 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 539 PROTECTION_FRAME_AD2_47_16); 540 /* protection frame address 3 */ 541 *(uint32_t *)&prot_status_info->addr3[0] = 542 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 543 PROTECTION_FRAME_AD3_31_0); 544 *(uint32_t *)&prot_status_info->addr3[4] = 545 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 546 PROTECTION_FRAME_AD3_47_32); 547 /* protection frame address 4 */ 548 *(uint32_t *)&prot_status_info->addr4[0] = 549 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 550 PROTECTION_FRAME_AD4_15_0); 551 *(uint32_t *)&prot_status_info->addr4[2] = 552 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 553 PROTECTION_FRAME_AD4_47_16); 554 } 555 556 /** 557 * hal_txmon_parse_peer_entry() - parse peer entry tlv 558 * 559 * @tx_tlv: pointer to peer_entry tlv header 560 * @user_id: user_id 561 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 562 * @tx_status_info: pointer to hal_tx_status_info 563 * 564 * Return: void 565 */ 566 static inline void 567 hal_txmon_parse_peer_entry(void *tx_tlv, 568 uint8_t user_id, 569 struct hal_tx_ppdu_info *tx_ppdu_info, 570 struct hal_tx_status_info *tx_status_info) 571 { 572 *(uint32_t *)&tx_status_info->addr1[0] = 573 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_A_31_0); 574 *(uint32_t *)&tx_status_info->addr1[4] = 575 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_A_47_32); 576 *(uint32_t *)&tx_status_info->addr2[0] = 577 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_B_15_0); 578 *(uint32_t *)&tx_status_info->addr2[2] = 579 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_B_47_16); 580 TXMON_HAL_USER(tx_ppdu_info, user_id, sw_peer_id) = 581 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, SW_PEER_ID); 582 } 583 584 /** 585 * hal_txmon_parse_queue_exten() - parse queue exten tlv 586 * 587 * @tx_tlv: pointer to queue exten tlv header 588 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 589 * 590 * Return: void 591 */ 592 static inline void 593 hal_txmon_parse_queue_exten(void *tx_tlv, 594 struct hal_tx_ppdu_info *tx_ppdu_info) 595 { 596 TXMON_HAL_STATUS(tx_ppdu_info, frame_control) = 597 HAL_TX_DESC_GET_64(tx_tlv, TX_QUEUE_EXTENSION, 598 FRAME_CTL); 599 TXMON_HAL_STATUS(tx_ppdu_info, frame_control_info_valid) = true; 600 } 601 602 /** 603 * hal_txmon_parse_mpdu_start() - parse mpdu start tlv 604 * 605 * @tx_tlv: pointer to mpdu start tlv header 606 * @user_id: user id 607 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 608 * 609 * Return: void 610 */ 611 static inline void 612 hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id, 613 struct hal_tx_ppdu_info *tx_ppdu_info) 614 { 615 TXMON_HAL_USER(tx_ppdu_info, user_id, 616 start_seq) = HAL_TX_DESC_GET_64(tx_tlv, TX_MPDU_START, 617 MPDU_SEQUENCE_NUMBER); 618 TXMON_HAL(tx_ppdu_info, cur_usr_idx) = user_id; 619 } 620 #endif 621 622 /** 623 * hal_txmon_status_get_num_users_generic_be() - api to get num users 624 * from start of fes window 625 * 626 * @tx_tlv_hdr: pointer to TLV header 627 * @num_users: reference to number of user 628 * 629 * Return: status 630 */ 631 static inline uint32_t 632 hal_txmon_status_get_num_users_generic_be(void *tx_tlv_hdr, uint8_t *num_users) 633 { 634 uint32_t tlv_tag, user_id, tlv_len; 635 uint32_t tlv_status = HAL_MON_TX_STATUS_PPDU_NOT_DONE; 636 void *tx_tlv; 637 638 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr); 639 user_id = HAL_RX_GET_USER_TLV32_USERID(tx_tlv_hdr); 640 tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv_hdr); 641 642 tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 643 /* window starts with either initiator or response */ 644 switch (tlv_tag) { 645 case WIFITX_FES_SETUP_E: 646 { 647 *num_users = hal_txmon_get_num_users(tx_tlv); 648 if (*num_users == 0) 649 *num_users = 1; 650 651 tlv_status = HAL_MON_TX_FES_SETUP; 652 break; 653 } 654 case WIFIRX_RESPONSE_REQUIRED_INFO_E: 655 { 656 *num_users = HAL_TX_DESC_GET_64(tx_tlv, 657 RX_RESPONSE_REQUIRED_INFO, 658 RESPONSE_STA_COUNT); 659 if (*num_users == 0) 660 *num_users = 1; 661 tlv_status = HAL_MON_RX_RESPONSE_REQUIRED_INFO; 662 break; 663 } 664 }; 665 666 return tlv_status; 667 } 668 669 /** 670 * hal_tx_get_ppdu_info() - api to get tx ppdu info 671 * @pdev_handle: DP_PDEV handle 672 * @prot_ppdu_info: populate dp_ppdu_info protection 673 * @tx_data_ppdu_info: populate dp_ppdu_info data 674 * @tlv_tag: Tag 675 * 676 * Return: dp_tx_ppdu_info pointer 677 */ 678 static inline void * 679 hal_tx_get_ppdu_info(void *data_info, void *prot_info, uint32_t tlv_tag) 680 { 681 struct hal_tx_ppdu_info *prot_ppdu_info = prot_info; 682 683 switch (tlv_tag) { 684 case WIFITX_FES_SETUP_E:/* DOWNSTREAM */ 685 case WIFITX_FLUSH_E:/* DOWNSTREAM */ 686 case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */ 687 case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */ 688 case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */ 689 case WIFITX_MPDU_START_E:/* DOWNSTREAM */ 690 case WIFITX_MSDU_START_E:/* DOWNSTREAM */ 691 case WIFITX_DATA_E:/* DOWNSTREAM */ 692 case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */ 693 case WIFITX_MPDU_END_E:/* DOWNSTREAM */ 694 case WIFITX_MSDU_END_E:/* DOWNSTREAM */ 695 case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */ 696 case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */ 697 case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */ 698 case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */ 699 case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */ 700 case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */ 701 case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */ 702 case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */ 703 case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */ 704 case WIFITX_WUR_DATA_E:/* DOWNSTREAM */ 705 case WIFISCHEDULER_END_E:/* DOWNSTREAM */ 706 case WIFITX_FES_STATUS_START_PPDU_E:/* UPSTREAM */ 707 { 708 return data_info; 709 } 710 } 711 712 /* 713 * check current prot_tlv_status is start protection 714 * check current tlv_tag is either start protection or end protection 715 */ 716 if (TXMON_HAL(prot_ppdu_info, 717 prot_tlv_status) == WIFITX_FES_STATUS_START_PROT_E) { 718 return prot_info; 719 } else if (tlv_tag == WIFITX_FES_STATUS_PROT_E || 720 tlv_tag == WIFITX_FES_STATUS_START_PROT_E) { 721 TXMON_HAL(prot_ppdu_info, prot_tlv_status) = tlv_tag; 722 return prot_info; 723 } else { 724 TXMON_HAL(prot_ppdu_info, prot_tlv_status) = tlv_tag; 725 return data_info; 726 } 727 728 return data_info; 729 } 730 731 /** 732 * hal_txmon_status_parse_tlv_generic_be() - api to parse status tlv. 733 * @data_ppdu_info: hal_txmon data ppdu info 734 * @prot_ppdu_info: hal_txmon prot ppdu info 735 * @data_status_info: pointer to data status info 736 * @prot_status_info: pointer to prot status info 737 * @tx_tlv_hdr: fragment of tx_tlv_hdr 738 * @status_frag: qdf_frag_t buffer 739 * 740 * Return: status 741 */ 742 static inline uint32_t 743 hal_txmon_status_parse_tlv_generic_be(void *data_ppdu_info, 744 void *prot_ppdu_info, 745 void *data_status_info, 746 void *prot_status_info, 747 void *tx_tlv_hdr, 748 qdf_frag_t status_frag) 749 { 750 struct hal_tx_ppdu_info *ppdu_info; 751 struct hal_tx_status_info *tx_status_info; 752 struct hal_mon_packet_info *packet_info = NULL; 753 uint32_t tlv_tag, user_id, tlv_len; 754 uint32_t status = HAL_MON_TX_STATUS_PPDU_NOT_DONE; 755 void *tx_tlv; 756 757 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr); 758 /* user_id start with 1, decrement by 1 to start from 0 */ 759 user_id = HAL_RX_GET_USER_TLV64_USERID(tx_tlv_hdr) - 1; 760 tlv_len = HAL_RX_GET_USER_TLV64_LEN(tx_tlv_hdr); 761 762 tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 763 764 /* parse tlv and populate tx_ppdu_info */ 765 ppdu_info = hal_tx_get_ppdu_info(data_ppdu_info, 766 prot_ppdu_info, tlv_tag); 767 tx_status_info = (ppdu_info->is_data ? data_status_info : 768 prot_status_info); 769 770 user_id = user_id > ppdu_info->num_users ? 0 : ppdu_info->num_users; 771 772 switch (tlv_tag) { 773 /* start of initiator FES window */ 774 case WIFITX_FES_SETUP_E:/* DOWNSTREAM */ 775 { 776 /* initiator PPDU window start */ 777 hal_txmon_parse_tx_fes_setup(tx_tlv, ppdu_info); 778 779 status = HAL_MON_TX_FES_SETUP; 780 SHOW_DEFINED(WIFITX_FES_SETUP_E); 781 break; 782 } 783 /* end of initiator FES window */ 784 case WIFITX_FES_STATUS_END_E:/* UPSTREAM */ 785 { 786 /* initiator PPDU window end */ 787 uint32_t ppdu_timestamp_start = 0; 788 uint32_t ppdu_timestamp_end = 0; 789 uint8_t response_type = 0; 790 uint8_t r2r_end_status_follow = 0; 791 792 status = HAL_MON_TX_FES_STATUS_END; 793 794 ppdu_timestamp_start = 795 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 796 START_OF_FRAME_TIMESTAMP_15_0) | 797 (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 798 START_OF_FRAME_TIMESTAMP_31_16) << 799 HAL_TX_LSB(TX_FES_STATUS_END, 800 START_OF_FRAME_TIMESTAMP_31_16)); 801 ppdu_timestamp_end = 802 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 803 END_OF_FRAME_TIMESTAMP_15_0) | 804 (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 805 END_OF_FRAME_TIMESTAMP_31_16) << 806 HAL_TX_LSB(TX_FES_STATUS_END, 807 END_OF_FRAME_TIMESTAMP_31_16)); 808 809 response_type = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 810 RESPONSE_TYPE); 811 /* 812 * r2r end status follow to inform whether to look for 813 * rx_response_required_info 814 */ 815 r2r_end_status_follow = 816 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 817 R2R_END_STATUS_TO_FOLLOW); 818 819 TXMON_STATUS_INFO(tx_status_info, 820 response_type) = response_type; 821 TXMON_STATUS_INFO(tx_status_info, 822 r2r_to_follow) = r2r_end_status_follow; 823 824 /* update phy timestamp to ppdu timestamp */ 825 TXMON_HAL_STATUS(ppdu_info, 826 ppdu_timestamp) = ppdu_timestamp_start; 827 828 SHOW_DEFINED(WIFITX_FES_STATUS_END_E); 829 break; 830 } 831 /* response window open */ 832 case WIFIRX_RESPONSE_REQUIRED_INFO_E:/* UPSTREAM */ 833 { 834 /* response PPDU window start */ 835 uint32_t ppdu_id = 0; 836 uint8_t reception_type = 0; 837 uint8_t response_sta_count = 0; 838 839 status = HAL_MON_RX_RESPONSE_REQUIRED_INFO; 840 841 ppdu_id = HAL_TX_DESC_GET_64(tx_tlv, 842 RX_RESPONSE_REQUIRED_INFO, 843 PHY_PPDU_ID); 844 reception_type = 845 HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO, 846 SU_OR_UPLINK_MU_RECEPTION); 847 response_sta_count = 848 HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO, 849 RESPONSE_STA_COUNT); 850 851 /* get mac address */ 852 *(uint32_t *)&tx_status_info->addr1[0] = 853 HAL_TX_DESC_GET_64(tx_tlv, 854 RX_RESPONSE_REQUIRED_INFO, 855 ADDR1_31_0); 856 *(uint32_t *)&tx_status_info->addr1[4] = 857 HAL_TX_DESC_GET_64(tx_tlv, 858 RX_RESPONSE_REQUIRED_INFO, 859 ADDR1_47_32); 860 *(uint32_t *)&tx_status_info->addr2[0] = 861 HAL_TX_DESC_GET_64(tx_tlv, 862 RX_RESPONSE_REQUIRED_INFO, 863 ADDR2_15_0); 864 *(uint32_t *)&tx_status_info->addr2[2] = 865 HAL_TX_DESC_GET_64(tx_tlv, 866 RX_RESPONSE_REQUIRED_INFO, 867 ADDR2_47_16); 868 869 TXMON_HAL(ppdu_info, ppdu_id) = ppdu_id; 870 TXMON_HAL_STATUS(ppdu_info, ppdu_id) = ppdu_id; 871 872 if (response_sta_count == 0) 873 response_sta_count = 1; 874 TXMON_HAL(ppdu_info, num_users) = response_sta_count; 875 876 if (reception_type) 877 TXMON_STATUS_INFO(tx_status_info, 878 transmission_type) = 879 TXMON_SU_TRANSMISSION; 880 else 881 TXMON_STATUS_INFO(tx_status_info, 882 transmission_type) = 883 TXMON_MU_TRANSMISSION; 884 885 SHOW_DEFINED(WIFIRX_RESPONSE_REQUIRED_INFO_E); 886 break; 887 } 888 /* Response window close */ 889 case WIFIRESPONSE_END_STATUS_E:/* UPSTREAM */ 890 { 891 /* response PPDU window end */ 892 uint8_t generated_response = 0; 893 uint32_t bandwidth = 0; 894 uint32_t ppdu_timestamp_start = 0; 895 uint32_t ppdu_timestamp_end = 0; 896 897 status = HAL_MON_RESPONSE_END_STATUS_INFO; 898 generated_response = HAL_TX_DESC_GET_64(tx_tlv, 899 RESPONSE_END_STATUS, 900 GENERATED_RESPONSE); 901 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 902 COEX_BASED_TX_BW); 903 /* 32 bits TSF */ 904 ppdu_timestamp_start = 905 (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 906 START_OF_FRAME_TIMESTAMP_15_0) | 907 (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 908 START_OF_FRAME_TIMESTAMP_31_16) << 909 16)); 910 ppdu_timestamp_end = 911 (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 912 END_OF_FRAME_TIMESTAMP_15_0) | 913 (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 914 END_OF_FRAME_TIMESTAMP_31_16) << 915 16)); 916 917 TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth; 918 /* update phy timestamp to ppdu timestamp */ 919 TXMON_HAL_STATUS(ppdu_info, 920 ppdu_timestamp) = ppdu_timestamp_start; 921 922 TXMON_STATUS_INFO(tx_status_info, 923 generated_response) = generated_response; 924 SHOW_DEFINED(WIFIRESPONSE_END_STATUS_E); 925 break; 926 } 927 case WIFITX_FLUSH_E:/* DOWNSTREAM */ 928 { 929 SHOW_DEFINED(WIFITX_FLUSH_E); 930 break; 931 } 932 933 /* Downstream tlv */ 934 case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */ 935 { 936 hal_txmon_parse_pcu_ppdu_setup_init(tx_tlv, data_status_info, 937 prot_status_info); 938 939 status = HAL_MON_TX_PCU_PPDU_SETUP_INIT; 940 SHOW_DEFINED(WIFIPCU_PPDU_SETUP_INIT_E); 941 break; 942 } 943 case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */ 944 { 945 hal_txmon_parse_peer_entry(tx_tlv, user_id, 946 ppdu_info, tx_status_info); 947 SHOW_DEFINED(WIFITX_PEER_ENTRY_E); 948 break; 949 } 950 case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */ 951 { 952 status = HAL_MON_TX_QUEUE_EXTENSION; 953 hal_txmon_parse_queue_exten(tx_tlv, ppdu_info); 954 955 SHOW_DEFINED(WIFITX_QUEUE_EXTENSION_E); 956 break; 957 } 958 /* payload and data frame handling */ 959 case WIFITX_MPDU_START_E:/* DOWNSTREAM */ 960 { 961 hal_txmon_parse_mpdu_start(tx_tlv, user_id, ppdu_info); 962 963 status = HAL_MON_TX_MPDU_START; 964 SHOW_DEFINED(WIFITX_MPDU_START_E); 965 break; 966 } 967 case WIFITX_MSDU_START_E:/* DOWNSTREAM */ 968 { 969 /* compacted */ 970 /* we expect frame to be 802.11 frame type */ 971 status = HAL_MON_TX_MSDU_START; 972 SHOW_DEFINED(WIFITX_MSDU_START_E); 973 break; 974 } 975 case WIFITX_DATA_E:/* DOWNSTREAM */ 976 { 977 status = HAL_MON_TX_DATA; 978 /* 979 * TODO: do we need a conversion api to convert 980 * user_id from hw to get host user_index 981 */ 982 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 983 TXMON_STATUS_INFO(tx_status_info, 984 buffer) = (void *)status_frag; 985 TXMON_STATUS_INFO(tx_status_info, 986 offset) = ((void *)tx_tlv - 987 (void *)status_frag); 988 TXMON_STATUS_INFO(tx_status_info, 989 length) = tlv_len; 990 991 /* 992 * reference of the status buffer will be held in 993 * dp_tx_update_ppdu_info_status() 994 */ 995 status = HAL_MON_TX_DATA; 996 SHOW_DEFINED(WIFITX_DATA_E); 997 break; 998 } 999 case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */ 1000 { 1001 packet_info = &ppdu_info->packet_info; 1002 status = HAL_MON_TX_BUFFER_ADDR; 1003 /* 1004 * TODO: do we need a conversion api to convert 1005 * user_id from hw to get host user_index 1006 */ 1007 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1008 1009 hal_txmon_populate_packet_info_generic_be(tx_tlv, packet_info); 1010 1011 SHOW_DEFINED(WIFIMON_BUFFER_ADDR_E); 1012 break; 1013 } 1014 case WIFITX_MPDU_END_E:/* DOWNSTREAM */ 1015 { 1016 /* no tlv content */ 1017 SHOW_DEFINED(WIFITX_MPDU_END_E); 1018 break; 1019 } 1020 case WIFITX_MSDU_END_E:/* DOWNSTREAM */ 1021 { 1022 /* no tlv content */ 1023 SHOW_DEFINED(WIFITX_MSDU_END_E); 1024 break; 1025 } 1026 case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */ 1027 { 1028 /* no tlv content */ 1029 SHOW_DEFINED(WIFITX_LAST_MPDU_FETCHED_E); 1030 break; 1031 } 1032 case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */ 1033 { 1034 /* no tlv content */ 1035 SHOW_DEFINED(WIFITX_LAST_MPDU_END_E); 1036 break; 1037 } 1038 case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */ 1039 { 1040 /* 1041 * transmitting power 1042 * minimum transmitting power 1043 * desired nss 1044 * tx chain mask 1045 * desired bw 1046 * duration of transmit and response 1047 * 1048 * since most of the field we are deriving from other tlv 1049 * we don't need to enable this in our tlv. 1050 */ 1051 SHOW_DEFINED(WIFICOEX_TX_REQ_E); 1052 break; 1053 } 1054 case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */ 1055 { 1056 /* user tlv */ 1057 /* 1058 * All Tx monitor will have 802.11 hdr 1059 * we don't need to enable this TLV 1060 */ 1061 SHOW_DEFINED(WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E); 1062 break; 1063 } 1064 case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */ 1065 { 1066 /* 1067 * no tlv content 1068 * 1069 * TLV that indicates to TXPCU that preamble phase for the NDP 1070 * frame transmission is now over 1071 */ 1072 SHOW_DEFINED(WIFINDP_PREAMBLE_DONE_E); 1073 break; 1074 } 1075 case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */ 1076 { 1077 /* 1078 * no tlv content 1079 * 1080 * TLV indicates to the SCH that all timing critical TLV 1081 * has been passed on to the transmit path 1082 */ 1083 SHOW_DEFINED(WIFISCH_CRITICAL_TLV_REFERENCE_E); 1084 break; 1085 } 1086 case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */ 1087 { 1088 /* 1089 * Loopback specific setup info - not needed for Tx monitor 1090 */ 1091 SHOW_DEFINED(WIFITX_LOOPBACK_SETUP_E); 1092 break; 1093 } 1094 case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */ 1095 { 1096 /* 1097 * no tlv content 1098 * 1099 * TLV indicates that other modules besides the scheduler can 1100 * now also start generating TLV's 1101 * prevent colliding or generating TLV's out of order 1102 */ 1103 SHOW_DEFINED(WIFITX_FES_SETUP_COMPLETE_E); 1104 break; 1105 } 1106 case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */ 1107 { 1108 /* 1109 * no tlv content 1110 * 1111 * TLV indicates to SCH that a burst of MPDU info will 1112 * start to come in over the TLV 1113 */ 1114 SHOW_DEFINED(WIFITQM_MPDU_GLOBAL_START_E); 1115 break; 1116 } 1117 case WIFITX_WUR_DATA_E:/* DOWNSTREAM */ 1118 { 1119 SHOW_DEFINED(WIFITX_WUR_DATA_E); 1120 break; 1121 } 1122 case WIFISCHEDULER_END_E:/* DOWNSTREAM */ 1123 { 1124 /* 1125 * no tlv content 1126 * 1127 * TLV indicates END of all TLV's within the scheduler TLV 1128 */ 1129 SHOW_DEFINED(WIFISCHEDULER_END_E); 1130 break; 1131 } 1132 1133 /* Upstream tlv */ 1134 case WIFIPDG_TX_REQ_E: 1135 { 1136 SHOW_DEFINED(WIFIPDG_TX_REQ_E); 1137 break; 1138 } 1139 case WIFITX_FES_STATUS_START_E: 1140 { 1141 /* 1142 * TLV indicating that first transmission on the medium 1143 */ 1144 uint8_t medium_prot_type = 0; 1145 1146 status = HAL_MON_TX_FES_STATUS_START; 1147 1148 medium_prot_type = HAL_TX_DESC_GET_64(tx_tlv, 1149 TX_FES_STATUS_START, 1150 MEDIUM_PROT_TYPE); 1151 1152 ppdu_info = (struct hal_tx_ppdu_info *)prot_ppdu_info; 1153 /* update what type of medium protection frame */ 1154 TXMON_STATUS_INFO(tx_status_info, 1155 medium_prot_type) = medium_prot_type; 1156 SHOW_DEFINED(WIFITX_FES_STATUS_START_E); 1157 break; 1158 } 1159 case WIFITX_FES_STATUS_PROT_E: 1160 { 1161 uint32_t start_timestamp = 0; 1162 uint32_t end_timestamp = 0; 1163 1164 /* 1165 * generated by TXPCU to indicate the result of having 1166 * received of the expected protection frame 1167 */ 1168 1169 status = HAL_MON_TX_FES_STATUS_PROT; 1170 start_timestamp = 1171 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT, 1172 START_OF_FRAME_TIMESTAMP_15_0); 1173 start_timestamp |= 1174 (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT, 1175 START_OF_FRAME_TIMESTAMP_31_16) << 1176 15); 1177 end_timestamp = HAL_TX_DESC_GET_64(tx_tlv, 1178 TX_FES_STATUS_PROT, 1179 END_OF_FRAME_TIMESTAMP_15_0); 1180 end_timestamp |= 1181 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT, 1182 END_OF_FRAME_TIMESTAMP_31_16) << 15; 1183 1184 /* ppdu timestamp as phy timestamp */ 1185 TXMON_HAL_STATUS(ppdu_info, 1186 ppdu_timestamp) = start_timestamp; 1187 1188 SHOW_DEFINED(WIFITX_FES_STATUS_PROT_E); 1189 break; 1190 } 1191 case WIFITX_FES_STATUS_START_PROT_E: 1192 { 1193 uint64_t tsft_64; 1194 uint32_t response_type; 1195 status = HAL_MON_TX_FES_STATUS_START_PROT; 1196 TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag; 1197 /* timestamp */ 1198 tsft_64 = HAL_TX_DESC_GET_64(tx_tlv, 1199 TX_FES_STATUS_START_PROT, 1200 PROT_TIMESTAMP_LOWER_32); 1201 tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv, 1202 TX_FES_STATUS_START_PROT, 1203 PROT_TIMESTAMP_UPPER_32) << 32); 1204 1205 response_type = HAL_TX_DESC_GET_64(tx_tlv, 1206 TX_FES_STATUS_START_PROT, 1207 RESPONSE_TYPE); 1208 1209 TXMON_STATUS_INFO(tx_status_info, 1210 response_type) = response_type; 1211 TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64; 1212 1213 SHOW_DEFINED(WIFITX_FES_STATUS_START_PROT_E); 1214 break; 1215 } 1216 case WIFIPROT_TX_END_E: 1217 { 1218 /* 1219 * no tlv content 1220 * 1221 * generated by TXPCU the moment that protection frame 1222 * transmission has finished on the medium 1223 */ 1224 SHOW_DEFINED(WIFIPROT_TX_END_E); 1225 break; 1226 } 1227 case WIFITX_FES_STATUS_START_PPDU_E: 1228 { 1229 uint64_t tsft_64; 1230 uint8_t ndp_frame; 1231 1232 status = HAL_MON_TX_FES_STATUS_START_PPDU; 1233 tsft_64 = HAL_TX_DESC_GET_64(tx_tlv, 1234 TX_FES_STATUS_START_PPDU, 1235 PPDU_TIMESTAMP_LOWER_32); 1236 tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv, 1237 TX_FES_STATUS_START_PPDU, 1238 PPDU_TIMESTAMP_UPPER_32) << 32); 1239 1240 ndp_frame = HAL_TX_DESC_GET_64(tx_tlv, 1241 TX_FES_STATUS_START_PPDU, 1242 NDP_FRAME); 1243 1244 TXMON_STATUS_INFO(tx_status_info, ndp_frame) = ndp_frame; 1245 TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64; 1246 1247 SHOW_DEFINED(WIFITX_FES_STATUS_START_PPDU_E); 1248 break; 1249 } 1250 case WIFITX_FES_STATUS_USER_PPDU_E: 1251 { 1252 /* user tlv */ 1253 uint16_t duration; 1254 uint8_t transmitted_tid; 1255 1256 duration = HAL_TX_DESC_GET_64(tx_tlv, 1257 TX_FES_STATUS_USER_PPDU, 1258 DURATION); 1259 transmitted_tid = HAL_TX_DESC_GET_64(tx_tlv, 1260 TX_FES_STATUS_USER_PPDU, 1261 TRANSMITTED_TID); 1262 1263 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1264 TXMON_HAL_USER(ppdu_info, user_id, tid) = transmitted_tid; 1265 TXMON_HAL_USER(ppdu_info, user_id, duration) = duration; 1266 1267 status = HAL_MON_TX_FES_STATUS_USER_PPDU; 1268 SHOW_DEFINED(WIFITX_FES_STATUS_USER_PPDU_E); 1269 break; 1270 } 1271 case WIFIPPDU_TX_END_E: 1272 { 1273 /* 1274 * no tlv content 1275 * 1276 * generated by TXPCU the moment that PPDU transmission has 1277 * finished on the medium 1278 */ 1279 SHOW_DEFINED(WIFIPPDU_TX_END_E); 1280 break; 1281 } 1282 1283 case WIFITX_FES_STATUS_USER_RESPONSE_E: 1284 { 1285 /* 1286 * TLV contains the FES transmit result of the each 1287 * of the MAC users. TLV are forwarded to HWSCH 1288 */ 1289 SHOW_DEFINED(WIFITX_FES_STATUS_USER_RESPONSE_E); 1290 break; 1291 } 1292 case WIFITX_FES_STATUS_ACK_OR_BA_E: 1293 { 1294 /* user tlv */ 1295 /* 1296 * TLV generated by RXPCU and provide information related to 1297 * the received BA or ACK frame 1298 */ 1299 SHOW_DEFINED(WIFITX_FES_STATUS_ACK_OR_BA_E); 1300 break; 1301 } 1302 case WIFITX_FES_STATUS_1K_BA_E: 1303 { 1304 /* user tlv */ 1305 /* 1306 * TLV generated by RXPCU and providing information related 1307 * to the received BA frame in case of 512/1024 bitmaps 1308 */ 1309 SHOW_DEFINED(WIFITX_FES_STATUS_1K_BA_E); 1310 break; 1311 } 1312 case WIFIRECEIVED_RESPONSE_USER_7_0_E: 1313 { 1314 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_7_0_E); 1315 break; 1316 } 1317 case WIFIRECEIVED_RESPONSE_USER_15_8_E: 1318 { 1319 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_15_8_E); 1320 break; 1321 } 1322 case WIFIRECEIVED_RESPONSE_USER_23_16_E: 1323 { 1324 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_23_16_E); 1325 break; 1326 } 1327 case WIFIRECEIVED_RESPONSE_USER_31_24_E: 1328 { 1329 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_31_24_E); 1330 break; 1331 } 1332 case WIFIRECEIVED_RESPONSE_USER_36_32_E: 1333 { 1334 /* 1335 * RXPCU generates this TLV when it receives a response frame 1336 * that TXPCU pre-announced it was waiting for and in 1337 * RXPCU_SETUP TLV, TLV generated before the 1338 * RECEIVED_RESPONSE_INFO TLV. 1339 * 1340 * received info user fields are there which is not needed 1341 * for TX monitor 1342 */ 1343 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_36_32_E); 1344 break; 1345 } 1346 1347 case WIFITXPCU_BUFFER_STATUS_E: 1348 { 1349 SHOW_DEFINED(WIFITXPCU_BUFFER_STATUS_E); 1350 break; 1351 } 1352 case WIFITXPCU_USER_BUFFER_STATUS_E: 1353 { 1354 /* 1355 * WIFITXPCU_USER_BUFFER_STATUS_E - user tlv 1356 * for TX monitor we aren't interested in this tlv 1357 */ 1358 SHOW_DEFINED(WIFITXPCU_USER_BUFFER_STATUS_E); 1359 break; 1360 } 1361 case WIFITXDMA_STOP_REQUEST_E: 1362 { 1363 /* 1364 * no tlv content 1365 * 1366 * TLV is destined to TXDMA and informs TXDMA to stop 1367 * pushing data into the transmit path. 1368 */ 1369 SHOW_DEFINED(WIFITXDMA_STOP_REQUEST_E); 1370 break; 1371 } 1372 case WIFITX_CBF_INFO_E: 1373 { 1374 /* 1375 * After NDPA + NDP is received, RXPCU sends the TX_CBF_INFO to 1376 * TXPCU to respond the CBF frame 1377 * 1378 * compressed beamforming pkt doesn't has mac header 1379 * Tx monitor not interested in this pkt. 1380 */ 1381 SHOW_DEFINED(WIFITX_CBF_INFO_E); 1382 break; 1383 } 1384 case WIFITX_MPDU_COUNT_TRANSFER_END_E: 1385 { 1386 /* 1387 * no tlv content 1388 * 1389 * TLV indicates that TXPCU has finished generating the 1390 * TQM_UPDATE_TX_MPDU_COUNT TLV for all users 1391 */ 1392 SHOW_DEFINED(WIFITX_MPDU_COUNT_TRANSFER_END_E); 1393 break; 1394 } 1395 case WIFIPDG_RESPONSE_E: 1396 { 1397 /* 1398 * most of the feilds are already covered in 1399 * other TLV 1400 * This is generated by TX_PCU to PDG to calculate 1401 * all the PHY header info. 1402 * 1403 * some useful fields like min transmit power, 1404 * rate used for transmitting packet is present. 1405 */ 1406 SHOW_DEFINED(WIFIPDG_RESPONSE_E); 1407 break; 1408 } 1409 case WIFIPDG_TRIG_RESPONSE_E: 1410 { 1411 /* no tlv content */ 1412 SHOW_DEFINED(WIFIPDG_TRIG_RESPONSE_E); 1413 break; 1414 } 1415 case WIFIRECEIVED_TRIGGER_INFO_E: 1416 { 1417 /* 1418 * TLV generated by RXPCU to inform the scheduler that 1419 * a trigger frame has been received 1420 */ 1421 SHOW_DEFINED(WIFIRECEIVED_TRIGGER_INFO_E); 1422 break; 1423 } 1424 case WIFIOFDMA_TRIGGER_DETAILS_E: 1425 { 1426 SHOW_DEFINED(WIFIOFDMA_TRIGGER_DETAILS_E); 1427 break; 1428 } 1429 case WIFIRX_FRAME_BITMAP_ACK_E: 1430 { 1431 /* user tlv */ 1432 status = HAL_MON_RX_FRAME_BITMAP_ACK; 1433 SHOW_DEFINED(WIFIRX_FRAME_BITMAP_ACK_E); 1434 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1435 TXMON_STATUS_INFO(tx_status_info, no_bitmap_avail) = 1436 HAL_TX_DESC_GET_64(tx_tlv, 1437 RX_FRAME_BITMAP_ACK, 1438 NO_BITMAP_AVAILABLE); 1439 1440 TXMON_STATUS_INFO(tx_status_info, explicit_ack) = 1441 HAL_TX_DESC_GET_64(tx_tlv, 1442 RX_FRAME_BITMAP_ACK, 1443 EXPLICIT_ACK); 1444 /* 1445 * get mac address, since address is received frame 1446 * change the order and store it 1447 */ 1448 *(uint32_t *)&tx_status_info->addr2[0] = 1449 HAL_TX_DESC_GET_64(tx_tlv, 1450 RX_FRAME_BITMAP_ACK, 1451 ADDR1_31_0); 1452 *(uint32_t *)&tx_status_info->addr2[4] = 1453 HAL_TX_DESC_GET_64(tx_tlv, 1454 RX_FRAME_BITMAP_ACK, 1455 ADDR1_47_32); 1456 *(uint32_t *)&tx_status_info->addr1[0] = 1457 HAL_TX_DESC_GET_64(tx_tlv, 1458 RX_FRAME_BITMAP_ACK, 1459 ADDR2_15_0); 1460 *(uint32_t *)&tx_status_info->addr1[2] = 1461 HAL_TX_DESC_GET_64(tx_tlv, 1462 RX_FRAME_BITMAP_ACK, 1463 ADDR2_47_16); 1464 1465 TXMON_STATUS_INFO(tx_status_info, explicit_ack_type) = 1466 HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_BITMAP_ACK, 1467 EXPLICT_ACK_TYPE); 1468 1469 TXMON_HAL_USER(ppdu_info, user_id, tid) = 1470 HAL_TX_DESC_GET_64(tx_tlv, 1471 RX_FRAME_BITMAP_ACK, 1472 BA_TID); 1473 TXMON_HAL_USER(ppdu_info, user_id, aid) = 1474 HAL_TX_DESC_GET_64(tx_tlv, 1475 RX_FRAME_BITMAP_ACK, 1476 STA_FULL_AID); 1477 TXMON_HAL_USER(ppdu_info, user_id, start_seq) = 1478 HAL_TX_DESC_GET_64(tx_tlv, 1479 RX_FRAME_BITMAP_ACK, 1480 BA_TS_SEQ); 1481 TXMON_HAL_USER(ppdu_info, user_id, ba_control) = 1482 HAL_TX_DESC_GET_64(tx_tlv, 1483 RX_FRAME_BITMAP_ACK, 1484 BA_TS_CTRL); 1485 TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) = 1486 HAL_TX_DESC_GET_64(tx_tlv, 1487 RX_FRAME_BITMAP_ACK, 1488 BA_BITMAP_SIZE); 1489 1490 /* ba bitmap */ 1491 qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap), 1492 &HAL_SET_FLD_OFFSET_64(tx_tlv, 1493 RX_FRAME_BITMAP_ACK, 1494 BA_TS_BITMAP_31_0, 0), 32); 1495 1496 break; 1497 } 1498 case WIFIRX_FRAME_1K_BITMAP_ACK_E: 1499 { 1500 /* user tlv */ 1501 status = HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K; 1502 SHOW_DEFINED(WIFIRX_FRAME_1K_BITMAP_ACK_E); 1503 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1504 TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) = 1505 (4 + HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_1K_BITMAP_ACK, 1506 BA_BITMAP_SIZE)); 1507 TXMON_HAL_USER(ppdu_info, user_id, tid) = 1508 HAL_TX_DESC_GET_64(tx_tlv, 1509 RX_FRAME_1K_BITMAP_ACK, 1510 BA_TID); 1511 TXMON_HAL_USER(ppdu_info, user_id, aid) = 1512 HAL_TX_DESC_GET_64(tx_tlv, 1513 RX_FRAME_1K_BITMAP_ACK, 1514 STA_FULL_AID); 1515 /* get mac address */ 1516 *(uint32_t *)&tx_status_info->addr1[0] = 1517 HAL_TX_DESC_GET_64(tx_tlv, 1518 RX_FRAME_1K_BITMAP_ACK, 1519 ADDR1_31_0); 1520 *(uint32_t *)&tx_status_info->addr1[4] = 1521 HAL_TX_DESC_GET_64(tx_tlv, 1522 RX_FRAME_1K_BITMAP_ACK, 1523 ADDR1_47_32); 1524 *(uint32_t *)&tx_status_info->addr2[0] = 1525 HAL_TX_DESC_GET_64(tx_tlv, 1526 RX_FRAME_1K_BITMAP_ACK, 1527 ADDR2_15_0); 1528 *(uint32_t *)&tx_status_info->addr2[2] = 1529 HAL_TX_DESC_GET_64(tx_tlv, 1530 RX_FRAME_1K_BITMAP_ACK, 1531 ADDR2_47_16); 1532 1533 TXMON_HAL_USER(ppdu_info, user_id, start_seq) = 1534 HAL_TX_DESC_GET_64(tx_tlv, 1535 RX_FRAME_1K_BITMAP_ACK, 1536 BA_TS_SEQ); 1537 TXMON_HAL_USER(ppdu_info, user_id, ba_control) = 1538 HAL_TX_DESC_GET_64(tx_tlv, 1539 RX_FRAME_1K_BITMAP_ACK, 1540 BA_TS_CTRL); 1541 /* memcpy ba bitmap */ 1542 qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap), 1543 &HAL_SET_FLD_OFFSET_64(tx_tlv, 1544 RX_FRAME_1K_BITMAP_ACK, 1545 BA_TS_BITMAP_31_0, 0), 1546 4 << TXMON_HAL_USER(ppdu_info, 1547 user_id, ba_bitmap_sz)); 1548 1549 break; 1550 } 1551 case WIFIRESPONSE_START_STATUS_E: 1552 { 1553 /* 1554 * TLV indicates which HW response the TXPCU 1555 * started generating 1556 * 1557 * HW generated frames like 1558 * ACK frame - handled 1559 * CTS frame - handled 1560 * BA frame - handled 1561 * MBA frame - handled 1562 * CBF frame - no frame header 1563 * Trigger response - TODO 1564 * NDP LMR - no frame header 1565 */ 1566 SHOW_DEFINED(WIFIRESPONSE_START_STATUS_E); 1567 break; 1568 } 1569 case WIFIRX_START_PARAM_E: 1570 { 1571 /* 1572 * RXPCU send this TLV after PHY RX detected a frame 1573 * in the medium 1574 * 1575 * TX monitor not interested in this TLV 1576 */ 1577 SHOW_DEFINED(WIFIRX_START_PARAM_E); 1578 break; 1579 } 1580 case WIFIRXPCU_EARLY_RX_INDICATION_E: 1581 { 1582 /* 1583 * early indication of pkt type and mcs rate 1584 * already captured in other tlv 1585 */ 1586 SHOW_DEFINED(WIFIRXPCU_EARLY_RX_INDICATION_E); 1587 break; 1588 } 1589 case WIFIRX_PM_INFO_E: 1590 { 1591 SHOW_DEFINED(WIFIRX_PM_INFO_E); 1592 break; 1593 } 1594 1595 /* Active window */ 1596 case WIFITX_FLUSH_REQ_E: 1597 { 1598 SHOW_DEFINED(WIFITX_FLUSH_REQ_E); 1599 break; 1600 } 1601 case WIFICOEX_TX_STATUS_E: 1602 { 1603 /* duration are retrieved from coex tx status */ 1604 uint16_t duration; 1605 uint8_t status_reason; 1606 1607 status = HAL_MON_COEX_TX_STATUS; 1608 duration = HAL_TX_DESC_GET_64(tx_tlv, 1609 COEX_TX_STATUS, 1610 CURRENT_TX_DURATION); 1611 status_reason = HAL_TX_DESC_GET_64(tx_tlv, 1612 COEX_TX_STATUS, 1613 TX_STATUS_REASON); 1614 1615 /* update duration */ 1616 if (status_reason == COEX_FES_TX_START || 1617 status_reason == COEX_RESPONSE_TX_START) 1618 TXMON_HAL_USER(ppdu_info, user_id, duration) = duration; 1619 1620 SHOW_DEFINED(WIFICOEX_TX_STATUS_E); 1621 break; 1622 } 1623 case WIFIR2R_STATUS_END_E: 1624 { 1625 SHOW_DEFINED(WIFIR2R_STATUS_END_E); 1626 break; 1627 } 1628 case WIFIRX_PREAMBLE_E: 1629 { 1630 SHOW_DEFINED(WIFIRX_PREAMBLE_E); 1631 break; 1632 } 1633 case WIFIMACTX_SERVICE_E: 1634 { 1635 SHOW_DEFINED(WIFIMACTX_SERVICE_E); 1636 break; 1637 } 1638 1639 case WIFIMACTX_U_SIG_EHT_SU_MU_E: 1640 { 1641 SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_SU_MU_E); 1642 break; 1643 } 1644 case WIFIMACTX_U_SIG_EHT_TB_E: 1645 { 1646 /* TODO: no radiotap info available */ 1647 SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_TB_E); 1648 break; 1649 } 1650 case WIFIMACTX_EHT_SIG_USR_OFDMA_E: 1651 { 1652 SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_OFDMA_E); 1653 break; 1654 } 1655 case WIFIMACTX_EHT_SIG_USR_MU_MIMO_E: 1656 { 1657 SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_MU_MIMO_E); 1658 break; 1659 } 1660 case WIFIMACTX_EHT_SIG_USR_SU_E: 1661 { 1662 SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_SU_E); 1663 /* TODO: no radiotap info available */ 1664 break; 1665 } 1666 1667 case WIFIMACTX_HE_SIG_A_SU_E: 1668 { 1669 uint8_t mcs_of_sig_b = 0; 1670 uint8_t dcm_of_sig_b = 0; 1671 uint8_t sig_a_bw = 0; 1672 uint16_t he_mu_flag_1 = 0; 1673 uint16_t he_mu_flag_2 = 0; 1674 1675 status = HAL_MON_MACTX_HE_SIG_A_SU; 1676 1677 mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1678 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1679 TRANSMIT_MCS); 1680 dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1681 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1682 DCM); 1683 sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv, 1684 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1685 TRANSMIT_BW); 1686 1687 he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1688 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1689 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN | 1690 QDF_MON_STATUS_CHANNEL_1_RU_KNOWN | 1691 QDF_MON_STATUS_CHANNEL_2_RU_KNOWN | 1692 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN; 1693 1694 /* MCS */ 1695 he_mu_flag_1 |= mcs_of_sig_b << 1696 QDF_MON_STATUS_SIG_B_MCS_SHIFT; 1697 /* DCM */ 1698 he_mu_flag_1 |= dcm_of_sig_b << 1699 QDF_MON_STATUS_SIG_B_DCM_SHIFT; 1700 /* bandwidth */ 1701 he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN; 1702 he_mu_flag_2 |= sig_a_bw << 1703 QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT; 1704 1705 TXMON_HAL_STATUS(ppdu_info, he_flags1) = he_mu_flag_1; 1706 TXMON_HAL_STATUS(ppdu_info, he_flags2) = he_mu_flag_2; 1707 1708 SHOW_DEFINED(WIFIMACTX_HE_SIG_A_SU_E); 1709 break; 1710 } 1711 case WIFIMACTX_HE_SIG_A_MU_DL_E: 1712 { 1713 uint8_t mcs_of_sig_b = 0; 1714 uint8_t dcm_of_sig_b = 0; 1715 uint8_t sig_a_bw = 0; 1716 uint8_t num_sig_b_symb = 0; 1717 uint8_t comp_mode_sig_b = 0; 1718 uint8_t punc_bw = 0; 1719 uint16_t he_mu_flag_1 = 0; 1720 uint16_t he_mu_flag_2 = 0; 1721 1722 status = HAL_MON_MACTX_HE_SIG_A_MU_DL; 1723 mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1724 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1725 MCS_OF_SIG_B); 1726 dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1727 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1728 DCM_OF_SIG_B); 1729 sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv, 1730 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1731 TRANSMIT_BW); 1732 num_sig_b_symb = HAL_TX_DESC_GET_64(tx_tlv, 1733 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1734 NUM_SIG_B_SYMBOLS); 1735 comp_mode_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1736 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1737 COMP_MODE_SIG_B); 1738 1739 he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1740 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1741 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1742 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN | 1743 QDF_MON_STATUS_CHANNEL_1_RU_KNOWN | 1744 QDF_MON_STATUS_CHANNEL_2_RU_KNOWN | 1745 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN | 1746 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1747 QDF_MON_STATUS_SIG_B_SYMBOL_USER_KNOWN; 1748 1749 /* MCS */ 1750 he_mu_flag_1 |= mcs_of_sig_b << 1751 QDF_MON_STATUS_SIG_B_MCS_SHIFT; 1752 /* DCM */ 1753 he_mu_flag_1 |= dcm_of_sig_b << 1754 QDF_MON_STATUS_SIG_B_DCM_SHIFT; 1755 /* Compression */ 1756 he_mu_flag_2 |= comp_mode_sig_b << 1757 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1758 /* bandwidth */ 1759 he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN; 1760 he_mu_flag_2 |= sig_a_bw << 1761 QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT; 1762 he_mu_flag_2 |= comp_mode_sig_b << 1763 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1764 /* number of symbol */ 1765 he_mu_flag_2 |= num_sig_b_symb << 1766 QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1767 /* puncture bw */ 1768 he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_KNOWN; 1769 punc_bw = sig_a_bw; 1770 he_mu_flag_2 |= 1771 punc_bw << QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_SHIFT; 1772 1773 /* copy per user info to all user */ 1774 TXMON_HAL_STATUS(ppdu_info, he_mu_flags) = 1; 1775 TXMON_HAL_STATUS(ppdu_info, he_flags1) = he_mu_flag_1; 1776 TXMON_HAL_STATUS(ppdu_info, he_flags2) = he_mu_flag_2; 1777 1778 SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_DL_E); 1779 break; 1780 } 1781 case WIFIMACTX_HE_SIG_A_MU_UL_E: 1782 { 1783 SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_UL_E); 1784 break; 1785 } 1786 case WIFIMACTX_HE_SIG_B1_MU_E: 1787 { 1788 status = HAL_MON_MACTX_HE_SIG_B1_MU; 1789 SHOW_DEFINED(WIFIMACTX_HE_SIG_B1_MU_E); 1790 break; 1791 } 1792 case WIFIMACTX_HE_SIG_B2_MU_E: 1793 { 1794 /* user tlv */ 1795 uint16_t sta_id = 0; 1796 uint16_t sta_spatial_config = 0; 1797 uint8_t sta_mcs = 0; 1798 uint8_t coding = 0; 1799 uint8_t nss = 0; 1800 uint8_t user_order = 0; 1801 1802 status = HAL_MON_MACTX_HE_SIG_B2_MU; 1803 1804 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1805 1806 sta_id = HAL_TX_DESC_GET_64(tx_tlv, 1807 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 1808 STA_ID); 1809 sta_spatial_config = HAL_TX_DESC_GET_64(tx_tlv, 1810 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 1811 STA_SPATIAL_CONFIG); 1812 sta_mcs = HAL_TX_DESC_GET_64(tx_tlv, 1813 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 1814 STA_MCS); 1815 coding = HAL_TX_DESC_GET_64(tx_tlv, 1816 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 1817 STA_CODING); 1818 nss = HAL_TX_DESC_GET_64(tx_tlv, 1819 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 1820 NSTS); 1821 user_order = HAL_TX_DESC_GET_64(tx_tlv, 1822 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 1823 USER_ORDER); 1824 1825 /* HE data 1 */ 1826 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 1827 QDF_MON_STATUS_HE_MCS_KNOWN | 1828 QDF_MON_STATUS_HE_CODING_KNOWN; 1829 /* HE data 2 */ 1830 1831 /* HE data 3 */ 1832 TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs; 1833 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 1834 sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1835 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 1836 coding << QDF_MON_STATUS_CODING_SHIFT; 1837 1838 /* HE data 4 */ 1839 TXMON_HAL_USER(ppdu_info, user_id, he_data4) |= 1840 sta_id << QDF_MON_STATUS_STA_ID_SHIFT; 1841 1842 /* HE data 5 */ 1843 1844 /* HE data 6 */ 1845 TXMON_HAL_USER(ppdu_info, user_id, nss) = nss; 1846 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss; 1847 1848 SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_MU_E); 1849 break; 1850 } 1851 case WIFIMACTX_HE_SIG_B2_OFDMA_E: 1852 { 1853 /* user tlv */ 1854 uint8_t *he_sig_b2_ofdma_info = NULL; 1855 uint16_t sta_id = 0; 1856 uint8_t nss = 0; 1857 uint8_t txbf = 0; 1858 uint8_t sta_mcs = 0; 1859 uint8_t sta_dcm = 0; 1860 uint8_t coding = 0; 1861 uint8_t user_order = 0; 1862 1863 status = HAL_MON_MACTX_HE_SIG_B2_OFDMA; 1864 1865 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1866 1867 he_sig_b2_ofdma_info = (uint8_t *)tx_tlv + 1868 HAL_OFFSET(MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 1869 STA_ID); 1870 1871 sta_id = HAL_TX_DESC_GET_64(tx_tlv, 1872 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 1873 STA_ID); 1874 nss = HAL_TX_DESC_GET_64(tx_tlv, 1875 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 1876 NSTS); 1877 txbf = HAL_TX_DESC_GET_64(tx_tlv, 1878 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 1879 TXBF); 1880 sta_mcs = HAL_TX_DESC_GET_64(tx_tlv, 1881 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 1882 STA_MCS); 1883 sta_dcm = HAL_TX_DESC_GET_64(tx_tlv, 1884 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 1885 STA_DCM); 1886 coding = HAL_TX_DESC_GET_64(tx_tlv, 1887 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 1888 STA_CODING); 1889 user_order = HAL_TX_DESC_GET_64(tx_tlv, 1890 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 1891 USER_ORDER); 1892 1893 /* HE data 1 */ 1894 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 1895 QDF_MON_STATUS_HE_MCS_KNOWN | 1896 QDF_MON_STATUS_HE_CODING_KNOWN | 1897 QDF_MON_STATUS_HE_DCM_KNOWN; 1898 /* HE data 2 */ 1899 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= 1900 QDF_MON_STATUS_TXBF_KNOWN; 1901 1902 /* HE data 3 */ 1903 TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs; 1904 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 1905 sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1906 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 1907 sta_dcm << QDF_MON_STATUS_DCM_SHIFT; 1908 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 1909 coding << QDF_MON_STATUS_CODING_SHIFT; 1910 1911 /* HE data 4 */ 1912 TXMON_HAL_USER(ppdu_info, user_id, he_data4) |= 1913 sta_id << QDF_MON_STATUS_STA_ID_SHIFT; 1914 1915 /* HE data 5 */ 1916 TXMON_HAL_USER(ppdu_info, user_id, he_data5) |= 1917 txbf << QDF_MON_STATUS_TXBF_SHIFT; 1918 1919 /* HE data 6 */ 1920 TXMON_HAL_USER(ppdu_info, user_id, nss) = nss; 1921 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss; 1922 1923 SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_OFDMA_E); 1924 break; 1925 } 1926 case WIFIMACTX_L_SIG_A_E: 1927 { 1928 uint8_t *l_sig_a_info = NULL; 1929 uint8_t rate = 0; 1930 1931 status = HAL_MON_MACTX_L_SIG_A; 1932 1933 l_sig_a_info = (uint8_t *)tx_tlv + 1934 HAL_OFFSET(MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS, 1935 RATE); 1936 rate = HAL_TX_DESC_GET_64(tx_tlv, 1937 MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS, 1938 RATE); 1939 1940 switch (rate) { 1941 case 8: 1942 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_0MCS; 1943 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0; 1944 break; 1945 case 9: 1946 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_1MCS; 1947 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1; 1948 break; 1949 case 10: 1950 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_2MCS; 1951 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2; 1952 break; 1953 case 11: 1954 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_3MCS; 1955 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3; 1956 break; 1957 case 12: 1958 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_4MCS; 1959 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4; 1960 break; 1961 case 13: 1962 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_5MCS; 1963 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5; 1964 break; 1965 case 14: 1966 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_6MCS; 1967 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6; 1968 break; 1969 case 15: 1970 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_7MCS; 1971 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS7; 1972 break; 1973 default: 1974 break; 1975 } 1976 1977 TXMON_HAL_STATUS(ppdu_info, ofdm_flag) = 1; 1978 TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU; 1979 TXMON_HAL_STATUS(ppdu_info, l_sig_a_info) = *l_sig_a_info; 1980 1981 SHOW_DEFINED(WIFIMACTX_L_SIG_A_E); 1982 break; 1983 } 1984 case WIFIMACTX_L_SIG_B_E: 1985 { 1986 uint8_t *l_sig_b_info = NULL; 1987 uint8_t rate = 0; 1988 1989 status = HAL_MON_MACTX_L_SIG_B; 1990 1991 l_sig_b_info = (uint8_t *)tx_tlv + 1992 HAL_OFFSET(MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS, 1993 RATE); 1994 rate = HAL_TX_DESC_GET_64(tx_tlv, 1995 MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS, 1996 RATE); 1997 1998 switch (rate) { 1999 case 1: 2000 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_3MCS; 2001 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3; 2002 break; 2003 case 2: 2004 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_2MCS; 2005 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2; 2006 break; 2007 case 3: 2008 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_1MCS; 2009 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1; 2010 break; 2011 case 4: 2012 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_0MCS; 2013 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0; 2014 break; 2015 case 5: 2016 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_6MCS; 2017 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6; 2018 break; 2019 case 6: 2020 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_5MCS; 2021 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5; 2022 break; 2023 case 7: 2024 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_4MCS; 2025 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4; 2026 break; 2027 default: 2028 break; 2029 } 2030 2031 TXMON_HAL_STATUS(ppdu_info, cck_flag) = 1; 2032 TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU; 2033 TXMON_HAL_STATUS(ppdu_info, l_sig_b_info) = *l_sig_b_info; 2034 2035 SHOW_DEFINED(WIFIMACTX_L_SIG_B_E); 2036 break; 2037 } 2038 case WIFIMACTX_HT_SIG_E: 2039 { 2040 uint8_t mcs = 0; 2041 uint8_t bw = 0; 2042 uint8_t is_stbc = 0; 2043 uint8_t coding = 0; 2044 uint8_t gi = 0; 2045 2046 status = HAL_MON_MACTX_HT_SIG; 2047 mcs = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, MCS); 2048 bw = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, CBW); 2049 is_stbc = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, STBC); 2050 coding = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, FEC_CODING); 2051 gi = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, SHORT_GI); 2052 2053 TXMON_HAL_STATUS(ppdu_info, ldpc) = 2054 (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0; 2055 TXMON_HAL_STATUS(ppdu_info, ht_mcs) = mcs; 2056 TXMON_HAL_STATUS(ppdu_info, bw) = bw; 2057 TXMON_HAL_STATUS(ppdu_info, sgi) = gi; 2058 TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc; 2059 TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU; 2060 2061 SHOW_DEFINED(WIFIMACTX_HT_SIG_E); 2062 break; 2063 } 2064 case WIFIMACTX_VHT_SIG_A_E: 2065 { 2066 uint8_t bandwidth = 0; 2067 uint8_t is_stbc = 0; 2068 uint8_t group_id = 0; 2069 uint32_t nss_comb = 0; 2070 uint8_t nss_su = 0; 2071 uint8_t nss_mu[4] = {0}; 2072 uint8_t sgi = 0; 2073 uint8_t coding = 0; 2074 uint8_t mcs = 0; 2075 uint8_t beamformed = 0; 2076 uint8_t partial_aid = 0; 2077 2078 status = HAL_MON_MACTX_VHT_SIG_A; 2079 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, 2080 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2081 BANDWIDTH); 2082 is_stbc = HAL_TX_DESC_GET_64(tx_tlv, 2083 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2084 STBC); 2085 group_id = HAL_TX_DESC_GET_64(tx_tlv, 2086 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2087 GROUP_ID); 2088 /* nss_comb is su nss, MU nss and partial AID */ 2089 nss_comb = HAL_TX_DESC_GET_64(tx_tlv, 2090 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2091 N_STS); 2092 /* if it is SU */ 2093 nss_su = nss_comb & 0x7; 2094 /* partial aid - applicable only for SU */ 2095 partial_aid = (nss_comb >> 3) & 0x1F; 2096 /* if it is MU */ 2097 nss_mu[0] = nss_comb & 0x7; 2098 nss_mu[1] = (nss_comb >> 3) & 0x7; 2099 nss_mu[2] = (nss_comb >> 6) & 0x7; 2100 nss_mu[3] = (nss_comb >> 9) & 0x7; 2101 2102 sgi = HAL_TX_DESC_GET_64(tx_tlv, 2103 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2104 GI_SETTING); 2105 coding = HAL_TX_DESC_GET_64(tx_tlv, 2106 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2107 SU_MU_CODING); 2108 mcs = HAL_TX_DESC_GET_64(tx_tlv, 2109 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2110 MCS); 2111 beamformed = HAL_TX_DESC_GET_64(tx_tlv, 2112 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2113 BEAMFORMED); 2114 2115 TXMON_HAL_STATUS(ppdu_info, ldpc) = 2116 (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0; 2117 TXMON_STATUS_INFO(tx_status_info, sw_frame_group_id) = group_id; 2118 2119 TXMON_HAL_STATUS(ppdu_info, sgi) = sgi; 2120 TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc; 2121 TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth; 2122 TXMON_HAL_STATUS(ppdu_info, beamformed) = beamformed; 2123 2124 if (group_id == 0 || group_id == 63) { 2125 TXMON_HAL_STATUS(ppdu_info, reception_type) = 2126 HAL_RX_TYPE_SU; 2127 TXMON_HAL_STATUS(ppdu_info, mcs) = mcs; 2128 TXMON_HAL_STATUS(ppdu_info, nss) = 2129 nss_su & VHT_SIG_SU_NSS_MASK; 2130 } else { 2131 TXMON_HAL_STATUS(ppdu_info, reception_type) = 2132 HAL_RX_TYPE_MU_MIMO; 2133 TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs; 2134 TXMON_HAL_USER(ppdu_info, user_id, nss) = 2135 nss_su & VHT_SIG_SU_NSS_MASK; 2136 } 2137 2138 /* TODO: loop over multiple user */ 2139 TXMON_HAL_USER(ppdu_info, user_id, 2140 vht_flag_values2) = bandwidth; 2141 TXMON_HAL_USER(ppdu_info, user_id, 2142 vht_flag_values3[0]) = (mcs << 4) | nss_su; 2143 TXMON_HAL_USER(ppdu_info, user_id, 2144 vht_flag_values3[1]) = (mcs << 4) | nss_mu[1]; 2145 TXMON_HAL_USER(ppdu_info, user_id, 2146 vht_flag_values3[2]) = (mcs << 4) | nss_mu[2]; 2147 TXMON_HAL_USER(ppdu_info, user_id, 2148 vht_flag_values3[3]) = (mcs << 4) | nss_mu[3]; 2149 TXMON_HAL_USER(ppdu_info, user_id, 2150 vht_flag_values4) = coding; 2151 TXMON_HAL_USER(ppdu_info, user_id, 2152 vht_flag_values5) = group_id; 2153 TXMON_HAL_USER(ppdu_info, user_id, 2154 vht_flag_values6) = partial_aid; 2155 SHOW_DEFINED(WIFIMACTX_VHT_SIG_A_E); 2156 break; 2157 } 2158 case WIFIMACTX_VHT_SIG_B_MU160_E: 2159 { 2160 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU160_E); 2161 break; 2162 } 2163 case WIFIMACTX_VHT_SIG_B_MU80_E: 2164 { 2165 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU80_E); 2166 break; 2167 } 2168 case WIFIMACTX_VHT_SIG_B_MU40_E: 2169 { 2170 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU40_E); 2171 break; 2172 } 2173 case WIFIMACTX_VHT_SIG_B_MU20_E: 2174 { 2175 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU20_E); 2176 break; 2177 } 2178 case WIFIMACTX_VHT_SIG_B_SU160_E: 2179 { 2180 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU160_E); 2181 break; 2182 } 2183 case WIFIMACTX_VHT_SIG_B_SU80_E: 2184 { 2185 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU80_E); 2186 break; 2187 } 2188 case WIFIMACTX_VHT_SIG_B_SU40_E: 2189 { 2190 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU40_E); 2191 break; 2192 } 2193 case WIFIMACTX_VHT_SIG_B_SU20_E: 2194 { 2195 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU20_E); 2196 break; 2197 } 2198 case WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E: 2199 { 2200 SHOW_DEFINED(WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E); 2201 break; 2202 } 2203 case WIFIMACTX_USER_DESC_PER_USER_E: 2204 { 2205 uint32_t psdu_length = 0; 2206 uint8_t ru_start_index = 0; 2207 uint8_t ru_size = 0; 2208 uint8_t nss = 0; 2209 uint8_t mcs = 0; 2210 uint8_t dcm = 0; 2211 uint8_t fec_type = 0; 2212 uint8_t is_ldpc_extra_symb = 0; 2213 uint32_t he_data1 = 0; 2214 uint32_t he_data2 = 0; 2215 uint32_t he_data3 = 0; 2216 uint32_t he_data4 = 0; 2217 uint32_t he_data5 = 0; 2218 uint32_t he_data6 = 0; 2219 2220 status = HAL_MON_MACTX_USER_DESC_PER_USER; 2221 2222 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 2223 2224 psdu_length = HAL_TX_DESC_GET_64(tx_tlv, 2225 MACTX_USER_DESC_PER_USER, 2226 PSDU_LENGTH); 2227 ru_start_index = HAL_TX_DESC_GET_64(tx_tlv, 2228 MACTX_USER_DESC_PER_USER, 2229 RU_START_INDEX); 2230 ru_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 2231 RU_SIZE); 2232 nss = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, NSS); 2233 mcs = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, MCS); 2234 dcm = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, DCM); 2235 fec_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 2236 FEC_TYPE); 2237 is_ldpc_extra_symb = 2238 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 2239 LDPC_EXTRA_SYMBOL); 2240 2241 if (!TXMON_HAL_STATUS(ppdu_info, he_flags)) 2242 break; 2243 2244 /* update */ 2245 /* MCS */ 2246 he_data1 |= QDF_MON_STATUS_HE_MCS_KNOWN; 2247 he_data3 |= (mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT); 2248 /* DCM */ 2249 he_data1 |= QDF_MON_STATUS_HE_DCM_KNOWN; 2250 he_data3 |= (dcm << QDF_MON_STATUS_DCM_SHIFT); 2251 /* LDPC EXTRA SYMB */ 2252 he_data1 |= QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN; 2253 he_data3 |= (is_ldpc_extra_symb << 2254 QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT); 2255 /* RU offset and RU */ 2256 he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 2257 he_data2 |= QDF_MON_STATUS_RU_ALLOCATION_OFFSET_KNOWN; 2258 he_data2 |= (ru_start_index << 2259 QDF_MON_STATUS_RU_ALLOCATION_SHIFT); 2260 2261 /* Data BW and RU allocation */ 2262 he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 2263 he_data5 |= ru_size << 2; 2264 2265 TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs; 2266 2267 /* update stack variable to ppdu_info */ 2268 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= he_data1; 2269 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= he_data2; 2270 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= he_data3; 2271 TXMON_HAL_USER(ppdu_info, user_id, he_data4) |= he_data4; 2272 TXMON_HAL_USER(ppdu_info, user_id, he_data5) |= he_data5; 2273 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= he_data6; 2274 2275 SHOW_DEFINED(WIFIMACTX_USER_DESC_PER_USER_E); 2276 break; 2277 } 2278 case WIFIMACTX_USER_DESC_COMMON_E: 2279 { 2280 SHOW_DEFINED(WIFIMACTX_USER_DESC_COMMON_E); 2281 break; 2282 } 2283 case WIFIMACTX_PHY_DESC_E: 2284 { 2285 uint32_t bf_type = 0; 2286 /* pkt_type - preamble type */ 2287 uint32_t pkt_type = 0; 2288 uint8_t bandwidth = 0; 2289 uint8_t mcs = 0; 2290 uint8_t is_stbc = 0; 2291 uint8_t nss = 0; 2292 uint8_t is_triggered = 0; 2293 uint8_t gi = 0; 2294 uint8_t he_ppdu_subtype = 0; 2295 uint32_t ltf_size = 0; 2296 uint32_t ru_start = 0; 2297 uint32_t he_data1 = 0; 2298 uint32_t he_data2 = 0; 2299 uint32_t he_data3 = 0; 2300 uint32_t he_data4 = 0; 2301 uint32_t he_data5 = 0; 2302 uint32_t he_data6 = 0; 2303 uint16_t he_mu_flag_1 = 0; 2304 uint16_t he_mu_flag_2 = 0; 2305 uint8_t i = 0; 2306 2307 status = HAL_MON_MACTX_PHY_DESC; 2308 2309 bf_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, BF_TYPE); 2310 pkt_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, PKT_TYPE); 2311 2312 mcs = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, MCS); 2313 is_stbc = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, STBC); 2314 is_triggered = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2315 TRIGGERED); 2316 if (!is_triggered) { 2317 nss = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2318 HEAVY_CLIP_NSS); 2319 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2320 BANDWIDTH); 2321 } else { 2322 nss = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, NSS); 2323 /* 2324 * is_triggered, bw is minimum of AP pkt bw 2325 * or STA bw 2326 */ 2327 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2328 AP_PKT_BW); 2329 if (pkt_type == TXMON_PKT_TYPE_11AX || 2330 pkt_type == TXMON_PKT_TYPE_11BE) 2331 ru_start = 2332 HAL_TX_DESC_GET_64(tx_tlv, 2333 MACTX_PHY_DESC, 2334 RU_SIZE_UPDATED_V2); 2335 } 2336 2337 gi = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2338 CP_SETTING); 2339 ltf_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, LTF_SIZE); 2340 he_ppdu_subtype = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2341 HE_PPDU_SUBTYPE); 2342 2343 TXMON_HAL_STATUS(ppdu_info, beamformed) = bf_type; 2344 TXMON_HAL_STATUS(ppdu_info, preamble_type) = pkt_type; 2345 TXMON_HAL_STATUS(ppdu_info, mcs) = mcs; 2346 TXMON_HAL_STATUS(ppdu_info, ltf_size) = ltf_size; 2347 TXMON_HAL_STATUS(ppdu_info, nss) = nss; 2348 TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc; 2349 TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth; 2350 2351 switch (ppdu_info->rx_status.preamble_type) { 2352 case TXMON_PKT_TYPE_11N_MM: 2353 TXMON_HAL_STATUS(ppdu_info, ht_flags) = 1; 2354 TXMON_HAL_STATUS(ppdu_info, 2355 rtap_flags) |= HT_SGI_PRESENT; 2356 break; 2357 case TXMON_PKT_TYPE_11AC: 2358 TXMON_HAL_STATUS(ppdu_info, vht_flags) = 1; 2359 break; 2360 case TXMON_PKT_TYPE_11AX: 2361 TXMON_HAL_STATUS(ppdu_info, he_flags) = 1; 2362 break; 2363 default: 2364 break; 2365 } 2366 2367 if (!TXMON_HAL_STATUS(ppdu_info, he_flags)) 2368 break; 2369 2370 /* update he flags */ 2371 /* PPDU FORMAT */ 2372 switch (he_ppdu_subtype) { 2373 case TXMON_HE_SUBTYPE_SU: 2374 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 2375 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 2376 break; 2377 case TXMON_HE_SUBTYPE_TRIG: 2378 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 2379 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 2380 break; 2381 case TXMON_HE_SUBTYPE_MU: 2382 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 2383 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 2384 break; 2385 case TXMON_HE_SUBTYPE_EXT_SU: 2386 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 2387 QDF_MON_STATUS_HE_EXT_SU_FORMAT_TYPE; 2388 break; 2389 }; 2390 2391 /* BEAM CHANGE */ 2392 he_data1 |= QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN; 2393 if (ppdu_info->rx_status.beamformed) { 2394 he_data1 |= QDF_MON_STATUS_TXBF_KNOWN; 2395 he_data5 |= (1 << QDF_MON_STATUS_TXBF_SHIFT); 2396 he_data3 |= (1 << QDF_MON_STATUS_BEAM_CHANGE_SHIFT); 2397 } 2398 2399 /* UL/DL known */ 2400 he_data1 |= QDF_MON_STATUS_HE_DL_UL_KNOWN; 2401 he_data3 |= (1 << QDF_MON_STATUS_DL_UL_SHIFT); 2402 2403 /* MCS */ 2404 he_data1 |= QDF_MON_STATUS_HE_MCS_KNOWN; 2405 he_data3 |= (mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT); 2406 2407 /* STBC */ 2408 he_data1 |= QDF_MON_STATUS_HE_STBC_KNOWN; 2409 he_data3 |= (is_stbc << QDF_MON_STATUS_STBC_SHIFT); 2410 2411 /* GI */ 2412 he_data2 |= QDF_MON_STATUS_HE_GI_KNOWN; 2413 he_data5 |= (gi << QDF_MON_STATUS_GI_SHIFT); 2414 2415 /* NSS */ 2416 he_data6 |= (nss << QDF_MON_STATUS_HE_DATA_6_NSS_SHIFT); 2417 2418 /* Data BW and RU allocation */ 2419 he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 2420 he_data5 |= bandwidth; 2421 2422 /* update stack variable to ppdu_info */ 2423 TXMON_HAL_STATUS(ppdu_info, he_data1) |= he_data1; 2424 TXMON_HAL_STATUS(ppdu_info, he_data2) |= he_data2; 2425 TXMON_HAL_STATUS(ppdu_info, he_data3) |= he_data3; 2426 TXMON_HAL_STATUS(ppdu_info, he_data4) |= he_data4; 2427 TXMON_HAL_STATUS(ppdu_info, he_data5) |= he_data5; 2428 TXMON_HAL_STATUS(ppdu_info, he_data6) |= he_data6; 2429 2430 for (i = 0; i < TXMON_HAL(ppdu_info, num_users); i++) { 2431 TXMON_HAL_USER(ppdu_info, i, he_data1) |= he_data1; 2432 TXMON_HAL_USER(ppdu_info, i, he_data2) |= he_data2; 2433 TXMON_HAL_USER(ppdu_info, i, he_data3) |= he_data3; 2434 TXMON_HAL_USER(ppdu_info, i, he_data4) |= he_data4; 2435 TXMON_HAL_USER(ppdu_info, i, he_data5) |= he_data5; 2436 TXMON_HAL_USER(ppdu_info, i, he_data6) |= he_data6; 2437 TXMON_HAL_USER(ppdu_info, i, he_flags1) = he_mu_flag_1; 2438 TXMON_HAL_USER(ppdu_info, i, he_flags2) = he_mu_flag_2; 2439 } 2440 2441 SHOW_DEFINED(WIFIMACTX_PHY_DESC_E); 2442 break; 2443 } 2444 case WIFICOEX_RX_STATUS_E: 2445 { 2446 SHOW_DEFINED(WIFICOEX_RX_STATUS_E); 2447 break; 2448 } 2449 case WIFIRX_PPDU_ACK_REPORT_E: 2450 { 2451 SHOW_DEFINED(WIFIRX_PPDU_ACK_REPORT_E); 2452 break; 2453 } 2454 case WIFIRX_PPDU_NO_ACK_REPORT_E: 2455 { 2456 SHOW_DEFINED(WIFIRX_PPDU_NO_ACK_REPORT_E); 2457 break; 2458 } 2459 case WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E: 2460 { 2461 SHOW_DEFINED(WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E); 2462 break; 2463 } 2464 case WIFITXPCU_PHYTX_DEBUG32_E: 2465 { 2466 SHOW_DEFINED(WIFITXPCU_PHYTX_DEBUG32_E); 2467 break; 2468 } 2469 case WIFITXPCU_PREAMBLE_DONE_E: 2470 { 2471 SHOW_DEFINED(WIFITXPCU_PREAMBLE_DONE_E); 2472 break; 2473 } 2474 case WIFIRX_PHY_SLEEP_E: 2475 { 2476 SHOW_DEFINED(WIFIRX_PHY_SLEEP_E); 2477 break; 2478 } 2479 case WIFIRX_FRAME_BITMAP_REQ_E: 2480 { 2481 SHOW_DEFINED(WIFIRX_FRAME_BITMAP_REQ_E); 2482 break; 2483 } 2484 case WIFIRXPCU_TX_SETUP_CLEAR_E: 2485 { 2486 SHOW_DEFINED(WIFIRXPCU_TX_SETUP_CLEAR_E); 2487 break; 2488 } 2489 case WIFIRX_TRIG_INFO_E: 2490 { 2491 SHOW_DEFINED(WIFIRX_TRIG_INFO_E); 2492 break; 2493 } 2494 case WIFIEXPECTED_RESPONSE_E: 2495 { 2496 SHOW_DEFINED(WIFIEXPECTED_RESPONSE_E); 2497 break; 2498 } 2499 case WIFITRIGGER_RESPONSE_TX_DONE_E: 2500 { 2501 SHOW_DEFINED(WIFITRIGGER_RESPONSE_TX_DONE_E); 2502 break; 2503 } 2504 } 2505 2506 return status; 2507 } 2508 #endif /* QCA_MONITOR_2_0_SUPPORT */ 2509 2510 #ifdef REO_SHARED_QREF_TABLE_EN 2511 static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl) 2512 { 2513 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2514 uint32_t reg_val = 0; 2515 2516 /* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers 2517 * of 37 peer/tids 2518 */ 2519 reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE)); 2520 reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1); 2521 HAL_REG_WRITE(hal, 2522 HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 2523 reg_val); 2524 2525 /* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers 2526 * of 37 peer/tids 2527 */ 2528 reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1)); 2529 HAL_REG_WRITE(hal, 2530 HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 2531 reg_val); 2532 2533 hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of" 2534 "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back" 2535 "to erase stale entries in reo storage: regval:%x", hal, reg_val); 2536 } 2537 2538 /* hal_reo_shared_qaddr_write(): Write REO tid queue addr 2539 * LUT shared by SW and HW at the index given by peer id 2540 * and tid. 2541 * 2542 * @hal_soc: hal soc pointer 2543 * @reo_qref_addr: pointer to index pointed to be peer_id 2544 * and tid 2545 * @tid: tid queue number 2546 * @hw_qdesc_paddr: reo queue addr 2547 */ 2548 2549 static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl, 2550 uint16_t peer_id, 2551 int tid, 2552 qdf_dma_addr_t hw_qdesc_paddr) 2553 { 2554 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2555 struct rx_reo_queue_reference *reo_qref; 2556 uint32_t peer_tid_idx; 2557 2558 /* Plug hw_desc_addr in Host reo queue reference table */ 2559 if (HAL_PEER_ID_IS_MLO(peer_id)) { 2560 peer_tid_idx = ((peer_id - HAL_ML_PEER_ID_START) * 2561 DP_MAX_TIDS) + tid; 2562 reo_qref = (struct rx_reo_queue_reference *) 2563 &hal->reo_qref.mlo_reo_qref_table_vaddr[peer_tid_idx]; 2564 } else { 2565 peer_tid_idx = (peer_id * DP_MAX_TIDS) + tid; 2566 reo_qref = (struct rx_reo_queue_reference *) 2567 &hal->reo_qref.non_mlo_reo_qref_table_vaddr[peer_tid_idx]; 2568 } 2569 reo_qref->rx_reo_queue_desc_addr_31_0 = 2570 hw_qdesc_paddr & 0xffffffff; 2571 reo_qref->rx_reo_queue_desc_addr_39_32 = 2572 (hw_qdesc_paddr & 0xff00000000) >> 32; 2573 if (hw_qdesc_paddr != 0) 2574 reo_qref->receive_queue_number = tid; 2575 else 2576 reo_qref->receive_queue_number = 0; 2577 2578 hal_reo_shared_qaddr_cache_clear_be(hal_soc_hdl); 2579 hal_verbose_debug("hw_qdesc_paddr: %pK, tid: %d, reo_qref:%pK," 2580 "rx_reo_queue_desc_addr_31_0: %x," 2581 "rx_reo_queue_desc_addr_39_32: %x", 2582 (void *)hw_qdesc_paddr, tid, reo_qref, 2583 reo_qref->rx_reo_queue_desc_addr_31_0, 2584 reo_qref->rx_reo_queue_desc_addr_39_32); 2585 } 2586 2587 /** 2588 * hal_reo_shared_qaddr_setup() - Allocate MLO and Non MLO reo queue 2589 * reference table shared between SW and HW and initialize in Qdesc Base0 2590 * base1 registers provided by HW. 2591 * 2592 * @hal_soc: HAL Soc handle 2593 * 2594 * Return: None 2595 */ 2596 static void hal_reo_shared_qaddr_setup_be(hal_soc_handle_t hal_soc_hdl) 2597 { 2598 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2599 2600 hal->reo_qref.reo_qref_table_en = 1; 2601 2602 hal->reo_qref.mlo_reo_qref_table_vaddr = 2603 (uint64_t *)qdf_mem_alloc_consistent( 2604 hal->qdf_dev, hal->qdf_dev->dev, 2605 REO_QUEUE_REF_ML_TABLE_SIZE, 2606 &hal->reo_qref.mlo_reo_qref_table_paddr); 2607 hal->reo_qref.non_mlo_reo_qref_table_vaddr = 2608 (uint64_t *)qdf_mem_alloc_consistent( 2609 hal->qdf_dev, hal->qdf_dev->dev, 2610 REO_QUEUE_REF_NON_ML_TABLE_SIZE, 2611 &hal->reo_qref.non_mlo_reo_qref_table_paddr); 2612 2613 hal_verbose_debug("MLO table start paddr:%pK," 2614 "Non-MLO table start paddr:%pK," 2615 "MLO table start vaddr: %pK," 2616 "Non MLO table start vaddr: %pK", 2617 (void *)hal->reo_qref.mlo_reo_qref_table_paddr, 2618 (void *)hal->reo_qref.non_mlo_reo_qref_table_paddr, 2619 hal->reo_qref.mlo_reo_qref_table_vaddr, 2620 hal->reo_qref.non_mlo_reo_qref_table_vaddr); 2621 } 2622 2623 /** 2624 * hal_reo_shared_qaddr_init() - Zero out REO qref LUT and 2625 * write start addr of MLO and Non MLO table in HW 2626 * 2627 * @hal_soc: HAL Soc handle 2628 * 2629 * Return: None 2630 */ 2631 static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl) 2632 { 2633 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2634 2635 qdf_mem_zero(hal->reo_qref.mlo_reo_qref_table_vaddr, 2636 REO_QUEUE_REF_ML_TABLE_SIZE); 2637 qdf_mem_zero(hal->reo_qref.non_mlo_reo_qref_table_vaddr, 2638 REO_QUEUE_REF_NON_ML_TABLE_SIZE); 2639 /* LUT_BASE0 and BASE1 registers expect upper 32bits of LUT base address 2640 * and lower 8 bits to be 0. Shift the physical address by 8 to plug 2641 * upper 32bits only 2642 */ 2643 HAL_REG_WRITE(hal, 2644 HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE), 2645 hal->reo_qref.non_mlo_reo_qref_table_paddr >> 8); 2646 HAL_REG_WRITE(hal, 2647 HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE), 2648 hal->reo_qref.mlo_reo_qref_table_paddr >> 8); 2649 HAL_REG_WRITE(hal, 2650 HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 2651 HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE, 2652 1)); 2653 HAL_REG_WRITE(hal, 2654 HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(REO_REG_REG_BASE), 2655 HAL_MS(HWIO_REO_R0_QDESC, MAX_SW_PEER_ID_MAX_SUPPORTED, 2656 0x1fff)); 2657 } 2658 2659 /** 2660 * hal_reo_shared_qaddr_detach() - Free MLO and Non MLO reo queue 2661 * reference table shared between SW and HW 2662 * 2663 * @hal_soc: HAL Soc handle 2664 * 2665 * Return: None 2666 */ 2667 static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl) 2668 { 2669 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2670 2671 HAL_REG_WRITE(hal, 2672 HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE), 2673 0); 2674 HAL_REG_WRITE(hal, 2675 HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE), 2676 0); 2677 2678 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 2679 REO_QUEUE_REF_ML_TABLE_SIZE, 2680 hal->reo_qref.mlo_reo_qref_table_vaddr, 2681 hal->reo_qref.mlo_reo_qref_table_paddr, 0); 2682 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 2683 REO_QUEUE_REF_NON_ML_TABLE_SIZE, 2684 hal->reo_qref.non_mlo_reo_qref_table_vaddr, 2685 hal->reo_qref.non_mlo_reo_qref_table_paddr, 0); 2686 } 2687 #endif 2688 2689 /** 2690 * hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing 2691 * @hal_soc: HAL SoC context 2692 * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM 2693 * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW 2694 * 2695 * Return: void 2696 */ 2697 #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK 2698 static inline void 2699 hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl, 2700 enum hal_tx_vdev_mismatch_notify 2701 config) 2702 { 2703 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2704 uint32_t reg_addr, reg_val = 0; 2705 uint32_t val = 0; 2706 2707 reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE); 2708 2709 val = HAL_REG_READ(hal_soc, reg_addr); 2710 2711 /* reset the corresponding bits in register */ 2712 val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK)); 2713 2714 /* set config value */ 2715 reg_val = val | (config << 2716 HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT); 2717 2718 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 2719 } 2720 #else 2721 static inline void 2722 hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl, 2723 enum hal_tx_vdev_mismatch_notify 2724 config) 2725 { 2726 } 2727 #endif 2728 2729 /** 2730 * hal_tx_mcast_mlo_reinject_routing_set - set MLO multicast reinject routing 2731 * @hal_soc: HAL SoC context 2732 * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW 2733 * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM 2734 * 2735 * Return: void 2736 */ 2737 #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \ 2738 defined(WLAN_MCAST_MLO) 2739 static inline void 2740 hal_tx_mcast_mlo_reinject_routing_set_generic_be( 2741 hal_soc_handle_t hal_soc_hdl, 2742 enum hal_tx_mcast_mlo_reinject_notify config) 2743 { 2744 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2745 uint32_t reg_addr, reg_val = 0; 2746 uint32_t val = 0; 2747 2748 reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE); 2749 val = HAL_REG_READ(hal_soc, reg_addr); 2750 2751 /* reset the corresponding bits in register */ 2752 val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK)); 2753 2754 /* set config value */ 2755 reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT); 2756 2757 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 2758 } 2759 #else 2760 static inline void 2761 hal_tx_mcast_mlo_reinject_routing_set_generic_be( 2762 hal_soc_handle_t hal_soc_hdl, 2763 enum hal_tx_mcast_mlo_reinject_notify config) 2764 { 2765 } 2766 #endif 2767 2768 /** 2769 * hal_get_ba_aging_timeout_be - Get BA Aging timeout 2770 * 2771 * @hal_soc: Opaque HAL SOC handle 2772 * @ac: Access category 2773 * @value: window size to get 2774 */ 2775 2776 static inline 2777 void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl, 2778 uint8_t ac, uint32_t *value) 2779 { 2780 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 2781 2782 switch (ac) { 2783 case WME_AC_BE: 2784 *value = HAL_REG_READ(soc, 2785 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 2786 REO_REG_REG_BASE)) / 1000; 2787 break; 2788 case WME_AC_BK: 2789 *value = HAL_REG_READ(soc, 2790 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 2791 REO_REG_REG_BASE)) / 1000; 2792 break; 2793 case WME_AC_VI: 2794 *value = HAL_REG_READ(soc, 2795 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 2796 REO_REG_REG_BASE)) / 1000; 2797 break; 2798 case WME_AC_VO: 2799 *value = HAL_REG_READ(soc, 2800 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 2801 REO_REG_REG_BASE)) / 1000; 2802 break; 2803 default: 2804 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 2805 "Invalid AC: %d\n", ac); 2806 } 2807 } 2808 2809 /** 2810 * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the 2811 * buffer list provided 2812 * 2813 * @hal_soc: Opaque HAL SOC handle 2814 * @scatter_bufs_base_paddr: Array of physical base addresses 2815 * @scatter_bufs_base_vaddr: Array of virtual base addresses 2816 * @num_scatter_bufs: Number of scatter buffers in the above lists 2817 * @scatter_buf_size: Size of each scatter buffer 2818 * @last_buf_end_offset: Offset to the last entry 2819 * @num_entries: Total entries of all scatter bufs 2820 * 2821 * Return: None 2822 */ 2823 static inline void 2824 hal_setup_link_idle_list_generic_be(struct hal_soc *soc, 2825 qdf_dma_addr_t scatter_bufs_base_paddr[], 2826 void *scatter_bufs_base_vaddr[], 2827 uint32_t num_scatter_bufs, 2828 uint32_t scatter_buf_size, 2829 uint32_t last_buf_end_offset, 2830 uint32_t num_entries) 2831 { 2832 int i; 2833 uint32_t *prev_buf_link_ptr = NULL; 2834 uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size; 2835 uint32_t val; 2836 2837 /* Link the scatter buffers */ 2838 for (i = 0; i < num_scatter_bufs; i++) { 2839 if (i > 0) { 2840 prev_buf_link_ptr[0] = 2841 scatter_bufs_base_paddr[i] & 0xffffffff; 2842 prev_buf_link_ptr[1] = HAL_SM( 2843 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2844 BASE_ADDRESS_39_32, 2845 ((uint64_t)(scatter_bufs_base_paddr[i]) 2846 >> 32)) | HAL_SM( 2847 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2848 ADDRESS_MATCH_TAG, 2849 ADDRESS_MATCH_TAG_VAL); 2850 } 2851 prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] + 2852 scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE); 2853 } 2854 2855 /* TBD: Register programming partly based on MLD & the rest based on 2856 * inputs from HW team. Not complete yet. 2857 */ 2858 2859 reg_scatter_buf_size = (scatter_buf_size - 2860 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64; 2861 reg_tot_scatter_buf_size = ((scatter_buf_size - 2862 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64; 2863 2864 HAL_REG_WRITE(soc, 2865 HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR( 2866 WBM_REG_REG_BASE), 2867 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE, 2868 reg_scatter_buf_size) | 2869 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE, 2870 0x1)); 2871 2872 HAL_REG_WRITE(soc, 2873 HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR( 2874 WBM_REG_REG_BASE), 2875 HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE, 2876 SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, 2877 reg_tot_scatter_buf_size)); 2878 2879 HAL_REG_WRITE(soc, 2880 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR( 2881 WBM_REG_REG_BASE), 2882 scatter_bufs_base_paddr[0] & 0xffffffff); 2883 2884 HAL_REG_WRITE(soc, 2885 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( 2886 WBM_REG_REG_BASE), 2887 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) & 2888 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK); 2889 2890 HAL_REG_WRITE(soc, 2891 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( 2892 WBM_REG_REG_BASE), 2893 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2894 BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0]) 2895 >> 32)) | 2896 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2897 ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL)); 2898 2899 /* ADDRESS_MATCH_TAG field in the above register is expected to match 2900 * with the upper bits of link pointer. The above write sets this field 2901 * to zero and we are also setting the upper bits of link pointers to 2902 * zero while setting up the link list of scatter buffers above 2903 */ 2904 2905 /* Setup head and tail pointers for the idle list */ 2906 HAL_REG_WRITE(soc, 2907 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( 2908 WBM_REG_REG_BASE), 2909 scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff); 2910 HAL_REG_WRITE(soc, 2911 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR( 2912 WBM_REG_REG_BASE), 2913 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 2914 BUFFER_ADDRESS_39_32, 2915 ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1]) 2916 >> 32)) | 2917 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 2918 HEAD_POINTER_OFFSET, last_buf_end_offset >> 2)); 2919 2920 HAL_REG_WRITE(soc, 2921 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( 2922 WBM_REG_REG_BASE), 2923 scatter_bufs_base_paddr[0] & 0xffffffff); 2924 2925 HAL_REG_WRITE(soc, 2926 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR( 2927 WBM_REG_REG_BASE), 2928 scatter_bufs_base_paddr[0] & 0xffffffff); 2929 HAL_REG_WRITE(soc, 2930 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR( 2931 WBM_REG_REG_BASE), 2932 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 2933 BUFFER_ADDRESS_39_32, 2934 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 2935 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 2936 TAIL_POINTER_OFFSET, 0)); 2937 2938 HAL_REG_WRITE(soc, 2939 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR( 2940 WBM_REG_REG_BASE), 2941 2 * num_entries); 2942 2943 /* Set RING_ID_DISABLE */ 2944 val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1); 2945 2946 /* 2947 * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence 2948 * check the presence of the bit before toggling it. 2949 */ 2950 #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 2951 val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1); 2952 #endif 2953 HAL_REG_WRITE(soc, 2954 HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE), 2955 val); 2956 } 2957 2958 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 2959 #define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000 2960 #endif 2961 2962 /** 2963 * hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register 2964 * for REO/WBM 2965 * @soc: HAL soc handle 2966 * @cc_cfg: structure pointer for HW cookie conversion configuration 2967 * 2968 * Return: None 2969 */ 2970 static inline 2971 void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl, 2972 struct hal_hw_cc_config *cc_cfg) 2973 { 2974 uint32_t reg_addr, reg_val = 0; 2975 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 2976 2977 /* REO CFG */ 2978 reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE); 2979 reg_val = cc_cfg->lut_base_addr_31_0; 2980 HAL_REG_WRITE(soc, reg_addr, reg_val); 2981 2982 reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE); 2983 reg_val = 0; 2984 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 2985 SW_COOKIE_CONVERT_GLOBAL_ENABLE, 2986 cc_cfg->cc_global_en); 2987 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 2988 SW_COOKIE_CONVERT_ENABLE, 2989 cc_cfg->cc_global_en); 2990 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 2991 PAGE_ALIGNMENT, 2992 cc_cfg->page_4k_align); 2993 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 2994 COOKIE_OFFSET_MSB, 2995 cc_cfg->cookie_offset_msb); 2996 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 2997 COOKIE_PAGE_MSB, 2998 cc_cfg->cookie_page_msb); 2999 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3000 CMEM_LUT_BASE_ADDR_39_32, 3001 cc_cfg->lut_base_addr_39_32); 3002 HAL_REG_WRITE(soc, reg_addr, reg_val); 3003 3004 /* WBM CFG */ 3005 reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE); 3006 reg_val = cc_cfg->lut_base_addr_31_0; 3007 HAL_REG_WRITE(soc, reg_addr, reg_val); 3008 3009 reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE); 3010 reg_val = 0; 3011 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3012 PAGE_ALIGNMENT, 3013 cc_cfg->page_4k_align); 3014 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3015 COOKIE_OFFSET_MSB, 3016 cc_cfg->cookie_offset_msb); 3017 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3018 COOKIE_PAGE_MSB, 3019 cc_cfg->cookie_page_msb); 3020 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3021 CMEM_LUT_BASE_ADDR_39_32, 3022 cc_cfg->lut_base_addr_39_32); 3023 HAL_REG_WRITE(soc, reg_addr, reg_val); 3024 3025 /* 3026 * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE, 3027 */ 3028 reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE); 3029 reg_val = 0; 3030 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3031 WBM_COOKIE_CONV_GLOBAL_ENABLE, 3032 cc_cfg->cc_global_en); 3033 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3034 WBM2SW6_COOKIE_CONVERSION_EN, 3035 cc_cfg->wbm2sw6_cc_en); 3036 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3037 WBM2SW5_COOKIE_CONVERSION_EN, 3038 cc_cfg->wbm2sw5_cc_en); 3039 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3040 WBM2SW4_COOKIE_CONVERSION_EN, 3041 cc_cfg->wbm2sw4_cc_en); 3042 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3043 WBM2SW3_COOKIE_CONVERSION_EN, 3044 cc_cfg->wbm2sw3_cc_en); 3045 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3046 WBM2SW2_COOKIE_CONVERSION_EN, 3047 cc_cfg->wbm2sw2_cc_en); 3048 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3049 WBM2SW1_COOKIE_CONVERSION_EN, 3050 cc_cfg->wbm2sw1_cc_en); 3051 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3052 WBM2SW0_COOKIE_CONVERSION_EN, 3053 cc_cfg->wbm2sw0_cc_en); 3054 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3055 WBM2FW_COOKIE_CONVERSION_EN, 3056 cc_cfg->wbm2fw_cc_en); 3057 HAL_REG_WRITE(soc, reg_addr, reg_val); 3058 3059 #ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK 3060 reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE); 3061 reg_val = 0; 3062 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3063 COOKIE_DEBUG_SEL, 3064 cc_cfg->cc_global_en); 3065 3066 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3067 COOKIE_CONV_INDICATION_EN, 3068 cc_cfg->cc_global_en); 3069 3070 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3071 ERROR_PATH_COOKIE_CONV_EN, 3072 cc_cfg->error_path_cookie_conv_en); 3073 3074 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3075 RELEASE_PATH_COOKIE_CONV_EN, 3076 cc_cfg->release_path_cookie_conv_en); 3077 3078 HAL_REG_WRITE(soc, reg_addr, reg_val); 3079 #endif 3080 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 3081 /* 3082 * To enable indication for HW cookie conversion done or not for 3083 * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th 3084 * bit spare_control[15] should be set. 3085 */ 3086 reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE); 3087 reg_val = HAL_REG_READ(soc, reg_addr); 3088 reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL, 3089 SPARE_CONTROL, 3090 HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15); 3091 HAL_REG_WRITE(soc, reg_addr, reg_val); 3092 #endif 3093 } 3094 3095 /** 3096 * hal_set_ba_aging_timeout_be - Set BA Aging timeout 3097 * 3098 * @hal_soc: Opaque HAL SOC handle 3099 * @ac: Access category 3100 * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice 3101 * @value: Input value to set 3102 */ 3103 static inline 3104 void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl, 3105 uint8_t ac, uint32_t value) 3106 { 3107 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 3108 3109 switch (ac) { 3110 case WME_AC_BE: 3111 HAL_REG_WRITE(soc, 3112 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 3113 REO_REG_REG_BASE), 3114 value * 1000); 3115 break; 3116 case WME_AC_BK: 3117 HAL_REG_WRITE(soc, 3118 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 3119 REO_REG_REG_BASE), 3120 value * 1000); 3121 break; 3122 case WME_AC_VI: 3123 HAL_REG_WRITE(soc, 3124 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 3125 REO_REG_REG_BASE), 3126 value * 1000); 3127 break; 3128 case WME_AC_VO: 3129 HAL_REG_WRITE(soc, 3130 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 3131 REO_REG_REG_BASE), 3132 value * 1000); 3133 break; 3134 default: 3135 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 3136 "Invalid AC: %d\n", ac); 3137 } 3138 } 3139 3140 /** 3141 * hal_tx_populate_bank_register() - populate the bank register with 3142 * the software configs. 3143 * @soc: HAL soc handle 3144 * @config: bank config 3145 * @bank_id: bank id to be configured 3146 * 3147 * Returns: None 3148 */ 3149 #ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT 3150 static inline void 3151 hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl, 3152 union hal_tx_bank_config *config, 3153 uint8_t bank_id) 3154 { 3155 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3156 uint32_t reg_addr, reg_val = 0; 3157 3158 reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE, 3159 bank_id); 3160 3161 reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT); 3162 reg_val |= (config->encap_type << 3163 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT); 3164 reg_val |= (config->encrypt_type << 3165 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT); 3166 reg_val |= (config->src_buffer_swap << 3167 HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT); 3168 reg_val |= (config->link_meta_swap << 3169 HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT); 3170 reg_val |= (config->index_lookup_enable << 3171 HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT); 3172 reg_val |= (config->addrx_en << 3173 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT); 3174 reg_val |= (config->addry_en << 3175 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT); 3176 reg_val |= (config->mesh_enable << 3177 HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT); 3178 reg_val |= (config->vdev_id_check_en << 3179 HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT); 3180 reg_val |= (config->pmac_id << 3181 HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT); 3182 reg_val |= (config->mcast_pkt_ctrl << 3183 HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT); 3184 3185 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3186 } 3187 #else 3188 static inline void 3189 hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl, 3190 union hal_tx_bank_config *config, 3191 uint8_t bank_id) 3192 { 3193 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3194 uint32_t reg_addr, reg_val = 0; 3195 3196 reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE, 3197 bank_id); 3198 3199 reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT); 3200 reg_val |= (config->encap_type << 3201 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT); 3202 reg_val |= (config->encrypt_type << 3203 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT); 3204 reg_val |= (config->src_buffer_swap << 3205 HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT); 3206 reg_val |= (config->link_meta_swap << 3207 HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT); 3208 reg_val |= (config->index_lookup_enable << 3209 HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT); 3210 reg_val |= (config->addrx_en << 3211 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT); 3212 reg_val |= (config->addry_en << 3213 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT); 3214 reg_val |= (config->mesh_enable << 3215 HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT); 3216 reg_val |= (config->vdev_id_check_en << 3217 HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT); 3218 reg_val |= (config->pmac_id << 3219 HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT); 3220 reg_val |= (config->dscp_tid_map_id << 3221 HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT); 3222 3223 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3224 } 3225 #endif 3226 3227 3228 #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT 3229 3230 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4) 3231 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF) 3232 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3 3233 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2 3234 3235 /** 3236 * hal_tx_vdev_mcast_ctrl_set - set mcast_ctrl value 3237 * @hal_soc: HAL SoC context 3238 * @mcast_ctrl_val: mcast ctrl value for this VAP 3239 * 3240 * Return: void 3241 */ 3242 static inline void 3243 hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl, 3244 uint8_t vdev_id, uint8_t mcast_ctrl_val) 3245 { 3246 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3247 uint32_t reg_addr, reg_val = 0; 3248 uint32_t val; 3249 uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id); 3250 uint8_t index_in_reg = 3251 HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id); 3252 3253 reg_addr = 3254 HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE, 3255 reg_idx); 3256 3257 val = HAL_REG_READ(hal_soc, reg_addr); 3258 3259 /* mask out other stored value */ 3260 val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK << 3261 (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg))); 3262 3263 reg_val = val | 3264 ((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) << 3265 (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)); 3266 3267 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3268 } 3269 #else 3270 static inline void 3271 hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl, 3272 uint8_t vdev_id, uint8_t mcast_ctrl_val) 3273 { 3274 } 3275 #endif 3276 3277 #endif /* _HAL_BE_GENERIC_API_H_ */ 3278