1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_BE_GENERIC_API_H_ 21 #define _HAL_BE_GENERIC_API_H_ 22 23 #include <hal_be_hw_headers.h> 24 #include "hal_be_tx.h" 25 #include "hal_be_reo.h" 26 #include <hal_api_mon.h> 27 #include <hal_generic_api.h> 28 #include <hal_be_api_mon.h> 29 30 /** 31 * Debug macro to print the TLV header tag 32 */ 33 #define SHOW_DEFINED(x) do {} while (0) 34 35 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY) 36 static inline void 37 hal_tx_comp_get_buffer_timestamp_be(void *desc, 38 struct hal_tx_completion_status *ts) 39 { 40 ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 41 BUFFER_TIMESTAMP); 42 } 43 #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */ 44 static inline void 45 hal_tx_comp_get_buffer_timestamp_be(void *desc, 46 struct hal_tx_completion_status *ts) 47 { 48 } 49 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */ 50 51 /** 52 * hal_tx_comp_get_status() - TQM Release reason 53 * @hal_desc: completion ring Tx status 54 * 55 * This function will parse the WBM completion descriptor and populate in 56 * HAL structure 57 * 58 * Return: none 59 */ 60 static inline void 61 hal_tx_comp_get_status_generic_be(void *desc, void *ts1, 62 struct hal_soc *hal) 63 { 64 uint8_t rate_stats_valid = 0; 65 uint32_t rate_stats = 0; 66 struct hal_tx_completion_status *ts = 67 (struct hal_tx_completion_status *)ts1; 68 69 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 70 TQM_STATUS_NUMBER); 71 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 72 ACK_FRAME_RSSI); 73 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 74 FIRST_MSDU); 75 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 76 LAST_MSDU); 77 #if 0 78 // TODO - This has to be calculated form first and last msdu 79 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, 80 WBM2SW_COMPLETION_RING_TX, 81 MSDU_PART_OF_AMSDU); 82 #endif 83 84 ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 85 SW_PEER_ID); 86 ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID); 87 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 88 TRANSMIT_COUNT); 89 90 rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS); 91 92 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO, 93 TX_RATE_STATS_INFO_VALID, rate_stats); 94 95 ts->valid = rate_stats_valid; 96 97 if (rate_stats_valid) { 98 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW, 99 rate_stats); 100 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO, 101 TRANSMIT_PKT_TYPE, rate_stats); 102 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO, 103 TRANSMIT_STBC, rate_stats); 104 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC, 105 rate_stats); 106 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI, 107 rate_stats); 108 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS, 109 rate_stats); 110 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION, 111 rate_stats); 112 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU, 113 rate_stats); 114 } 115 116 ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc); 117 ts->status = hal_tx_comp_get_release_reason( 118 desc, 119 hal_soc_to_hal_soc_handle(hal)); 120 121 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 122 TX_RATE_STATS_INFO_TX_RATE_STATS); 123 hal_tx_comp_get_buffer_timestamp_be(desc, ts); 124 } 125 126 /** 127 * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table 128 * @soc: HAL SoC context 129 * @map: PCP-TID mapping table 130 * 131 * PCP are mapped to 8 TID values using TID values programmed 132 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 133 * The mapping register has TID mapping for 8 PCP values 134 * 135 * Return: none 136 */ 137 static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map) 138 { 139 uint32_t addr, value; 140 141 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 142 MAC_TCL_REG_REG_BASE); 143 144 value = (map[0] | 145 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 146 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 147 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 148 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 149 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 150 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 151 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 152 153 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 154 } 155 156 /** 157 * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with 158 * value received from user-space 159 * @soc: HAL SoC context 160 * @pcp: pcp value 161 * @tid : tid value 162 * 163 * Return: void 164 */ 165 static void 166 hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc, 167 uint8_t pcp, uint8_t tid) 168 { 169 uint32_t addr, value, regval; 170 171 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 172 MAC_TCL_REG_REG_BASE); 173 174 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 175 176 /* Read back previous PCP TID config and update 177 * with new config. 178 */ 179 regval = HAL_REG_READ(soc, addr); 180 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 181 regval |= value; 182 183 HAL_REG_WRITE(soc, addr, 184 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 185 } 186 187 /** 188 * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority 189 * @soc: HAL SoC context 190 * @val: priority value 191 * 192 * Return: void 193 */ 194 static 195 void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value) 196 { 197 uint32_t addr; 198 199 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 200 MAC_TCL_REG_REG_BASE); 201 202 HAL_REG_WRITE(soc, addr, 203 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 204 } 205 206 /** 207 * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size 208 * @rx_pkt_tlv_size: TLV size for regular RX packets 209 * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets 210 * 211 * Return: size of rx pkt tlv before the actual data 212 */ 213 static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size, 214 uint16_t *rx_mon_pkt_tlv_size) 215 { 216 *rx_pkt_tlv_size = RX_PKT_TLVS_LEN; 217 /* For now mon pkt tlv is same as rx pkt tlv */ 218 *rx_mon_pkt_tlv_size = MON_RX_PKT_TLVS_LEN; 219 } 220 221 /** 222 * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST 223 * @fst: Pointer to the Rx Flow Search Table 224 * @hal_hash: HAL 5 tuple hash 225 * @tuple_info: 5-tuple info of the flow returned to the caller 226 * 227 * Return: Success/Failure 228 */ 229 static void * 230 hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash, 231 uint8_t *flow_tuple_info) 232 { 233 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 234 void *hal_fse = NULL; 235 struct hal_flow_tuple_info *tuple_info 236 = (struct hal_flow_tuple_info *)flow_tuple_info; 237 238 hal_fse = (uint8_t *)fst->base_vaddr + 239 (hal_hash * HAL_RX_FST_ENTRY_SIZE); 240 241 if (!hal_fse || !tuple_info) 242 return NULL; 243 244 if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY, VALID)) 245 return NULL; 246 247 tuple_info->src_ip_127_96 = 248 qdf_ntohl(HAL_GET_FLD(hal_fse, 249 RX_FLOW_SEARCH_ENTRY, 250 SRC_IP_127_96)); 251 tuple_info->src_ip_95_64 = 252 qdf_ntohl(HAL_GET_FLD(hal_fse, 253 RX_FLOW_SEARCH_ENTRY, 254 SRC_IP_95_64)); 255 tuple_info->src_ip_63_32 = 256 qdf_ntohl(HAL_GET_FLD(hal_fse, 257 RX_FLOW_SEARCH_ENTRY, 258 SRC_IP_63_32)); 259 tuple_info->src_ip_31_0 = 260 qdf_ntohl(HAL_GET_FLD(hal_fse, 261 RX_FLOW_SEARCH_ENTRY, 262 SRC_IP_31_0)); 263 tuple_info->dest_ip_127_96 = 264 qdf_ntohl(HAL_GET_FLD(hal_fse, 265 RX_FLOW_SEARCH_ENTRY, 266 DEST_IP_127_96)); 267 tuple_info->dest_ip_95_64 = 268 qdf_ntohl(HAL_GET_FLD(hal_fse, 269 RX_FLOW_SEARCH_ENTRY, 270 DEST_IP_95_64)); 271 tuple_info->dest_ip_63_32 = 272 qdf_ntohl(HAL_GET_FLD(hal_fse, 273 RX_FLOW_SEARCH_ENTRY, 274 DEST_IP_63_32)); 275 tuple_info->dest_ip_31_0 = 276 qdf_ntohl(HAL_GET_FLD(hal_fse, 277 RX_FLOW_SEARCH_ENTRY, 278 DEST_IP_31_0)); 279 tuple_info->dest_port = HAL_GET_FLD(hal_fse, 280 RX_FLOW_SEARCH_ENTRY, 281 DEST_PORT); 282 tuple_info->src_port = HAL_GET_FLD(hal_fse, 283 RX_FLOW_SEARCH_ENTRY, 284 SRC_PORT); 285 tuple_info->l4_protocol = HAL_GET_FLD(hal_fse, 286 RX_FLOW_SEARCH_ENTRY, 287 L4_PROTOCOL); 288 289 return hal_fse; 290 } 291 292 /** 293 * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST 294 * @fst: Pointer to the Rx Flow Search Table 295 * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST 296 * 297 * Return: Success/Failure 298 */ 299 static QDF_STATUS 300 hal_rx_flow_delete_entry_be(uint8_t *rx_fst, void *hal_rx_fse) 301 { 302 uint8_t *fse = (uint8_t *)hal_rx_fse; 303 304 if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID)) 305 return QDF_STATUS_E_NOENT; 306 307 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 308 309 return QDF_STATUS_SUCCESS; 310 } 311 312 /** 313 * hal_rx_fst_get_fse_size_be() - Retrieve the size of each entry in Rx FST 314 * 315 * Return: size of each entry/flow in Rx FST 316 */ 317 static inline uint32_t 318 hal_rx_fst_get_fse_size_be(void) 319 { 320 return HAL_RX_FST_ENTRY_SIZE; 321 } 322 323 /* 324 * TX MONITOR 325 */ 326 327 #ifdef QCA_MONITOR_2_0_SUPPORT 328 /** 329 * hal_txmon_is_mon_buf_addr_tlv_generic_be() - api to find mon buffer tlv 330 * @tx_tlv: pointer to TLV header 331 * 332 * Return: bool based on tlv tag matches monitor buffer address tlv 333 */ 334 static inline bool 335 hal_txmon_is_mon_buf_addr_tlv_generic_be(void *tx_tlv_hdr) 336 { 337 uint32_t tlv_tag; 338 339 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr); 340 341 if (WIFIMON_BUFFER_ADDR_E == tlv_tag) 342 return true; 343 344 return false; 345 } 346 347 /** 348 * hal_txmon_populate_packet_info_generic_be() - api to populate packet info 349 * @tx_tlv: pointer to TLV header 350 * @packet_info: place holder for packet info 351 * 352 * Return: Address to void 353 */ 354 static inline void 355 hal_txmon_populate_packet_info_generic_be(void *tx_tlv, void *packet_info) 356 { 357 struct hal_mon_packet_info *pkt_info; 358 struct mon_buffer_addr *addr = (struct mon_buffer_addr *)tx_tlv; 359 360 pkt_info = (struct hal_mon_packet_info *)packet_info; 361 pkt_info->sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) | 362 (addr->buffer_virt_addr_31_0)); 363 pkt_info->dma_length = addr->dma_length + 1; 364 pkt_info->msdu_continuation = addr->msdu_continuation; 365 pkt_info->truncated = addr->truncated; 366 } 367 368 #if defined(TX_MONITOR_WORD_MASK) 369 /** 370 * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv 371 * 372 * @tx_tlv: pointer to tx_fes_setup tlv header 373 * 374 * Return: number of users 375 */ 376 static inline uint8_t 377 hal_txmon_get_num_users(void *tx_tlv) 378 { 379 hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv; 380 381 return tx_fes_setup->number_of_users; 382 } 383 384 /** 385 * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv 386 * 387 * @tx_tlv: pointer to tx_fes_setup tlv header 388 * @ppdu_info: pointer to hal_tx_ppdu_info 389 * 390 * Return: void 391 */ 392 static inline void 393 hal_txmon_parse_tx_fes_setup(void *tx_tlv, 394 struct hal_tx_ppdu_info *tx_ppdu_info) 395 { 396 hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv; 397 398 tx_ppdu_info->num_users = tx_fes_setup->number_of_users; 399 if (tx_ppdu_info->num_users == 0) 400 tx_ppdu_info->num_users = 1; 401 402 TXMON_HAL(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id; 403 TXMON_HAL_STATUS(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id; 404 } 405 406 /** 407 * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv 408 * 409 * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header 410 * @data_status_info: pointer to data hal_tx_status_info 411 * @prot_status_info: pointer to protection hal_tx_status_info 412 * 413 * Return: void 414 */ 415 static inline void 416 hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv, 417 struct hal_tx_status_info *data_status_info, 418 struct hal_tx_status_info *prot_status_info) 419 { 420 } 421 422 /** 423 * hal_txmon_parse_peer_entry() - parse peer entry tlv 424 * 425 * @tx_tlv: pointer to peer_entry tlv header 426 * @user_id: user_id 427 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 428 * @tx_status_info: pointer to hal_tx_status_info 429 * 430 * Return: void 431 */ 432 static inline void 433 hal_txmon_parse_peer_entry(void *tx_tlv, 434 uint8_t user_id, 435 struct hal_tx_ppdu_info *tx_ppdu_info, 436 struct hal_tx_status_info *tx_status_info) 437 { 438 } 439 440 /** 441 * hal_txmon_parse_queue_exten() - parse queue exten tlv 442 * 443 * @tx_tlv: pointer to queue exten tlv header 444 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 445 * 446 * Return: void 447 */ 448 static inline void 449 hal_txmon_parse_queue_exten(void *tx_tlv, 450 struct hal_tx_ppdu_info *tx_ppdu_info) 451 { 452 } 453 454 /** 455 * hal_txmon_parse_mpdu_start() - parse mpdu start tlv 456 * 457 * @tx_tlv: pointer to mpdu start tlv header 458 * @user_id: user id 459 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 460 * 461 * Return: void 462 */ 463 static inline void 464 hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id, 465 struct hal_tx_ppdu_info *tx_ppdu_info) 466 { 467 } 468 469 #else 470 /** 471 * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv 472 * 473 * @tx_tlv: pointer to tx_fes_setup tlv header 474 * 475 * Return: number of users 476 */ 477 static inline uint8_t 478 hal_txmon_get_num_users(void *tx_tlv) 479 { 480 uint8_t num_users = HAL_TX_DESC_GET_64(tx_tlv, 481 TX_FES_SETUP, NUMBER_OF_USERS); 482 483 return num_users; 484 } 485 486 /** 487 * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv 488 * 489 * @tx_tlv: pointer to tx_fes_setup tlv header 490 * @ppdu_info: pointer to hal_tx_ppdu_info 491 * 492 * Return: void 493 */ 494 static inline void 495 hal_txmon_parse_tx_fes_setup(void *tx_tlv, 496 struct hal_tx_ppdu_info *tx_ppdu_info) 497 { 498 uint32_t num_users = 0; 499 uint32_t ppdu_id = 0; 500 501 num_users = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_SETUP, NUMBER_OF_USERS); 502 ppdu_id = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_SETUP, SCHEDULE_ID); 503 504 if (num_users == 0) 505 num_users = 1; 506 507 tx_ppdu_info->num_users = num_users; 508 509 TXMON_HAL(tx_ppdu_info, ppdu_id) = ppdu_id; 510 TXMON_HAL_STATUS(tx_ppdu_info, ppdu_id) = ppdu_id; 511 } 512 513 /** 514 * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv 515 * 516 * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header 517 * @data_status_info: pointer to data hal_tx_status_info 518 * @prot_status_info: pointer to protection hal_tx_status_info 519 * 520 * Return: void 521 */ 522 static inline void 523 hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv, 524 struct hal_tx_status_info *data_status_info, 525 struct hal_tx_status_info *prot_status_info) 526 { 527 prot_status_info->protection_addr = 528 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 529 USE_ADDRESS_FIELDS_FOR_PROTECTION); 530 /* protection frame address 1 */ 531 *(uint32_t *)&prot_status_info->addr1[0] = 532 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 533 PROTECTION_FRAME_AD1_31_0); 534 *(uint32_t *)&prot_status_info->addr1[4] = 535 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 536 PROTECTION_FRAME_AD1_47_32); 537 /* protection frame address 2 */ 538 *(uint32_t *)&prot_status_info->addr2[0] = 539 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 540 PROTECTION_FRAME_AD2_15_0); 541 *(uint32_t *)&prot_status_info->addr2[2] = 542 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 543 PROTECTION_FRAME_AD2_47_16); 544 /* protection frame address 3 */ 545 *(uint32_t *)&prot_status_info->addr3[0] = 546 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 547 PROTECTION_FRAME_AD3_31_0); 548 *(uint32_t *)&prot_status_info->addr3[4] = 549 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 550 PROTECTION_FRAME_AD3_47_32); 551 /* protection frame address 4 */ 552 *(uint32_t *)&prot_status_info->addr4[0] = 553 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 554 PROTECTION_FRAME_AD4_15_0); 555 *(uint32_t *)&prot_status_info->addr4[2] = 556 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 557 PROTECTION_FRAME_AD4_47_16); 558 } 559 560 /** 561 * hal_txmon_parse_peer_entry() - parse peer entry tlv 562 * 563 * @tx_tlv: pointer to peer_entry tlv header 564 * @user_id: user_id 565 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 566 * @tx_status_info: pointer to hal_tx_status_info 567 * 568 * Return: void 569 */ 570 static inline void 571 hal_txmon_parse_peer_entry(void *tx_tlv, 572 uint8_t user_id, 573 struct hal_tx_ppdu_info *tx_ppdu_info, 574 struct hal_tx_status_info *tx_status_info) 575 { 576 *(uint32_t *)&tx_status_info->addr1[0] = 577 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_A_31_0); 578 *(uint32_t *)&tx_status_info->addr1[4] = 579 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_A_47_32); 580 *(uint32_t *)&tx_status_info->addr2[0] = 581 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_B_15_0); 582 *(uint32_t *)&tx_status_info->addr2[2] = 583 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_B_47_16); 584 TXMON_HAL_USER(tx_ppdu_info, user_id, sw_peer_id) = 585 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, SW_PEER_ID); 586 } 587 588 /** 589 * hal_txmon_parse_queue_exten() - parse queue exten tlv 590 * 591 * @tx_tlv: pointer to queue exten tlv header 592 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 593 * 594 * Return: void 595 */ 596 static inline void 597 hal_txmon_parse_queue_exten(void *tx_tlv, 598 struct hal_tx_ppdu_info *tx_ppdu_info) 599 { 600 TXMON_HAL_STATUS(tx_ppdu_info, frame_control) = 601 HAL_TX_DESC_GET_64(tx_tlv, TX_QUEUE_EXTENSION, 602 FRAME_CTL); 603 TXMON_HAL_STATUS(tx_ppdu_info, frame_control_info_valid) = true; 604 } 605 606 /** 607 * hal_txmon_parse_mpdu_start() - parse mpdu start tlv 608 * 609 * @tx_tlv: pointer to mpdu start tlv header 610 * @user_id: user id 611 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 612 * 613 * Return: void 614 */ 615 static inline void 616 hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id, 617 struct hal_tx_ppdu_info *tx_ppdu_info) 618 { 619 TXMON_HAL_USER(tx_ppdu_info, user_id, 620 start_seq) = HAL_TX_DESC_GET_64(tx_tlv, TX_MPDU_START, 621 MPDU_SEQUENCE_NUMBER); 622 TXMON_HAL(tx_ppdu_info, cur_usr_idx) = user_id; 623 } 624 #endif 625 626 /** 627 * get_ru_offset_from_start_index() - api to get ru offset from ru index 628 * 629 * @ru_size: RU size 630 * @start_idx: Start index 631 * 632 * Return: uint8_t ru allocation offset 633 */ 634 static inline 635 uint8_t get_ru_offset_from_start_index(uint8_t ru_size, uint8_t start_idx) 636 { 637 uint8_t ru_alloc_offset[HAL_MAX_DL_MU_USERS][HAL_MAX_RU_INDEX] = { 638 {0, 0, 0, 0, 0, 0, 0}, 639 {1, 0, 0, 0, 0, 0, 0}, 640 {2, 1, 0, 0, 0, 0, 0}, 641 {3, 1, 0, 0, 0, 0, 0}, 642 {4, 0, 0, 0, 0, 0, 0}, 643 {5, 2, 1, 0, 0, 0, 0}, 644 {6, 2, 1, 0, 0, 0, 0}, 645 {7, 3, 1, 0, 0, 0, 0}, 646 {8, 3, 1, 0, 0, 0, 0}, 647 {9, 4, 2, 1, 0, 0, 0}, 648 {10, 4, 2, 1, 0, 0, 0}, 649 {11, 5, 2, 1, 0, 0, 0}, 650 {12, 5, 2, 1, 0, 0, 0}, 651 {13, 0, 0, 1, 0, 0, 0}, 652 {14, 6, 3, 1, 0, 0, 0}, 653 {15, 6, 3, 1, 0, 0, 0}, 654 {16, 7, 3, 1, 0, 0, 0}, 655 {17, 7, 3, 1, 0, 0, 0}, 656 {18, 0, 0, 0, 0, 0, 0}, 657 {19, 8, 4, 2, 1, 0, 0}, 658 {20, 8, 4, 2, 1, 0, 0}, 659 {21, 9, 4, 2, 1, 0, 0}, 660 {22, 9, 4, 2, 1, 0, 0}, 661 {23, 0, 0, 2, 1, 0, 0}, 662 {24, 10, 5, 2, 1, 0, 0}, 663 {25, 10, 5, 2, 1, 0, 0}, 664 {26, 11, 5, 2, 1, 0, 0}, 665 {27, 11, 5, 2, 1, 0, 0}, 666 {28, 12, 6, 3, 1, 0, 0}, 667 {29, 12, 6, 3, 1, 0, 0}, 668 {30, 13, 6, 3, 1, 0, 0}, 669 {31, 13, 6, 3, 1, 0, 0}, 670 {32, 0, 0, 3, 1, 0, 0}, 671 {33, 14, 7, 3, 1, 0, 0}, 672 {34, 14, 7, 3, 1, 0, 0}, 673 {35, 15, 7, 3, 1, 0, 0}, 674 {36, 15, 7, 3, 1, 0, 0}, 675 }; 676 677 if (start_idx >= HAL_MAX_UL_MU_USERS || ru_size >= HAL_MAX_RU_INDEX) 678 return 0; 679 680 return ru_alloc_offset[start_idx][ru_size]; 681 } 682 683 /** 684 * hal_txmon_status_get_num_users_generic_be() - api to get num users 685 * from start of fes window 686 * 687 * @tx_tlv_hdr: pointer to TLV header 688 * @num_users: reference to number of user 689 * 690 * Return: status 691 */ 692 static inline uint32_t 693 hal_txmon_status_get_num_users_generic_be(void *tx_tlv_hdr, uint8_t *num_users) 694 { 695 uint32_t tlv_tag, user_id, tlv_len; 696 uint32_t tlv_status = HAL_MON_TX_STATUS_PPDU_NOT_DONE; 697 void *tx_tlv; 698 699 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr); 700 user_id = HAL_RX_GET_USER_TLV32_USERID(tx_tlv_hdr); 701 tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv_hdr); 702 703 tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 704 /* window starts with either initiator or response */ 705 switch (tlv_tag) { 706 case WIFITX_FES_SETUP_E: 707 { 708 *num_users = hal_txmon_get_num_users(tx_tlv); 709 if (*num_users == 0) 710 *num_users = 1; 711 712 tlv_status = HAL_MON_TX_FES_SETUP; 713 break; 714 } 715 case WIFIRX_RESPONSE_REQUIRED_INFO_E: 716 { 717 *num_users = HAL_TX_DESC_GET_64(tx_tlv, 718 RX_RESPONSE_REQUIRED_INFO, 719 RESPONSE_STA_COUNT); 720 if (*num_users == 0) 721 *num_users = 1; 722 tlv_status = HAL_MON_RX_RESPONSE_REQUIRED_INFO; 723 break; 724 } 725 }; 726 727 return tlv_status; 728 } 729 730 /** 731 * hal_tx_get_ppdu_info() - api to get tx ppdu info 732 * @pdev_handle: DP_PDEV handle 733 * @prot_ppdu_info: populate dp_ppdu_info protection 734 * @tx_data_ppdu_info: populate dp_ppdu_info data 735 * @tlv_tag: Tag 736 * 737 * Return: dp_tx_ppdu_info pointer 738 */ 739 static inline void * 740 hal_tx_get_ppdu_info(void *data_info, void *prot_info, uint32_t tlv_tag) 741 { 742 struct hal_tx_ppdu_info *prot_ppdu_info = prot_info; 743 744 switch (tlv_tag) { 745 case WIFITX_FES_SETUP_E:/* DOWNSTREAM */ 746 case WIFITX_FLUSH_E:/* DOWNSTREAM */ 747 case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */ 748 case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */ 749 case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */ 750 case WIFITX_MPDU_START_E:/* DOWNSTREAM */ 751 case WIFITX_MSDU_START_E:/* DOWNSTREAM */ 752 case WIFITX_DATA_E:/* DOWNSTREAM */ 753 case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */ 754 case WIFITX_MPDU_END_E:/* DOWNSTREAM */ 755 case WIFITX_MSDU_END_E:/* DOWNSTREAM */ 756 case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */ 757 case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */ 758 case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */ 759 case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */ 760 case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */ 761 case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */ 762 case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */ 763 case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */ 764 case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */ 765 case WIFITX_WUR_DATA_E:/* DOWNSTREAM */ 766 case WIFISCHEDULER_END_E:/* DOWNSTREAM */ 767 case WIFITX_FES_STATUS_START_PPDU_E:/* UPSTREAM */ 768 { 769 return data_info; 770 } 771 } 772 773 /* 774 * check current prot_tlv_status is start protection 775 * check current tlv_tag is either start protection or end protection 776 */ 777 if (TXMON_HAL(prot_ppdu_info, 778 prot_tlv_status) == WIFITX_FES_STATUS_START_PROT_E) { 779 return prot_info; 780 } else if (tlv_tag == WIFITX_FES_STATUS_PROT_E || 781 tlv_tag == WIFITX_FES_STATUS_START_PROT_E) { 782 TXMON_HAL(prot_ppdu_info, prot_tlv_status) = tlv_tag; 783 return prot_info; 784 } 785 786 return data_info; 787 } 788 789 /** 790 * hal_txmon_status_parse_tlv_generic_be() - api to parse status tlv. 791 * @data_ppdu_info: hal_txmon data ppdu info 792 * @prot_ppdu_info: hal_txmon prot ppdu info 793 * @data_status_info: pointer to data status info 794 * @prot_status_info: pointer to prot status info 795 * @tx_tlv_hdr: fragment of tx_tlv_hdr 796 * @status_frag: qdf_frag_t buffer 797 * 798 * Return: status 799 */ 800 static inline uint32_t 801 hal_txmon_status_parse_tlv_generic_be(void *data_ppdu_info, 802 void *prot_ppdu_info, 803 void *data_status_info, 804 void *prot_status_info, 805 void *tx_tlv_hdr, 806 qdf_frag_t status_frag) 807 { 808 struct hal_tx_ppdu_info *ppdu_info; 809 struct hal_tx_status_info *tx_status_info; 810 struct hal_mon_packet_info *packet_info = NULL; 811 uint32_t tlv_tag, user_id, tlv_len; 812 uint32_t status = HAL_MON_TX_STATUS_PPDU_NOT_DONE; 813 void *tx_tlv; 814 815 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr); 816 /* user_id start with 1, decrement by 1 to start from 0 */ 817 user_id = HAL_RX_GET_USER_TLV64_USERID(tx_tlv_hdr); 818 tlv_len = HAL_RX_GET_USER_TLV64_LEN(tx_tlv_hdr); 819 820 tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 821 822 /* parse tlv and populate tx_ppdu_info */ 823 ppdu_info = hal_tx_get_ppdu_info(data_ppdu_info, 824 prot_ppdu_info, tlv_tag); 825 tx_status_info = (ppdu_info->is_data ? data_status_info : 826 prot_status_info); 827 828 user_id = user_id > ppdu_info->num_users ? 0 : user_id; 829 830 switch (tlv_tag) { 831 /* start of initiator FES window */ 832 case WIFITX_FES_SETUP_E:/* DOWNSTREAM */ 833 { 834 /* initiator PPDU window start */ 835 hal_txmon_parse_tx_fes_setup(tx_tlv, ppdu_info); 836 837 status = HAL_MON_TX_FES_SETUP; 838 SHOW_DEFINED(WIFITX_FES_SETUP_E); 839 break; 840 } 841 /* end of initiator FES window */ 842 case WIFITX_FES_STATUS_END_E:/* UPSTREAM */ 843 { 844 /* initiator PPDU window end */ 845 uint32_t ppdu_timestamp_start = 0; 846 uint32_t ppdu_timestamp_end = 0; 847 uint16_t phy_abort_reason = 0; 848 uint8_t phy_abort_is_valid = 0; 849 uint8_t abort_usr_id = 0; 850 uint8_t response_type = 0; 851 uint8_t r2r_end_status_follow = 0; 852 853 status = HAL_MON_TX_FES_STATUS_END; 854 855 ppdu_timestamp_start = 856 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 857 START_OF_FRAME_TIMESTAMP_15_0) | 858 (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 859 START_OF_FRAME_TIMESTAMP_31_16) << 860 HAL_TX_LSB(TX_FES_STATUS_END, 861 START_OF_FRAME_TIMESTAMP_31_16)); 862 ppdu_timestamp_end = 863 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 864 END_OF_FRAME_TIMESTAMP_15_0) | 865 (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 866 END_OF_FRAME_TIMESTAMP_31_16) << 867 HAL_TX_LSB(TX_FES_STATUS_END, 868 END_OF_FRAME_TIMESTAMP_31_16)); 869 870 response_type = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 871 RESPONSE_TYPE); 872 /* 873 * r2r end status follow to inform whether to look for 874 * rx_response_required_info 875 */ 876 r2r_end_status_follow = 877 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 878 R2R_END_STATUS_TO_FOLLOW); 879 880 phy_abort_is_valid = 881 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 882 PHYTX_ABORT_REQUEST_INFO_VALID); 883 884 if (phy_abort_is_valid) { 885 phy_abort_reason = 886 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 887 PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON); 888 889 abort_usr_id = 890 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 891 PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER); 892 893 TXMON_STATUS_INFO(tx_status_info, 894 phy_abort_reason) = phy_abort_reason; 895 TXMON_STATUS_INFO(tx_status_info, 896 phy_abort_user_number) = abort_usr_id; 897 } 898 899 TXMON_STATUS_INFO(tx_status_info, 900 response_type) = response_type; 901 TXMON_STATUS_INFO(tx_status_info, 902 r2r_to_follow) = r2r_end_status_follow; 903 904 /* update phy timestamp to ppdu timestamp */ 905 TXMON_HAL_STATUS(ppdu_info, 906 ppdu_timestamp) = ppdu_timestamp_start; 907 908 SHOW_DEFINED(WIFITX_FES_STATUS_END_E); 909 break; 910 } 911 /* response window open */ 912 case WIFIRX_RESPONSE_REQUIRED_INFO_E:/* UPSTREAM */ 913 { 914 /* response PPDU window start */ 915 uint32_t ppdu_id = 0; 916 uint8_t reception_type = 0; 917 uint8_t response_sta_count = 0; 918 919 status = HAL_MON_RX_RESPONSE_REQUIRED_INFO; 920 921 ppdu_id = HAL_TX_DESC_GET_64(tx_tlv, 922 RX_RESPONSE_REQUIRED_INFO, 923 PHY_PPDU_ID); 924 reception_type = 925 HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO, 926 SU_OR_UPLINK_MU_RECEPTION); 927 response_sta_count = 928 HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO, 929 RESPONSE_STA_COUNT); 930 931 /* get mac address */ 932 *(uint32_t *)&tx_status_info->addr1[0] = 933 HAL_TX_DESC_GET_64(tx_tlv, 934 RX_RESPONSE_REQUIRED_INFO, 935 ADDR1_31_0); 936 *(uint32_t *)&tx_status_info->addr1[4] = 937 HAL_TX_DESC_GET_64(tx_tlv, 938 RX_RESPONSE_REQUIRED_INFO, 939 ADDR1_47_32); 940 *(uint32_t *)&tx_status_info->addr2[0] = 941 HAL_TX_DESC_GET_64(tx_tlv, 942 RX_RESPONSE_REQUIRED_INFO, 943 ADDR2_15_0); 944 *(uint32_t *)&tx_status_info->addr2[2] = 945 HAL_TX_DESC_GET_64(tx_tlv, 946 RX_RESPONSE_REQUIRED_INFO, 947 ADDR2_47_16); 948 949 TXMON_HAL(ppdu_info, ppdu_id) = ppdu_id; 950 TXMON_HAL_STATUS(ppdu_info, ppdu_id) = ppdu_id; 951 952 if (response_sta_count == 0) 953 response_sta_count = 1; 954 TXMON_HAL(ppdu_info, num_users) = response_sta_count; 955 956 if (reception_type) 957 TXMON_STATUS_INFO(tx_status_info, 958 transmission_type) = 959 TXMON_SU_TRANSMISSION; 960 else 961 TXMON_STATUS_INFO(tx_status_info, 962 transmission_type) = 963 TXMON_MU_TRANSMISSION; 964 965 SHOW_DEFINED(WIFIRX_RESPONSE_REQUIRED_INFO_E); 966 break; 967 } 968 /* Response window close */ 969 case WIFIRESPONSE_END_STATUS_E:/* UPSTREAM */ 970 { 971 /* response PPDU window end */ 972 uint8_t generated_response = 0; 973 uint32_t bandwidth = 0; 974 uint32_t ppdu_timestamp_start = 0; 975 uint32_t ppdu_timestamp_end = 0; 976 uint32_t mba_usr_cnt = 0; 977 uint32_t mba_fake_bitmap_cnt = 0; 978 979 status = HAL_MON_RESPONSE_END_STATUS_INFO; 980 generated_response = HAL_TX_DESC_GET_64(tx_tlv, 981 RESPONSE_END_STATUS, 982 GENERATED_RESPONSE); 983 mba_usr_cnt = HAL_TX_DESC_GET_64(tx_tlv, 984 RESPONSE_END_STATUS, 985 MBA_USER_COUNT); 986 mba_fake_bitmap_cnt = HAL_TX_DESC_GET_64(tx_tlv, 987 RESPONSE_END_STATUS, 988 MBA_FAKE_BITMAP_COUNT); 989 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 990 COEX_BASED_TX_BW); 991 /* 32 bits TSF */ 992 ppdu_timestamp_start = 993 (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 994 START_OF_FRAME_TIMESTAMP_15_0) | 995 (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 996 START_OF_FRAME_TIMESTAMP_31_16) << 997 16)); 998 ppdu_timestamp_end = 999 (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 1000 END_OF_FRAME_TIMESTAMP_15_0) | 1001 (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 1002 END_OF_FRAME_TIMESTAMP_31_16) << 1003 16)); 1004 1005 TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth; 1006 /* update phy timestamp to ppdu timestamp */ 1007 TXMON_HAL_STATUS(ppdu_info, 1008 ppdu_timestamp) = ppdu_timestamp_start; 1009 1010 TXMON_STATUS_INFO(tx_status_info, 1011 generated_response) = generated_response; 1012 TXMON_STATUS_INFO(tx_status_info, mba_count) = mba_usr_cnt; 1013 TXMON_STATUS_INFO(tx_status_info, 1014 mba_fake_bitmap_count) = mba_fake_bitmap_cnt; 1015 1016 SHOW_DEFINED(WIFIRESPONSE_END_STATUS_E); 1017 break; 1018 } 1019 case WIFITX_FLUSH_E:/* DOWNSTREAM */ 1020 { 1021 SHOW_DEFINED(WIFITX_FLUSH_E); 1022 break; 1023 } 1024 1025 /* Downstream tlv */ 1026 case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */ 1027 { 1028 hal_txmon_parse_pcu_ppdu_setup_init(tx_tlv, data_status_info, 1029 prot_status_info); 1030 1031 status = HAL_MON_TX_PCU_PPDU_SETUP_INIT; 1032 SHOW_DEFINED(WIFIPCU_PPDU_SETUP_INIT_E); 1033 break; 1034 } 1035 case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */ 1036 { 1037 hal_txmon_parse_peer_entry(tx_tlv, user_id, 1038 ppdu_info, tx_status_info); 1039 SHOW_DEFINED(WIFITX_PEER_ENTRY_E); 1040 break; 1041 } 1042 case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */ 1043 { 1044 status = HAL_MON_TX_QUEUE_EXTENSION; 1045 hal_txmon_parse_queue_exten(tx_tlv, ppdu_info); 1046 1047 SHOW_DEFINED(WIFITX_QUEUE_EXTENSION_E); 1048 break; 1049 } 1050 /* payload and data frame handling */ 1051 case WIFITX_MPDU_START_E:/* DOWNSTREAM */ 1052 { 1053 hal_txmon_parse_mpdu_start(tx_tlv, user_id, ppdu_info); 1054 1055 status = HAL_MON_TX_MPDU_START; 1056 SHOW_DEFINED(WIFITX_MPDU_START_E); 1057 break; 1058 } 1059 case WIFITX_MSDU_START_E:/* DOWNSTREAM */ 1060 { 1061 /* compacted */ 1062 /* we expect frame to be 802.11 frame type */ 1063 status = HAL_MON_TX_MSDU_START; 1064 SHOW_DEFINED(WIFITX_MSDU_START_E); 1065 break; 1066 } 1067 case WIFITX_DATA_E:/* DOWNSTREAM */ 1068 { 1069 status = HAL_MON_TX_DATA; 1070 /* 1071 * TODO: do we need a conversion api to convert 1072 * user_id from hw to get host user_index 1073 */ 1074 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1075 TXMON_STATUS_INFO(tx_status_info, 1076 buffer) = (void *)status_frag; 1077 TXMON_STATUS_INFO(tx_status_info, 1078 offset) = ((void *)tx_tlv - 1079 (void *)status_frag); 1080 TXMON_STATUS_INFO(tx_status_info, 1081 length) = tlv_len; 1082 1083 /* 1084 * reference of the status buffer will be held in 1085 * dp_tx_update_ppdu_info_status() 1086 */ 1087 status = HAL_MON_TX_DATA; 1088 SHOW_DEFINED(WIFITX_DATA_E); 1089 break; 1090 } 1091 case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */ 1092 { 1093 packet_info = &ppdu_info->packet_info; 1094 status = HAL_MON_TX_BUFFER_ADDR; 1095 /* 1096 * TODO: do we need a conversion api to convert 1097 * user_id from hw to get host user_index 1098 */ 1099 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1100 1101 hal_txmon_populate_packet_info_generic_be(tx_tlv, packet_info); 1102 1103 SHOW_DEFINED(WIFIMON_BUFFER_ADDR_E); 1104 break; 1105 } 1106 case WIFITX_MPDU_END_E:/* DOWNSTREAM */ 1107 { 1108 /* no tlv content */ 1109 SHOW_DEFINED(WIFITX_MPDU_END_E); 1110 break; 1111 } 1112 case WIFITX_MSDU_END_E:/* DOWNSTREAM */ 1113 { 1114 /* no tlv content */ 1115 SHOW_DEFINED(WIFITX_MSDU_END_E); 1116 break; 1117 } 1118 case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */ 1119 { 1120 /* no tlv content */ 1121 SHOW_DEFINED(WIFITX_LAST_MPDU_FETCHED_E); 1122 break; 1123 } 1124 case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */ 1125 { 1126 /* no tlv content */ 1127 SHOW_DEFINED(WIFITX_LAST_MPDU_END_E); 1128 break; 1129 } 1130 case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */ 1131 { 1132 /* 1133 * transmitting power 1134 * minimum transmitting power 1135 * desired nss 1136 * tx chain mask 1137 * desired bw 1138 * duration of transmit and response 1139 * 1140 * since most of the field we are deriving from other tlv 1141 * we don't need to enable this in our tlv. 1142 */ 1143 SHOW_DEFINED(WIFICOEX_TX_REQ_E); 1144 break; 1145 } 1146 case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */ 1147 { 1148 /* user tlv */ 1149 /* 1150 * All Tx monitor will have 802.11 hdr 1151 * we don't need to enable this TLV 1152 */ 1153 SHOW_DEFINED(WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E); 1154 break; 1155 } 1156 case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */ 1157 { 1158 /* 1159 * no tlv content 1160 * 1161 * TLV that indicates to TXPCU that preamble phase for the NDP 1162 * frame transmission is now over 1163 */ 1164 SHOW_DEFINED(WIFINDP_PREAMBLE_DONE_E); 1165 break; 1166 } 1167 case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */ 1168 { 1169 /* 1170 * no tlv content 1171 * 1172 * TLV indicates to the SCH that all timing critical TLV 1173 * has been passed on to the transmit path 1174 */ 1175 SHOW_DEFINED(WIFISCH_CRITICAL_TLV_REFERENCE_E); 1176 break; 1177 } 1178 case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */ 1179 { 1180 /* 1181 * Loopback specific setup info - not needed for Tx monitor 1182 */ 1183 SHOW_DEFINED(WIFITX_LOOPBACK_SETUP_E); 1184 break; 1185 } 1186 case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */ 1187 { 1188 /* 1189 * no tlv content 1190 * 1191 * TLV indicates that other modules besides the scheduler can 1192 * now also start generating TLV's 1193 * prevent colliding or generating TLV's out of order 1194 */ 1195 SHOW_DEFINED(WIFITX_FES_SETUP_COMPLETE_E); 1196 break; 1197 } 1198 case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */ 1199 { 1200 /* 1201 * no tlv content 1202 * 1203 * TLV indicates to SCH that a burst of MPDU info will 1204 * start to come in over the TLV 1205 */ 1206 SHOW_DEFINED(WIFITQM_MPDU_GLOBAL_START_E); 1207 break; 1208 } 1209 case WIFITX_WUR_DATA_E:/* DOWNSTREAM */ 1210 { 1211 SHOW_DEFINED(WIFITX_WUR_DATA_E); 1212 break; 1213 } 1214 case WIFISCHEDULER_END_E:/* DOWNSTREAM */ 1215 { 1216 /* 1217 * no tlv content 1218 * 1219 * TLV indicates END of all TLV's within the scheduler TLV 1220 */ 1221 SHOW_DEFINED(WIFISCHEDULER_END_E); 1222 break; 1223 } 1224 1225 /* Upstream tlv */ 1226 case WIFIPDG_TX_REQ_E: 1227 { 1228 SHOW_DEFINED(WIFIPDG_TX_REQ_E); 1229 break; 1230 } 1231 case WIFITX_FES_STATUS_START_E: 1232 { 1233 /* 1234 * TLV indicating that first transmission on the medium 1235 */ 1236 uint8_t medium_prot_type = 0; 1237 1238 status = HAL_MON_TX_FES_STATUS_START; 1239 1240 medium_prot_type = HAL_TX_DESC_GET_64(tx_tlv, 1241 TX_FES_STATUS_START, 1242 MEDIUM_PROT_TYPE); 1243 1244 ppdu_info = (struct hal_tx_ppdu_info *)prot_ppdu_info; 1245 /* update what type of medium protection frame */ 1246 TXMON_STATUS_INFO(tx_status_info, 1247 medium_prot_type) = medium_prot_type; 1248 SHOW_DEFINED(WIFITX_FES_STATUS_START_E); 1249 break; 1250 } 1251 case WIFITX_FES_STATUS_PROT_E: 1252 { 1253 uint32_t start_timestamp = 0; 1254 uint32_t end_timestamp = 0; 1255 1256 /* 1257 * generated by TXPCU to indicate the result of having 1258 * received of the expected protection frame 1259 */ 1260 1261 status = HAL_MON_TX_FES_STATUS_PROT; 1262 start_timestamp = 1263 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT, 1264 START_OF_FRAME_TIMESTAMP_15_0); 1265 start_timestamp |= 1266 (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT, 1267 START_OF_FRAME_TIMESTAMP_31_16) << 1268 15); 1269 end_timestamp = HAL_TX_DESC_GET_64(tx_tlv, 1270 TX_FES_STATUS_PROT, 1271 END_OF_FRAME_TIMESTAMP_15_0); 1272 end_timestamp |= 1273 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT, 1274 END_OF_FRAME_TIMESTAMP_31_16) << 15; 1275 1276 /* ppdu timestamp as phy timestamp */ 1277 TXMON_HAL_STATUS(ppdu_info, 1278 ppdu_timestamp) = start_timestamp; 1279 1280 SHOW_DEFINED(WIFITX_FES_STATUS_PROT_E); 1281 break; 1282 } 1283 case WIFITX_FES_STATUS_START_PROT_E: 1284 { 1285 uint64_t tsft_64; 1286 uint32_t response_type; 1287 status = HAL_MON_TX_FES_STATUS_START_PROT; 1288 TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag; 1289 /* timestamp */ 1290 tsft_64 = HAL_TX_DESC_GET_64(tx_tlv, 1291 TX_FES_STATUS_START_PROT, 1292 PROT_TIMESTAMP_LOWER_32); 1293 tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv, 1294 TX_FES_STATUS_START_PROT, 1295 PROT_TIMESTAMP_UPPER_32) << 32); 1296 1297 response_type = HAL_TX_DESC_GET_64(tx_tlv, 1298 TX_FES_STATUS_START_PROT, 1299 RESPONSE_TYPE); 1300 1301 TXMON_STATUS_INFO(tx_status_info, 1302 response_type) = response_type; 1303 TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64; 1304 1305 SHOW_DEFINED(WIFITX_FES_STATUS_START_PROT_E); 1306 break; 1307 } 1308 case WIFIPROT_TX_END_E: 1309 { 1310 /* 1311 * no tlv content 1312 * 1313 * generated by TXPCU the moment that protection frame 1314 * transmission has finished on the medium 1315 */ 1316 SHOW_DEFINED(WIFIPROT_TX_END_E); 1317 break; 1318 } 1319 case WIFITX_FES_STATUS_START_PPDU_E: 1320 { 1321 uint64_t tsft_64; 1322 uint8_t ndp_frame; 1323 1324 status = HAL_MON_TX_FES_STATUS_START_PPDU; 1325 tsft_64 = HAL_TX_DESC_GET_64(tx_tlv, 1326 TX_FES_STATUS_START_PPDU, 1327 PPDU_TIMESTAMP_LOWER_32); 1328 tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv, 1329 TX_FES_STATUS_START_PPDU, 1330 PPDU_TIMESTAMP_UPPER_32) << 32); 1331 1332 ndp_frame = HAL_TX_DESC_GET_64(tx_tlv, 1333 TX_FES_STATUS_START_PPDU, 1334 NDP_FRAME); 1335 1336 TXMON_STATUS_INFO(tx_status_info, ndp_frame) = ndp_frame; 1337 TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64; 1338 1339 SHOW_DEFINED(WIFITX_FES_STATUS_START_PPDU_E); 1340 break; 1341 } 1342 case WIFITX_FES_STATUS_USER_PPDU_E: 1343 { 1344 /* user tlv */ 1345 uint16_t duration; 1346 uint8_t transmitted_tid; 1347 1348 duration = HAL_TX_DESC_GET_64(tx_tlv, 1349 TX_FES_STATUS_USER_PPDU, 1350 DURATION); 1351 transmitted_tid = HAL_TX_DESC_GET_64(tx_tlv, 1352 TX_FES_STATUS_USER_PPDU, 1353 TRANSMITTED_TID); 1354 1355 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1356 TXMON_HAL_USER(ppdu_info, user_id, tid) = transmitted_tid; 1357 TXMON_HAL_USER(ppdu_info, user_id, duration) = duration; 1358 1359 status = HAL_MON_TX_FES_STATUS_USER_PPDU; 1360 SHOW_DEFINED(WIFITX_FES_STATUS_USER_PPDU_E); 1361 break; 1362 } 1363 case WIFIPPDU_TX_END_E: 1364 { 1365 /* 1366 * no tlv content 1367 * 1368 * generated by TXPCU the moment that PPDU transmission has 1369 * finished on the medium 1370 */ 1371 SHOW_DEFINED(WIFIPPDU_TX_END_E); 1372 break; 1373 } 1374 1375 case WIFITX_FES_STATUS_USER_RESPONSE_E: 1376 { 1377 /* 1378 * TLV contains the FES transmit result of the each 1379 * of the MAC users. TLV are forwarded to HWSCH 1380 */ 1381 SHOW_DEFINED(WIFITX_FES_STATUS_USER_RESPONSE_E); 1382 break; 1383 } 1384 case WIFITX_FES_STATUS_ACK_OR_BA_E: 1385 { 1386 /* user tlv */ 1387 /* 1388 * TLV generated by RXPCU and provide information related to 1389 * the received BA or ACK frame 1390 */ 1391 SHOW_DEFINED(WIFITX_FES_STATUS_ACK_OR_BA_E); 1392 break; 1393 } 1394 case WIFITX_FES_STATUS_1K_BA_E: 1395 { 1396 /* user tlv */ 1397 /* 1398 * TLV generated by RXPCU and providing information related 1399 * to the received BA frame in case of 512/1024 bitmaps 1400 */ 1401 SHOW_DEFINED(WIFITX_FES_STATUS_1K_BA_E); 1402 break; 1403 } 1404 case WIFIRECEIVED_RESPONSE_USER_7_0_E: 1405 { 1406 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_7_0_E); 1407 break; 1408 } 1409 case WIFIRECEIVED_RESPONSE_USER_15_8_E: 1410 { 1411 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_15_8_E); 1412 break; 1413 } 1414 case WIFIRECEIVED_RESPONSE_USER_23_16_E: 1415 { 1416 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_23_16_E); 1417 break; 1418 } 1419 case WIFIRECEIVED_RESPONSE_USER_31_24_E: 1420 { 1421 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_31_24_E); 1422 break; 1423 } 1424 case WIFIRECEIVED_RESPONSE_USER_36_32_E: 1425 { 1426 /* 1427 * RXPCU generates this TLV when it receives a response frame 1428 * that TXPCU pre-announced it was waiting for and in 1429 * RXPCU_SETUP TLV, TLV generated before the 1430 * RECEIVED_RESPONSE_INFO TLV. 1431 * 1432 * received info user fields are there which is not needed 1433 * for TX monitor 1434 */ 1435 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_36_32_E); 1436 break; 1437 } 1438 1439 case WIFITXPCU_BUFFER_STATUS_E: 1440 { 1441 SHOW_DEFINED(WIFITXPCU_BUFFER_STATUS_E); 1442 break; 1443 } 1444 case WIFITXPCU_USER_BUFFER_STATUS_E: 1445 { 1446 /* 1447 * WIFITXPCU_USER_BUFFER_STATUS_E - user tlv 1448 * for TX monitor we aren't interested in this tlv 1449 */ 1450 SHOW_DEFINED(WIFITXPCU_USER_BUFFER_STATUS_E); 1451 break; 1452 } 1453 case WIFITXDMA_STOP_REQUEST_E: 1454 { 1455 /* 1456 * no tlv content 1457 * 1458 * TLV is destined to TXDMA and informs TXDMA to stop 1459 * pushing data into the transmit path. 1460 */ 1461 SHOW_DEFINED(WIFITXDMA_STOP_REQUEST_E); 1462 break; 1463 } 1464 case WIFITX_CBF_INFO_E: 1465 { 1466 /* 1467 * After NDPA + NDP is received, RXPCU sends the TX_CBF_INFO to 1468 * TXPCU to respond the CBF frame 1469 * 1470 * compressed beamforming pkt doesn't has mac header 1471 * Tx monitor not interested in this pkt. 1472 */ 1473 SHOW_DEFINED(WIFITX_CBF_INFO_E); 1474 break; 1475 } 1476 case WIFITX_MPDU_COUNT_TRANSFER_END_E: 1477 { 1478 /* 1479 * no tlv content 1480 * 1481 * TLV indicates that TXPCU has finished generating the 1482 * TQM_UPDATE_TX_MPDU_COUNT TLV for all users 1483 */ 1484 SHOW_DEFINED(WIFITX_MPDU_COUNT_TRANSFER_END_E); 1485 break; 1486 } 1487 case WIFIPDG_RESPONSE_E: 1488 { 1489 /* 1490 * most of the feilds are already covered in 1491 * other TLV 1492 * This is generated by TX_PCU to PDG to calculate 1493 * all the PHY header info. 1494 * 1495 * some useful fields like min transmit power, 1496 * rate used for transmitting packet is present. 1497 */ 1498 SHOW_DEFINED(WIFIPDG_RESPONSE_E); 1499 break; 1500 } 1501 case WIFIPDG_TRIG_RESPONSE_E: 1502 { 1503 /* no tlv content */ 1504 SHOW_DEFINED(WIFIPDG_TRIG_RESPONSE_E); 1505 break; 1506 } 1507 case WIFIRECEIVED_TRIGGER_INFO_E: 1508 { 1509 /* 1510 * TLV generated by RXPCU to inform the scheduler that 1511 * a trigger frame has been received 1512 */ 1513 SHOW_DEFINED(WIFIRECEIVED_TRIGGER_INFO_E); 1514 break; 1515 } 1516 case WIFIOFDMA_TRIGGER_DETAILS_E: 1517 { 1518 SHOW_DEFINED(WIFIOFDMA_TRIGGER_DETAILS_E); 1519 break; 1520 } 1521 case WIFIRX_FRAME_BITMAP_ACK_E: 1522 { 1523 /* user tlv */ 1524 status = HAL_MON_RX_FRAME_BITMAP_ACK; 1525 SHOW_DEFINED(WIFIRX_FRAME_BITMAP_ACK_E); 1526 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1527 TXMON_STATUS_INFO(tx_status_info, no_bitmap_avail) = 1528 HAL_TX_DESC_GET_64(tx_tlv, 1529 RX_FRAME_BITMAP_ACK, 1530 NO_BITMAP_AVAILABLE); 1531 1532 TXMON_STATUS_INFO(tx_status_info, explicit_ack) = 1533 HAL_TX_DESC_GET_64(tx_tlv, 1534 RX_FRAME_BITMAP_ACK, 1535 EXPLICIT_ACK); 1536 /* 1537 * get mac address, since address is received frame 1538 * change the order and store it 1539 */ 1540 *(uint32_t *)&tx_status_info->addr2[0] = 1541 HAL_TX_DESC_GET_64(tx_tlv, 1542 RX_FRAME_BITMAP_ACK, 1543 ADDR1_31_0); 1544 *(uint32_t *)&tx_status_info->addr2[4] = 1545 HAL_TX_DESC_GET_64(tx_tlv, 1546 RX_FRAME_BITMAP_ACK, 1547 ADDR1_47_32); 1548 *(uint32_t *)&tx_status_info->addr1[0] = 1549 HAL_TX_DESC_GET_64(tx_tlv, 1550 RX_FRAME_BITMAP_ACK, 1551 ADDR2_15_0); 1552 *(uint32_t *)&tx_status_info->addr1[2] = 1553 HAL_TX_DESC_GET_64(tx_tlv, 1554 RX_FRAME_BITMAP_ACK, 1555 ADDR2_47_16); 1556 1557 TXMON_STATUS_INFO(tx_status_info, explicit_ack_type) = 1558 HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_BITMAP_ACK, 1559 EXPLICT_ACK_TYPE); 1560 1561 TXMON_HAL_USER(ppdu_info, user_id, tid) = 1562 HAL_TX_DESC_GET_64(tx_tlv, 1563 RX_FRAME_BITMAP_ACK, 1564 BA_TID); 1565 TXMON_HAL_USER(ppdu_info, user_id, aid) = 1566 HAL_TX_DESC_GET_64(tx_tlv, 1567 RX_FRAME_BITMAP_ACK, 1568 STA_FULL_AID); 1569 TXMON_HAL_USER(ppdu_info, user_id, start_seq) = 1570 HAL_TX_DESC_GET_64(tx_tlv, 1571 RX_FRAME_BITMAP_ACK, 1572 BA_TS_SEQ); 1573 TXMON_HAL_USER(ppdu_info, user_id, ba_control) = 1574 HAL_TX_DESC_GET_64(tx_tlv, 1575 RX_FRAME_BITMAP_ACK, 1576 BA_TS_CTRL); 1577 TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) = 1578 HAL_TX_DESC_GET_64(tx_tlv, 1579 RX_FRAME_BITMAP_ACK, 1580 BA_BITMAP_SIZE); 1581 1582 /* ba bitmap */ 1583 qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap), 1584 &HAL_SET_FLD_OFFSET_64(tx_tlv, 1585 RX_FRAME_BITMAP_ACK, 1586 BA_TS_BITMAP_31_0, 0), 32); 1587 1588 break; 1589 } 1590 case WIFIRX_FRAME_1K_BITMAP_ACK_E: 1591 { 1592 /* user tlv */ 1593 status = HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K; 1594 SHOW_DEFINED(WIFIRX_FRAME_1K_BITMAP_ACK_E); 1595 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1596 TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) = 1597 (4 + HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_1K_BITMAP_ACK, 1598 BA_BITMAP_SIZE)); 1599 TXMON_HAL_USER(ppdu_info, user_id, tid) = 1600 HAL_TX_DESC_GET_64(tx_tlv, 1601 RX_FRAME_1K_BITMAP_ACK, 1602 BA_TID); 1603 TXMON_HAL_USER(ppdu_info, user_id, aid) = 1604 HAL_TX_DESC_GET_64(tx_tlv, 1605 RX_FRAME_1K_BITMAP_ACK, 1606 STA_FULL_AID); 1607 /* get mac address */ 1608 *(uint32_t *)&tx_status_info->addr1[0] = 1609 HAL_TX_DESC_GET_64(tx_tlv, 1610 RX_FRAME_1K_BITMAP_ACK, 1611 ADDR1_31_0); 1612 *(uint32_t *)&tx_status_info->addr1[4] = 1613 HAL_TX_DESC_GET_64(tx_tlv, 1614 RX_FRAME_1K_BITMAP_ACK, 1615 ADDR1_47_32); 1616 *(uint32_t *)&tx_status_info->addr2[0] = 1617 HAL_TX_DESC_GET_64(tx_tlv, 1618 RX_FRAME_1K_BITMAP_ACK, 1619 ADDR2_15_0); 1620 *(uint32_t *)&tx_status_info->addr2[2] = 1621 HAL_TX_DESC_GET_64(tx_tlv, 1622 RX_FRAME_1K_BITMAP_ACK, 1623 ADDR2_47_16); 1624 1625 TXMON_HAL_USER(ppdu_info, user_id, start_seq) = 1626 HAL_TX_DESC_GET_64(tx_tlv, 1627 RX_FRAME_1K_BITMAP_ACK, 1628 BA_TS_SEQ); 1629 TXMON_HAL_USER(ppdu_info, user_id, ba_control) = 1630 HAL_TX_DESC_GET_64(tx_tlv, 1631 RX_FRAME_1K_BITMAP_ACK, 1632 BA_TS_CTRL); 1633 /* memcpy ba bitmap */ 1634 qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap), 1635 &HAL_SET_FLD_OFFSET_64(tx_tlv, 1636 RX_FRAME_1K_BITMAP_ACK, 1637 BA_TS_BITMAP_31_0, 0), 1638 4 << TXMON_HAL_USER(ppdu_info, 1639 user_id, ba_bitmap_sz)); 1640 1641 break; 1642 } 1643 case WIFIRESPONSE_START_STATUS_E: 1644 { 1645 /* 1646 * TLV indicates which HW response the TXPCU 1647 * started generating 1648 * 1649 * HW generated frames like 1650 * ACK frame - handled 1651 * CTS frame - handled 1652 * BA frame - handled 1653 * MBA frame - handled 1654 * CBF frame - no frame header 1655 * Trigger response - TODO 1656 * NDP LMR - no frame header 1657 */ 1658 SHOW_DEFINED(WIFIRESPONSE_START_STATUS_E); 1659 break; 1660 } 1661 case WIFIRX_START_PARAM_E: 1662 { 1663 /* 1664 * RXPCU send this TLV after PHY RX detected a frame 1665 * in the medium 1666 * 1667 * TX monitor not interested in this TLV 1668 */ 1669 SHOW_DEFINED(WIFIRX_START_PARAM_E); 1670 break; 1671 } 1672 case WIFIRXPCU_EARLY_RX_INDICATION_E: 1673 { 1674 /* 1675 * early indication of pkt type and mcs rate 1676 * already captured in other tlv 1677 */ 1678 SHOW_DEFINED(WIFIRXPCU_EARLY_RX_INDICATION_E); 1679 break; 1680 } 1681 case WIFIRX_PM_INFO_E: 1682 { 1683 SHOW_DEFINED(WIFIRX_PM_INFO_E); 1684 break; 1685 } 1686 1687 /* Active window */ 1688 case WIFITX_FLUSH_REQ_E: 1689 { 1690 SHOW_DEFINED(WIFITX_FLUSH_REQ_E); 1691 break; 1692 } 1693 case WIFICOEX_TX_STATUS_E: 1694 { 1695 /* duration are retrieved from coex tx status */ 1696 uint16_t duration; 1697 uint8_t status_reason; 1698 1699 status = HAL_MON_COEX_TX_STATUS; 1700 duration = HAL_TX_DESC_GET_64(tx_tlv, 1701 COEX_TX_STATUS, 1702 CURRENT_TX_DURATION); 1703 status_reason = HAL_TX_DESC_GET_64(tx_tlv, 1704 COEX_TX_STATUS, 1705 TX_STATUS_REASON); 1706 1707 /* update duration */ 1708 if (status_reason == COEX_FES_TX_START || 1709 status_reason == COEX_RESPONSE_TX_START) 1710 TXMON_HAL_USER(ppdu_info, user_id, duration) = duration; 1711 1712 SHOW_DEFINED(WIFICOEX_TX_STATUS_E); 1713 break; 1714 } 1715 case WIFIR2R_STATUS_END_E: 1716 { 1717 SHOW_DEFINED(WIFIR2R_STATUS_END_E); 1718 break; 1719 } 1720 case WIFIRX_PREAMBLE_E: 1721 { 1722 SHOW_DEFINED(WIFIRX_PREAMBLE_E); 1723 break; 1724 } 1725 case WIFIMACTX_SERVICE_E: 1726 { 1727 SHOW_DEFINED(WIFIMACTX_SERVICE_E); 1728 break; 1729 } 1730 1731 case WIFIMACTX_U_SIG_EHT_SU_MU_E: 1732 { 1733 SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_SU_MU_E); 1734 break; 1735 } 1736 case WIFIMACTX_U_SIG_EHT_TB_E: 1737 { 1738 /* TODO: no radiotap info available */ 1739 SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_TB_E); 1740 break; 1741 } 1742 case WIFIMACTX_EHT_SIG_USR_OFDMA_E: 1743 { 1744 SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_OFDMA_E); 1745 break; 1746 } 1747 case WIFIMACTX_EHT_SIG_USR_MU_MIMO_E: 1748 { 1749 SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_MU_MIMO_E); 1750 break; 1751 } 1752 case WIFIMACTX_EHT_SIG_USR_SU_E: 1753 { 1754 SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_SU_E); 1755 /* TODO: no radiotap info available */ 1756 break; 1757 } 1758 1759 case WIFIMACTX_HE_SIG_A_SU_E: 1760 { 1761 uint16_t he_mu_flag_1 = 0; 1762 uint16_t he_mu_flag_2 = 0; 1763 uint16_t num_users = 0; 1764 uint8_t mcs_of_sig_b = 0; 1765 uint8_t dcm_of_sig_b = 0; 1766 uint8_t sig_a_bw = 0; 1767 uint8_t i = 0; 1768 uint8_t bss_color_id; 1769 uint8_t coding; 1770 uint8_t stbc; 1771 uint8_t a_factor; 1772 uint8_t pe_disambiguity; 1773 uint8_t txbf; 1774 uint8_t txbw; 1775 uint8_t txop; 1776 1777 status = HAL_MON_MACTX_HE_SIG_A_SU; 1778 num_users = TXMON_HAL(ppdu_info, num_users); 1779 1780 mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1781 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1782 TRANSMIT_MCS); 1783 dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1784 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1785 DCM); 1786 sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv, 1787 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1788 TRANSMIT_BW); 1789 1790 bss_color_id = HAL_TX_DESC_GET_64(tx_tlv, 1791 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1792 BSS_COLOR_ID); 1793 coding = HAL_TX_DESC_GET_64(tx_tlv, 1794 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1795 CODING); 1796 stbc = HAL_TX_DESC_GET_64(tx_tlv, 1797 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1798 STBC); 1799 a_factor = HAL_TX_DESC_GET_64(tx_tlv, 1800 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1801 PACKET_EXTENSION_A_FACTOR); 1802 pe_disambiguity = HAL_TX_DESC_GET_64(tx_tlv, 1803 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1804 PACKET_EXTENSION_PE_DISAMBIGUITY); 1805 txbf = HAL_TX_DESC_GET_64(tx_tlv, 1806 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1807 TXBF); 1808 txbw = HAL_TX_DESC_GET_64(tx_tlv, 1809 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1810 TRANSMIT_BW); 1811 txop = HAL_TX_DESC_GET_64(tx_tlv, 1812 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1813 TXOP_DURATION); 1814 1815 he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1816 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1817 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN | 1818 QDF_MON_STATUS_CHANNEL_1_RU_KNOWN | 1819 QDF_MON_STATUS_CHANNEL_2_RU_KNOWN | 1820 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN; 1821 1822 /* MCS */ 1823 he_mu_flag_1 |= mcs_of_sig_b << 1824 QDF_MON_STATUS_SIG_B_MCS_SHIFT; 1825 /* DCM */ 1826 he_mu_flag_1 |= dcm_of_sig_b << 1827 QDF_MON_STATUS_SIG_B_DCM_SHIFT; 1828 /* bandwidth */ 1829 he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN; 1830 he_mu_flag_2 |= sig_a_bw << 1831 QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT; 1832 1833 TXMON_HAL_STATUS(ppdu_info, 1834 he_mu_flags) = IS_MULTI_USERS(num_users); 1835 for (i = 0; i < num_users; i++) { 1836 TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1; 1837 TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2; 1838 } 1839 1840 /* HE data 1 */ 1841 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 1842 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1843 QDF_MON_STATUS_HE_CODING_KNOWN; 1844 1845 /* HE data 2 */ 1846 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= 1847 QDF_MON_STATUS_TXBF_KNOWN | 1848 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1849 QDF_MON_STATUS_TXOP_KNOWN | 1850 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1851 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1852 1853 /* HE data 3 */ 1854 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 1855 bss_color_id | 1856 (!!txbf << QDF_MON_STATUS_BEAM_CHANGE_SHIFT) | 1857 (coding << QDF_MON_STATUS_CODING_SHIFT) | 1858 (stbc << QDF_MON_STATUS_STBC_SHIFT); 1859 1860 /* HE data 6 */ 1861 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= 1862 (txop << QDF_MON_STATUS_TXOP_SHIFT); 1863 1864 SHOW_DEFINED(WIFIMACTX_HE_SIG_A_SU_E); 1865 break; 1866 } 1867 case WIFIMACTX_HE_SIG_A_MU_DL_E: 1868 { 1869 uint16_t he_mu_flag_1 = 0; 1870 uint16_t he_mu_flag_2 = 0; 1871 uint16_t num_users = 0; 1872 uint8_t bss_color_id; 1873 uint8_t txop; 1874 uint8_t mcs_of_sig_b = 0; 1875 uint8_t dcm_of_sig_b = 0; 1876 uint8_t sig_a_bw = 0; 1877 uint8_t num_sig_b_symb = 0; 1878 uint8_t comp_mode_sig_b = 0; 1879 uint8_t punc_bw = 0; 1880 uint8_t i = 0; 1881 1882 status = HAL_MON_MACTX_HE_SIG_A_MU_DL; 1883 num_users = TXMON_HAL(ppdu_info, num_users); 1884 1885 mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1886 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1887 MCS_OF_SIG_B); 1888 dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1889 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1890 DCM_OF_SIG_B); 1891 sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv, 1892 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1893 TRANSMIT_BW); 1894 num_sig_b_symb = HAL_TX_DESC_GET_64(tx_tlv, 1895 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1896 NUM_SIG_B_SYMBOLS); 1897 comp_mode_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1898 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1899 COMP_MODE_SIG_B); 1900 bss_color_id = HAL_TX_DESC_GET_64(tx_tlv, 1901 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1902 BSS_COLOR_ID); 1903 txop = HAL_TX_DESC_GET_64(tx_tlv, 1904 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1905 TXOP_DURATION); 1906 1907 he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1908 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1909 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1910 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN | 1911 QDF_MON_STATUS_CHANNEL_1_RU_KNOWN | 1912 QDF_MON_STATUS_CHANNEL_2_RU_KNOWN | 1913 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN | 1914 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1915 QDF_MON_STATUS_SIG_B_SYMBOL_USER_KNOWN; 1916 1917 /* MCS */ 1918 he_mu_flag_1 |= mcs_of_sig_b << 1919 QDF_MON_STATUS_SIG_B_MCS_SHIFT; 1920 /* DCM */ 1921 he_mu_flag_1 |= dcm_of_sig_b << 1922 QDF_MON_STATUS_SIG_B_DCM_SHIFT; 1923 /* Compression */ 1924 he_mu_flag_2 |= comp_mode_sig_b << 1925 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1926 /* bandwidth */ 1927 he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN; 1928 he_mu_flag_2 |= sig_a_bw << 1929 QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT; 1930 he_mu_flag_2 |= comp_mode_sig_b << 1931 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1932 /* number of symbol */ 1933 he_mu_flag_2 |= num_sig_b_symb << 1934 QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1935 /* puncture bw */ 1936 he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_KNOWN; 1937 punc_bw = sig_a_bw; 1938 he_mu_flag_2 |= 1939 punc_bw << QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_SHIFT; 1940 1941 /* copy per user info to all user */ 1942 TXMON_HAL_STATUS(ppdu_info, 1943 he_mu_flags) = IS_MULTI_USERS(num_users); 1944 for (i = 0; i < num_users; i++) { 1945 TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1; 1946 TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2; 1947 } 1948 1949 /* HE data 1 */ 1950 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 1951 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN; 1952 1953 /* HE data 2 */ 1954 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= 1955 QDF_MON_STATUS_TXOP_KNOWN; 1956 1957 /* HE data 3 */ 1958 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= bss_color_id; 1959 1960 /* HE data 6 */ 1961 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= 1962 (txop << QDF_MON_STATUS_TXOP_SHIFT); 1963 1964 SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_DL_E); 1965 break; 1966 } 1967 case WIFIMACTX_HE_SIG_A_MU_UL_E: 1968 { 1969 SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_UL_E); 1970 break; 1971 } 1972 case WIFIMACTX_HE_SIG_B1_MU_E: 1973 { 1974 status = HAL_MON_MACTX_HE_SIG_B1_MU; 1975 SHOW_DEFINED(WIFIMACTX_HE_SIG_B1_MU_E); 1976 break; 1977 } 1978 case WIFIMACTX_HE_SIG_B2_MU_E: 1979 { 1980 /* user tlv */ 1981 uint16_t sta_id = 0; 1982 uint16_t sta_spatial_config = 0; 1983 uint8_t sta_mcs = 0; 1984 uint8_t coding = 0; 1985 uint8_t nss = 0; 1986 uint8_t user_order = 0; 1987 1988 status = HAL_MON_MACTX_HE_SIG_B2_MU; 1989 1990 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1991 1992 sta_id = HAL_TX_DESC_GET_64(tx_tlv, 1993 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 1994 STA_ID); 1995 sta_spatial_config = HAL_TX_DESC_GET_64(tx_tlv, 1996 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 1997 STA_SPATIAL_CONFIG); 1998 sta_mcs = HAL_TX_DESC_GET_64(tx_tlv, 1999 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2000 STA_MCS); 2001 coding = HAL_TX_DESC_GET_64(tx_tlv, 2002 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2003 STA_CODING); 2004 nss = HAL_TX_DESC_GET_64(tx_tlv, 2005 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2006 NSTS) + 1; 2007 user_order = HAL_TX_DESC_GET_64(tx_tlv, 2008 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2009 USER_ORDER); 2010 2011 /* HE data 1 */ 2012 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 2013 QDF_MON_STATUS_HE_MCS_KNOWN | 2014 QDF_MON_STATUS_HE_CODING_KNOWN; 2015 /* HE data 2 */ 2016 2017 /* HE data 3 */ 2018 TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs; 2019 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2020 sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2021 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2022 coding << QDF_MON_STATUS_CODING_SHIFT; 2023 2024 /* HE data 4 */ 2025 TXMON_HAL_USER(ppdu_info, user_id, he_data4) |= 2026 sta_id << QDF_MON_STATUS_STA_ID_SHIFT; 2027 2028 /* HE data 5 */ 2029 2030 /* HE data 6 */ 2031 TXMON_HAL_USER(ppdu_info, user_id, nss) = nss; 2032 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss; 2033 2034 SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_MU_E); 2035 break; 2036 } 2037 case WIFIMACTX_HE_SIG_B2_OFDMA_E: 2038 { 2039 /* user tlv */ 2040 uint8_t *he_sig_b2_ofdma_info = NULL; 2041 uint16_t sta_id = 0; 2042 uint8_t nss = 0; 2043 uint8_t txbf = 0; 2044 uint8_t sta_mcs = 0; 2045 uint8_t sta_dcm = 0; 2046 uint8_t coding = 0; 2047 uint8_t user_order = 0; 2048 2049 status = HAL_MON_MACTX_HE_SIG_B2_OFDMA; 2050 2051 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 2052 2053 he_sig_b2_ofdma_info = (uint8_t *)tx_tlv + 2054 HAL_OFFSET(MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2055 STA_ID); 2056 2057 sta_id = HAL_TX_DESC_GET_64(tx_tlv, 2058 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2059 STA_ID); 2060 nss = HAL_TX_DESC_GET_64(tx_tlv, 2061 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2062 NSTS); 2063 txbf = HAL_TX_DESC_GET_64(tx_tlv, 2064 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2065 TXBF); 2066 sta_mcs = HAL_TX_DESC_GET_64(tx_tlv, 2067 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2068 STA_MCS); 2069 sta_dcm = HAL_TX_DESC_GET_64(tx_tlv, 2070 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2071 STA_DCM); 2072 coding = HAL_TX_DESC_GET_64(tx_tlv, 2073 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2074 STA_CODING); 2075 user_order = HAL_TX_DESC_GET_64(tx_tlv, 2076 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2077 USER_ORDER); 2078 2079 /* HE data 1 */ 2080 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 2081 QDF_MON_STATUS_HE_MCS_KNOWN | 2082 QDF_MON_STATUS_HE_CODING_KNOWN | 2083 QDF_MON_STATUS_HE_DCM_KNOWN; 2084 /* HE data 2 */ 2085 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= 2086 QDF_MON_STATUS_TXBF_KNOWN; 2087 2088 /* HE data 3 */ 2089 TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs; 2090 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2091 sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2092 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2093 sta_dcm << QDF_MON_STATUS_DCM_SHIFT; 2094 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2095 coding << QDF_MON_STATUS_CODING_SHIFT; 2096 2097 /* HE data 4 */ 2098 TXMON_HAL_USER(ppdu_info, user_id, he_data4) |= 2099 sta_id << QDF_MON_STATUS_STA_ID_SHIFT; 2100 2101 /* HE data 5 */ 2102 TXMON_HAL_USER(ppdu_info, user_id, he_data5) |= 2103 txbf << QDF_MON_STATUS_TXBF_SHIFT; 2104 2105 /* HE data 6 */ 2106 TXMON_HAL_USER(ppdu_info, user_id, nss) = nss; 2107 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss; 2108 2109 SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_OFDMA_E); 2110 break; 2111 } 2112 case WIFIMACTX_L_SIG_A_E: 2113 { 2114 uint8_t *l_sig_a_info = NULL; 2115 uint8_t rate = 0; 2116 2117 status = HAL_MON_MACTX_L_SIG_A; 2118 2119 l_sig_a_info = (uint8_t *)tx_tlv + 2120 HAL_OFFSET(MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS, 2121 RATE); 2122 rate = HAL_TX_DESC_GET_64(tx_tlv, 2123 MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS, 2124 RATE); 2125 2126 switch (rate) { 2127 case 8: 2128 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_0MCS; 2129 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0; 2130 break; 2131 case 9: 2132 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_1MCS; 2133 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1; 2134 break; 2135 case 10: 2136 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_2MCS; 2137 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2; 2138 break; 2139 case 11: 2140 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_3MCS; 2141 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3; 2142 break; 2143 case 12: 2144 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_4MCS; 2145 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4; 2146 break; 2147 case 13: 2148 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_5MCS; 2149 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5; 2150 break; 2151 case 14: 2152 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_6MCS; 2153 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6; 2154 break; 2155 case 15: 2156 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_7MCS; 2157 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS7; 2158 break; 2159 default: 2160 break; 2161 } 2162 2163 TXMON_HAL_STATUS(ppdu_info, ofdm_flag) = 1; 2164 TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU; 2165 TXMON_HAL_STATUS(ppdu_info, l_sig_a_info) = *l_sig_a_info; 2166 2167 SHOW_DEFINED(WIFIMACTX_L_SIG_A_E); 2168 break; 2169 } 2170 case WIFIMACTX_L_SIG_B_E: 2171 { 2172 uint8_t *l_sig_b_info = NULL; 2173 uint8_t rate = 0; 2174 2175 status = HAL_MON_MACTX_L_SIG_B; 2176 2177 l_sig_b_info = (uint8_t *)tx_tlv + 2178 HAL_OFFSET(MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS, 2179 RATE); 2180 rate = HAL_TX_DESC_GET_64(tx_tlv, 2181 MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS, 2182 RATE); 2183 2184 switch (rate) { 2185 case 1: 2186 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_3MCS; 2187 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3; 2188 break; 2189 case 2: 2190 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_2MCS; 2191 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2; 2192 break; 2193 case 3: 2194 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_1MCS; 2195 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1; 2196 break; 2197 case 4: 2198 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_0MCS; 2199 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0; 2200 break; 2201 case 5: 2202 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_6MCS; 2203 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6; 2204 break; 2205 case 6: 2206 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_5MCS; 2207 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5; 2208 break; 2209 case 7: 2210 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_4MCS; 2211 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4; 2212 break; 2213 default: 2214 break; 2215 } 2216 2217 TXMON_HAL_STATUS(ppdu_info, cck_flag) = 1; 2218 TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU; 2219 TXMON_HAL_STATUS(ppdu_info, l_sig_b_info) = *l_sig_b_info; 2220 2221 SHOW_DEFINED(WIFIMACTX_L_SIG_B_E); 2222 break; 2223 } 2224 case WIFIMACTX_HT_SIG_E: 2225 { 2226 uint8_t mcs = 0; 2227 uint8_t bw = 0; 2228 uint8_t is_stbc = 0; 2229 uint8_t coding = 0; 2230 uint8_t gi = 0; 2231 2232 status = HAL_MON_MACTX_HT_SIG; 2233 mcs = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, MCS); 2234 bw = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, CBW); 2235 is_stbc = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, STBC); 2236 coding = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, FEC_CODING); 2237 gi = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, SHORT_GI); 2238 2239 TXMON_HAL_STATUS(ppdu_info, ldpc) = 2240 (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0; 2241 TXMON_HAL_STATUS(ppdu_info, ht_mcs) = mcs; 2242 TXMON_HAL_STATUS(ppdu_info, bw) = bw; 2243 TXMON_HAL_STATUS(ppdu_info, sgi) = gi; 2244 TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc; 2245 TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU; 2246 2247 SHOW_DEFINED(WIFIMACTX_HT_SIG_E); 2248 break; 2249 } 2250 case WIFIMACTX_VHT_SIG_A_E: 2251 { 2252 uint8_t bandwidth = 0; 2253 uint8_t is_stbc = 0; 2254 uint8_t group_id = 0; 2255 uint32_t nss_comb = 0; 2256 uint8_t nss_su = 0; 2257 uint8_t nss_mu[4] = {0}; 2258 uint8_t sgi = 0; 2259 uint8_t coding = 0; 2260 uint8_t mcs = 0; 2261 uint8_t beamformed = 0; 2262 uint8_t partial_aid = 0; 2263 2264 status = HAL_MON_MACTX_VHT_SIG_A; 2265 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, 2266 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2267 BANDWIDTH); 2268 is_stbc = HAL_TX_DESC_GET_64(tx_tlv, 2269 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2270 STBC); 2271 group_id = HAL_TX_DESC_GET_64(tx_tlv, 2272 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2273 GROUP_ID); 2274 /* nss_comb is su nss, MU nss and partial AID */ 2275 nss_comb = HAL_TX_DESC_GET_64(tx_tlv, 2276 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2277 N_STS); 2278 /* if it is SU */ 2279 nss_su = (nss_comb & 0x7) + 1; 2280 /* partial aid - applicable only for SU */ 2281 partial_aid = (nss_comb >> 3) & 0x1F; 2282 /* if it is MU */ 2283 nss_mu[0] = (nss_comb & 0x7) + 1; 2284 nss_mu[1] = ((nss_comb >> 3) & 0x7) + 1; 2285 nss_mu[2] = ((nss_comb >> 6) & 0x7) + 1; 2286 nss_mu[3] = ((nss_comb >> 9) & 0x7) + 1; 2287 2288 sgi = HAL_TX_DESC_GET_64(tx_tlv, 2289 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2290 GI_SETTING); 2291 coding = HAL_TX_DESC_GET_64(tx_tlv, 2292 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2293 SU_MU_CODING); 2294 mcs = HAL_TX_DESC_GET_64(tx_tlv, 2295 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2296 MCS); 2297 beamformed = HAL_TX_DESC_GET_64(tx_tlv, 2298 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2299 BEAMFORMED); 2300 2301 TXMON_HAL_STATUS(ppdu_info, ldpc) = 2302 (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0; 2303 TXMON_STATUS_INFO(tx_status_info, sw_frame_group_id) = group_id; 2304 2305 TXMON_HAL_STATUS(ppdu_info, sgi) = sgi; 2306 TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc; 2307 TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth; 2308 TXMON_HAL_STATUS(ppdu_info, beamformed) = beamformed; 2309 2310 if (group_id == 0 || group_id == 63) { 2311 TXMON_HAL_STATUS(ppdu_info, reception_type) = 2312 HAL_RX_TYPE_SU; 2313 TXMON_HAL_STATUS(ppdu_info, mcs) = mcs; 2314 TXMON_HAL_STATUS(ppdu_info, nss) = 2315 nss_su & VHT_SIG_SU_NSS_MASK; 2316 2317 TXMON_HAL_USER(ppdu_info, user_id, 2318 vht_flag_values3[0]) = ((mcs << 4) | 2319 nss_su); 2320 } else { 2321 TXMON_HAL_STATUS(ppdu_info, reception_type) = 2322 HAL_RX_TYPE_MU_MIMO; 2323 TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs; 2324 TXMON_HAL_USER(ppdu_info, user_id, nss) = 2325 nss_su & VHT_SIG_SU_NSS_MASK; 2326 2327 TXMON_HAL_USER(ppdu_info, user_id, 2328 vht_flag_values3[0]) = ((mcs << 4) | 2329 nss_su); 2330 TXMON_HAL_USER(ppdu_info, user_id, 2331 vht_flag_values3[1]) = ((mcs << 4) | 2332 nss_mu[1]); 2333 TXMON_HAL_USER(ppdu_info, user_id, 2334 vht_flag_values3[2]) = ((mcs << 4) | 2335 nss_mu[2]); 2336 TXMON_HAL_USER(ppdu_info, user_id, 2337 vht_flag_values3[3]) = ((mcs << 4) | 2338 nss_mu[3]); 2339 } 2340 2341 /* TODO: loop over multiple user */ 2342 TXMON_HAL_USER(ppdu_info, user_id, 2343 vht_flag_values2) = bandwidth; 2344 TXMON_HAL_USER(ppdu_info, user_id, 2345 vht_flag_values4) = coding; 2346 TXMON_HAL_USER(ppdu_info, user_id, 2347 vht_flag_values5) = group_id; 2348 TXMON_HAL_USER(ppdu_info, user_id, 2349 vht_flag_values6) = partial_aid; 2350 SHOW_DEFINED(WIFIMACTX_VHT_SIG_A_E); 2351 break; 2352 } 2353 case WIFIMACTX_VHT_SIG_B_MU160_E: 2354 { 2355 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU160_E); 2356 break; 2357 } 2358 case WIFIMACTX_VHT_SIG_B_MU80_E: 2359 { 2360 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU80_E); 2361 break; 2362 } 2363 case WIFIMACTX_VHT_SIG_B_MU40_E: 2364 { 2365 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU40_E); 2366 break; 2367 } 2368 case WIFIMACTX_VHT_SIG_B_MU20_E: 2369 { 2370 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU20_E); 2371 break; 2372 } 2373 case WIFIMACTX_VHT_SIG_B_SU160_E: 2374 { 2375 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU160_E); 2376 break; 2377 } 2378 case WIFIMACTX_VHT_SIG_B_SU80_E: 2379 { 2380 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU80_E); 2381 break; 2382 } 2383 case WIFIMACTX_VHT_SIG_B_SU40_E: 2384 { 2385 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU40_E); 2386 break; 2387 } 2388 case WIFIMACTX_VHT_SIG_B_SU20_E: 2389 { 2390 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU20_E); 2391 break; 2392 } 2393 case WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E: 2394 { 2395 SHOW_DEFINED(WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E); 2396 break; 2397 } 2398 case WIFIMACTX_USER_DESC_PER_USER_E: 2399 { 2400 /* user tlv */ 2401 uint32_t bf = 0; 2402 uint32_t psdu_length = 0; 2403 uint8_t ru_start_index = 0; 2404 uint8_t ru_size = 0; 2405 uint8_t nss = 0; 2406 uint8_t mcs = 0; 2407 uint8_t dcm = 0; 2408 uint8_t fec_type = 0; 2409 uint8_t is_ldpc_extra_symb = 0; 2410 uint32_t he_data1 = TXMON_HAL_USER(ppdu_info, user_id, 2411 he_data1); 2412 uint32_t he_data2 = TXMON_HAL_USER(ppdu_info, user_id, 2413 he_data2); 2414 uint32_t he_data3 = TXMON_HAL_USER(ppdu_info, user_id, 2415 he_data3); 2416 uint32_t he_data5 = TXMON_HAL_USER(ppdu_info, user_id, 2417 he_data5); 2418 uint32_t he_data6 = TXMON_HAL_USER(ppdu_info, user_id, 2419 he_data6); 2420 2421 status = HAL_MON_MACTX_USER_DESC_PER_USER; 2422 2423 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 2424 2425 psdu_length = HAL_TX_DESC_GET_64(tx_tlv, 2426 MACTX_USER_DESC_PER_USER, 2427 PSDU_LENGTH); 2428 ru_start_index = HAL_TX_DESC_GET_64(tx_tlv, 2429 MACTX_USER_DESC_PER_USER, 2430 RU_START_INDEX); 2431 ru_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 2432 RU_SIZE); 2433 bf = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 2434 USER_BF_TYPE); 2435 2436 nss = HAL_TX_DESC_GET_64(tx_tlv, 2437 MACTX_USER_DESC_PER_USER, NSS) + 1; 2438 mcs = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, MCS); 2439 dcm = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, DCM); 2440 fec_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 2441 FEC_TYPE); 2442 is_ldpc_extra_symb = 2443 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 2444 LDPC_EXTRA_SYMBOL); 2445 2446 if (!TXMON_HAL_STATUS(ppdu_info, he_flags)) 2447 break; 2448 2449 /* update */ 2450 /* BEAM CHANGE */ 2451 he_data1 |= QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN; 2452 he_data1 |= QDF_MON_STATUS_TXBF_KNOWN; 2453 he_data5 |= (!!bf << QDF_MON_STATUS_TXBF_SHIFT); 2454 he_data3 |= (!!bf << QDF_MON_STATUS_BEAM_CHANGE_SHIFT); 2455 2456 /* UL/DL known */ 2457 he_data1 |= QDF_MON_STATUS_HE_DL_UL_KNOWN; 2458 he_data3 |= (1 << QDF_MON_STATUS_DL_UL_SHIFT); 2459 2460 /* MCS */ 2461 he_data1 |= QDF_MON_STATUS_HE_MCS_KNOWN; 2462 he_data3 |= (mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT); 2463 /* DCM */ 2464 he_data1 |= QDF_MON_STATUS_HE_DCM_KNOWN; 2465 he_data3 |= (dcm << QDF_MON_STATUS_DCM_SHIFT); 2466 /* LDPC EXTRA SYMB */ 2467 he_data1 |= QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN; 2468 he_data3 |= (is_ldpc_extra_symb << 2469 QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT); 2470 /* RU offset and RU */ 2471 he_data2 |= QDF_MON_STATUS_RU_ALLOCATION_OFFSET_KNOWN; 2472 he_data2 |= (get_ru_offset_from_start_index(ru_size, 2473 ru_start_index) << 2474 QDF_MON_STATUS_RU_ALLOCATION_SHIFT); 2475 2476 /* Data BW and RU allocation */ 2477 if (ru_size < HAL_MAX_RU_INDEX) { 2478 /* update bandwidth if it is full bandwidth */ 2479 he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 2480 he_data5 = (he_data5 & 0xFFF0) | (4 + ru_size); 2481 } 2482 2483 he_data6 |= (nss & 0xF); 2484 TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs; 2485 2486 /* update stack variable to ppdu_info */ 2487 TXMON_HAL_USER(ppdu_info, user_id, he_data1) = he_data1; 2488 TXMON_HAL_USER(ppdu_info, user_id, he_data2) = he_data2; 2489 TXMON_HAL_USER(ppdu_info, user_id, he_data3) = he_data3; 2490 TXMON_HAL_USER(ppdu_info, user_id, he_data5) = he_data5; 2491 TXMON_HAL_USER(ppdu_info, user_id, he_data6) = he_data6; 2492 2493 SHOW_DEFINED(WIFIMACTX_USER_DESC_PER_USER_E); 2494 break; 2495 } 2496 case WIFIMACTX_USER_DESC_COMMON_E: 2497 { 2498 uint16_t he_mu_flag_1 = 0; 2499 uint16_t he_mu_flag_2 = 0; 2500 uint16_t ru_channel_1[4] = {0}; 2501 uint16_t ru_channel_2[4] = {0}; 2502 uint16_t num_users = 0; 2503 uint8_t doppler; 2504 uint8_t ltf_size; 2505 uint8_t num_ltf_symbols; 2506 uint8_t pkt_extn_pe; 2507 uint8_t a_factor; 2508 uint8_t center_ru_0; 2509 uint8_t center_ru_1; 2510 uint8_t i = 0; 2511 2512 num_users = TXMON_HAL(ppdu_info, num_users); 2513 2514 doppler = HAL_TX_DESC_GET_64(tx_tlv, 2515 MACTX_USER_DESC_COMMON, 2516 DOPPLER_INDICATION); 2517 2518 ltf_size = HAL_TX_DESC_GET_64(tx_tlv, 2519 MACTX_USER_DESC_COMMON, 2520 LTF_SIZE); 2521 2522 num_ltf_symbols = HAL_TX_DESC_GET_64(tx_tlv, 2523 MACTX_USER_DESC_COMMON, 2524 NUM_DATA_SYMBOLS); 2525 2526 pkt_extn_pe = HAL_TX_DESC_GET_64(tx_tlv, 2527 MACTX_USER_DESC_COMMON, 2528 PACKET_EXTENSION_PE_DISAMBIGUITY); 2529 2530 a_factor = HAL_TX_DESC_GET_64(tx_tlv, 2531 MACTX_USER_DESC_COMMON, 2532 PACKET_EXTENSION_A_FACTOR); 2533 2534 center_ru_0 = HAL_TX_DESC_GET_64(tx_tlv, 2535 MACTX_USER_DESC_COMMON, 2536 CENTER_RU_0); 2537 2538 center_ru_1 = HAL_TX_DESC_GET_64(tx_tlv, 2539 MACTX_USER_DESC_COMMON, 2540 CENTER_RU_1); 2541 2542 ru_channel_1[0] = HAL_TX_DESC_GET_64(tx_tlv, 2543 MACTX_USER_DESC_COMMON, 2544 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0); 2545 ru_channel_1[1] = HAL_TX_DESC_GET_64(tx_tlv, 2546 MACTX_USER_DESC_COMMON, 2547 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1); 2548 ru_channel_1[2] = HAL_TX_DESC_GET_64(tx_tlv, 2549 MACTX_USER_DESC_COMMON, 2550 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2); 2551 ru_channel_1[3] = HAL_TX_DESC_GET_64(tx_tlv, 2552 MACTX_USER_DESC_COMMON, 2553 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3); 2554 2555 ru_channel_2[0] = HAL_TX_DESC_GET_64(tx_tlv, 2556 MACTX_USER_DESC_COMMON, 2557 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0); 2558 ru_channel_2[1] = HAL_TX_DESC_GET_64(tx_tlv, 2559 MACTX_USER_DESC_COMMON, 2560 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1); 2561 ru_channel_2[2] = HAL_TX_DESC_GET_64(tx_tlv, 2562 MACTX_USER_DESC_COMMON, 2563 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2); 2564 ru_channel_2[3] = HAL_TX_DESC_GET_64(tx_tlv, 2565 MACTX_USER_DESC_COMMON, 2566 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3); 2567 2568 /* HE data 1 */ 2569 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 2570 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 2571 2572 /* HE data 2 */ 2573 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= 2574 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 2575 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN; 2576 2577 /* HE data 5 */ 2578 TXMON_HAL_USER(ppdu_info, user_id, he_data5) |= 2579 (pkt_extn_pe << 2580 QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT) | 2581 (a_factor << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT) | 2582 ((1 + ltf_size) << 2583 QDF_MON_STATUS_HE_LTF_SIZE_SHIFT) | 2584 (num_ltf_symbols << 2585 QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 2586 2587 /* HE data 6 */ 2588 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= 2589 (doppler << QDF_MON_STATUS_DOPPLER_SHIFT); 2590 2591 /* number of symbol */ 2592 he_mu_flag_1 |= 2593 (QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN | 2594 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN | 2595 ((center_ru_0 << 2596 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_SHIFT) & 2597 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_VALUE)); 2598 2599 he_mu_flag_2 |= ((center_ru_1 << 2600 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_SHIFT) & 2601 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_VALUE); 2602 2603 TXMON_HAL_STATUS(ppdu_info, 2604 he_mu_flags) = IS_MULTI_USERS(num_users); 2605 for (i = 0; i < num_users; i++) { 2606 TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1; 2607 TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2; 2608 2609 /* channel 1 */ 2610 TXMON_HAL_USER(ppdu_info, i, 2611 he_RU[0]) = ru_channel_1[0]; 2612 TXMON_HAL_USER(ppdu_info, i, 2613 he_RU[1]) = ru_channel_1[1]; 2614 TXMON_HAL_USER(ppdu_info, i, 2615 he_RU[2]) = ru_channel_1[2]; 2616 TXMON_HAL_USER(ppdu_info, i, 2617 he_RU[3]) = ru_channel_1[3]; 2618 /* channel 2 */ 2619 TXMON_HAL_USER(ppdu_info, i, 2620 he_RU[4]) = ru_channel_2[0]; 2621 TXMON_HAL_USER(ppdu_info, i, 2622 he_RU[5]) = ru_channel_2[1]; 2623 TXMON_HAL_USER(ppdu_info, i, 2624 he_RU[6]) = ru_channel_2[2]; 2625 TXMON_HAL_USER(ppdu_info, i, 2626 he_RU[7]) = ru_channel_2[3]; 2627 } 2628 /* channel 1 */ 2629 TXMON_HAL_STATUS(ppdu_info, he_RU[0]) = ru_channel_1[0]; 2630 TXMON_HAL_STATUS(ppdu_info, he_RU[1]) = ru_channel_1[1]; 2631 TXMON_HAL_STATUS(ppdu_info, he_RU[2]) = ru_channel_1[2]; 2632 TXMON_HAL_STATUS(ppdu_info, he_RU[3]) = ru_channel_1[3]; 2633 /* channel 2 */ 2634 TXMON_HAL_STATUS(ppdu_info, he_RU[4]) = ru_channel_2[0]; 2635 TXMON_HAL_STATUS(ppdu_info, he_RU[5]) = ru_channel_2[1]; 2636 TXMON_HAL_STATUS(ppdu_info, he_RU[6]) = ru_channel_2[2]; 2637 TXMON_HAL_STATUS(ppdu_info, he_RU[7]) = ru_channel_2[3]; 2638 2639 /* copy per user info to all user */ 2640 SHOW_DEFINED(WIFIMACTX_USER_DESC_COMMON_E); 2641 break; 2642 } 2643 case WIFIMACTX_PHY_DESC_E: 2644 { 2645 /* pkt_type - preamble type */ 2646 uint32_t pkt_type = 0; 2647 uint8_t bandwidth = 0; 2648 uint8_t is_stbc = 0; 2649 uint8_t is_triggered = 0; 2650 uint8_t gi = 0; 2651 uint8_t he_ppdu_subtype = 0; 2652 uint32_t ltf_size = 0; 2653 uint32_t he_data1 = 0; 2654 uint32_t he_data2 = 0; 2655 uint32_t he_data3 = 0; 2656 uint32_t he_data5 = 0; 2657 uint16_t he_mu_flag_1 = 0; 2658 uint16_t he_mu_flag_2 = 0; 2659 uint16_t num_users = 0; 2660 uint8_t i = 0; 2661 2662 status = HAL_MON_MACTX_PHY_DESC; 2663 2664 num_users = TXMON_HAL(ppdu_info, num_users); 2665 pkt_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, PKT_TYPE); 2666 is_stbc = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, STBC); 2667 is_triggered = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2668 TRIGGERED); 2669 if (!is_triggered) { 2670 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2671 BANDWIDTH); 2672 } else { 2673 /* 2674 * is_triggered, bw is minimum of AP pkt bw 2675 * or STA bw 2676 */ 2677 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2678 AP_PKT_BW); 2679 } 2680 2681 gi = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2682 CP_SETTING); 2683 ltf_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, LTF_SIZE); 2684 he_ppdu_subtype = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2685 HE_PPDU_SUBTYPE); 2686 2687 TXMON_HAL_STATUS(ppdu_info, preamble_type) = pkt_type; 2688 TXMON_HAL_STATUS(ppdu_info, ltf_size) = ltf_size; 2689 TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc; 2690 TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth; 2691 2692 switch (ppdu_info->rx_status.preamble_type) { 2693 case TXMON_PKT_TYPE_11N_MM: 2694 TXMON_HAL_STATUS(ppdu_info, ht_flags) = 1; 2695 TXMON_HAL_STATUS(ppdu_info, 2696 rtap_flags) |= HT_SGI_PRESENT; 2697 break; 2698 case TXMON_PKT_TYPE_11AC: 2699 TXMON_HAL_STATUS(ppdu_info, vht_flags) = 1; 2700 break; 2701 case TXMON_PKT_TYPE_11AX: 2702 TXMON_HAL_STATUS(ppdu_info, he_flags) = 1; 2703 break; 2704 default: 2705 break; 2706 } 2707 2708 if (!TXMON_HAL_STATUS(ppdu_info, he_flags)) 2709 break; 2710 2711 /* update he flags */ 2712 /* PPDU FORMAT */ 2713 switch (he_ppdu_subtype) { 2714 case TXMON_HE_SUBTYPE_SU: 2715 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 2716 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 2717 break; 2718 case TXMON_HE_SUBTYPE_TRIG: 2719 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 2720 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 2721 break; 2722 case TXMON_HE_SUBTYPE_MU: 2723 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 2724 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 2725 break; 2726 case TXMON_HE_SUBTYPE_EXT_SU: 2727 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 2728 QDF_MON_STATUS_HE_EXT_SU_FORMAT_TYPE; 2729 break; 2730 }; 2731 2732 /* STBC */ 2733 he_data1 |= QDF_MON_STATUS_HE_STBC_KNOWN; 2734 he_data3 |= (is_stbc << QDF_MON_STATUS_STBC_SHIFT); 2735 2736 /* GI */ 2737 he_data2 |= QDF_MON_STATUS_HE_GI_KNOWN; 2738 he_data5 |= (gi << QDF_MON_STATUS_GI_SHIFT); 2739 2740 /* Data BW and RU allocation */ 2741 he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 2742 he_data5 = (he_data5 & 0xFFF0) | bandwidth; 2743 2744 he_data2 |= QDF_MON_STATUS_LTF_SYMBOLS_KNOWN; 2745 he_data5 |= ((1 + ltf_size) << 2746 QDF_MON_STATUS_HE_LTF_SIZE_SHIFT); 2747 2748 TXMON_HAL_STATUS(ppdu_info, 2749 he_mu_flags) = IS_MULTI_USERS(num_users); 2750 /* MAC TX PHY DESC is not a user tlv */ 2751 for (i = 0; i < num_users; i++) { 2752 TXMON_HAL_USER(ppdu_info, i, he_data1) = he_data1; 2753 TXMON_HAL_USER(ppdu_info, i, he_data2) = he_data2; 2754 TXMON_HAL_USER(ppdu_info, i, he_data3) = he_data3; 2755 TXMON_HAL_USER(ppdu_info, i, he_data5) = he_data5; 2756 2757 /* HE MU flags */ 2758 TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1; 2759 TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2; 2760 } 2761 2762 SHOW_DEFINED(WIFIMACTX_PHY_DESC_E); 2763 break; 2764 } 2765 case WIFICOEX_RX_STATUS_E: 2766 { 2767 SHOW_DEFINED(WIFICOEX_RX_STATUS_E); 2768 break; 2769 } 2770 case WIFIRX_PPDU_ACK_REPORT_E: 2771 { 2772 SHOW_DEFINED(WIFIRX_PPDU_ACK_REPORT_E); 2773 break; 2774 } 2775 case WIFIRX_PPDU_NO_ACK_REPORT_E: 2776 { 2777 SHOW_DEFINED(WIFIRX_PPDU_NO_ACK_REPORT_E); 2778 break; 2779 } 2780 case WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E: 2781 { 2782 SHOW_DEFINED(WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E); 2783 break; 2784 } 2785 case WIFITXPCU_PHYTX_DEBUG32_E: 2786 { 2787 SHOW_DEFINED(WIFITXPCU_PHYTX_DEBUG32_E); 2788 break; 2789 } 2790 case WIFITXPCU_PREAMBLE_DONE_E: 2791 { 2792 SHOW_DEFINED(WIFITXPCU_PREAMBLE_DONE_E); 2793 break; 2794 } 2795 case WIFIRX_PHY_SLEEP_E: 2796 { 2797 SHOW_DEFINED(WIFIRX_PHY_SLEEP_E); 2798 break; 2799 } 2800 case WIFIRX_FRAME_BITMAP_REQ_E: 2801 { 2802 SHOW_DEFINED(WIFIRX_FRAME_BITMAP_REQ_E); 2803 break; 2804 } 2805 case WIFIRXPCU_TX_SETUP_CLEAR_E: 2806 { 2807 SHOW_DEFINED(WIFIRXPCU_TX_SETUP_CLEAR_E); 2808 break; 2809 } 2810 case WIFIRX_TRIG_INFO_E: 2811 { 2812 SHOW_DEFINED(WIFIRX_TRIG_INFO_E); 2813 break; 2814 } 2815 case WIFIEXPECTED_RESPONSE_E: 2816 { 2817 SHOW_DEFINED(WIFIEXPECTED_RESPONSE_E); 2818 break; 2819 } 2820 case WIFITRIGGER_RESPONSE_TX_DONE_E: 2821 { 2822 SHOW_DEFINED(WIFITRIGGER_RESPONSE_TX_DONE_E); 2823 break; 2824 } 2825 case WIFIFW2SW_MON_E: 2826 { 2827 SHOW_DEFINED(WIFIFW2SW_MON_E); 2828 break; 2829 } 2830 } 2831 2832 return status; 2833 } 2834 #endif /* QCA_MONITOR_2_0_SUPPORT */ 2835 2836 #ifdef REO_SHARED_QREF_TABLE_EN 2837 static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl) 2838 { 2839 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2840 uint32_t reg_val = 0; 2841 2842 /* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers 2843 * of 37 peer/tids 2844 */ 2845 reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE)); 2846 reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1); 2847 HAL_REG_WRITE(hal, 2848 HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 2849 reg_val); 2850 2851 /* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers 2852 * of 37 peer/tids 2853 */ 2854 reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1)); 2855 HAL_REG_WRITE(hal, 2856 HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 2857 reg_val); 2858 2859 hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of" 2860 "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back" 2861 "to erase stale entries in reo storage: regval:%x", hal, reg_val); 2862 } 2863 2864 /* hal_reo_shared_qaddr_write(): Write REO tid queue addr 2865 * LUT shared by SW and HW at the index given by peer id 2866 * and tid. 2867 * 2868 * @hal_soc: hal soc pointer 2869 * @reo_qref_addr: pointer to index pointed to be peer_id 2870 * and tid 2871 * @tid: tid queue number 2872 * @hw_qdesc_paddr: reo queue addr 2873 */ 2874 2875 static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl, 2876 uint16_t peer_id, 2877 int tid, 2878 qdf_dma_addr_t hw_qdesc_paddr) 2879 { 2880 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2881 struct rx_reo_queue_reference *reo_qref; 2882 uint32_t peer_tid_idx; 2883 2884 /* Plug hw_desc_addr in Host reo queue reference table */ 2885 if (HAL_PEER_ID_IS_MLO(peer_id)) { 2886 peer_tid_idx = ((peer_id - HAL_ML_PEER_ID_START) * 2887 DP_MAX_TIDS) + tid; 2888 reo_qref = (struct rx_reo_queue_reference *) 2889 &hal->reo_qref.mlo_reo_qref_table_vaddr[peer_tid_idx]; 2890 } else { 2891 peer_tid_idx = (peer_id * DP_MAX_TIDS) + tid; 2892 reo_qref = (struct rx_reo_queue_reference *) 2893 &hal->reo_qref.non_mlo_reo_qref_table_vaddr[peer_tid_idx]; 2894 } 2895 reo_qref->rx_reo_queue_desc_addr_31_0 = 2896 hw_qdesc_paddr & 0xffffffff; 2897 reo_qref->rx_reo_queue_desc_addr_39_32 = 2898 (hw_qdesc_paddr & 0xff00000000) >> 32; 2899 if (hw_qdesc_paddr != 0) 2900 reo_qref->receive_queue_number = tid; 2901 else 2902 reo_qref->receive_queue_number = 0; 2903 2904 hal_reo_shared_qaddr_cache_clear_be(hal_soc_hdl); 2905 hal_verbose_debug("hw_qdesc_paddr: %pK, tid: %d, reo_qref:%pK," 2906 "rx_reo_queue_desc_addr_31_0: %x," 2907 "rx_reo_queue_desc_addr_39_32: %x", 2908 (void *)hw_qdesc_paddr, tid, reo_qref, 2909 reo_qref->rx_reo_queue_desc_addr_31_0, 2910 reo_qref->rx_reo_queue_desc_addr_39_32); 2911 } 2912 2913 /** 2914 * hal_reo_shared_qaddr_setup() - Allocate MLO and Non MLO reo queue 2915 * reference table shared between SW and HW and initialize in Qdesc Base0 2916 * base1 registers provided by HW. 2917 * 2918 * @hal_soc: HAL Soc handle 2919 * 2920 * Return: None 2921 */ 2922 static void hal_reo_shared_qaddr_setup_be(hal_soc_handle_t hal_soc_hdl) 2923 { 2924 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2925 2926 hal->reo_qref.reo_qref_table_en = 1; 2927 2928 hal->reo_qref.mlo_reo_qref_table_vaddr = 2929 (uint64_t *)qdf_mem_alloc_consistent( 2930 hal->qdf_dev, hal->qdf_dev->dev, 2931 REO_QUEUE_REF_ML_TABLE_SIZE, 2932 &hal->reo_qref.mlo_reo_qref_table_paddr); 2933 hal->reo_qref.non_mlo_reo_qref_table_vaddr = 2934 (uint64_t *)qdf_mem_alloc_consistent( 2935 hal->qdf_dev, hal->qdf_dev->dev, 2936 REO_QUEUE_REF_NON_ML_TABLE_SIZE, 2937 &hal->reo_qref.non_mlo_reo_qref_table_paddr); 2938 2939 hal_verbose_debug("MLO table start paddr:%pK," 2940 "Non-MLO table start paddr:%pK," 2941 "MLO table start vaddr: %pK," 2942 "Non MLO table start vaddr: %pK", 2943 (void *)hal->reo_qref.mlo_reo_qref_table_paddr, 2944 (void *)hal->reo_qref.non_mlo_reo_qref_table_paddr, 2945 hal->reo_qref.mlo_reo_qref_table_vaddr, 2946 hal->reo_qref.non_mlo_reo_qref_table_vaddr); 2947 } 2948 2949 /** 2950 * hal_reo_shared_qaddr_init() - Zero out REO qref LUT and 2951 * write start addr of MLO and Non MLO table in HW 2952 * 2953 * @hal_soc: HAL Soc handle 2954 * @qref_reset: reset qref LUT 2955 * 2956 * Return: None 2957 */ 2958 static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl, 2959 int qref_reset) 2960 { 2961 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2962 2963 if (qref_reset) { 2964 qdf_mem_zero(hal->reo_qref.mlo_reo_qref_table_vaddr, 2965 REO_QUEUE_REF_ML_TABLE_SIZE); 2966 qdf_mem_zero(hal->reo_qref.non_mlo_reo_qref_table_vaddr, 2967 REO_QUEUE_REF_NON_ML_TABLE_SIZE); 2968 } 2969 /* LUT_BASE0 and BASE1 registers expect upper 32bits of LUT base address 2970 * and lower 8 bits to be 0. Shift the physical address by 8 to plug 2971 * upper 32bits only 2972 */ 2973 HAL_REG_WRITE(hal, 2974 HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE), 2975 hal->reo_qref.non_mlo_reo_qref_table_paddr >> 8); 2976 HAL_REG_WRITE(hal, 2977 HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE), 2978 hal->reo_qref.mlo_reo_qref_table_paddr >> 8); 2979 HAL_REG_WRITE(hal, 2980 HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 2981 HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE, 2982 1)); 2983 HAL_REG_WRITE(hal, 2984 HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(REO_REG_REG_BASE), 2985 HAL_MS(HWIO_REO_R0_QDESC, MAX_SW_PEER_ID_MAX_SUPPORTED, 2986 0x1fff)); 2987 } 2988 2989 /** 2990 * hal_reo_shared_qaddr_detach() - Free MLO and Non MLO reo queue 2991 * reference table shared between SW and HW 2992 * 2993 * @hal_soc: HAL Soc handle 2994 * 2995 * Return: None 2996 */ 2997 static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl) 2998 { 2999 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3000 3001 HAL_REG_WRITE(hal, 3002 HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE), 3003 0); 3004 HAL_REG_WRITE(hal, 3005 HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE), 3006 0); 3007 3008 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 3009 REO_QUEUE_REF_ML_TABLE_SIZE, 3010 hal->reo_qref.mlo_reo_qref_table_vaddr, 3011 hal->reo_qref.mlo_reo_qref_table_paddr, 0); 3012 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 3013 REO_QUEUE_REF_NON_ML_TABLE_SIZE, 3014 hal->reo_qref.non_mlo_reo_qref_table_vaddr, 3015 hal->reo_qref.non_mlo_reo_qref_table_paddr, 0); 3016 } 3017 #endif 3018 3019 /** 3020 * hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing 3021 * @hal_soc: HAL SoC context 3022 * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM 3023 * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW 3024 * 3025 * Return: void 3026 */ 3027 #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK 3028 static inline void 3029 hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl, 3030 enum hal_tx_vdev_mismatch_notify 3031 config) 3032 { 3033 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3034 uint32_t reg_addr, reg_val = 0; 3035 uint32_t val = 0; 3036 3037 reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE); 3038 3039 val = HAL_REG_READ(hal_soc, reg_addr); 3040 3041 /* reset the corresponding bits in register */ 3042 val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK)); 3043 3044 /* set config value */ 3045 reg_val = val | (config << 3046 HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT); 3047 3048 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3049 } 3050 #else 3051 static inline void 3052 hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl, 3053 enum hal_tx_vdev_mismatch_notify 3054 config) 3055 { 3056 } 3057 #endif 3058 3059 /** 3060 * hal_tx_mcast_mlo_reinject_routing_set - set MLO multicast reinject routing 3061 * @hal_soc: HAL SoC context 3062 * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW 3063 * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM 3064 * 3065 * Return: void 3066 */ 3067 #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \ 3068 defined(WLAN_MCAST_MLO) 3069 static inline void 3070 hal_tx_mcast_mlo_reinject_routing_set_generic_be( 3071 hal_soc_handle_t hal_soc_hdl, 3072 enum hal_tx_mcast_mlo_reinject_notify config) 3073 { 3074 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3075 uint32_t reg_addr, reg_val = 0; 3076 uint32_t val = 0; 3077 3078 reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE); 3079 val = HAL_REG_READ(hal_soc, reg_addr); 3080 3081 /* reset the corresponding bits in register */ 3082 val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK)); 3083 3084 /* set config value */ 3085 reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT); 3086 3087 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3088 } 3089 #else 3090 static inline void 3091 hal_tx_mcast_mlo_reinject_routing_set_generic_be( 3092 hal_soc_handle_t hal_soc_hdl, 3093 enum hal_tx_mcast_mlo_reinject_notify config) 3094 { 3095 } 3096 #endif 3097 3098 /** 3099 * hal_get_ba_aging_timeout_be - Get BA Aging timeout 3100 * 3101 * @hal_soc: Opaque HAL SOC handle 3102 * @ac: Access category 3103 * @value: window size to get 3104 */ 3105 3106 static inline 3107 void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl, 3108 uint8_t ac, uint32_t *value) 3109 { 3110 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 3111 3112 switch (ac) { 3113 case WME_AC_BE: 3114 *value = HAL_REG_READ(soc, 3115 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 3116 REO_REG_REG_BASE)) / 1000; 3117 break; 3118 case WME_AC_BK: 3119 *value = HAL_REG_READ(soc, 3120 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 3121 REO_REG_REG_BASE)) / 1000; 3122 break; 3123 case WME_AC_VI: 3124 *value = HAL_REG_READ(soc, 3125 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 3126 REO_REG_REG_BASE)) / 1000; 3127 break; 3128 case WME_AC_VO: 3129 *value = HAL_REG_READ(soc, 3130 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 3131 REO_REG_REG_BASE)) / 1000; 3132 break; 3133 default: 3134 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 3135 "Invalid AC: %d\n", ac); 3136 } 3137 } 3138 3139 /** 3140 * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the 3141 * buffer list provided 3142 * 3143 * @hal_soc: Opaque HAL SOC handle 3144 * @scatter_bufs_base_paddr: Array of physical base addresses 3145 * @scatter_bufs_base_vaddr: Array of virtual base addresses 3146 * @num_scatter_bufs: Number of scatter buffers in the above lists 3147 * @scatter_buf_size: Size of each scatter buffer 3148 * @last_buf_end_offset: Offset to the last entry 3149 * @num_entries: Total entries of all scatter bufs 3150 * 3151 * Return: None 3152 */ 3153 static inline void 3154 hal_setup_link_idle_list_generic_be(struct hal_soc *soc, 3155 qdf_dma_addr_t scatter_bufs_base_paddr[], 3156 void *scatter_bufs_base_vaddr[], 3157 uint32_t num_scatter_bufs, 3158 uint32_t scatter_buf_size, 3159 uint32_t last_buf_end_offset, 3160 uint32_t num_entries) 3161 { 3162 int i; 3163 uint32_t *prev_buf_link_ptr = NULL; 3164 uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size; 3165 uint32_t val; 3166 3167 /* Link the scatter buffers */ 3168 for (i = 0; i < num_scatter_bufs; i++) { 3169 if (i > 0) { 3170 prev_buf_link_ptr[0] = 3171 scatter_bufs_base_paddr[i] & 0xffffffff; 3172 prev_buf_link_ptr[1] = HAL_SM( 3173 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 3174 BASE_ADDRESS_39_32, 3175 ((uint64_t)(scatter_bufs_base_paddr[i]) 3176 >> 32)) | HAL_SM( 3177 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 3178 ADDRESS_MATCH_TAG, 3179 ADDRESS_MATCH_TAG_VAL); 3180 } 3181 prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] + 3182 scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE); 3183 } 3184 3185 /* TBD: Register programming partly based on MLD & the rest based on 3186 * inputs from HW team. Not complete yet. 3187 */ 3188 3189 reg_scatter_buf_size = (scatter_buf_size - 3190 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64; 3191 reg_tot_scatter_buf_size = ((scatter_buf_size - 3192 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64; 3193 3194 HAL_REG_WRITE(soc, 3195 HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR( 3196 WBM_REG_REG_BASE), 3197 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE, 3198 reg_scatter_buf_size) | 3199 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE, 3200 0x1)); 3201 3202 HAL_REG_WRITE(soc, 3203 HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR( 3204 WBM_REG_REG_BASE), 3205 HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE, 3206 SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, 3207 reg_tot_scatter_buf_size)); 3208 3209 HAL_REG_WRITE(soc, 3210 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR( 3211 WBM_REG_REG_BASE), 3212 scatter_bufs_base_paddr[0] & 0xffffffff); 3213 3214 HAL_REG_WRITE(soc, 3215 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( 3216 WBM_REG_REG_BASE), 3217 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) & 3218 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK); 3219 3220 HAL_REG_WRITE(soc, 3221 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( 3222 WBM_REG_REG_BASE), 3223 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 3224 BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0]) 3225 >> 32)) | 3226 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 3227 ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL)); 3228 3229 /* ADDRESS_MATCH_TAG field in the above register is expected to match 3230 * with the upper bits of link pointer. The above write sets this field 3231 * to zero and we are also setting the upper bits of link pointers to 3232 * zero while setting up the link list of scatter buffers above 3233 */ 3234 3235 /* Setup head and tail pointers for the idle list */ 3236 HAL_REG_WRITE(soc, 3237 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( 3238 WBM_REG_REG_BASE), 3239 scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff); 3240 HAL_REG_WRITE(soc, 3241 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR( 3242 WBM_REG_REG_BASE), 3243 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 3244 BUFFER_ADDRESS_39_32, 3245 ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1]) 3246 >> 32)) | 3247 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 3248 HEAD_POINTER_OFFSET, last_buf_end_offset >> 2)); 3249 3250 HAL_REG_WRITE(soc, 3251 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( 3252 WBM_REG_REG_BASE), 3253 scatter_bufs_base_paddr[0] & 0xffffffff); 3254 3255 HAL_REG_WRITE(soc, 3256 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR( 3257 WBM_REG_REG_BASE), 3258 scatter_bufs_base_paddr[0] & 0xffffffff); 3259 HAL_REG_WRITE(soc, 3260 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR( 3261 WBM_REG_REG_BASE), 3262 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 3263 BUFFER_ADDRESS_39_32, 3264 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 3265 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 3266 TAIL_POINTER_OFFSET, 0)); 3267 3268 HAL_REG_WRITE(soc, 3269 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR( 3270 WBM_REG_REG_BASE), 3271 2 * num_entries); 3272 3273 /* Set RING_ID_DISABLE */ 3274 val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1); 3275 3276 /* 3277 * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence 3278 * check the presence of the bit before toggling it. 3279 */ 3280 #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 3281 val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1); 3282 #endif 3283 HAL_REG_WRITE(soc, 3284 HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE), 3285 val); 3286 } 3287 3288 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 3289 #define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000 3290 #endif 3291 3292 /** 3293 * hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register 3294 * for REO/WBM 3295 * @soc: HAL soc handle 3296 * @cc_cfg: structure pointer for HW cookie conversion configuration 3297 * 3298 * Return: None 3299 */ 3300 static inline 3301 void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl, 3302 struct hal_hw_cc_config *cc_cfg) 3303 { 3304 uint32_t reg_addr, reg_val = 0; 3305 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 3306 3307 /* REO CFG */ 3308 reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE); 3309 reg_val = cc_cfg->lut_base_addr_31_0; 3310 HAL_REG_WRITE(soc, reg_addr, reg_val); 3311 3312 reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE); 3313 reg_val = 0; 3314 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3315 SW_COOKIE_CONVERT_GLOBAL_ENABLE, 3316 cc_cfg->cc_global_en); 3317 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3318 SW_COOKIE_CONVERT_ENABLE, 3319 cc_cfg->cc_global_en); 3320 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3321 PAGE_ALIGNMENT, 3322 cc_cfg->page_4k_align); 3323 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3324 COOKIE_OFFSET_MSB, 3325 cc_cfg->cookie_offset_msb); 3326 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3327 COOKIE_PAGE_MSB, 3328 cc_cfg->cookie_page_msb); 3329 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3330 CMEM_LUT_BASE_ADDR_39_32, 3331 cc_cfg->lut_base_addr_39_32); 3332 HAL_REG_WRITE(soc, reg_addr, reg_val); 3333 3334 /* WBM CFG */ 3335 reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE); 3336 reg_val = cc_cfg->lut_base_addr_31_0; 3337 HAL_REG_WRITE(soc, reg_addr, reg_val); 3338 3339 reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE); 3340 reg_val = 0; 3341 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3342 PAGE_ALIGNMENT, 3343 cc_cfg->page_4k_align); 3344 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3345 COOKIE_OFFSET_MSB, 3346 cc_cfg->cookie_offset_msb); 3347 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3348 COOKIE_PAGE_MSB, 3349 cc_cfg->cookie_page_msb); 3350 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3351 CMEM_LUT_BASE_ADDR_39_32, 3352 cc_cfg->lut_base_addr_39_32); 3353 HAL_REG_WRITE(soc, reg_addr, reg_val); 3354 3355 /* 3356 * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE, 3357 */ 3358 reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE); 3359 reg_val = 0; 3360 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3361 WBM_COOKIE_CONV_GLOBAL_ENABLE, 3362 cc_cfg->cc_global_en); 3363 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3364 WBM2SW6_COOKIE_CONVERSION_EN, 3365 cc_cfg->wbm2sw6_cc_en); 3366 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3367 WBM2SW5_COOKIE_CONVERSION_EN, 3368 cc_cfg->wbm2sw5_cc_en); 3369 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3370 WBM2SW4_COOKIE_CONVERSION_EN, 3371 cc_cfg->wbm2sw4_cc_en); 3372 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3373 WBM2SW3_COOKIE_CONVERSION_EN, 3374 cc_cfg->wbm2sw3_cc_en); 3375 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3376 WBM2SW2_COOKIE_CONVERSION_EN, 3377 cc_cfg->wbm2sw2_cc_en); 3378 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3379 WBM2SW1_COOKIE_CONVERSION_EN, 3380 cc_cfg->wbm2sw1_cc_en); 3381 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3382 WBM2SW0_COOKIE_CONVERSION_EN, 3383 cc_cfg->wbm2sw0_cc_en); 3384 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3385 WBM2FW_COOKIE_CONVERSION_EN, 3386 cc_cfg->wbm2fw_cc_en); 3387 HAL_REG_WRITE(soc, reg_addr, reg_val); 3388 3389 #ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK 3390 reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE); 3391 reg_val = 0; 3392 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3393 COOKIE_DEBUG_SEL, 3394 cc_cfg->cc_global_en); 3395 3396 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3397 COOKIE_CONV_INDICATION_EN, 3398 cc_cfg->cc_global_en); 3399 3400 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3401 ERROR_PATH_COOKIE_CONV_EN, 3402 cc_cfg->error_path_cookie_conv_en); 3403 3404 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3405 RELEASE_PATH_COOKIE_CONV_EN, 3406 cc_cfg->release_path_cookie_conv_en); 3407 3408 HAL_REG_WRITE(soc, reg_addr, reg_val); 3409 #endif 3410 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 3411 /* 3412 * To enable indication for HW cookie conversion done or not for 3413 * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th 3414 * bit spare_control[15] should be set. 3415 */ 3416 reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE); 3417 reg_val = HAL_REG_READ(soc, reg_addr); 3418 reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL, 3419 SPARE_CONTROL, 3420 HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15); 3421 HAL_REG_WRITE(soc, reg_addr, reg_val); 3422 #endif 3423 } 3424 3425 /** 3426 * hal_set_ba_aging_timeout_be - Set BA Aging timeout 3427 * 3428 * @hal_soc: Opaque HAL SOC handle 3429 * @ac: Access category 3430 * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice 3431 * @value: Input value to set 3432 */ 3433 static inline 3434 void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl, 3435 uint8_t ac, uint32_t value) 3436 { 3437 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 3438 3439 switch (ac) { 3440 case WME_AC_BE: 3441 HAL_REG_WRITE(soc, 3442 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 3443 REO_REG_REG_BASE), 3444 value * 1000); 3445 break; 3446 case WME_AC_BK: 3447 HAL_REG_WRITE(soc, 3448 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 3449 REO_REG_REG_BASE), 3450 value * 1000); 3451 break; 3452 case WME_AC_VI: 3453 HAL_REG_WRITE(soc, 3454 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 3455 REO_REG_REG_BASE), 3456 value * 1000); 3457 break; 3458 case WME_AC_VO: 3459 HAL_REG_WRITE(soc, 3460 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 3461 REO_REG_REG_BASE), 3462 value * 1000); 3463 break; 3464 default: 3465 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 3466 "Invalid AC: %d\n", ac); 3467 } 3468 } 3469 3470 /** 3471 * hal_tx_populate_bank_register() - populate the bank register with 3472 * the software configs. 3473 * @soc: HAL soc handle 3474 * @config: bank config 3475 * @bank_id: bank id to be configured 3476 * 3477 * Returns: None 3478 */ 3479 #ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT 3480 static inline void 3481 hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl, 3482 union hal_tx_bank_config *config, 3483 uint8_t bank_id) 3484 { 3485 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3486 uint32_t reg_addr, reg_val = 0; 3487 3488 reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE, 3489 bank_id); 3490 3491 reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT); 3492 reg_val |= (config->encap_type << 3493 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT); 3494 reg_val |= (config->encrypt_type << 3495 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT); 3496 reg_val |= (config->src_buffer_swap << 3497 HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT); 3498 reg_val |= (config->link_meta_swap << 3499 HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT); 3500 reg_val |= (config->index_lookup_enable << 3501 HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT); 3502 reg_val |= (config->addrx_en << 3503 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT); 3504 reg_val |= (config->addry_en << 3505 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT); 3506 reg_val |= (config->mesh_enable << 3507 HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT); 3508 reg_val |= (config->vdev_id_check_en << 3509 HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT); 3510 reg_val |= (config->pmac_id << 3511 HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT); 3512 reg_val |= (config->mcast_pkt_ctrl << 3513 HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT); 3514 3515 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3516 } 3517 #else 3518 static inline void 3519 hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl, 3520 union hal_tx_bank_config *config, 3521 uint8_t bank_id) 3522 { 3523 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3524 uint32_t reg_addr, reg_val = 0; 3525 3526 reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE, 3527 bank_id); 3528 3529 reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT); 3530 reg_val |= (config->encap_type << 3531 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT); 3532 reg_val |= (config->encrypt_type << 3533 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT); 3534 reg_val |= (config->src_buffer_swap << 3535 HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT); 3536 reg_val |= (config->link_meta_swap << 3537 HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT); 3538 reg_val |= (config->index_lookup_enable << 3539 HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT); 3540 reg_val |= (config->addrx_en << 3541 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT); 3542 reg_val |= (config->addry_en << 3543 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT); 3544 reg_val |= (config->mesh_enable << 3545 HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT); 3546 reg_val |= (config->vdev_id_check_en << 3547 HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT); 3548 reg_val |= (config->pmac_id << 3549 HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT); 3550 reg_val |= (config->dscp_tid_map_id << 3551 HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT); 3552 3553 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3554 } 3555 #endif 3556 3557 3558 #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT 3559 3560 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4) 3561 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF) 3562 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3 3563 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2 3564 3565 /** 3566 * hal_tx_vdev_mcast_ctrl_set - set mcast_ctrl value 3567 * @hal_soc: HAL SoC context 3568 * @mcast_ctrl_val: mcast ctrl value for this VAP 3569 * 3570 * Return: void 3571 */ 3572 static inline void 3573 hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl, 3574 uint8_t vdev_id, uint8_t mcast_ctrl_val) 3575 { 3576 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3577 uint32_t reg_addr, reg_val = 0; 3578 uint32_t val; 3579 uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id); 3580 uint8_t index_in_reg = 3581 HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id); 3582 3583 reg_addr = 3584 HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE, 3585 reg_idx); 3586 3587 val = HAL_REG_READ(hal_soc, reg_addr); 3588 3589 /* mask out other stored value */ 3590 val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK << 3591 (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg))); 3592 3593 reg_val = val | 3594 ((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) << 3595 (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)); 3596 3597 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3598 } 3599 #else 3600 static inline void 3601 hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl, 3602 uint8_t vdev_id, uint8_t mcast_ctrl_val) 3603 { 3604 } 3605 #endif 3606 3607 #endif /* _HAL_BE_GENERIC_API_H_ */ 3608