1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_BE_GENERIC_API_H_ 21 #define _HAL_BE_GENERIC_API_H_ 22 23 #include <hal_be_hw_headers.h> 24 #include "hal_be_tx.h" 25 #include "hal_be_reo.h" 26 #include <hal_api_mon.h> 27 #include <hal_generic_api.h> 28 #include "txmon_tlvs.h" 29 30 /** 31 * Debug macro to print the TLV header tag 32 */ 33 #define SHOW_DEFINED(x) do {} while (0) 34 35 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY) 36 static inline void 37 hal_tx_comp_get_buffer_timestamp_be(void *desc, 38 struct hal_tx_completion_status *ts) 39 { 40 ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 41 BUFFER_TIMESTAMP); 42 } 43 #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */ 44 static inline void 45 hal_tx_comp_get_buffer_timestamp_be(void *desc, 46 struct hal_tx_completion_status *ts) 47 { 48 } 49 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */ 50 51 /** 52 * hal_tx_comp_get_status() - TQM Release reason 53 * @hal_desc: completion ring Tx status 54 * 55 * This function will parse the WBM completion descriptor and populate in 56 * HAL structure 57 * 58 * Return: none 59 */ 60 static inline void 61 hal_tx_comp_get_status_generic_be(void *desc, void *ts1, 62 struct hal_soc *hal) 63 { 64 uint8_t rate_stats_valid = 0; 65 uint32_t rate_stats = 0; 66 struct hal_tx_completion_status *ts = 67 (struct hal_tx_completion_status *)ts1; 68 69 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 70 TQM_STATUS_NUMBER); 71 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 72 ACK_FRAME_RSSI); 73 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 74 FIRST_MSDU); 75 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 76 LAST_MSDU); 77 #if 0 78 // TODO - This has to be calculated form first and last msdu 79 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, 80 WBM2SW_COMPLETION_RING_TX, 81 MSDU_PART_OF_AMSDU); 82 #endif 83 84 ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 85 SW_PEER_ID); 86 ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID); 87 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 88 TRANSMIT_COUNT); 89 90 rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS); 91 92 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO, 93 TX_RATE_STATS_INFO_VALID, rate_stats); 94 95 ts->valid = rate_stats_valid; 96 97 if (rate_stats_valid) { 98 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW, 99 rate_stats); 100 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO, 101 TRANSMIT_PKT_TYPE, rate_stats); 102 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO, 103 TRANSMIT_STBC, rate_stats); 104 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC, 105 rate_stats); 106 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI, 107 rate_stats); 108 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS, 109 rate_stats); 110 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION, 111 rate_stats); 112 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU, 113 rate_stats); 114 } 115 116 ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc); 117 ts->status = hal_tx_comp_get_release_reason( 118 desc, 119 hal_soc_to_hal_soc_handle(hal)); 120 121 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 122 TX_RATE_STATS_INFO_TX_RATE_STATS); 123 hal_tx_comp_get_buffer_timestamp_be(desc, ts); 124 } 125 126 /** 127 * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table 128 * @soc: HAL SoC context 129 * @map: PCP-TID mapping table 130 * 131 * PCP are mapped to 8 TID values using TID values programmed 132 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 133 * The mapping register has TID mapping for 8 PCP values 134 * 135 * Return: none 136 */ 137 static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map) 138 { 139 uint32_t addr, value; 140 141 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 142 MAC_TCL_REG_REG_BASE); 143 144 value = (map[0] | 145 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 146 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 147 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 148 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 149 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 150 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 151 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 152 153 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 154 } 155 156 /** 157 * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with 158 * value received from user-space 159 * @soc: HAL SoC context 160 * @pcp: pcp value 161 * @tid : tid value 162 * 163 * Return: void 164 */ 165 static void 166 hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc, 167 uint8_t pcp, uint8_t tid) 168 { 169 uint32_t addr, value, regval; 170 171 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 172 MAC_TCL_REG_REG_BASE); 173 174 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 175 176 /* Read back previous PCP TID config and update 177 * with new config. 178 */ 179 regval = HAL_REG_READ(soc, addr); 180 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 181 regval |= value; 182 183 HAL_REG_WRITE(soc, addr, 184 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 185 } 186 187 /** 188 * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority 189 * @soc: HAL SoC context 190 * @val: priority value 191 * 192 * Return: void 193 */ 194 static 195 void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value) 196 { 197 uint32_t addr; 198 199 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 200 MAC_TCL_REG_REG_BASE); 201 202 HAL_REG_WRITE(soc, addr, 203 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 204 } 205 206 /** 207 * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size 208 * @rx_pkt_tlv_size: TLV size for regular RX packets 209 * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets 210 * 211 * Return: size of rx pkt tlv before the actual data 212 */ 213 static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size, 214 uint16_t *rx_mon_pkt_tlv_size) 215 { 216 *rx_pkt_tlv_size = RX_PKT_TLVS_LEN; 217 /* For now mon pkt tlv is same as rx pkt tlv */ 218 *rx_mon_pkt_tlv_size = MON_RX_PKT_TLVS_LEN; 219 } 220 221 /** 222 * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST 223 * @fst: Pointer to the Rx Flow Search Table 224 * @hal_hash: HAL 5 tuple hash 225 * @tuple_info: 5-tuple info of the flow returned to the caller 226 * 227 * Return: Success/Failure 228 */ 229 static void * 230 hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash, 231 uint8_t *flow_tuple_info) 232 { 233 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 234 void *hal_fse = NULL; 235 struct hal_flow_tuple_info *tuple_info 236 = (struct hal_flow_tuple_info *)flow_tuple_info; 237 238 hal_fse = (uint8_t *)fst->base_vaddr + 239 (hal_hash * HAL_RX_FST_ENTRY_SIZE); 240 241 if (!hal_fse || !tuple_info) 242 return NULL; 243 244 if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY, VALID)) 245 return NULL; 246 247 tuple_info->src_ip_127_96 = 248 qdf_ntohl(HAL_GET_FLD(hal_fse, 249 RX_FLOW_SEARCH_ENTRY, 250 SRC_IP_127_96)); 251 tuple_info->src_ip_95_64 = 252 qdf_ntohl(HAL_GET_FLD(hal_fse, 253 RX_FLOW_SEARCH_ENTRY, 254 SRC_IP_95_64)); 255 tuple_info->src_ip_63_32 = 256 qdf_ntohl(HAL_GET_FLD(hal_fse, 257 RX_FLOW_SEARCH_ENTRY, 258 SRC_IP_63_32)); 259 tuple_info->src_ip_31_0 = 260 qdf_ntohl(HAL_GET_FLD(hal_fse, 261 RX_FLOW_SEARCH_ENTRY, 262 SRC_IP_31_0)); 263 tuple_info->dest_ip_127_96 = 264 qdf_ntohl(HAL_GET_FLD(hal_fse, 265 RX_FLOW_SEARCH_ENTRY, 266 DEST_IP_127_96)); 267 tuple_info->dest_ip_95_64 = 268 qdf_ntohl(HAL_GET_FLD(hal_fse, 269 RX_FLOW_SEARCH_ENTRY, 270 DEST_IP_95_64)); 271 tuple_info->dest_ip_63_32 = 272 qdf_ntohl(HAL_GET_FLD(hal_fse, 273 RX_FLOW_SEARCH_ENTRY, 274 DEST_IP_63_32)); 275 tuple_info->dest_ip_31_0 = 276 qdf_ntohl(HAL_GET_FLD(hal_fse, 277 RX_FLOW_SEARCH_ENTRY, 278 DEST_IP_31_0)); 279 tuple_info->dest_port = HAL_GET_FLD(hal_fse, 280 RX_FLOW_SEARCH_ENTRY, 281 DEST_PORT); 282 tuple_info->src_port = HAL_GET_FLD(hal_fse, 283 RX_FLOW_SEARCH_ENTRY, 284 SRC_PORT); 285 tuple_info->l4_protocol = HAL_GET_FLD(hal_fse, 286 RX_FLOW_SEARCH_ENTRY, 287 L4_PROTOCOL); 288 289 return hal_fse; 290 } 291 292 /** 293 * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST 294 * @fst: Pointer to the Rx Flow Search Table 295 * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST 296 * 297 * Return: Success/Failure 298 */ 299 static QDF_STATUS 300 hal_rx_flow_delete_entry_be(uint8_t *rx_fst, void *hal_rx_fse) 301 { 302 uint8_t *fse = (uint8_t *)hal_rx_fse; 303 304 if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID)) 305 return QDF_STATUS_E_NOENT; 306 307 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 308 309 return QDF_STATUS_SUCCESS; 310 } 311 312 /** 313 * hal_rx_fst_get_fse_size_be() - Retrieve the size of each entry in Rx FST 314 * 315 * Return: size of each entry/flow in Rx FST 316 */ 317 static inline uint32_t 318 hal_rx_fst_get_fse_size_be(void) 319 { 320 return HAL_RX_FST_ENTRY_SIZE; 321 } 322 323 /* 324 * TX MONITOR 325 */ 326 327 #ifdef QCA_MONITOR_2_0_SUPPORT 328 /** 329 * hal_txmon_is_mon_buf_addr_tlv_generic_be() - api to find mon buffer tlv 330 * @tx_tlv: pointer to TLV header 331 * 332 * Return: bool based on tlv tag matches monitor buffer address tlv 333 */ 334 static inline bool 335 hal_txmon_is_mon_buf_addr_tlv_generic_be(void *tx_tlv_hdr) 336 { 337 uint32_t tlv_tag; 338 339 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr); 340 341 if (WIFIMON_BUFFER_ADDR_E == tlv_tag) 342 return true; 343 344 return false; 345 } 346 347 /** 348 * hal_txmon_populate_packet_info_generic_be() - api to populate packet info 349 * @tx_tlv: pointer to TLV header 350 * @packet_info: place holder for packet info 351 * 352 * Return: Address to void 353 */ 354 static inline void 355 hal_txmon_populate_packet_info_generic_be(void *tx_tlv, void *packet_info) 356 { 357 struct hal_mon_packet_info *pkt_info; 358 struct mon_buffer_addr *addr = (struct mon_buffer_addr *)tx_tlv; 359 360 pkt_info = (struct hal_mon_packet_info *)packet_info; 361 pkt_info->sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) | 362 (addr->buffer_virt_addr_31_0)); 363 pkt_info->dma_length = addr->dma_length + 1; 364 pkt_info->msdu_continuation = addr->msdu_continuation; 365 pkt_info->truncated = addr->truncated; 366 } 367 368 #if defined(TX_MONITOR_WORD_MASK) 369 /** 370 * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv 371 * 372 * @tx_tlv: pointer to tx_fes_setup tlv header 373 * 374 * Return: number of users 375 */ 376 static inline uint8_t 377 hal_txmon_get_num_users(void *tx_tlv) 378 { 379 hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv; 380 381 return tx_fes_setup->number_of_users; 382 } 383 384 /** 385 * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv 386 * 387 * @tx_tlv: pointer to tx_fes_setup tlv header 388 * @ppdu_info: pointer to hal_tx_ppdu_info 389 * 390 * Return: void 391 */ 392 static inline void 393 hal_txmon_parse_tx_fes_setup(void *tx_tlv, 394 struct hal_tx_ppdu_info *tx_ppdu_info) 395 { 396 hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv; 397 398 tx_ppdu_info->num_users = tx_fes_setup->number_of_users; 399 if (tx_ppdu_info->num_users == 0) 400 tx_ppdu_info->num_users = 1; 401 402 TXMON_HAL(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id; 403 TXMON_HAL_STATUS(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id; 404 } 405 406 /** 407 * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv 408 * 409 * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header 410 * @data_status_info: pointer to data hal_tx_status_info 411 * @prot_status_info: pointer to protection hal_tx_status_info 412 * 413 * Return: void 414 */ 415 static inline void 416 hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv, 417 struct hal_tx_status_info *data_status_info, 418 struct hal_tx_status_info *prot_status_info) 419 { 420 } 421 422 /** 423 * hal_txmon_parse_peer_entry() - parse peer entry tlv 424 * 425 * @tx_tlv: pointer to peer_entry tlv header 426 * @user_id: user_id 427 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 428 * @tx_status_info: pointer to hal_tx_status_info 429 * 430 * Return: void 431 */ 432 static inline void 433 hal_txmon_parse_peer_entry(void *tx_tlv, 434 uint8_t user_id, 435 struct hal_tx_ppdu_info *tx_ppdu_info, 436 struct hal_tx_status_info *tx_status_info) 437 { 438 } 439 440 /** 441 * hal_txmon_parse_queue_exten() - parse queue exten tlv 442 * 443 * @tx_tlv: pointer to queue exten tlv header 444 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 445 * 446 * Return: void 447 */ 448 static inline void 449 hal_txmon_parse_queue_exten(void *tx_tlv, 450 struct hal_tx_ppdu_info *tx_ppdu_info) 451 { 452 } 453 454 /** 455 * hal_txmon_parse_mpdu_start() - parse mpdu start tlv 456 * 457 * @tx_tlv: pointer to mpdu start tlv header 458 * @user_id: user id 459 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 460 * 461 * Return: void 462 */ 463 static inline void 464 hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id, 465 struct hal_tx_ppdu_info *tx_ppdu_info) 466 { 467 } 468 469 #else 470 /** 471 * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv 472 * 473 * @tx_tlv: pointer to tx_fes_setup tlv header 474 * 475 * Return: number of users 476 */ 477 static inline uint8_t 478 hal_txmon_get_num_users(void *tx_tlv) 479 { 480 uint8_t num_users = HAL_TX_DESC_GET_64(tx_tlv, 481 TX_FES_SETUP, NUMBER_OF_USERS); 482 483 return num_users; 484 } 485 486 /** 487 * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv 488 * 489 * @tx_tlv: pointer to tx_fes_setup tlv header 490 * @ppdu_info: pointer to hal_tx_ppdu_info 491 * 492 * Return: void 493 */ 494 static inline void 495 hal_txmon_parse_tx_fes_setup(void *tx_tlv, 496 struct hal_tx_ppdu_info *tx_ppdu_info) 497 { 498 uint32_t num_users = 0; 499 uint32_t ppdu_id = 0; 500 501 num_users = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_SETUP, NUMBER_OF_USERS); 502 ppdu_id = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_SETUP, SCHEDULE_ID); 503 504 if (num_users == 0) 505 num_users = 1; 506 507 tx_ppdu_info->num_users = num_users; 508 509 TXMON_HAL(tx_ppdu_info, ppdu_id) = ppdu_id; 510 TXMON_HAL_STATUS(tx_ppdu_info, ppdu_id) = ppdu_id; 511 } 512 513 /** 514 * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv 515 * 516 * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header 517 * @data_status_info: pointer to data hal_tx_status_info 518 * @prot_status_info: pointer to protection hal_tx_status_info 519 * 520 * Return: void 521 */ 522 static inline void 523 hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv, 524 struct hal_tx_status_info *data_status_info, 525 struct hal_tx_status_info *prot_status_info) 526 { 527 prot_status_info->protection_addr = 528 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 529 USE_ADDRESS_FIELDS_FOR_PROTECTION); 530 /* protection frame address 1 */ 531 *(uint32_t *)&prot_status_info->addr1[0] = 532 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 533 PROTECTION_FRAME_AD1_31_0); 534 *(uint32_t *)&prot_status_info->addr1[4] = 535 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 536 PROTECTION_FRAME_AD1_47_32); 537 /* protection frame address 2 */ 538 *(uint32_t *)&prot_status_info->addr2[0] = 539 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 540 PROTECTION_FRAME_AD2_15_0); 541 *(uint32_t *)&prot_status_info->addr2[2] = 542 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 543 PROTECTION_FRAME_AD2_47_16); 544 /* protection frame address 3 */ 545 *(uint32_t *)&prot_status_info->addr3[0] = 546 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 547 PROTECTION_FRAME_AD3_31_0); 548 *(uint32_t *)&prot_status_info->addr3[4] = 549 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 550 PROTECTION_FRAME_AD3_47_32); 551 /* protection frame address 4 */ 552 *(uint32_t *)&prot_status_info->addr4[0] = 553 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 554 PROTECTION_FRAME_AD4_15_0); 555 *(uint32_t *)&prot_status_info->addr4[2] = 556 HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT, 557 PROTECTION_FRAME_AD4_47_16); 558 } 559 560 /** 561 * hal_txmon_parse_peer_entry() - parse peer entry tlv 562 * 563 * @tx_tlv: pointer to peer_entry tlv header 564 * @user_id: user_id 565 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 566 * @tx_status_info: pointer to hal_tx_status_info 567 * 568 * Return: void 569 */ 570 static inline void 571 hal_txmon_parse_peer_entry(void *tx_tlv, 572 uint8_t user_id, 573 struct hal_tx_ppdu_info *tx_ppdu_info, 574 struct hal_tx_status_info *tx_status_info) 575 { 576 *(uint32_t *)&tx_status_info->addr1[0] = 577 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_A_31_0); 578 *(uint32_t *)&tx_status_info->addr1[4] = 579 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_A_47_32); 580 *(uint32_t *)&tx_status_info->addr2[0] = 581 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_B_15_0); 582 *(uint32_t *)&tx_status_info->addr2[2] = 583 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_B_47_16); 584 TXMON_HAL_USER(tx_ppdu_info, user_id, sw_peer_id) = 585 HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, SW_PEER_ID); 586 } 587 588 /** 589 * hal_txmon_parse_queue_exten() - parse queue exten tlv 590 * 591 * @tx_tlv: pointer to queue exten tlv header 592 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 593 * 594 * Return: void 595 */ 596 static inline void 597 hal_txmon_parse_queue_exten(void *tx_tlv, 598 struct hal_tx_ppdu_info *tx_ppdu_info) 599 { 600 TXMON_HAL_STATUS(tx_ppdu_info, frame_control) = 601 HAL_TX_DESC_GET_64(tx_tlv, TX_QUEUE_EXTENSION, 602 FRAME_CTL); 603 TXMON_HAL_STATUS(tx_ppdu_info, frame_control_info_valid) = true; 604 } 605 606 /** 607 * hal_txmon_parse_mpdu_start() - parse mpdu start tlv 608 * 609 * @tx_tlv: pointer to mpdu start tlv header 610 * @user_id: user id 611 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 612 * 613 * Return: void 614 */ 615 static inline void 616 hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id, 617 struct hal_tx_ppdu_info *tx_ppdu_info) 618 { 619 TXMON_HAL_USER(tx_ppdu_info, user_id, 620 start_seq) = HAL_TX_DESC_GET_64(tx_tlv, TX_MPDU_START, 621 MPDU_SEQUENCE_NUMBER); 622 TXMON_HAL(tx_ppdu_info, cur_usr_idx) = user_id; 623 } 624 #endif 625 626 /** 627 * get_ru_offset_from_start_index() - api to get ru offset from ru index 628 * 629 * @ru_size: RU size 630 * @start_idx: Start index 631 * 632 * Return: uint8_t ru allocation offset 633 */ 634 static inline 635 uint8_t get_ru_offset_from_start_index(uint8_t ru_size, uint8_t start_idx) 636 { 637 uint8_t ru_alloc_offset[HAL_MAX_DL_MU_USERS][HAL_MAX_RU_INDEX] = { 638 {0, 0, 0, 0, 0, 0, 0}, 639 {1, 0, 0, 0, 0, 0, 0}, 640 {2, 1, 0, 0, 0, 0, 0}, 641 {3, 1, 0, 0, 0, 0, 0}, 642 {4, 0, 0, 0, 0, 0, 0}, 643 {5, 2, 1, 0, 0, 0, 0}, 644 {6, 2, 1, 0, 0, 0, 0}, 645 {7, 3, 1, 0, 0, 0, 0}, 646 {8, 3, 1, 0, 0, 0, 0}, 647 {9, 4, 2, 1, 0, 0, 0}, 648 {10, 4, 2, 1, 0, 0, 0}, 649 {11, 5, 2, 1, 0, 0, 0}, 650 {12, 5, 2, 1, 0, 0, 0}, 651 {13, 0, 0, 1, 0, 0, 0}, 652 {14, 6, 3, 1, 0, 0, 0}, 653 {15, 6, 3, 1, 0, 0, 0}, 654 {16, 7, 3, 1, 0, 0, 0}, 655 {17, 7, 3, 1, 0, 0, 0}, 656 {18, 0, 0, 0, 0, 0, 0}, 657 {19, 8, 4, 2, 1, 0, 0}, 658 {20, 8, 4, 2, 1, 0, 0}, 659 {21, 9, 4, 2, 1, 0, 0}, 660 {22, 9, 4, 2, 1, 0, 0}, 661 {23, 0, 0, 2, 1, 0, 0}, 662 {24, 10, 5, 2, 1, 0, 0}, 663 {25, 10, 5, 2, 1, 0, 0}, 664 {26, 11, 5, 2, 1, 0, 0}, 665 {27, 11, 5, 2, 1, 0, 0}, 666 {28, 12, 6, 3, 1, 0, 0}, 667 {29, 12, 6, 3, 1, 0, 0}, 668 {30, 13, 6, 3, 1, 0, 0}, 669 {31, 13, 6, 3, 1, 0, 0}, 670 {32, 0, 0, 3, 1, 0, 0}, 671 {33, 14, 7, 3, 1, 0, 0}, 672 {34, 14, 7, 3, 1, 0, 0}, 673 {35, 15, 7, 3, 1, 0, 0}, 674 {36, 15, 7, 3, 1, 0, 0}, 675 }; 676 677 if (start_idx >= HAL_MAX_UL_MU_USERS || ru_size >= HAL_MAX_RU_INDEX) 678 return 0; 679 680 return ru_alloc_offset[start_idx][ru_size]; 681 } 682 683 /** 684 * hal_txmon_parse_fw2sw() - parse firmware to software tlv 685 * 686 * @tx_tlv: pointer to firmware to software tlvmpdu start tlv header 687 * @type: place where this tlv is generated 688 * @tx_status_info: pointer to hal_tx_status_info 689 * 690 * Return: void 691 */ 692 static inline void 693 hal_txmon_parse_fw2sw(void *tx_tlv, uint8_t type, 694 struct hal_tx_status_info *status_info) 695 { 696 uint32_t *msg = (uint32_t *)tx_tlv; 697 698 switch (type) { 699 case TXMON_FW2SW_TYPE_FES_SETUP: 700 { 701 uint32_t schedule_id; 702 uint16_t c_freq1; 703 uint16_t c_freq2; 704 uint16_t freq_mhz; 705 uint8_t phy_mode; 706 707 c_freq1 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_GET(*msg); 708 c_freq2 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_GET(*msg); 709 710 msg++; 711 phy_mode = TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_GET(*msg); 712 freq_mhz = TXMON_FW2SW_MON_FES_SETUP_MHZ_GET(*msg); 713 714 msg++; 715 schedule_id = TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_GET(*msg); 716 717 TXMON_STATUS_INFO(status_info, band_center_freq1) = c_freq1; 718 TXMON_STATUS_INFO(status_info, band_center_freq2) = c_freq2; 719 TXMON_STATUS_INFO(status_info, freq) = freq_mhz; 720 TXMON_STATUS_INFO(status_info, phy_mode) = phy_mode; 721 TXMON_STATUS_INFO(status_info, schedule_id) = schedule_id; 722 723 break; 724 } 725 case TXMON_FW2SW_TYPE_FES_SETUP_USER: 726 { 727 break; 728 } 729 case TXMON_FW2SW_TYPE_FES_SETUP_EXT: 730 { 731 break; 732 } 733 }; 734 } 735 736 /** 737 * hal_txmon_status_get_num_users_generic_be() - api to get num users 738 * from start of fes window 739 * 740 * @tx_tlv_hdr: pointer to TLV header 741 * @num_users: reference to number of user 742 * 743 * Return: status 744 */ 745 static inline uint32_t 746 hal_txmon_status_get_num_users_generic_be(void *tx_tlv_hdr, uint8_t *num_users) 747 { 748 uint32_t tlv_tag, user_id, tlv_len; 749 uint32_t tlv_status = HAL_MON_TX_STATUS_PPDU_NOT_DONE; 750 void *tx_tlv; 751 752 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr); 753 user_id = HAL_RX_GET_USER_TLV32_USERID(tx_tlv_hdr); 754 tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv_hdr); 755 756 tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 757 /* window starts with either initiator or response */ 758 switch (tlv_tag) { 759 case WIFITX_FES_SETUP_E: 760 { 761 *num_users = hal_txmon_get_num_users(tx_tlv); 762 if (*num_users == 0) 763 *num_users = 1; 764 765 tlv_status = HAL_MON_TX_FES_SETUP; 766 break; 767 } 768 case WIFIRX_RESPONSE_REQUIRED_INFO_E: 769 { 770 *num_users = HAL_TX_DESC_GET_64(tx_tlv, 771 RX_RESPONSE_REQUIRED_INFO, 772 RESPONSE_STA_COUNT); 773 if (*num_users == 0) 774 *num_users = 1; 775 tlv_status = HAL_MON_RX_RESPONSE_REQUIRED_INFO; 776 break; 777 } 778 }; 779 780 return tlv_status; 781 } 782 783 /** 784 * hal_tx_get_ppdu_info() - api to get tx ppdu info 785 * @pdev_handle: DP_PDEV handle 786 * @prot_ppdu_info: populate dp_ppdu_info protection 787 * @tx_data_ppdu_info: populate dp_ppdu_info data 788 * @tlv_tag: Tag 789 * 790 * Return: dp_tx_ppdu_info pointer 791 */ 792 static inline void * 793 hal_tx_get_ppdu_info(void *data_info, void *prot_info, uint32_t tlv_tag) 794 { 795 struct hal_tx_ppdu_info *prot_ppdu_info = prot_info; 796 797 switch (tlv_tag) { 798 case WIFITX_FES_SETUP_E:/* DOWNSTREAM */ 799 case WIFITX_FLUSH_E:/* DOWNSTREAM */ 800 case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */ 801 case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */ 802 case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */ 803 case WIFITX_MPDU_START_E:/* DOWNSTREAM */ 804 case WIFITX_MSDU_START_E:/* DOWNSTREAM */ 805 case WIFITX_DATA_E:/* DOWNSTREAM */ 806 case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */ 807 case WIFITX_MPDU_END_E:/* DOWNSTREAM */ 808 case WIFITX_MSDU_END_E:/* DOWNSTREAM */ 809 case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */ 810 case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */ 811 case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */ 812 case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */ 813 case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */ 814 case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */ 815 case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */ 816 case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */ 817 case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */ 818 case WIFITX_WUR_DATA_E:/* DOWNSTREAM */ 819 case WIFISCHEDULER_END_E:/* DOWNSTREAM */ 820 case WIFITX_FES_STATUS_START_PPDU_E:/* UPSTREAM */ 821 { 822 return data_info; 823 } 824 } 825 826 /* 827 * check current prot_tlv_status is start protection 828 * check current tlv_tag is either start protection or end protection 829 */ 830 if (TXMON_HAL(prot_ppdu_info, 831 prot_tlv_status) == WIFITX_FES_STATUS_START_PROT_E) { 832 return prot_info; 833 } else if (tlv_tag == WIFITX_FES_STATUS_PROT_E || 834 tlv_tag == WIFITX_FES_STATUS_START_PROT_E) { 835 TXMON_HAL(prot_ppdu_info, prot_tlv_status) = tlv_tag; 836 return prot_info; 837 } 838 839 return data_info; 840 } 841 842 /** 843 * hal_txmon_status_parse_tlv_generic_be() - api to parse status tlv. 844 * @data_ppdu_info: hal_txmon data ppdu info 845 * @prot_ppdu_info: hal_txmon prot ppdu info 846 * @data_status_info: pointer to data status info 847 * @prot_status_info: pointer to prot status info 848 * @tx_tlv_hdr: fragment of tx_tlv_hdr 849 * @status_frag: qdf_frag_t buffer 850 * 851 * Return: status 852 */ 853 static inline uint32_t 854 hal_txmon_status_parse_tlv_generic_be(void *data_ppdu_info, 855 void *prot_ppdu_info, 856 void *data_status_info, 857 void *prot_status_info, 858 void *tx_tlv_hdr, 859 qdf_frag_t status_frag) 860 { 861 struct hal_tx_ppdu_info *ppdu_info; 862 struct hal_tx_status_info *tx_status_info; 863 struct hal_mon_packet_info *packet_info = NULL; 864 uint32_t tlv_tag, user_id, tlv_len, tlv_user_id; 865 uint32_t status = HAL_MON_TX_STATUS_PPDU_NOT_DONE; 866 void *tx_tlv; 867 868 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr); 869 tlv_user_id = HAL_RX_GET_USER_TLV64_USERID(tx_tlv_hdr); 870 tlv_len = HAL_RX_GET_USER_TLV64_LEN(tx_tlv_hdr); 871 872 tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 873 874 /* parse tlv and populate tx_ppdu_info */ 875 ppdu_info = hal_tx_get_ppdu_info(data_ppdu_info, 876 prot_ppdu_info, tlv_tag); 877 tx_status_info = (ppdu_info->is_data ? data_status_info : 878 prot_status_info); 879 880 user_id = (tlv_user_id > ppdu_info->num_users ? 0 : tlv_user_id); 881 882 switch (tlv_tag) { 883 /* start of initiator FES window */ 884 case WIFITX_FES_SETUP_E:/* DOWNSTREAM */ 885 { 886 /* initiator PPDU window start */ 887 hal_txmon_parse_tx_fes_setup(tx_tlv, ppdu_info); 888 889 status = HAL_MON_TX_FES_SETUP; 890 SHOW_DEFINED(WIFITX_FES_SETUP_E); 891 break; 892 } 893 /* end of initiator FES window */ 894 case WIFITX_FES_STATUS_END_E:/* UPSTREAM */ 895 { 896 /* initiator PPDU window end */ 897 uint32_t ppdu_timestamp_start = 0; 898 uint32_t ppdu_timestamp_end = 0; 899 uint16_t phy_abort_reason = 0; 900 uint8_t phy_abort_is_valid = 0; 901 uint8_t abort_usr_id = 0; 902 uint8_t response_type = 0; 903 uint8_t r2r_end_status_follow = 0; 904 905 status = HAL_MON_TX_FES_STATUS_END; 906 907 ppdu_timestamp_start = 908 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 909 START_OF_FRAME_TIMESTAMP_15_0) | 910 (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 911 START_OF_FRAME_TIMESTAMP_31_16) << 912 HAL_TX_LSB(TX_FES_STATUS_END, 913 START_OF_FRAME_TIMESTAMP_31_16)); 914 ppdu_timestamp_end = 915 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 916 END_OF_FRAME_TIMESTAMP_15_0) | 917 (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 918 END_OF_FRAME_TIMESTAMP_31_16) << 919 HAL_TX_LSB(TX_FES_STATUS_END, 920 END_OF_FRAME_TIMESTAMP_31_16)); 921 922 response_type = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 923 RESPONSE_TYPE); 924 /* 925 * r2r end status follow to inform whether to look for 926 * rx_response_required_info 927 */ 928 r2r_end_status_follow = 929 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 930 R2R_END_STATUS_TO_FOLLOW); 931 932 phy_abort_is_valid = 933 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 934 PHYTX_ABORT_REQUEST_INFO_VALID); 935 936 if (phy_abort_is_valid) { 937 phy_abort_reason = 938 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 939 PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON); 940 941 abort_usr_id = 942 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END, 943 PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER); 944 945 TXMON_STATUS_INFO(tx_status_info, 946 phy_abort_reason) = phy_abort_reason; 947 TXMON_STATUS_INFO(tx_status_info, 948 phy_abort_user_number) = abort_usr_id; 949 } 950 951 TXMON_STATUS_INFO(tx_status_info, 952 response_type) = response_type; 953 TXMON_STATUS_INFO(tx_status_info, 954 r2r_to_follow) = r2r_end_status_follow; 955 956 /* update phy timestamp to ppdu timestamp */ 957 TXMON_HAL_STATUS(ppdu_info, 958 ppdu_timestamp) = ppdu_timestamp_start; 959 960 SHOW_DEFINED(WIFITX_FES_STATUS_END_E); 961 break; 962 } 963 /* response window open */ 964 case WIFIRX_RESPONSE_REQUIRED_INFO_E:/* UPSTREAM */ 965 { 966 /* response PPDU window start */ 967 uint32_t ppdu_id = 0; 968 uint8_t reception_type = 0; 969 uint8_t response_sta_count = 0; 970 971 status = HAL_MON_RX_RESPONSE_REQUIRED_INFO; 972 973 ppdu_id = HAL_TX_DESC_GET_64(tx_tlv, 974 RX_RESPONSE_REQUIRED_INFO, 975 PHY_PPDU_ID); 976 reception_type = 977 HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO, 978 SU_OR_UPLINK_MU_RECEPTION); 979 response_sta_count = 980 HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO, 981 RESPONSE_STA_COUNT); 982 983 /* get mac address */ 984 *(uint32_t *)&tx_status_info->addr1[0] = 985 HAL_TX_DESC_GET_64(tx_tlv, 986 RX_RESPONSE_REQUIRED_INFO, 987 ADDR1_31_0); 988 *(uint32_t *)&tx_status_info->addr1[4] = 989 HAL_TX_DESC_GET_64(tx_tlv, 990 RX_RESPONSE_REQUIRED_INFO, 991 ADDR1_47_32); 992 *(uint32_t *)&tx_status_info->addr2[0] = 993 HAL_TX_DESC_GET_64(tx_tlv, 994 RX_RESPONSE_REQUIRED_INFO, 995 ADDR2_15_0); 996 *(uint32_t *)&tx_status_info->addr2[2] = 997 HAL_TX_DESC_GET_64(tx_tlv, 998 RX_RESPONSE_REQUIRED_INFO, 999 ADDR2_47_16); 1000 1001 TXMON_HAL(ppdu_info, ppdu_id) = ppdu_id; 1002 TXMON_HAL_STATUS(ppdu_info, ppdu_id) = ppdu_id; 1003 1004 if (response_sta_count == 0) 1005 response_sta_count = 1; 1006 TXMON_HAL(ppdu_info, num_users) = response_sta_count; 1007 1008 if (reception_type) 1009 TXMON_STATUS_INFO(tx_status_info, 1010 transmission_type) = 1011 TXMON_SU_TRANSMISSION; 1012 else 1013 TXMON_STATUS_INFO(tx_status_info, 1014 transmission_type) = 1015 TXMON_MU_TRANSMISSION; 1016 1017 SHOW_DEFINED(WIFIRX_RESPONSE_REQUIRED_INFO_E); 1018 break; 1019 } 1020 /* Response window close */ 1021 case WIFIRESPONSE_END_STATUS_E:/* UPSTREAM */ 1022 { 1023 /* response PPDU window end */ 1024 uint8_t generated_response = 0; 1025 uint32_t bandwidth = 0; 1026 uint32_t ppdu_timestamp_start = 0; 1027 uint32_t ppdu_timestamp_end = 0; 1028 uint32_t mba_usr_cnt = 0; 1029 uint32_t mba_fake_bitmap_cnt = 0; 1030 1031 status = HAL_MON_RESPONSE_END_STATUS_INFO; 1032 generated_response = HAL_TX_DESC_GET_64(tx_tlv, 1033 RESPONSE_END_STATUS, 1034 GENERATED_RESPONSE); 1035 mba_usr_cnt = HAL_TX_DESC_GET_64(tx_tlv, 1036 RESPONSE_END_STATUS, 1037 MBA_USER_COUNT); 1038 mba_fake_bitmap_cnt = HAL_TX_DESC_GET_64(tx_tlv, 1039 RESPONSE_END_STATUS, 1040 MBA_FAKE_BITMAP_COUNT); 1041 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 1042 COEX_BASED_TX_BW); 1043 /* 32 bits TSF */ 1044 ppdu_timestamp_start = 1045 (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 1046 START_OF_FRAME_TIMESTAMP_15_0) | 1047 (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 1048 START_OF_FRAME_TIMESTAMP_31_16) << 1049 16)); 1050 ppdu_timestamp_end = 1051 (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 1052 END_OF_FRAME_TIMESTAMP_15_0) | 1053 (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS, 1054 END_OF_FRAME_TIMESTAMP_31_16) << 1055 16)); 1056 1057 TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth; 1058 /* update phy timestamp to ppdu timestamp */ 1059 TXMON_HAL_STATUS(ppdu_info, 1060 ppdu_timestamp) = ppdu_timestamp_start; 1061 1062 TXMON_STATUS_INFO(tx_status_info, 1063 generated_response) = generated_response; 1064 TXMON_STATUS_INFO(tx_status_info, mba_count) = mba_usr_cnt; 1065 TXMON_STATUS_INFO(tx_status_info, 1066 mba_fake_bitmap_count) = mba_fake_bitmap_cnt; 1067 1068 SHOW_DEFINED(WIFIRESPONSE_END_STATUS_E); 1069 break; 1070 } 1071 case WIFITX_FLUSH_E:/* DOWNSTREAM */ 1072 { 1073 SHOW_DEFINED(WIFITX_FLUSH_E); 1074 break; 1075 } 1076 1077 /* Downstream tlv */ 1078 case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */ 1079 { 1080 hal_txmon_parse_pcu_ppdu_setup_init(tx_tlv, data_status_info, 1081 prot_status_info); 1082 1083 status = HAL_MON_TX_PCU_PPDU_SETUP_INIT; 1084 SHOW_DEFINED(WIFIPCU_PPDU_SETUP_INIT_E); 1085 break; 1086 } 1087 case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */ 1088 { 1089 hal_txmon_parse_peer_entry(tx_tlv, user_id, 1090 ppdu_info, tx_status_info); 1091 SHOW_DEFINED(WIFITX_PEER_ENTRY_E); 1092 break; 1093 } 1094 case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */ 1095 { 1096 status = HAL_MON_TX_QUEUE_EXTENSION; 1097 hal_txmon_parse_queue_exten(tx_tlv, ppdu_info); 1098 1099 SHOW_DEFINED(WIFITX_QUEUE_EXTENSION_E); 1100 break; 1101 } 1102 /* payload and data frame handling */ 1103 case WIFITX_MPDU_START_E:/* DOWNSTREAM */ 1104 { 1105 hal_txmon_parse_mpdu_start(tx_tlv, user_id, ppdu_info); 1106 1107 status = HAL_MON_TX_MPDU_START; 1108 SHOW_DEFINED(WIFITX_MPDU_START_E); 1109 break; 1110 } 1111 case WIFITX_MSDU_START_E:/* DOWNSTREAM */ 1112 { 1113 /* compacted */ 1114 /* we expect frame to be 802.11 frame type */ 1115 status = HAL_MON_TX_MSDU_START; 1116 SHOW_DEFINED(WIFITX_MSDU_START_E); 1117 break; 1118 } 1119 case WIFITX_DATA_E:/* DOWNSTREAM */ 1120 { 1121 status = HAL_MON_TX_DATA; 1122 /* 1123 * TODO: do we need a conversion api to convert 1124 * user_id from hw to get host user_index 1125 */ 1126 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1127 TXMON_STATUS_INFO(tx_status_info, 1128 buffer) = (void *)status_frag; 1129 TXMON_STATUS_INFO(tx_status_info, 1130 offset) = ((void *)tx_tlv - 1131 (void *)status_frag); 1132 TXMON_STATUS_INFO(tx_status_info, 1133 length) = tlv_len; 1134 1135 /* 1136 * reference of the status buffer will be held in 1137 * dp_tx_update_ppdu_info_status() 1138 */ 1139 status = HAL_MON_TX_DATA; 1140 SHOW_DEFINED(WIFITX_DATA_E); 1141 break; 1142 } 1143 case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */ 1144 { 1145 packet_info = &ppdu_info->packet_info; 1146 status = HAL_MON_TX_BUFFER_ADDR; 1147 /* 1148 * TODO: do we need a conversion api to convert 1149 * user_id from hw to get host user_index 1150 */ 1151 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1152 1153 hal_txmon_populate_packet_info_generic_be(tx_tlv, packet_info); 1154 1155 SHOW_DEFINED(WIFIMON_BUFFER_ADDR_E); 1156 break; 1157 } 1158 case WIFITX_MPDU_END_E:/* DOWNSTREAM */ 1159 { 1160 /* no tlv content */ 1161 SHOW_DEFINED(WIFITX_MPDU_END_E); 1162 break; 1163 } 1164 case WIFITX_MSDU_END_E:/* DOWNSTREAM */ 1165 { 1166 /* no tlv content */ 1167 SHOW_DEFINED(WIFITX_MSDU_END_E); 1168 break; 1169 } 1170 case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */ 1171 { 1172 /* no tlv content */ 1173 SHOW_DEFINED(WIFITX_LAST_MPDU_FETCHED_E); 1174 break; 1175 } 1176 case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */ 1177 { 1178 /* no tlv content */ 1179 SHOW_DEFINED(WIFITX_LAST_MPDU_END_E); 1180 break; 1181 } 1182 case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */ 1183 { 1184 /* 1185 * transmitting power 1186 * minimum transmitting power 1187 * desired nss 1188 * tx chain mask 1189 * desired bw 1190 * duration of transmit and response 1191 * 1192 * since most of the field we are deriving from other tlv 1193 * we don't need to enable this in our tlv. 1194 */ 1195 SHOW_DEFINED(WIFICOEX_TX_REQ_E); 1196 break; 1197 } 1198 case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */ 1199 { 1200 /* user tlv */ 1201 /* 1202 * All Tx monitor will have 802.11 hdr 1203 * we don't need to enable this TLV 1204 */ 1205 SHOW_DEFINED(WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E); 1206 break; 1207 } 1208 case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */ 1209 { 1210 /* 1211 * no tlv content 1212 * 1213 * TLV that indicates to TXPCU that preamble phase for the NDP 1214 * frame transmission is now over 1215 */ 1216 SHOW_DEFINED(WIFINDP_PREAMBLE_DONE_E); 1217 break; 1218 } 1219 case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */ 1220 { 1221 /* 1222 * no tlv content 1223 * 1224 * TLV indicates to the SCH that all timing critical TLV 1225 * has been passed on to the transmit path 1226 */ 1227 SHOW_DEFINED(WIFISCH_CRITICAL_TLV_REFERENCE_E); 1228 break; 1229 } 1230 case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */ 1231 { 1232 /* 1233 * Loopback specific setup info - not needed for Tx monitor 1234 */ 1235 SHOW_DEFINED(WIFITX_LOOPBACK_SETUP_E); 1236 break; 1237 } 1238 case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */ 1239 { 1240 /* 1241 * no tlv content 1242 * 1243 * TLV indicates that other modules besides the scheduler can 1244 * now also start generating TLV's 1245 * prevent colliding or generating TLV's out of order 1246 */ 1247 SHOW_DEFINED(WIFITX_FES_SETUP_COMPLETE_E); 1248 break; 1249 } 1250 case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */ 1251 { 1252 /* 1253 * no tlv content 1254 * 1255 * TLV indicates to SCH that a burst of MPDU info will 1256 * start to come in over the TLV 1257 */ 1258 SHOW_DEFINED(WIFITQM_MPDU_GLOBAL_START_E); 1259 break; 1260 } 1261 case WIFITX_WUR_DATA_E:/* DOWNSTREAM */ 1262 { 1263 SHOW_DEFINED(WIFITX_WUR_DATA_E); 1264 break; 1265 } 1266 case WIFISCHEDULER_END_E:/* DOWNSTREAM */ 1267 { 1268 /* 1269 * no tlv content 1270 * 1271 * TLV indicates END of all TLV's within the scheduler TLV 1272 */ 1273 SHOW_DEFINED(WIFISCHEDULER_END_E); 1274 break; 1275 } 1276 1277 /* Upstream tlv */ 1278 case WIFIPDG_TX_REQ_E: 1279 { 1280 SHOW_DEFINED(WIFIPDG_TX_REQ_E); 1281 break; 1282 } 1283 case WIFITX_FES_STATUS_START_E: 1284 { 1285 /* 1286 * TLV indicating that first transmission on the medium 1287 */ 1288 uint8_t medium_prot_type = 0; 1289 1290 status = HAL_MON_TX_FES_STATUS_START; 1291 1292 medium_prot_type = HAL_TX_DESC_GET_64(tx_tlv, 1293 TX_FES_STATUS_START, 1294 MEDIUM_PROT_TYPE); 1295 1296 ppdu_info = (struct hal_tx_ppdu_info *)prot_ppdu_info; 1297 /* update what type of medium protection frame */ 1298 TXMON_STATUS_INFO(tx_status_info, 1299 medium_prot_type) = medium_prot_type; 1300 SHOW_DEFINED(WIFITX_FES_STATUS_START_E); 1301 break; 1302 } 1303 case WIFITX_FES_STATUS_PROT_E: 1304 { 1305 uint32_t start_timestamp = 0; 1306 uint32_t end_timestamp = 0; 1307 1308 /* 1309 * generated by TXPCU to indicate the result of having 1310 * received of the expected protection frame 1311 */ 1312 1313 status = HAL_MON_TX_FES_STATUS_PROT; 1314 start_timestamp = 1315 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT, 1316 START_OF_FRAME_TIMESTAMP_15_0); 1317 start_timestamp |= 1318 (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT, 1319 START_OF_FRAME_TIMESTAMP_31_16) << 1320 15); 1321 end_timestamp = HAL_TX_DESC_GET_64(tx_tlv, 1322 TX_FES_STATUS_PROT, 1323 END_OF_FRAME_TIMESTAMP_15_0); 1324 end_timestamp |= 1325 HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT, 1326 END_OF_FRAME_TIMESTAMP_31_16) << 15; 1327 1328 /* ppdu timestamp as phy timestamp */ 1329 TXMON_HAL_STATUS(ppdu_info, 1330 ppdu_timestamp) = start_timestamp; 1331 1332 SHOW_DEFINED(WIFITX_FES_STATUS_PROT_E); 1333 break; 1334 } 1335 case WIFITX_FES_STATUS_START_PROT_E: 1336 { 1337 uint64_t tsft_64; 1338 uint32_t response_type; 1339 status = HAL_MON_TX_FES_STATUS_START_PROT; 1340 TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag; 1341 /* timestamp */ 1342 tsft_64 = HAL_TX_DESC_GET_64(tx_tlv, 1343 TX_FES_STATUS_START_PROT, 1344 PROT_TIMESTAMP_LOWER_32); 1345 tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv, 1346 TX_FES_STATUS_START_PROT, 1347 PROT_TIMESTAMP_UPPER_32) << 32); 1348 1349 response_type = HAL_TX_DESC_GET_64(tx_tlv, 1350 TX_FES_STATUS_START_PROT, 1351 RESPONSE_TYPE); 1352 1353 TXMON_STATUS_INFO(tx_status_info, 1354 response_type) = response_type; 1355 TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64; 1356 1357 SHOW_DEFINED(WIFITX_FES_STATUS_START_PROT_E); 1358 break; 1359 } 1360 case WIFIPROT_TX_END_E: 1361 { 1362 /* 1363 * no tlv content 1364 * 1365 * generated by TXPCU the moment that protection frame 1366 * transmission has finished on the medium 1367 */ 1368 SHOW_DEFINED(WIFIPROT_TX_END_E); 1369 break; 1370 } 1371 case WIFITX_FES_STATUS_START_PPDU_E: 1372 { 1373 uint64_t tsft_64; 1374 uint8_t ndp_frame; 1375 1376 status = HAL_MON_TX_FES_STATUS_START_PPDU; 1377 tsft_64 = HAL_TX_DESC_GET_64(tx_tlv, 1378 TX_FES_STATUS_START_PPDU, 1379 PPDU_TIMESTAMP_LOWER_32); 1380 tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv, 1381 TX_FES_STATUS_START_PPDU, 1382 PPDU_TIMESTAMP_UPPER_32) << 32); 1383 1384 ndp_frame = HAL_TX_DESC_GET_64(tx_tlv, 1385 TX_FES_STATUS_START_PPDU, 1386 NDP_FRAME); 1387 1388 TXMON_STATUS_INFO(tx_status_info, ndp_frame) = ndp_frame; 1389 TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64; 1390 1391 SHOW_DEFINED(WIFITX_FES_STATUS_START_PPDU_E); 1392 break; 1393 } 1394 case WIFITX_FES_STATUS_USER_PPDU_E: 1395 { 1396 /* user tlv */ 1397 uint16_t duration; 1398 uint8_t transmitted_tid; 1399 1400 duration = HAL_TX_DESC_GET_64(tx_tlv, 1401 TX_FES_STATUS_USER_PPDU, 1402 DURATION); 1403 transmitted_tid = HAL_TX_DESC_GET_64(tx_tlv, 1404 TX_FES_STATUS_USER_PPDU, 1405 TRANSMITTED_TID); 1406 1407 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1408 TXMON_HAL_USER(ppdu_info, user_id, tid) = transmitted_tid; 1409 TXMON_HAL_USER(ppdu_info, user_id, duration) = duration; 1410 1411 status = HAL_MON_TX_FES_STATUS_USER_PPDU; 1412 SHOW_DEFINED(WIFITX_FES_STATUS_USER_PPDU_E); 1413 break; 1414 } 1415 case WIFIPPDU_TX_END_E: 1416 { 1417 /* 1418 * no tlv content 1419 * 1420 * generated by TXPCU the moment that PPDU transmission has 1421 * finished on the medium 1422 */ 1423 SHOW_DEFINED(WIFIPPDU_TX_END_E); 1424 break; 1425 } 1426 1427 case WIFITX_FES_STATUS_USER_RESPONSE_E: 1428 { 1429 /* 1430 * TLV contains the FES transmit result of the each 1431 * of the MAC users. TLV are forwarded to HWSCH 1432 */ 1433 SHOW_DEFINED(WIFITX_FES_STATUS_USER_RESPONSE_E); 1434 break; 1435 } 1436 case WIFITX_FES_STATUS_ACK_OR_BA_E: 1437 { 1438 /* user tlv */ 1439 /* 1440 * TLV generated by RXPCU and provide information related to 1441 * the received BA or ACK frame 1442 */ 1443 SHOW_DEFINED(WIFITX_FES_STATUS_ACK_OR_BA_E); 1444 break; 1445 } 1446 case WIFITX_FES_STATUS_1K_BA_E: 1447 { 1448 /* user tlv */ 1449 /* 1450 * TLV generated by RXPCU and providing information related 1451 * to the received BA frame in case of 512/1024 bitmaps 1452 */ 1453 SHOW_DEFINED(WIFITX_FES_STATUS_1K_BA_E); 1454 break; 1455 } 1456 case WIFIRECEIVED_RESPONSE_USER_7_0_E: 1457 { 1458 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_7_0_E); 1459 break; 1460 } 1461 case WIFIRECEIVED_RESPONSE_USER_15_8_E: 1462 { 1463 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_15_8_E); 1464 break; 1465 } 1466 case WIFIRECEIVED_RESPONSE_USER_23_16_E: 1467 { 1468 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_23_16_E); 1469 break; 1470 } 1471 case WIFIRECEIVED_RESPONSE_USER_31_24_E: 1472 { 1473 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_31_24_E); 1474 break; 1475 } 1476 case WIFIRECEIVED_RESPONSE_USER_36_32_E: 1477 { 1478 /* 1479 * RXPCU generates this TLV when it receives a response frame 1480 * that TXPCU pre-announced it was waiting for and in 1481 * RXPCU_SETUP TLV, TLV generated before the 1482 * RECEIVED_RESPONSE_INFO TLV. 1483 * 1484 * received info user fields are there which is not needed 1485 * for TX monitor 1486 */ 1487 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_36_32_E); 1488 break; 1489 } 1490 1491 case WIFITXPCU_BUFFER_STATUS_E: 1492 { 1493 SHOW_DEFINED(WIFITXPCU_BUFFER_STATUS_E); 1494 break; 1495 } 1496 case WIFITXPCU_USER_BUFFER_STATUS_E: 1497 { 1498 /* 1499 * WIFITXPCU_USER_BUFFER_STATUS_E - user tlv 1500 * for TX monitor we aren't interested in this tlv 1501 */ 1502 SHOW_DEFINED(WIFITXPCU_USER_BUFFER_STATUS_E); 1503 break; 1504 } 1505 case WIFITXDMA_STOP_REQUEST_E: 1506 { 1507 /* 1508 * no tlv content 1509 * 1510 * TLV is destined to TXDMA and informs TXDMA to stop 1511 * pushing data into the transmit path. 1512 */ 1513 SHOW_DEFINED(WIFITXDMA_STOP_REQUEST_E); 1514 break; 1515 } 1516 case WIFITX_CBF_INFO_E: 1517 { 1518 /* 1519 * After NDPA + NDP is received, RXPCU sends the TX_CBF_INFO to 1520 * TXPCU to respond the CBF frame 1521 * 1522 * compressed beamforming pkt doesn't has mac header 1523 * Tx monitor not interested in this pkt. 1524 */ 1525 SHOW_DEFINED(WIFITX_CBF_INFO_E); 1526 break; 1527 } 1528 case WIFITX_MPDU_COUNT_TRANSFER_END_E: 1529 { 1530 /* 1531 * no tlv content 1532 * 1533 * TLV indicates that TXPCU has finished generating the 1534 * TQM_UPDATE_TX_MPDU_COUNT TLV for all users 1535 */ 1536 SHOW_DEFINED(WIFITX_MPDU_COUNT_TRANSFER_END_E); 1537 break; 1538 } 1539 case WIFIPDG_RESPONSE_E: 1540 { 1541 /* 1542 * most of the feilds are already covered in 1543 * other TLV 1544 * This is generated by TX_PCU to PDG to calculate 1545 * all the PHY header info. 1546 * 1547 * some useful fields like min transmit power, 1548 * rate used for transmitting packet is present. 1549 */ 1550 SHOW_DEFINED(WIFIPDG_RESPONSE_E); 1551 break; 1552 } 1553 case WIFIPDG_TRIG_RESPONSE_E: 1554 { 1555 /* no tlv content */ 1556 SHOW_DEFINED(WIFIPDG_TRIG_RESPONSE_E); 1557 break; 1558 } 1559 case WIFIRECEIVED_TRIGGER_INFO_E: 1560 { 1561 /* 1562 * TLV generated by RXPCU to inform the scheduler that 1563 * a trigger frame has been received 1564 */ 1565 SHOW_DEFINED(WIFIRECEIVED_TRIGGER_INFO_E); 1566 break; 1567 } 1568 case WIFIOFDMA_TRIGGER_DETAILS_E: 1569 { 1570 SHOW_DEFINED(WIFIOFDMA_TRIGGER_DETAILS_E); 1571 break; 1572 } 1573 case WIFIRX_FRAME_BITMAP_ACK_E: 1574 { 1575 /* user tlv */ 1576 status = HAL_MON_RX_FRAME_BITMAP_ACK; 1577 SHOW_DEFINED(WIFIRX_FRAME_BITMAP_ACK_E); 1578 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1579 TXMON_STATUS_INFO(tx_status_info, no_bitmap_avail) = 1580 HAL_TX_DESC_GET_64(tx_tlv, 1581 RX_FRAME_BITMAP_ACK, 1582 NO_BITMAP_AVAILABLE); 1583 1584 TXMON_STATUS_INFO(tx_status_info, explicit_ack) = 1585 HAL_TX_DESC_GET_64(tx_tlv, 1586 RX_FRAME_BITMAP_ACK, 1587 EXPLICIT_ACK); 1588 /* 1589 * get mac address, since address is received frame 1590 * change the order and store it 1591 */ 1592 *(uint32_t *)&tx_status_info->addr2[0] = 1593 HAL_TX_DESC_GET_64(tx_tlv, 1594 RX_FRAME_BITMAP_ACK, 1595 ADDR1_31_0); 1596 *(uint32_t *)&tx_status_info->addr2[4] = 1597 HAL_TX_DESC_GET_64(tx_tlv, 1598 RX_FRAME_BITMAP_ACK, 1599 ADDR1_47_32); 1600 *(uint32_t *)&tx_status_info->addr1[0] = 1601 HAL_TX_DESC_GET_64(tx_tlv, 1602 RX_FRAME_BITMAP_ACK, 1603 ADDR2_15_0); 1604 *(uint32_t *)&tx_status_info->addr1[2] = 1605 HAL_TX_DESC_GET_64(tx_tlv, 1606 RX_FRAME_BITMAP_ACK, 1607 ADDR2_47_16); 1608 1609 TXMON_STATUS_INFO(tx_status_info, explicit_ack_type) = 1610 HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_BITMAP_ACK, 1611 EXPLICT_ACK_TYPE); 1612 1613 TXMON_HAL_USER(ppdu_info, user_id, tid) = 1614 HAL_TX_DESC_GET_64(tx_tlv, 1615 RX_FRAME_BITMAP_ACK, 1616 BA_TID); 1617 TXMON_HAL_USER(ppdu_info, user_id, aid) = 1618 HAL_TX_DESC_GET_64(tx_tlv, 1619 RX_FRAME_BITMAP_ACK, 1620 STA_FULL_AID); 1621 TXMON_HAL_USER(ppdu_info, user_id, start_seq) = 1622 HAL_TX_DESC_GET_64(tx_tlv, 1623 RX_FRAME_BITMAP_ACK, 1624 BA_TS_SEQ); 1625 TXMON_HAL_USER(ppdu_info, user_id, ba_control) = 1626 HAL_TX_DESC_GET_64(tx_tlv, 1627 RX_FRAME_BITMAP_ACK, 1628 BA_TS_CTRL); 1629 TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) = 1630 HAL_TX_DESC_GET_64(tx_tlv, 1631 RX_FRAME_BITMAP_ACK, 1632 BA_BITMAP_SIZE); 1633 1634 /* ba bitmap */ 1635 qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap), 1636 &HAL_SET_FLD_OFFSET_64(tx_tlv, 1637 RX_FRAME_BITMAP_ACK, 1638 BA_TS_BITMAP_31_0, 0), 32); 1639 1640 break; 1641 } 1642 case WIFIRX_FRAME_1K_BITMAP_ACK_E: 1643 { 1644 /* user tlv */ 1645 status = HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K; 1646 SHOW_DEFINED(WIFIRX_FRAME_1K_BITMAP_ACK_E); 1647 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1648 TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) = 1649 (4 + HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_1K_BITMAP_ACK, 1650 BA_BITMAP_SIZE)); 1651 TXMON_HAL_USER(ppdu_info, user_id, tid) = 1652 HAL_TX_DESC_GET_64(tx_tlv, 1653 RX_FRAME_1K_BITMAP_ACK, 1654 BA_TID); 1655 TXMON_HAL_USER(ppdu_info, user_id, aid) = 1656 HAL_TX_DESC_GET_64(tx_tlv, 1657 RX_FRAME_1K_BITMAP_ACK, 1658 STA_FULL_AID); 1659 /* get mac address */ 1660 *(uint32_t *)&tx_status_info->addr1[0] = 1661 HAL_TX_DESC_GET_64(tx_tlv, 1662 RX_FRAME_1K_BITMAP_ACK, 1663 ADDR1_31_0); 1664 *(uint32_t *)&tx_status_info->addr1[4] = 1665 HAL_TX_DESC_GET_64(tx_tlv, 1666 RX_FRAME_1K_BITMAP_ACK, 1667 ADDR1_47_32); 1668 *(uint32_t *)&tx_status_info->addr2[0] = 1669 HAL_TX_DESC_GET_64(tx_tlv, 1670 RX_FRAME_1K_BITMAP_ACK, 1671 ADDR2_15_0); 1672 *(uint32_t *)&tx_status_info->addr2[2] = 1673 HAL_TX_DESC_GET_64(tx_tlv, 1674 RX_FRAME_1K_BITMAP_ACK, 1675 ADDR2_47_16); 1676 1677 TXMON_HAL_USER(ppdu_info, user_id, start_seq) = 1678 HAL_TX_DESC_GET_64(tx_tlv, 1679 RX_FRAME_1K_BITMAP_ACK, 1680 BA_TS_SEQ); 1681 TXMON_HAL_USER(ppdu_info, user_id, ba_control) = 1682 HAL_TX_DESC_GET_64(tx_tlv, 1683 RX_FRAME_1K_BITMAP_ACK, 1684 BA_TS_CTRL); 1685 /* memcpy ba bitmap */ 1686 qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap), 1687 &HAL_SET_FLD_OFFSET_64(tx_tlv, 1688 RX_FRAME_1K_BITMAP_ACK, 1689 BA_TS_BITMAP_31_0, 0), 1690 4 << TXMON_HAL_USER(ppdu_info, 1691 user_id, ba_bitmap_sz)); 1692 1693 break; 1694 } 1695 case WIFIRESPONSE_START_STATUS_E: 1696 { 1697 /* 1698 * TLV indicates which HW response the TXPCU 1699 * started generating 1700 * 1701 * HW generated frames like 1702 * ACK frame - handled 1703 * CTS frame - handled 1704 * BA frame - handled 1705 * MBA frame - handled 1706 * CBF frame - no frame header 1707 * Trigger response - TODO 1708 * NDP LMR - no frame header 1709 */ 1710 SHOW_DEFINED(WIFIRESPONSE_START_STATUS_E); 1711 break; 1712 } 1713 case WIFIRX_START_PARAM_E: 1714 { 1715 /* 1716 * RXPCU send this TLV after PHY RX detected a frame 1717 * in the medium 1718 * 1719 * TX monitor not interested in this TLV 1720 */ 1721 SHOW_DEFINED(WIFIRX_START_PARAM_E); 1722 break; 1723 } 1724 case WIFIRXPCU_EARLY_RX_INDICATION_E: 1725 { 1726 /* 1727 * early indication of pkt type and mcs rate 1728 * already captured in other tlv 1729 */ 1730 SHOW_DEFINED(WIFIRXPCU_EARLY_RX_INDICATION_E); 1731 break; 1732 } 1733 case WIFIRX_PM_INFO_E: 1734 { 1735 SHOW_DEFINED(WIFIRX_PM_INFO_E); 1736 break; 1737 } 1738 1739 /* Active window */ 1740 case WIFITX_FLUSH_REQ_E: 1741 { 1742 SHOW_DEFINED(WIFITX_FLUSH_REQ_E); 1743 break; 1744 } 1745 case WIFICOEX_TX_STATUS_E: 1746 { 1747 /* duration are retrieved from coex tx status */ 1748 uint16_t duration; 1749 uint8_t status_reason; 1750 1751 status = HAL_MON_COEX_TX_STATUS; 1752 duration = HAL_TX_DESC_GET_64(tx_tlv, 1753 COEX_TX_STATUS, 1754 CURRENT_TX_DURATION); 1755 status_reason = HAL_TX_DESC_GET_64(tx_tlv, 1756 COEX_TX_STATUS, 1757 TX_STATUS_REASON); 1758 1759 /* update duration */ 1760 if (status_reason == COEX_FES_TX_START || 1761 status_reason == COEX_RESPONSE_TX_START) 1762 TXMON_HAL_USER(ppdu_info, user_id, duration) = duration; 1763 1764 SHOW_DEFINED(WIFICOEX_TX_STATUS_E); 1765 break; 1766 } 1767 case WIFIR2R_STATUS_END_E: 1768 { 1769 SHOW_DEFINED(WIFIR2R_STATUS_END_E); 1770 break; 1771 } 1772 case WIFIRX_PREAMBLE_E: 1773 { 1774 SHOW_DEFINED(WIFIRX_PREAMBLE_E); 1775 break; 1776 } 1777 case WIFIMACTX_SERVICE_E: 1778 { 1779 SHOW_DEFINED(WIFIMACTX_SERVICE_E); 1780 break; 1781 } 1782 1783 case WIFIMACTX_U_SIG_EHT_SU_MU_E: 1784 { 1785 SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_SU_MU_E); 1786 break; 1787 } 1788 case WIFIMACTX_U_SIG_EHT_TB_E: 1789 { 1790 /* TODO: no radiotap info available */ 1791 SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_TB_E); 1792 break; 1793 } 1794 case WIFIMACTX_EHT_SIG_USR_OFDMA_E: 1795 { 1796 SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_OFDMA_E); 1797 break; 1798 } 1799 case WIFIMACTX_EHT_SIG_USR_MU_MIMO_E: 1800 { 1801 SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_MU_MIMO_E); 1802 break; 1803 } 1804 case WIFIMACTX_EHT_SIG_USR_SU_E: 1805 { 1806 SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_SU_E); 1807 /* TODO: no radiotap info available */ 1808 break; 1809 } 1810 1811 case WIFIMACTX_HE_SIG_A_SU_E: 1812 { 1813 uint16_t he_mu_flag_1 = 0; 1814 uint16_t he_mu_flag_2 = 0; 1815 uint16_t num_users = 0; 1816 uint8_t mcs_of_sig_b = 0; 1817 uint8_t dcm_of_sig_b = 0; 1818 uint8_t sig_a_bw = 0; 1819 uint8_t i = 0; 1820 uint8_t bss_color_id; 1821 uint8_t coding; 1822 uint8_t stbc; 1823 uint8_t a_factor; 1824 uint8_t pe_disambiguity; 1825 uint8_t txbf; 1826 uint8_t txbw; 1827 uint8_t txop; 1828 1829 status = HAL_MON_MACTX_HE_SIG_A_SU; 1830 num_users = TXMON_HAL(ppdu_info, num_users); 1831 1832 mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1833 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1834 TRANSMIT_MCS); 1835 dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1836 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1837 DCM); 1838 sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv, 1839 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1840 TRANSMIT_BW); 1841 1842 bss_color_id = HAL_TX_DESC_GET_64(tx_tlv, 1843 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1844 BSS_COLOR_ID); 1845 coding = HAL_TX_DESC_GET_64(tx_tlv, 1846 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1847 CODING); 1848 stbc = HAL_TX_DESC_GET_64(tx_tlv, 1849 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1850 STBC); 1851 a_factor = HAL_TX_DESC_GET_64(tx_tlv, 1852 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1853 PACKET_EXTENSION_A_FACTOR); 1854 pe_disambiguity = HAL_TX_DESC_GET_64(tx_tlv, 1855 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1856 PACKET_EXTENSION_PE_DISAMBIGUITY); 1857 txbf = HAL_TX_DESC_GET_64(tx_tlv, 1858 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1859 TXBF); 1860 txbw = HAL_TX_DESC_GET_64(tx_tlv, 1861 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1862 TRANSMIT_BW); 1863 txop = HAL_TX_DESC_GET_64(tx_tlv, 1864 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 1865 TXOP_DURATION); 1866 1867 he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1868 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1869 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN | 1870 QDF_MON_STATUS_CHANNEL_1_RU_KNOWN | 1871 QDF_MON_STATUS_CHANNEL_2_RU_KNOWN | 1872 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN; 1873 1874 /* MCS */ 1875 he_mu_flag_1 |= mcs_of_sig_b << 1876 QDF_MON_STATUS_SIG_B_MCS_SHIFT; 1877 /* DCM */ 1878 he_mu_flag_1 |= dcm_of_sig_b << 1879 QDF_MON_STATUS_SIG_B_DCM_SHIFT; 1880 /* bandwidth */ 1881 he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN; 1882 he_mu_flag_2 |= sig_a_bw << 1883 QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT; 1884 1885 TXMON_HAL_STATUS(ppdu_info, 1886 he_mu_flags) = IS_MULTI_USERS(num_users); 1887 for (i = 0; i < num_users; i++) { 1888 TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1; 1889 TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2; 1890 } 1891 1892 /* HE data 1 */ 1893 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 1894 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1895 QDF_MON_STATUS_HE_CODING_KNOWN; 1896 1897 /* HE data 2 */ 1898 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= 1899 QDF_MON_STATUS_TXBF_KNOWN | 1900 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1901 QDF_MON_STATUS_TXOP_KNOWN | 1902 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1903 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1904 1905 /* HE data 3 */ 1906 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 1907 bss_color_id | 1908 (!!txbf << QDF_MON_STATUS_BEAM_CHANGE_SHIFT) | 1909 (coding << QDF_MON_STATUS_CODING_SHIFT) | 1910 (stbc << QDF_MON_STATUS_STBC_SHIFT); 1911 1912 /* HE data 6 */ 1913 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= 1914 (txop << QDF_MON_STATUS_TXOP_SHIFT); 1915 1916 SHOW_DEFINED(WIFIMACTX_HE_SIG_A_SU_E); 1917 break; 1918 } 1919 case WIFIMACTX_HE_SIG_A_MU_DL_E: 1920 { 1921 uint16_t he_mu_flag_1 = 0; 1922 uint16_t he_mu_flag_2 = 0; 1923 uint16_t num_users = 0; 1924 uint8_t bss_color_id; 1925 uint8_t txop; 1926 uint8_t mcs_of_sig_b = 0; 1927 uint8_t dcm_of_sig_b = 0; 1928 uint8_t sig_a_bw = 0; 1929 uint8_t num_sig_b_symb = 0; 1930 uint8_t comp_mode_sig_b = 0; 1931 uint8_t punc_bw = 0; 1932 uint8_t i = 0; 1933 1934 status = HAL_MON_MACTX_HE_SIG_A_MU_DL; 1935 num_users = TXMON_HAL(ppdu_info, num_users); 1936 1937 mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1938 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1939 MCS_OF_SIG_B); 1940 dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1941 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1942 DCM_OF_SIG_B); 1943 sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv, 1944 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1945 TRANSMIT_BW); 1946 num_sig_b_symb = HAL_TX_DESC_GET_64(tx_tlv, 1947 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1948 NUM_SIG_B_SYMBOLS); 1949 comp_mode_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 1950 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1951 COMP_MODE_SIG_B); 1952 bss_color_id = HAL_TX_DESC_GET_64(tx_tlv, 1953 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1954 BSS_COLOR_ID); 1955 txop = HAL_TX_DESC_GET_64(tx_tlv, 1956 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 1957 TXOP_DURATION); 1958 1959 he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1960 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1961 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1962 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN | 1963 QDF_MON_STATUS_CHANNEL_1_RU_KNOWN | 1964 QDF_MON_STATUS_CHANNEL_2_RU_KNOWN | 1965 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN | 1966 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1967 QDF_MON_STATUS_SIG_B_SYMBOL_USER_KNOWN; 1968 1969 /* MCS */ 1970 he_mu_flag_1 |= mcs_of_sig_b << 1971 QDF_MON_STATUS_SIG_B_MCS_SHIFT; 1972 /* DCM */ 1973 he_mu_flag_1 |= dcm_of_sig_b << 1974 QDF_MON_STATUS_SIG_B_DCM_SHIFT; 1975 /* Compression */ 1976 he_mu_flag_2 |= comp_mode_sig_b << 1977 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1978 /* bandwidth */ 1979 he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN; 1980 he_mu_flag_2 |= sig_a_bw << 1981 QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT; 1982 he_mu_flag_2 |= comp_mode_sig_b << 1983 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1984 /* number of symbol */ 1985 he_mu_flag_2 |= num_sig_b_symb << 1986 QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1987 /* puncture bw */ 1988 he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_KNOWN; 1989 punc_bw = sig_a_bw; 1990 he_mu_flag_2 |= 1991 punc_bw << QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_SHIFT; 1992 1993 /* copy per user info to all user */ 1994 TXMON_HAL_STATUS(ppdu_info, 1995 he_mu_flags) = IS_MULTI_USERS(num_users); 1996 for (i = 0; i < num_users; i++) { 1997 TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1; 1998 TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2; 1999 } 2000 2001 /* HE data 1 */ 2002 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 2003 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN; 2004 2005 /* HE data 2 */ 2006 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= 2007 QDF_MON_STATUS_TXOP_KNOWN; 2008 2009 /* HE data 3 */ 2010 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= bss_color_id; 2011 2012 /* HE data 6 */ 2013 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= 2014 (txop << QDF_MON_STATUS_TXOP_SHIFT); 2015 2016 SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_DL_E); 2017 break; 2018 } 2019 case WIFIMACTX_HE_SIG_A_MU_UL_E: 2020 { 2021 SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_UL_E); 2022 break; 2023 } 2024 case WIFIMACTX_HE_SIG_B1_MU_E: 2025 { 2026 status = HAL_MON_MACTX_HE_SIG_B1_MU; 2027 SHOW_DEFINED(WIFIMACTX_HE_SIG_B1_MU_E); 2028 break; 2029 } 2030 case WIFIMACTX_HE_SIG_B2_MU_E: 2031 { 2032 /* user tlv */ 2033 uint16_t sta_id = 0; 2034 uint16_t sta_spatial_config = 0; 2035 uint8_t sta_mcs = 0; 2036 uint8_t coding = 0; 2037 uint8_t nss = 0; 2038 uint8_t user_order = 0; 2039 2040 status = HAL_MON_MACTX_HE_SIG_B2_MU; 2041 2042 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 2043 2044 sta_id = HAL_TX_DESC_GET_64(tx_tlv, 2045 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2046 STA_ID); 2047 sta_spatial_config = HAL_TX_DESC_GET_64(tx_tlv, 2048 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2049 STA_SPATIAL_CONFIG); 2050 sta_mcs = HAL_TX_DESC_GET_64(tx_tlv, 2051 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2052 STA_MCS); 2053 coding = HAL_TX_DESC_GET_64(tx_tlv, 2054 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2055 STA_CODING); 2056 nss = HAL_TX_DESC_GET_64(tx_tlv, 2057 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2058 NSTS) + 1; 2059 user_order = HAL_TX_DESC_GET_64(tx_tlv, 2060 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2061 USER_ORDER); 2062 2063 /* HE data 1 */ 2064 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 2065 QDF_MON_STATUS_HE_MCS_KNOWN | 2066 QDF_MON_STATUS_HE_CODING_KNOWN; 2067 /* HE data 2 */ 2068 2069 /* HE data 3 */ 2070 TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs; 2071 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2072 sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2073 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2074 coding << QDF_MON_STATUS_CODING_SHIFT; 2075 2076 /* HE data 4 */ 2077 TXMON_HAL_USER(ppdu_info, user_id, he_data4) |= 2078 sta_id << QDF_MON_STATUS_STA_ID_SHIFT; 2079 2080 /* HE data 5 */ 2081 2082 /* HE data 6 */ 2083 TXMON_HAL_USER(ppdu_info, user_id, nss) = nss; 2084 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss; 2085 2086 SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_MU_E); 2087 break; 2088 } 2089 case WIFIMACTX_HE_SIG_B2_OFDMA_E: 2090 { 2091 /* user tlv */ 2092 uint8_t *he_sig_b2_ofdma_info = NULL; 2093 uint16_t sta_id = 0; 2094 uint8_t nss = 0; 2095 uint8_t txbf = 0; 2096 uint8_t sta_mcs = 0; 2097 uint8_t sta_dcm = 0; 2098 uint8_t coding = 0; 2099 uint8_t user_order = 0; 2100 2101 status = HAL_MON_MACTX_HE_SIG_B2_OFDMA; 2102 2103 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 2104 2105 he_sig_b2_ofdma_info = (uint8_t *)tx_tlv + 2106 HAL_OFFSET(MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2107 STA_ID); 2108 2109 sta_id = HAL_TX_DESC_GET_64(tx_tlv, 2110 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2111 STA_ID); 2112 nss = HAL_TX_DESC_GET_64(tx_tlv, 2113 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2114 NSTS); 2115 txbf = HAL_TX_DESC_GET_64(tx_tlv, 2116 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2117 TXBF); 2118 sta_mcs = HAL_TX_DESC_GET_64(tx_tlv, 2119 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2120 STA_MCS); 2121 sta_dcm = HAL_TX_DESC_GET_64(tx_tlv, 2122 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2123 STA_DCM); 2124 coding = HAL_TX_DESC_GET_64(tx_tlv, 2125 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2126 STA_CODING); 2127 user_order = HAL_TX_DESC_GET_64(tx_tlv, 2128 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2129 USER_ORDER); 2130 2131 /* HE data 1 */ 2132 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 2133 QDF_MON_STATUS_HE_MCS_KNOWN | 2134 QDF_MON_STATUS_HE_CODING_KNOWN | 2135 QDF_MON_STATUS_HE_DCM_KNOWN; 2136 /* HE data 2 */ 2137 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= 2138 QDF_MON_STATUS_TXBF_KNOWN; 2139 2140 /* HE data 3 */ 2141 TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs; 2142 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2143 sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2144 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2145 sta_dcm << QDF_MON_STATUS_DCM_SHIFT; 2146 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2147 coding << QDF_MON_STATUS_CODING_SHIFT; 2148 2149 /* HE data 4 */ 2150 TXMON_HAL_USER(ppdu_info, user_id, he_data4) |= 2151 sta_id << QDF_MON_STATUS_STA_ID_SHIFT; 2152 2153 /* HE data 5 */ 2154 TXMON_HAL_USER(ppdu_info, user_id, he_data5) |= 2155 txbf << QDF_MON_STATUS_TXBF_SHIFT; 2156 2157 /* HE data 6 */ 2158 TXMON_HAL_USER(ppdu_info, user_id, nss) = nss; 2159 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss; 2160 2161 SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_OFDMA_E); 2162 break; 2163 } 2164 case WIFIMACTX_L_SIG_A_E: 2165 { 2166 uint8_t *l_sig_a_info = NULL; 2167 uint8_t rate = 0; 2168 2169 status = HAL_MON_MACTX_L_SIG_A; 2170 2171 l_sig_a_info = (uint8_t *)tx_tlv + 2172 HAL_OFFSET(MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS, 2173 RATE); 2174 rate = HAL_TX_DESC_GET_64(tx_tlv, 2175 MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS, 2176 RATE); 2177 2178 switch (rate) { 2179 case 8: 2180 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_0MCS; 2181 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0; 2182 break; 2183 case 9: 2184 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_1MCS; 2185 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1; 2186 break; 2187 case 10: 2188 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_2MCS; 2189 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2; 2190 break; 2191 case 11: 2192 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_3MCS; 2193 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3; 2194 break; 2195 case 12: 2196 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_4MCS; 2197 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4; 2198 break; 2199 case 13: 2200 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_5MCS; 2201 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5; 2202 break; 2203 case 14: 2204 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_6MCS; 2205 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6; 2206 break; 2207 case 15: 2208 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_7MCS; 2209 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS7; 2210 break; 2211 default: 2212 break; 2213 } 2214 2215 TXMON_HAL_STATUS(ppdu_info, ofdm_flag) = 1; 2216 TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU; 2217 TXMON_HAL_STATUS(ppdu_info, l_sig_a_info) = *l_sig_a_info; 2218 2219 SHOW_DEFINED(WIFIMACTX_L_SIG_A_E); 2220 break; 2221 } 2222 case WIFIMACTX_L_SIG_B_E: 2223 { 2224 uint8_t *l_sig_b_info = NULL; 2225 uint8_t rate = 0; 2226 2227 status = HAL_MON_MACTX_L_SIG_B; 2228 2229 l_sig_b_info = (uint8_t *)tx_tlv + 2230 HAL_OFFSET(MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS, 2231 RATE); 2232 rate = HAL_TX_DESC_GET_64(tx_tlv, 2233 MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS, 2234 RATE); 2235 2236 switch (rate) { 2237 case 1: 2238 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_3MCS; 2239 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3; 2240 break; 2241 case 2: 2242 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_2MCS; 2243 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2; 2244 break; 2245 case 3: 2246 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_1MCS; 2247 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1; 2248 break; 2249 case 4: 2250 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_0MCS; 2251 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0; 2252 break; 2253 case 5: 2254 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_6MCS; 2255 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6; 2256 break; 2257 case 6: 2258 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_5MCS; 2259 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5; 2260 break; 2261 case 7: 2262 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_4MCS; 2263 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4; 2264 break; 2265 default: 2266 break; 2267 } 2268 2269 TXMON_HAL_STATUS(ppdu_info, cck_flag) = 1; 2270 TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU; 2271 TXMON_HAL_STATUS(ppdu_info, l_sig_b_info) = *l_sig_b_info; 2272 2273 SHOW_DEFINED(WIFIMACTX_L_SIG_B_E); 2274 break; 2275 } 2276 case WIFIMACTX_HT_SIG_E: 2277 { 2278 uint8_t mcs = 0; 2279 uint8_t bw = 0; 2280 uint8_t is_stbc = 0; 2281 uint8_t coding = 0; 2282 uint8_t gi = 0; 2283 2284 status = HAL_MON_MACTX_HT_SIG; 2285 mcs = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, MCS); 2286 bw = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, CBW); 2287 is_stbc = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, STBC); 2288 coding = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, FEC_CODING); 2289 gi = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, SHORT_GI); 2290 2291 TXMON_HAL_STATUS(ppdu_info, ldpc) = 2292 (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0; 2293 TXMON_HAL_STATUS(ppdu_info, ht_mcs) = mcs; 2294 TXMON_HAL_STATUS(ppdu_info, bw) = bw; 2295 TXMON_HAL_STATUS(ppdu_info, sgi) = gi; 2296 TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc; 2297 TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU; 2298 2299 SHOW_DEFINED(WIFIMACTX_HT_SIG_E); 2300 break; 2301 } 2302 case WIFIMACTX_VHT_SIG_A_E: 2303 { 2304 uint8_t bandwidth = 0; 2305 uint8_t is_stbc = 0; 2306 uint8_t group_id = 0; 2307 uint32_t nss_comb = 0; 2308 uint8_t nss_su = 0; 2309 uint8_t nss_mu[4] = {0}; 2310 uint8_t sgi = 0; 2311 uint8_t coding = 0; 2312 uint8_t mcs = 0; 2313 uint8_t beamformed = 0; 2314 uint8_t partial_aid = 0; 2315 2316 status = HAL_MON_MACTX_VHT_SIG_A; 2317 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, 2318 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2319 BANDWIDTH); 2320 is_stbc = HAL_TX_DESC_GET_64(tx_tlv, 2321 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2322 STBC); 2323 group_id = HAL_TX_DESC_GET_64(tx_tlv, 2324 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2325 GROUP_ID); 2326 /* nss_comb is su nss, MU nss and partial AID */ 2327 nss_comb = HAL_TX_DESC_GET_64(tx_tlv, 2328 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2329 N_STS); 2330 /* if it is SU */ 2331 nss_su = (nss_comb & 0x7) + 1; 2332 /* partial aid - applicable only for SU */ 2333 partial_aid = (nss_comb >> 3) & 0x1F; 2334 /* if it is MU */ 2335 nss_mu[0] = (nss_comb & 0x7) + 1; 2336 nss_mu[1] = ((nss_comb >> 3) & 0x7) + 1; 2337 nss_mu[2] = ((nss_comb >> 6) & 0x7) + 1; 2338 nss_mu[3] = ((nss_comb >> 9) & 0x7) + 1; 2339 2340 sgi = HAL_TX_DESC_GET_64(tx_tlv, 2341 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2342 GI_SETTING); 2343 coding = HAL_TX_DESC_GET_64(tx_tlv, 2344 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2345 SU_MU_CODING); 2346 mcs = HAL_TX_DESC_GET_64(tx_tlv, 2347 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2348 MCS); 2349 beamformed = HAL_TX_DESC_GET_64(tx_tlv, 2350 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2351 BEAMFORMED); 2352 2353 TXMON_HAL_STATUS(ppdu_info, ldpc) = 2354 (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0; 2355 TXMON_STATUS_INFO(tx_status_info, sw_frame_group_id) = group_id; 2356 2357 TXMON_HAL_STATUS(ppdu_info, sgi) = sgi; 2358 TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc; 2359 TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth; 2360 TXMON_HAL_STATUS(ppdu_info, beamformed) = beamformed; 2361 2362 if (group_id == 0 || group_id == 63) { 2363 TXMON_HAL_STATUS(ppdu_info, reception_type) = 2364 HAL_RX_TYPE_SU; 2365 TXMON_HAL_STATUS(ppdu_info, mcs) = mcs; 2366 TXMON_HAL_STATUS(ppdu_info, nss) = 2367 nss_su & VHT_SIG_SU_NSS_MASK; 2368 2369 TXMON_HAL_USER(ppdu_info, user_id, 2370 vht_flag_values3[0]) = ((mcs << 4) | 2371 nss_su); 2372 } else { 2373 TXMON_HAL_STATUS(ppdu_info, reception_type) = 2374 HAL_RX_TYPE_MU_MIMO; 2375 TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs; 2376 TXMON_HAL_USER(ppdu_info, user_id, nss) = 2377 nss_su & VHT_SIG_SU_NSS_MASK; 2378 2379 TXMON_HAL_USER(ppdu_info, user_id, 2380 vht_flag_values3[0]) = ((mcs << 4) | 2381 nss_su); 2382 TXMON_HAL_USER(ppdu_info, user_id, 2383 vht_flag_values3[1]) = ((mcs << 4) | 2384 nss_mu[1]); 2385 TXMON_HAL_USER(ppdu_info, user_id, 2386 vht_flag_values3[2]) = ((mcs << 4) | 2387 nss_mu[2]); 2388 TXMON_HAL_USER(ppdu_info, user_id, 2389 vht_flag_values3[3]) = ((mcs << 4) | 2390 nss_mu[3]); 2391 } 2392 2393 /* TODO: loop over multiple user */ 2394 TXMON_HAL_USER(ppdu_info, user_id, 2395 vht_flag_values2) = bandwidth; 2396 TXMON_HAL_USER(ppdu_info, user_id, 2397 vht_flag_values4) = coding; 2398 TXMON_HAL_USER(ppdu_info, user_id, 2399 vht_flag_values5) = group_id; 2400 TXMON_HAL_USER(ppdu_info, user_id, 2401 vht_flag_values6) = partial_aid; 2402 SHOW_DEFINED(WIFIMACTX_VHT_SIG_A_E); 2403 break; 2404 } 2405 case WIFIMACTX_VHT_SIG_B_MU160_E: 2406 { 2407 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU160_E); 2408 break; 2409 } 2410 case WIFIMACTX_VHT_SIG_B_MU80_E: 2411 { 2412 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU80_E); 2413 break; 2414 } 2415 case WIFIMACTX_VHT_SIG_B_MU40_E: 2416 { 2417 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU40_E); 2418 break; 2419 } 2420 case WIFIMACTX_VHT_SIG_B_MU20_E: 2421 { 2422 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU20_E); 2423 break; 2424 } 2425 case WIFIMACTX_VHT_SIG_B_SU160_E: 2426 { 2427 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU160_E); 2428 break; 2429 } 2430 case WIFIMACTX_VHT_SIG_B_SU80_E: 2431 { 2432 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU80_E); 2433 break; 2434 } 2435 case WIFIMACTX_VHT_SIG_B_SU40_E: 2436 { 2437 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU40_E); 2438 break; 2439 } 2440 case WIFIMACTX_VHT_SIG_B_SU20_E: 2441 { 2442 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU20_E); 2443 break; 2444 } 2445 case WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E: 2446 { 2447 SHOW_DEFINED(WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E); 2448 break; 2449 } 2450 case WIFIMACTX_USER_DESC_PER_USER_E: 2451 { 2452 /* user tlv */ 2453 uint32_t bf = 0; 2454 uint32_t psdu_length = 0; 2455 uint8_t ru_start_index = 0; 2456 uint8_t ru_size = 0; 2457 uint8_t nss = 0; 2458 uint8_t mcs = 0; 2459 uint8_t dcm = 0; 2460 uint8_t fec_type = 0; 2461 uint8_t is_ldpc_extra_symb = 0; 2462 uint32_t he_data1 = TXMON_HAL_USER(ppdu_info, user_id, 2463 he_data1); 2464 uint32_t he_data2 = TXMON_HAL_USER(ppdu_info, user_id, 2465 he_data2); 2466 uint32_t he_data3 = TXMON_HAL_USER(ppdu_info, user_id, 2467 he_data3); 2468 uint32_t he_data5 = TXMON_HAL_USER(ppdu_info, user_id, 2469 he_data5); 2470 uint32_t he_data6 = TXMON_HAL_USER(ppdu_info, user_id, 2471 he_data6); 2472 2473 status = HAL_MON_MACTX_USER_DESC_PER_USER; 2474 2475 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 2476 2477 psdu_length = HAL_TX_DESC_GET_64(tx_tlv, 2478 MACTX_USER_DESC_PER_USER, 2479 PSDU_LENGTH); 2480 ru_start_index = HAL_TX_DESC_GET_64(tx_tlv, 2481 MACTX_USER_DESC_PER_USER, 2482 RU_START_INDEX); 2483 ru_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 2484 RU_SIZE); 2485 bf = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 2486 USER_BF_TYPE); 2487 2488 nss = HAL_TX_DESC_GET_64(tx_tlv, 2489 MACTX_USER_DESC_PER_USER, NSS) + 1; 2490 mcs = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, MCS); 2491 dcm = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, DCM); 2492 fec_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 2493 FEC_TYPE); 2494 is_ldpc_extra_symb = 2495 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 2496 LDPC_EXTRA_SYMBOL); 2497 2498 if (!TXMON_HAL_STATUS(ppdu_info, he_flags)) 2499 break; 2500 2501 /* update */ 2502 /* BEAM CHANGE */ 2503 he_data1 |= QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN; 2504 he_data1 |= QDF_MON_STATUS_TXBF_KNOWN; 2505 he_data5 |= (!!bf << QDF_MON_STATUS_TXBF_SHIFT); 2506 he_data3 |= (!!bf << QDF_MON_STATUS_BEAM_CHANGE_SHIFT); 2507 2508 /* UL/DL known */ 2509 he_data1 |= QDF_MON_STATUS_HE_DL_UL_KNOWN; 2510 he_data3 |= (1 << QDF_MON_STATUS_DL_UL_SHIFT); 2511 2512 /* MCS */ 2513 he_data1 |= QDF_MON_STATUS_HE_MCS_KNOWN; 2514 he_data3 |= (mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT); 2515 /* DCM */ 2516 he_data1 |= QDF_MON_STATUS_HE_DCM_KNOWN; 2517 he_data3 |= (dcm << QDF_MON_STATUS_DCM_SHIFT); 2518 /* LDPC EXTRA SYMB */ 2519 he_data1 |= QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN; 2520 he_data3 |= (is_ldpc_extra_symb << 2521 QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT); 2522 /* RU offset and RU */ 2523 he_data2 |= QDF_MON_STATUS_RU_ALLOCATION_OFFSET_KNOWN; 2524 he_data2 |= (get_ru_offset_from_start_index(ru_size, 2525 ru_start_index) << 2526 QDF_MON_STATUS_RU_ALLOCATION_SHIFT); 2527 2528 /* Data BW and RU allocation */ 2529 if (ru_size < HAL_MAX_RU_INDEX) { 2530 /* update bandwidth if it is full bandwidth */ 2531 he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 2532 he_data5 = (he_data5 & 0xFFF0) | (4 + ru_size); 2533 } 2534 2535 he_data6 |= (nss & 0xF); 2536 TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs; 2537 2538 /* update stack variable to ppdu_info */ 2539 TXMON_HAL_USER(ppdu_info, user_id, he_data1) = he_data1; 2540 TXMON_HAL_USER(ppdu_info, user_id, he_data2) = he_data2; 2541 TXMON_HAL_USER(ppdu_info, user_id, he_data3) = he_data3; 2542 TXMON_HAL_USER(ppdu_info, user_id, he_data5) = he_data5; 2543 TXMON_HAL_USER(ppdu_info, user_id, he_data6) = he_data6; 2544 2545 SHOW_DEFINED(WIFIMACTX_USER_DESC_PER_USER_E); 2546 break; 2547 } 2548 case WIFIMACTX_USER_DESC_COMMON_E: 2549 { 2550 uint16_t he_mu_flag_1 = 0; 2551 uint16_t he_mu_flag_2 = 0; 2552 uint16_t ru_channel_1[4] = {0}; 2553 uint16_t ru_channel_2[4] = {0}; 2554 uint16_t num_users = 0; 2555 uint8_t doppler; 2556 uint8_t ltf_size; 2557 uint8_t num_ltf_symbols; 2558 uint8_t pkt_extn_pe; 2559 uint8_t a_factor; 2560 uint8_t center_ru_0; 2561 uint8_t center_ru_1; 2562 uint8_t i = 0; 2563 2564 num_users = TXMON_HAL(ppdu_info, num_users); 2565 2566 doppler = HAL_TX_DESC_GET_64(tx_tlv, 2567 MACTX_USER_DESC_COMMON, 2568 DOPPLER_INDICATION); 2569 2570 ltf_size = HAL_TX_DESC_GET_64(tx_tlv, 2571 MACTX_USER_DESC_COMMON, 2572 LTF_SIZE); 2573 2574 num_ltf_symbols = HAL_TX_DESC_GET_64(tx_tlv, 2575 MACTX_USER_DESC_COMMON, 2576 NUM_DATA_SYMBOLS); 2577 2578 pkt_extn_pe = HAL_TX_DESC_GET_64(tx_tlv, 2579 MACTX_USER_DESC_COMMON, 2580 PACKET_EXTENSION_PE_DISAMBIGUITY); 2581 2582 a_factor = HAL_TX_DESC_GET_64(tx_tlv, 2583 MACTX_USER_DESC_COMMON, 2584 PACKET_EXTENSION_A_FACTOR); 2585 2586 center_ru_0 = HAL_TX_DESC_GET_64(tx_tlv, 2587 MACTX_USER_DESC_COMMON, 2588 CENTER_RU_0); 2589 2590 center_ru_1 = HAL_TX_DESC_GET_64(tx_tlv, 2591 MACTX_USER_DESC_COMMON, 2592 CENTER_RU_1); 2593 2594 ru_channel_1[0] = HAL_TX_DESC_GET_64(tx_tlv, 2595 MACTX_USER_DESC_COMMON, 2596 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0); 2597 ru_channel_1[1] = HAL_TX_DESC_GET_64(tx_tlv, 2598 MACTX_USER_DESC_COMMON, 2599 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1); 2600 ru_channel_1[2] = HAL_TX_DESC_GET_64(tx_tlv, 2601 MACTX_USER_DESC_COMMON, 2602 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2); 2603 ru_channel_1[3] = HAL_TX_DESC_GET_64(tx_tlv, 2604 MACTX_USER_DESC_COMMON, 2605 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3); 2606 2607 ru_channel_2[0] = HAL_TX_DESC_GET_64(tx_tlv, 2608 MACTX_USER_DESC_COMMON, 2609 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0); 2610 ru_channel_2[1] = HAL_TX_DESC_GET_64(tx_tlv, 2611 MACTX_USER_DESC_COMMON, 2612 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1); 2613 ru_channel_2[2] = HAL_TX_DESC_GET_64(tx_tlv, 2614 MACTX_USER_DESC_COMMON, 2615 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2); 2616 ru_channel_2[3] = HAL_TX_DESC_GET_64(tx_tlv, 2617 MACTX_USER_DESC_COMMON, 2618 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3); 2619 2620 /* HE data 1 */ 2621 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 2622 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 2623 2624 /* HE data 2 */ 2625 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= 2626 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 2627 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN; 2628 2629 /* HE data 5 */ 2630 TXMON_HAL_USER(ppdu_info, user_id, he_data5) |= 2631 (pkt_extn_pe << 2632 QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT) | 2633 (a_factor << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT) | 2634 ((1 + ltf_size) << 2635 QDF_MON_STATUS_HE_LTF_SIZE_SHIFT) | 2636 (num_ltf_symbols << 2637 QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 2638 2639 /* HE data 6 */ 2640 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= 2641 (doppler << QDF_MON_STATUS_DOPPLER_SHIFT); 2642 2643 /* number of symbol */ 2644 he_mu_flag_1 |= 2645 (QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN | 2646 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN | 2647 ((center_ru_0 << 2648 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_SHIFT) & 2649 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_VALUE)); 2650 2651 he_mu_flag_2 |= ((center_ru_1 << 2652 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_SHIFT) & 2653 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_VALUE); 2654 2655 TXMON_HAL_STATUS(ppdu_info, 2656 he_mu_flags) = IS_MULTI_USERS(num_users); 2657 for (i = 0; i < num_users; i++) { 2658 TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1; 2659 TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2; 2660 2661 /* channel 1 */ 2662 TXMON_HAL_USER(ppdu_info, i, 2663 he_RU[0]) = ru_channel_1[0]; 2664 TXMON_HAL_USER(ppdu_info, i, 2665 he_RU[1]) = ru_channel_1[1]; 2666 TXMON_HAL_USER(ppdu_info, i, 2667 he_RU[2]) = ru_channel_1[2]; 2668 TXMON_HAL_USER(ppdu_info, i, 2669 he_RU[3]) = ru_channel_1[3]; 2670 /* channel 2 */ 2671 TXMON_HAL_USER(ppdu_info, i, 2672 he_RU[4]) = ru_channel_2[0]; 2673 TXMON_HAL_USER(ppdu_info, i, 2674 he_RU[5]) = ru_channel_2[1]; 2675 TXMON_HAL_USER(ppdu_info, i, 2676 he_RU[6]) = ru_channel_2[2]; 2677 TXMON_HAL_USER(ppdu_info, i, 2678 he_RU[7]) = ru_channel_2[3]; 2679 } 2680 /* channel 1 */ 2681 TXMON_HAL_STATUS(ppdu_info, he_RU[0]) = ru_channel_1[0]; 2682 TXMON_HAL_STATUS(ppdu_info, he_RU[1]) = ru_channel_1[1]; 2683 TXMON_HAL_STATUS(ppdu_info, he_RU[2]) = ru_channel_1[2]; 2684 TXMON_HAL_STATUS(ppdu_info, he_RU[3]) = ru_channel_1[3]; 2685 /* channel 2 */ 2686 TXMON_HAL_STATUS(ppdu_info, he_RU[4]) = ru_channel_2[0]; 2687 TXMON_HAL_STATUS(ppdu_info, he_RU[5]) = ru_channel_2[1]; 2688 TXMON_HAL_STATUS(ppdu_info, he_RU[6]) = ru_channel_2[2]; 2689 TXMON_HAL_STATUS(ppdu_info, he_RU[7]) = ru_channel_2[3]; 2690 2691 /* copy per user info to all user */ 2692 SHOW_DEFINED(WIFIMACTX_USER_DESC_COMMON_E); 2693 break; 2694 } 2695 case WIFIMACTX_PHY_DESC_E: 2696 { 2697 /* pkt_type - preamble type */ 2698 uint32_t pkt_type = 0; 2699 uint8_t bandwidth = 0; 2700 uint8_t is_stbc = 0; 2701 uint8_t is_triggered = 0; 2702 uint8_t gi = 0; 2703 uint8_t he_ppdu_subtype = 0; 2704 uint32_t ltf_size = 0; 2705 uint32_t he_data1 = 0; 2706 uint32_t he_data2 = 0; 2707 uint32_t he_data3 = 0; 2708 uint32_t he_data5 = 0; 2709 uint16_t he_mu_flag_1 = 0; 2710 uint16_t he_mu_flag_2 = 0; 2711 uint16_t num_users = 0; 2712 uint8_t i = 0; 2713 2714 status = HAL_MON_MACTX_PHY_DESC; 2715 2716 num_users = TXMON_HAL(ppdu_info, num_users); 2717 pkt_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, PKT_TYPE); 2718 is_stbc = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, STBC); 2719 is_triggered = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2720 TRIGGERED); 2721 if (!is_triggered) { 2722 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2723 BANDWIDTH); 2724 } else { 2725 /* 2726 * is_triggered, bw is minimum of AP pkt bw 2727 * or STA bw 2728 */ 2729 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2730 AP_PKT_BW); 2731 } 2732 2733 gi = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2734 CP_SETTING); 2735 ltf_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, LTF_SIZE); 2736 he_ppdu_subtype = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 2737 HE_PPDU_SUBTYPE); 2738 2739 TXMON_HAL_STATUS(ppdu_info, preamble_type) = pkt_type; 2740 TXMON_HAL_STATUS(ppdu_info, ltf_size) = ltf_size; 2741 TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc; 2742 TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth; 2743 2744 switch (ppdu_info->rx_status.preamble_type) { 2745 case TXMON_PKT_TYPE_11N_MM: 2746 TXMON_HAL_STATUS(ppdu_info, ht_flags) = 1; 2747 TXMON_HAL_STATUS(ppdu_info, 2748 rtap_flags) |= HT_SGI_PRESENT; 2749 break; 2750 case TXMON_PKT_TYPE_11AC: 2751 TXMON_HAL_STATUS(ppdu_info, vht_flags) = 1; 2752 break; 2753 case TXMON_PKT_TYPE_11AX: 2754 TXMON_HAL_STATUS(ppdu_info, he_flags) = 1; 2755 break; 2756 default: 2757 break; 2758 } 2759 2760 if (!TXMON_HAL_STATUS(ppdu_info, he_flags)) 2761 break; 2762 2763 /* update he flags */ 2764 /* PPDU FORMAT */ 2765 switch (he_ppdu_subtype) { 2766 case TXMON_HE_SUBTYPE_SU: 2767 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 2768 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 2769 break; 2770 case TXMON_HE_SUBTYPE_TRIG: 2771 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 2772 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 2773 break; 2774 case TXMON_HE_SUBTYPE_MU: 2775 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 2776 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 2777 break; 2778 case TXMON_HE_SUBTYPE_EXT_SU: 2779 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 2780 QDF_MON_STATUS_HE_EXT_SU_FORMAT_TYPE; 2781 break; 2782 }; 2783 2784 /* STBC */ 2785 he_data1 |= QDF_MON_STATUS_HE_STBC_KNOWN; 2786 he_data3 |= (is_stbc << QDF_MON_STATUS_STBC_SHIFT); 2787 2788 /* GI */ 2789 he_data2 |= QDF_MON_STATUS_HE_GI_KNOWN; 2790 he_data5 |= (gi << QDF_MON_STATUS_GI_SHIFT); 2791 2792 /* Data BW and RU allocation */ 2793 he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 2794 he_data5 = (he_data5 & 0xFFF0) | bandwidth; 2795 2796 he_data2 |= QDF_MON_STATUS_LTF_SYMBOLS_KNOWN; 2797 he_data5 |= ((1 + ltf_size) << 2798 QDF_MON_STATUS_HE_LTF_SIZE_SHIFT); 2799 2800 TXMON_HAL_STATUS(ppdu_info, 2801 he_mu_flags) = IS_MULTI_USERS(num_users); 2802 /* MAC TX PHY DESC is not a user tlv */ 2803 for (i = 0; i < num_users; i++) { 2804 TXMON_HAL_USER(ppdu_info, i, he_data1) = he_data1; 2805 TXMON_HAL_USER(ppdu_info, i, he_data2) = he_data2; 2806 TXMON_HAL_USER(ppdu_info, i, he_data3) = he_data3; 2807 TXMON_HAL_USER(ppdu_info, i, he_data5) = he_data5; 2808 2809 /* HE MU flags */ 2810 TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1; 2811 TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2; 2812 } 2813 2814 SHOW_DEFINED(WIFIMACTX_PHY_DESC_E); 2815 break; 2816 } 2817 case WIFICOEX_RX_STATUS_E: 2818 { 2819 SHOW_DEFINED(WIFICOEX_RX_STATUS_E); 2820 break; 2821 } 2822 case WIFIRX_PPDU_ACK_REPORT_E: 2823 { 2824 SHOW_DEFINED(WIFIRX_PPDU_ACK_REPORT_E); 2825 break; 2826 } 2827 case WIFIRX_PPDU_NO_ACK_REPORT_E: 2828 { 2829 SHOW_DEFINED(WIFIRX_PPDU_NO_ACK_REPORT_E); 2830 break; 2831 } 2832 case WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E: 2833 { 2834 SHOW_DEFINED(WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E); 2835 break; 2836 } 2837 case WIFITXPCU_PHYTX_DEBUG32_E: 2838 { 2839 SHOW_DEFINED(WIFITXPCU_PHYTX_DEBUG32_E); 2840 break; 2841 } 2842 case WIFITXPCU_PREAMBLE_DONE_E: 2843 { 2844 SHOW_DEFINED(WIFITXPCU_PREAMBLE_DONE_E); 2845 break; 2846 } 2847 case WIFIRX_PHY_SLEEP_E: 2848 { 2849 SHOW_DEFINED(WIFIRX_PHY_SLEEP_E); 2850 break; 2851 } 2852 case WIFIRX_FRAME_BITMAP_REQ_E: 2853 { 2854 SHOW_DEFINED(WIFIRX_FRAME_BITMAP_REQ_E); 2855 break; 2856 } 2857 case WIFIRXPCU_TX_SETUP_CLEAR_E: 2858 { 2859 SHOW_DEFINED(WIFIRXPCU_TX_SETUP_CLEAR_E); 2860 break; 2861 } 2862 case WIFIRX_TRIG_INFO_E: 2863 { 2864 SHOW_DEFINED(WIFIRX_TRIG_INFO_E); 2865 break; 2866 } 2867 case WIFIEXPECTED_RESPONSE_E: 2868 { 2869 SHOW_DEFINED(WIFIEXPECTED_RESPONSE_E); 2870 break; 2871 } 2872 case WIFITRIGGER_RESPONSE_TX_DONE_E: 2873 { 2874 SHOW_DEFINED(WIFITRIGGER_RESPONSE_TX_DONE_E); 2875 break; 2876 } 2877 case WIFIFW2SW_MON_E: 2878 { 2879 /* parse fw2sw tlv */ 2880 hal_txmon_parse_fw2sw(tx_tlv, tlv_user_id, data_status_info); 2881 status = HAL_MON_TX_FW2SW; 2882 SHOW_DEFINED(WIFIFW2SW_MON_E); 2883 break; 2884 } 2885 } 2886 2887 return status; 2888 } 2889 #endif /* QCA_MONITOR_2_0_SUPPORT */ 2890 2891 #ifdef REO_SHARED_QREF_TABLE_EN 2892 static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl) 2893 { 2894 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2895 uint32_t reg_val = 0; 2896 2897 /* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers 2898 * of 37 peer/tids 2899 */ 2900 reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE)); 2901 reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1); 2902 HAL_REG_WRITE(hal, 2903 HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 2904 reg_val); 2905 2906 /* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers 2907 * of 37 peer/tids 2908 */ 2909 reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1)); 2910 HAL_REG_WRITE(hal, 2911 HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 2912 reg_val); 2913 2914 hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of" 2915 "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back" 2916 "to erase stale entries in reo storage: regval:%x", hal, reg_val); 2917 } 2918 2919 /* hal_reo_shared_qaddr_write(): Write REO tid queue addr 2920 * LUT shared by SW and HW at the index given by peer id 2921 * and tid. 2922 * 2923 * @hal_soc: hal soc pointer 2924 * @reo_qref_addr: pointer to index pointed to be peer_id 2925 * and tid 2926 * @tid: tid queue number 2927 * @hw_qdesc_paddr: reo queue addr 2928 */ 2929 2930 static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl, 2931 uint16_t peer_id, 2932 int tid, 2933 qdf_dma_addr_t hw_qdesc_paddr) 2934 { 2935 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2936 struct rx_reo_queue_reference *reo_qref; 2937 uint32_t peer_tid_idx; 2938 2939 /* Plug hw_desc_addr in Host reo queue reference table */ 2940 if (HAL_PEER_ID_IS_MLO(peer_id)) { 2941 peer_tid_idx = ((peer_id - HAL_ML_PEER_ID_START) * 2942 DP_MAX_TIDS) + tid; 2943 reo_qref = (struct rx_reo_queue_reference *) 2944 &hal->reo_qref.mlo_reo_qref_table_vaddr[peer_tid_idx]; 2945 } else { 2946 peer_tid_idx = (peer_id * DP_MAX_TIDS) + tid; 2947 reo_qref = (struct rx_reo_queue_reference *) 2948 &hal->reo_qref.non_mlo_reo_qref_table_vaddr[peer_tid_idx]; 2949 } 2950 reo_qref->rx_reo_queue_desc_addr_31_0 = 2951 hw_qdesc_paddr & 0xffffffff; 2952 reo_qref->rx_reo_queue_desc_addr_39_32 = 2953 (hw_qdesc_paddr & 0xff00000000) >> 32; 2954 if (hw_qdesc_paddr != 0) 2955 reo_qref->receive_queue_number = tid; 2956 else 2957 reo_qref->receive_queue_number = 0; 2958 2959 hal_reo_shared_qaddr_cache_clear_be(hal_soc_hdl); 2960 hal_verbose_debug("hw_qdesc_paddr: %pK, tid: %d, reo_qref:%pK," 2961 "rx_reo_queue_desc_addr_31_0: %x," 2962 "rx_reo_queue_desc_addr_39_32: %x", 2963 (void *)hw_qdesc_paddr, tid, reo_qref, 2964 reo_qref->rx_reo_queue_desc_addr_31_0, 2965 reo_qref->rx_reo_queue_desc_addr_39_32); 2966 } 2967 2968 /** 2969 * hal_reo_shared_qaddr_setup() - Allocate MLO and Non MLO reo queue 2970 * reference table shared between SW and HW and initialize in Qdesc Base0 2971 * base1 registers provided by HW. 2972 * 2973 * @hal_soc: HAL Soc handle 2974 * 2975 * Return: QDF_STATUS_SUCCESS on success else a QDF error. 2976 */ 2977 static QDF_STATUS hal_reo_shared_qaddr_setup_be(hal_soc_handle_t hal_soc_hdl) 2978 { 2979 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2980 2981 hal->reo_qref.reo_qref_table_en = 1; 2982 2983 hal->reo_qref.mlo_reo_qref_table_vaddr = 2984 (uint64_t *)qdf_mem_alloc_consistent( 2985 hal->qdf_dev, hal->qdf_dev->dev, 2986 REO_QUEUE_REF_ML_TABLE_SIZE, 2987 &hal->reo_qref.mlo_reo_qref_table_paddr); 2988 if (!hal->reo_qref.mlo_reo_qref_table_vaddr) 2989 return QDF_STATUS_E_NOMEM; 2990 2991 hal->reo_qref.non_mlo_reo_qref_table_vaddr = 2992 (uint64_t *)qdf_mem_alloc_consistent( 2993 hal->qdf_dev, hal->qdf_dev->dev, 2994 REO_QUEUE_REF_NON_ML_TABLE_SIZE, 2995 &hal->reo_qref.non_mlo_reo_qref_table_paddr); 2996 if (!hal->reo_qref.non_mlo_reo_qref_table_vaddr) { 2997 qdf_mem_free_consistent( 2998 hal->qdf_dev, hal->qdf_dev->dev, 2999 REO_QUEUE_REF_ML_TABLE_SIZE, 3000 hal->reo_qref.mlo_reo_qref_table_vaddr, 3001 hal->reo_qref.mlo_reo_qref_table_paddr, 3002 0); 3003 return QDF_STATUS_E_NOMEM; 3004 } 3005 3006 hal_verbose_debug("MLO table start paddr:%pK," 3007 "Non-MLO table start paddr:%pK," 3008 "MLO table start vaddr: %pK," 3009 "Non MLO table start vaddr: %pK", 3010 (void *)hal->reo_qref.mlo_reo_qref_table_paddr, 3011 (void *)hal->reo_qref.non_mlo_reo_qref_table_paddr, 3012 hal->reo_qref.mlo_reo_qref_table_vaddr, 3013 hal->reo_qref.non_mlo_reo_qref_table_vaddr); 3014 3015 return QDF_STATUS_SUCCESS; 3016 } 3017 3018 /** 3019 * hal_reo_shared_qaddr_init() - Zero out REO qref LUT and 3020 * write start addr of MLO and Non MLO table in HW 3021 * 3022 * @hal_soc: HAL Soc handle 3023 * @qref_reset: reset qref LUT 3024 * 3025 * Return: None 3026 */ 3027 static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl, 3028 int qref_reset) 3029 { 3030 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3031 3032 if (qref_reset) { 3033 qdf_mem_zero(hal->reo_qref.mlo_reo_qref_table_vaddr, 3034 REO_QUEUE_REF_ML_TABLE_SIZE); 3035 qdf_mem_zero(hal->reo_qref.non_mlo_reo_qref_table_vaddr, 3036 REO_QUEUE_REF_NON_ML_TABLE_SIZE); 3037 } 3038 /* LUT_BASE0 and BASE1 registers expect upper 32bits of LUT base address 3039 * and lower 8 bits to be 0. Shift the physical address by 8 to plug 3040 * upper 32bits only 3041 */ 3042 HAL_REG_WRITE(hal, 3043 HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE), 3044 hal->reo_qref.non_mlo_reo_qref_table_paddr >> 8); 3045 HAL_REG_WRITE(hal, 3046 HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE), 3047 hal->reo_qref.mlo_reo_qref_table_paddr >> 8); 3048 HAL_REG_WRITE(hal, 3049 HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 3050 HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE, 3051 1)); 3052 HAL_REG_WRITE(hal, 3053 HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(REO_REG_REG_BASE), 3054 HAL_MS(HWIO_REO_R0_QDESC, MAX_SW_PEER_ID_MAX_SUPPORTED, 3055 0x1fff)); 3056 } 3057 3058 /** 3059 * hal_reo_shared_qaddr_detach() - Free MLO and Non MLO reo queue 3060 * reference table shared between SW and HW 3061 * 3062 * @hal_soc: HAL Soc handle 3063 * 3064 * Return: None 3065 */ 3066 static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl) 3067 { 3068 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3069 3070 HAL_REG_WRITE(hal, 3071 HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE), 3072 0); 3073 HAL_REG_WRITE(hal, 3074 HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE), 3075 0); 3076 3077 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 3078 REO_QUEUE_REF_ML_TABLE_SIZE, 3079 hal->reo_qref.mlo_reo_qref_table_vaddr, 3080 hal->reo_qref.mlo_reo_qref_table_paddr, 0); 3081 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 3082 REO_QUEUE_REF_NON_ML_TABLE_SIZE, 3083 hal->reo_qref.non_mlo_reo_qref_table_vaddr, 3084 hal->reo_qref.non_mlo_reo_qref_table_paddr, 0); 3085 } 3086 #endif 3087 3088 /** 3089 * hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing 3090 * @hal_soc: HAL SoC context 3091 * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM 3092 * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW 3093 * 3094 * Return: void 3095 */ 3096 #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK 3097 static inline void 3098 hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl, 3099 enum hal_tx_vdev_mismatch_notify 3100 config) 3101 { 3102 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3103 uint32_t reg_addr, reg_val = 0; 3104 uint32_t val = 0; 3105 3106 reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE); 3107 3108 val = HAL_REG_READ(hal_soc, reg_addr); 3109 3110 /* reset the corresponding bits in register */ 3111 val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK)); 3112 3113 /* set config value */ 3114 reg_val = val | (config << 3115 HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT); 3116 3117 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3118 } 3119 #else 3120 static inline void 3121 hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl, 3122 enum hal_tx_vdev_mismatch_notify 3123 config) 3124 { 3125 } 3126 #endif 3127 3128 /** 3129 * hal_tx_mcast_mlo_reinject_routing_set - set MLO multicast reinject routing 3130 * @hal_soc: HAL SoC context 3131 * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW 3132 * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM 3133 * 3134 * Return: void 3135 */ 3136 #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \ 3137 defined(WLAN_MCAST_MLO) 3138 static inline void 3139 hal_tx_mcast_mlo_reinject_routing_set_generic_be( 3140 hal_soc_handle_t hal_soc_hdl, 3141 enum hal_tx_mcast_mlo_reinject_notify config) 3142 { 3143 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3144 uint32_t reg_addr, reg_val = 0; 3145 uint32_t val = 0; 3146 3147 reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE); 3148 val = HAL_REG_READ(hal_soc, reg_addr); 3149 3150 /* reset the corresponding bits in register */ 3151 val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK)); 3152 3153 /* set config value */ 3154 reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT); 3155 3156 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3157 } 3158 #else 3159 static inline void 3160 hal_tx_mcast_mlo_reinject_routing_set_generic_be( 3161 hal_soc_handle_t hal_soc_hdl, 3162 enum hal_tx_mcast_mlo_reinject_notify config) 3163 { 3164 } 3165 #endif 3166 3167 /** 3168 * hal_get_ba_aging_timeout_be - Get BA Aging timeout 3169 * 3170 * @hal_soc: Opaque HAL SOC handle 3171 * @ac: Access category 3172 * @value: window size to get 3173 */ 3174 3175 static inline 3176 void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl, 3177 uint8_t ac, uint32_t *value) 3178 { 3179 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 3180 3181 switch (ac) { 3182 case WME_AC_BE: 3183 *value = HAL_REG_READ(soc, 3184 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 3185 REO_REG_REG_BASE)) / 1000; 3186 break; 3187 case WME_AC_BK: 3188 *value = HAL_REG_READ(soc, 3189 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 3190 REO_REG_REG_BASE)) / 1000; 3191 break; 3192 case WME_AC_VI: 3193 *value = HAL_REG_READ(soc, 3194 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 3195 REO_REG_REG_BASE)) / 1000; 3196 break; 3197 case WME_AC_VO: 3198 *value = HAL_REG_READ(soc, 3199 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 3200 REO_REG_REG_BASE)) / 1000; 3201 break; 3202 default: 3203 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 3204 "Invalid AC: %d\n", ac); 3205 } 3206 } 3207 3208 /** 3209 * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the 3210 * buffer list provided 3211 * 3212 * @hal_soc: Opaque HAL SOC handle 3213 * @scatter_bufs_base_paddr: Array of physical base addresses 3214 * @scatter_bufs_base_vaddr: Array of virtual base addresses 3215 * @num_scatter_bufs: Number of scatter buffers in the above lists 3216 * @scatter_buf_size: Size of each scatter buffer 3217 * @last_buf_end_offset: Offset to the last entry 3218 * @num_entries: Total entries of all scatter bufs 3219 * 3220 * Return: None 3221 */ 3222 static inline void 3223 hal_setup_link_idle_list_generic_be(struct hal_soc *soc, 3224 qdf_dma_addr_t scatter_bufs_base_paddr[], 3225 void *scatter_bufs_base_vaddr[], 3226 uint32_t num_scatter_bufs, 3227 uint32_t scatter_buf_size, 3228 uint32_t last_buf_end_offset, 3229 uint32_t num_entries) 3230 { 3231 int i; 3232 uint32_t *prev_buf_link_ptr = NULL; 3233 uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size; 3234 uint32_t val; 3235 3236 /* Link the scatter buffers */ 3237 for (i = 0; i < num_scatter_bufs; i++) { 3238 if (i > 0) { 3239 prev_buf_link_ptr[0] = 3240 scatter_bufs_base_paddr[i] & 0xffffffff; 3241 prev_buf_link_ptr[1] = HAL_SM( 3242 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 3243 BASE_ADDRESS_39_32, 3244 ((uint64_t)(scatter_bufs_base_paddr[i]) 3245 >> 32)) | HAL_SM( 3246 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 3247 ADDRESS_MATCH_TAG, 3248 ADDRESS_MATCH_TAG_VAL); 3249 } 3250 prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] + 3251 scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE); 3252 } 3253 3254 /* TBD: Register programming partly based on MLD & the rest based on 3255 * inputs from HW team. Not complete yet. 3256 */ 3257 3258 reg_scatter_buf_size = (scatter_buf_size - 3259 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64; 3260 reg_tot_scatter_buf_size = ((scatter_buf_size - 3261 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64; 3262 3263 HAL_REG_WRITE(soc, 3264 HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR( 3265 WBM_REG_REG_BASE), 3266 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE, 3267 reg_scatter_buf_size) | 3268 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE, 3269 0x1)); 3270 3271 HAL_REG_WRITE(soc, 3272 HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR( 3273 WBM_REG_REG_BASE), 3274 HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE, 3275 SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, 3276 reg_tot_scatter_buf_size)); 3277 3278 HAL_REG_WRITE(soc, 3279 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR( 3280 WBM_REG_REG_BASE), 3281 scatter_bufs_base_paddr[0] & 0xffffffff); 3282 3283 HAL_REG_WRITE(soc, 3284 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( 3285 WBM_REG_REG_BASE), 3286 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) & 3287 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK); 3288 3289 HAL_REG_WRITE(soc, 3290 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( 3291 WBM_REG_REG_BASE), 3292 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 3293 BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0]) 3294 >> 32)) | 3295 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 3296 ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL)); 3297 3298 /* ADDRESS_MATCH_TAG field in the above register is expected to match 3299 * with the upper bits of link pointer. The above write sets this field 3300 * to zero and we are also setting the upper bits of link pointers to 3301 * zero while setting up the link list of scatter buffers above 3302 */ 3303 3304 /* Setup head and tail pointers for the idle list */ 3305 HAL_REG_WRITE(soc, 3306 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( 3307 WBM_REG_REG_BASE), 3308 scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff); 3309 HAL_REG_WRITE(soc, 3310 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR( 3311 WBM_REG_REG_BASE), 3312 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 3313 BUFFER_ADDRESS_39_32, 3314 ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1]) 3315 >> 32)) | 3316 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 3317 HEAD_POINTER_OFFSET, last_buf_end_offset >> 2)); 3318 3319 HAL_REG_WRITE(soc, 3320 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( 3321 WBM_REG_REG_BASE), 3322 scatter_bufs_base_paddr[0] & 0xffffffff); 3323 3324 HAL_REG_WRITE(soc, 3325 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR( 3326 WBM_REG_REG_BASE), 3327 scatter_bufs_base_paddr[0] & 0xffffffff); 3328 HAL_REG_WRITE(soc, 3329 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR( 3330 WBM_REG_REG_BASE), 3331 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 3332 BUFFER_ADDRESS_39_32, 3333 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 3334 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 3335 TAIL_POINTER_OFFSET, 0)); 3336 3337 HAL_REG_WRITE(soc, 3338 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR( 3339 WBM_REG_REG_BASE), 3340 2 * num_entries); 3341 3342 /* Set RING_ID_DISABLE */ 3343 val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1); 3344 3345 /* 3346 * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence 3347 * check the presence of the bit before toggling it. 3348 */ 3349 #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 3350 val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1); 3351 #endif 3352 HAL_REG_WRITE(soc, 3353 HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE), 3354 val); 3355 } 3356 3357 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 3358 #define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000 3359 #endif 3360 3361 /** 3362 * hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register 3363 * for REO/WBM 3364 * @soc: HAL soc handle 3365 * @cc_cfg: structure pointer for HW cookie conversion configuration 3366 * 3367 * Return: None 3368 */ 3369 static inline 3370 void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl, 3371 struct hal_hw_cc_config *cc_cfg) 3372 { 3373 uint32_t reg_addr, reg_val = 0; 3374 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 3375 3376 /* REO CFG */ 3377 reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE); 3378 reg_val = cc_cfg->lut_base_addr_31_0; 3379 HAL_REG_WRITE(soc, reg_addr, reg_val); 3380 3381 reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE); 3382 reg_val = 0; 3383 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3384 SW_COOKIE_CONVERT_GLOBAL_ENABLE, 3385 cc_cfg->cc_global_en); 3386 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3387 SW_COOKIE_CONVERT_ENABLE, 3388 cc_cfg->cc_global_en); 3389 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3390 PAGE_ALIGNMENT, 3391 cc_cfg->page_4k_align); 3392 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3393 COOKIE_OFFSET_MSB, 3394 cc_cfg->cookie_offset_msb); 3395 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3396 COOKIE_PAGE_MSB, 3397 cc_cfg->cookie_page_msb); 3398 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3399 CMEM_LUT_BASE_ADDR_39_32, 3400 cc_cfg->lut_base_addr_39_32); 3401 HAL_REG_WRITE(soc, reg_addr, reg_val); 3402 3403 /* WBM CFG */ 3404 reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE); 3405 reg_val = cc_cfg->lut_base_addr_31_0; 3406 HAL_REG_WRITE(soc, reg_addr, reg_val); 3407 3408 reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE); 3409 reg_val = 0; 3410 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3411 PAGE_ALIGNMENT, 3412 cc_cfg->page_4k_align); 3413 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3414 COOKIE_OFFSET_MSB, 3415 cc_cfg->cookie_offset_msb); 3416 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3417 COOKIE_PAGE_MSB, 3418 cc_cfg->cookie_page_msb); 3419 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3420 CMEM_LUT_BASE_ADDR_39_32, 3421 cc_cfg->lut_base_addr_39_32); 3422 HAL_REG_WRITE(soc, reg_addr, reg_val); 3423 3424 /* 3425 * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE, 3426 */ 3427 reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE); 3428 reg_val = 0; 3429 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3430 WBM_COOKIE_CONV_GLOBAL_ENABLE, 3431 cc_cfg->cc_global_en); 3432 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3433 WBM2SW6_COOKIE_CONVERSION_EN, 3434 cc_cfg->wbm2sw6_cc_en); 3435 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3436 WBM2SW5_COOKIE_CONVERSION_EN, 3437 cc_cfg->wbm2sw5_cc_en); 3438 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3439 WBM2SW4_COOKIE_CONVERSION_EN, 3440 cc_cfg->wbm2sw4_cc_en); 3441 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3442 WBM2SW3_COOKIE_CONVERSION_EN, 3443 cc_cfg->wbm2sw3_cc_en); 3444 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3445 WBM2SW2_COOKIE_CONVERSION_EN, 3446 cc_cfg->wbm2sw2_cc_en); 3447 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3448 WBM2SW1_COOKIE_CONVERSION_EN, 3449 cc_cfg->wbm2sw1_cc_en); 3450 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3451 WBM2SW0_COOKIE_CONVERSION_EN, 3452 cc_cfg->wbm2sw0_cc_en); 3453 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3454 WBM2FW_COOKIE_CONVERSION_EN, 3455 cc_cfg->wbm2fw_cc_en); 3456 HAL_REG_WRITE(soc, reg_addr, reg_val); 3457 3458 #ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK 3459 reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE); 3460 reg_val = 0; 3461 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3462 COOKIE_DEBUG_SEL, 3463 cc_cfg->cc_global_en); 3464 3465 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3466 COOKIE_CONV_INDICATION_EN, 3467 cc_cfg->cc_global_en); 3468 3469 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3470 ERROR_PATH_COOKIE_CONV_EN, 3471 cc_cfg->error_path_cookie_conv_en); 3472 3473 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3474 RELEASE_PATH_COOKIE_CONV_EN, 3475 cc_cfg->release_path_cookie_conv_en); 3476 3477 HAL_REG_WRITE(soc, reg_addr, reg_val); 3478 #endif 3479 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 3480 /* 3481 * To enable indication for HW cookie conversion done or not for 3482 * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th 3483 * bit spare_control[15] should be set. 3484 */ 3485 reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE); 3486 reg_val = HAL_REG_READ(soc, reg_addr); 3487 reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL, 3488 SPARE_CONTROL, 3489 HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15); 3490 HAL_REG_WRITE(soc, reg_addr, reg_val); 3491 #endif 3492 } 3493 3494 /** 3495 * hal_set_ba_aging_timeout_be - Set BA Aging timeout 3496 * 3497 * @hal_soc: Opaque HAL SOC handle 3498 * @ac: Access category 3499 * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice 3500 * @value: Input value to set 3501 */ 3502 static inline 3503 void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl, 3504 uint8_t ac, uint32_t value) 3505 { 3506 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 3507 3508 switch (ac) { 3509 case WME_AC_BE: 3510 HAL_REG_WRITE(soc, 3511 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 3512 REO_REG_REG_BASE), 3513 value * 1000); 3514 break; 3515 case WME_AC_BK: 3516 HAL_REG_WRITE(soc, 3517 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 3518 REO_REG_REG_BASE), 3519 value * 1000); 3520 break; 3521 case WME_AC_VI: 3522 HAL_REG_WRITE(soc, 3523 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 3524 REO_REG_REG_BASE), 3525 value * 1000); 3526 break; 3527 case WME_AC_VO: 3528 HAL_REG_WRITE(soc, 3529 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 3530 REO_REG_REG_BASE), 3531 value * 1000); 3532 break; 3533 default: 3534 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 3535 "Invalid AC: %d\n", ac); 3536 } 3537 } 3538 3539 /** 3540 * hal_tx_populate_bank_register() - populate the bank register with 3541 * the software configs. 3542 * @soc: HAL soc handle 3543 * @config: bank config 3544 * @bank_id: bank id to be configured 3545 * 3546 * Returns: None 3547 */ 3548 #ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT 3549 static inline void 3550 hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl, 3551 union hal_tx_bank_config *config, 3552 uint8_t bank_id) 3553 { 3554 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3555 uint32_t reg_addr, reg_val = 0; 3556 3557 reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE, 3558 bank_id); 3559 3560 reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT); 3561 reg_val |= (config->encap_type << 3562 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT); 3563 reg_val |= (config->encrypt_type << 3564 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT); 3565 reg_val |= (config->src_buffer_swap << 3566 HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT); 3567 reg_val |= (config->link_meta_swap << 3568 HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT); 3569 reg_val |= (config->index_lookup_enable << 3570 HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT); 3571 reg_val |= (config->addrx_en << 3572 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT); 3573 reg_val |= (config->addry_en << 3574 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT); 3575 reg_val |= (config->mesh_enable << 3576 HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT); 3577 reg_val |= (config->vdev_id_check_en << 3578 HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT); 3579 reg_val |= (config->pmac_id << 3580 HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT); 3581 reg_val |= (config->mcast_pkt_ctrl << 3582 HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT); 3583 3584 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3585 } 3586 #else 3587 static inline void 3588 hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl, 3589 union hal_tx_bank_config *config, 3590 uint8_t bank_id) 3591 { 3592 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3593 uint32_t reg_addr, reg_val = 0; 3594 3595 reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE, 3596 bank_id); 3597 3598 reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT); 3599 reg_val |= (config->encap_type << 3600 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT); 3601 reg_val |= (config->encrypt_type << 3602 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT); 3603 reg_val |= (config->src_buffer_swap << 3604 HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT); 3605 reg_val |= (config->link_meta_swap << 3606 HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT); 3607 reg_val |= (config->index_lookup_enable << 3608 HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT); 3609 reg_val |= (config->addrx_en << 3610 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT); 3611 reg_val |= (config->addry_en << 3612 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT); 3613 reg_val |= (config->mesh_enable << 3614 HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT); 3615 reg_val |= (config->vdev_id_check_en << 3616 HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT); 3617 reg_val |= (config->pmac_id << 3618 HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT); 3619 reg_val |= (config->dscp_tid_map_id << 3620 HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT); 3621 3622 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3623 } 3624 #endif 3625 3626 3627 #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT 3628 3629 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4) 3630 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF) 3631 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3 3632 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2 3633 3634 /** 3635 * hal_tx_vdev_mcast_ctrl_set - set mcast_ctrl value 3636 * @hal_soc: HAL SoC context 3637 * @mcast_ctrl_val: mcast ctrl value for this VAP 3638 * 3639 * Return: void 3640 */ 3641 static inline void 3642 hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl, 3643 uint8_t vdev_id, uint8_t mcast_ctrl_val) 3644 { 3645 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3646 uint32_t reg_addr, reg_val = 0; 3647 uint32_t val; 3648 uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id); 3649 uint8_t index_in_reg = 3650 HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id); 3651 3652 reg_addr = 3653 HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE, 3654 reg_idx); 3655 3656 val = HAL_REG_READ(hal_soc, reg_addr); 3657 3658 /* mask out other stored value */ 3659 val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK << 3660 (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg))); 3661 3662 reg_val = val | 3663 ((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) << 3664 (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)); 3665 3666 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3667 } 3668 #else 3669 static inline void 3670 hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl, 3671 uint8_t vdev_id, uint8_t mcast_ctrl_val) 3672 { 3673 } 3674 #endif 3675 3676 #endif /* _HAL_BE_GENERIC_API_H_ */ 3677