1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_BE_GENERIC_API_H_ 20 #define _HAL_BE_GENERIC_API_H_ 21 22 #include <hal_be_hw_headers.h> 23 #include "hal_be_tx.h" 24 #include "hal_be_reo.h" 25 #include <hal_api_mon.h> 26 #include <hal_generic_api.h> 27 28 /** 29 * hal_tx_comp_get_status() - TQM Release reason 30 * @hal_desc: completion ring Tx status 31 * 32 * This function will parse the WBM completion descriptor and populate in 33 * HAL structure 34 * 35 * Return: none 36 */ 37 static inline void 38 hal_tx_comp_get_status_generic_be(void *desc, void *ts1, 39 struct hal_soc *hal) 40 { 41 uint8_t rate_stats_valid = 0; 42 uint32_t rate_stats = 0; 43 struct hal_tx_completion_status *ts = 44 (struct hal_tx_completion_status *)ts1; 45 46 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 47 TQM_STATUS_NUMBER); 48 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 49 ACK_FRAME_RSSI); 50 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 51 FIRST_MSDU); 52 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 53 LAST_MSDU); 54 #if 0 55 // TODO - This has to be calculated form first and last msdu 56 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, 57 WBM2SW_COMPLETION_RING_TX, 58 MSDU_PART_OF_AMSDU); 59 #endif 60 61 ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 62 SW_PEER_ID); 63 ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID); 64 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 65 TRANSMIT_COUNT); 66 67 rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS); 68 69 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO, 70 TX_RATE_STATS_INFO_VALID, rate_stats); 71 72 ts->valid = rate_stats_valid; 73 74 if (rate_stats_valid) { 75 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW, 76 rate_stats); 77 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO, 78 TRANSMIT_PKT_TYPE, rate_stats); 79 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO, 80 TRANSMIT_STBC, rate_stats); 81 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC, 82 rate_stats); 83 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI, 84 rate_stats); 85 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS, 86 rate_stats); 87 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION, 88 rate_stats); 89 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU, 90 rate_stats); 91 } 92 93 ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc); 94 ts->status = hal_tx_comp_get_release_reason( 95 desc, 96 hal_soc_to_hal_soc_handle(hal)); 97 98 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 99 TX_RATE_STATS_INFO_TX_RATE_STATS); 100 } 101 102 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 103 /** 104 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 105 * tlv_tag: Taf of the TLVs 106 * rx_tlv: the pointer to the TLVs 107 * @ppdu_info: pointer to ppdu_info 108 * 109 * Return: true if the tlv is handled, false if not 110 */ 111 static inline bool 112 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 113 struct hal_rx_ppdu_info *ppdu_info) 114 { 115 uint32_t value; 116 117 switch (tlv_tag) { 118 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 119 { 120 uint8_t *he_sig_a_mu_ul_info = 121 (uint8_t *)rx_tlv + 122 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL, 123 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 124 ppdu_info->rx_status.he_flags = 1; 125 126 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO, 127 FORMAT_INDICATION); 128 if (value == 0) { 129 ppdu_info->rx_status.he_data1 = 130 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 131 } else { 132 ppdu_info->rx_status.he_data1 = 133 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 134 } 135 136 /* data1 */ 137 ppdu_info->rx_status.he_data1 |= 138 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 139 QDF_MON_STATUS_HE_DL_UL_KNOWN | 140 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 141 142 /* data2 */ 143 ppdu_info->rx_status.he_data2 |= 144 QDF_MON_STATUS_TXOP_KNOWN; 145 146 /*data3*/ 147 value = HAL_RX_GET(he_sig_a_mu_ul_info, 148 HE_SIG_A_MU_UL_INFO, BSS_COLOR_ID); 149 ppdu_info->rx_status.he_data3 = value; 150 /* 1 for UL and 0 for DL */ 151 value = 1; 152 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 153 ppdu_info->rx_status.he_data3 |= value; 154 155 /*data4*/ 156 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO, 157 SPATIAL_REUSE); 158 ppdu_info->rx_status.he_data4 = value; 159 160 /*data5*/ 161 value = HAL_RX_GET(he_sig_a_mu_ul_info, 162 HE_SIG_A_MU_UL_INFO, TRANSMIT_BW); 163 ppdu_info->rx_status.he_data5 = value; 164 ppdu_info->rx_status.bw = value; 165 166 /*data6*/ 167 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO, 168 TXOP_DURATION); 169 value = value << QDF_MON_STATUS_TXOP_SHIFT; 170 ppdu_info->rx_status.he_data6 |= value; 171 return true; 172 } 173 default: 174 return false; 175 } 176 } 177 #else 178 static inline bool 179 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 180 struct hal_rx_ppdu_info *ppdu_info) 181 { 182 return false; 183 } 184 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ 185 186 #if defined(RX_PPDU_END_USER_STATS_OFDMA_INFO_VALID_OFFSET) && \ 187 defined(RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 188 189 static inline void 190 hal_rx_handle_mu_ul_info(void *rx_tlv, 191 struct mon_rx_user_status *mon_rx_user_status) 192 { 193 mon_rx_user_status->mu_ul_user_v0_word0 = 194 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 195 SW_RESPONSE_REFERENCE_PTR); 196 197 mon_rx_user_status->mu_ul_user_v0_word1 = 198 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 199 SW_RESPONSE_REFERENCE_PTR_EXT); 200 } 201 202 static inline void 203 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 204 struct mon_rx_user_status *mon_rx_user_status) 205 { 206 uint32_t mpdu_ok_byte_count; 207 uint32_t mpdu_err_byte_count; 208 209 mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, 210 RX_PPDU_END_USER_STATS, 211 MPDU_OK_BYTE_COUNT); 212 mpdu_err_byte_count = HAL_RX_GET(rx_tlv, 213 RX_PPDU_END_USER_STATS, 214 MPDU_ERR_BYTE_COUNT); 215 216 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 217 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 218 } 219 #else 220 static inline void 221 hal_rx_handle_mu_ul_info(void *rx_tlv, 222 struct mon_rx_user_status *mon_rx_user_status) 223 { 224 } 225 226 static inline void 227 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 228 struct mon_rx_user_status *mon_rx_user_status) 229 { 230 struct hal_rx_ppdu_info *ppdu_info = 231 (struct hal_rx_ppdu_info *)ppduinfo; 232 233 /* HKV1: doesn't support mpdu byte count */ 234 mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; 235 mon_rx_user_status->mpdu_err_byte_count = 0; 236 } 237 #endif 238 239 static inline void 240 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id, 241 struct mon_rx_user_status *mon_rx_user_status) 242 { 243 struct mon_rx_info *mon_rx_info; 244 struct mon_rx_user_info *mon_rx_user_info; 245 struct hal_rx_ppdu_info *ppdu_info = 246 (struct hal_rx_ppdu_info *)ppduinfo; 247 248 mon_rx_info = &ppdu_info->rx_info; 249 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 250 mon_rx_user_info->qos_control_info_valid = 251 mon_rx_info->qos_control_info_valid; 252 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 253 254 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 255 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 256 mon_rx_user_status->tcp_msdu_count = 257 ppdu_info->rx_status.tcp_msdu_count; 258 mon_rx_user_status->udp_msdu_count = 259 ppdu_info->rx_status.udp_msdu_count; 260 mon_rx_user_status->other_msdu_count = 261 ppdu_info->rx_status.other_msdu_count; 262 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 263 mon_rx_user_status->frame_control_info_valid = 264 ppdu_info->rx_status.frame_control_info_valid; 265 mon_rx_user_status->data_sequence_control_info_valid = 266 ppdu_info->rx_status.data_sequence_control_info_valid; 267 mon_rx_user_status->first_data_seq_ctrl = 268 ppdu_info->rx_status.first_data_seq_ctrl; 269 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 270 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 271 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 272 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 273 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 274 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 275 276 mon_rx_user_status->mpdu_cnt_fcs_ok = 277 ppdu_info->com_info.mpdu_cnt_fcs_ok; 278 mon_rx_user_status->mpdu_cnt_fcs_err = 279 ppdu_info->com_info.mpdu_cnt_fcs_err; 280 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 281 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 282 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 283 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 284 285 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 286 } 287 288 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, \ 289 ppdu_info, rssi_info_tlv) \ 290 { \ 291 ppdu_info->rx_status.rssi_chain[chain][0] = \ 292 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 293 RSSI_PRI20_CHAIN##chain); \ 294 ppdu_info->rx_status.rssi_chain[chain][1] = \ 295 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 296 RSSI_EXT20_CHAIN##chain); \ 297 ppdu_info->rx_status.rssi_chain[chain][2] = \ 298 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 299 RSSI_EXT40_LOW20_CHAIN##chain); \ 300 ppdu_info->rx_status.rssi_chain[chain][3] = \ 301 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 302 RSSI_EXT40_HIGH20_CHAIN##chain); \ 303 ppdu_info->rx_status.rssi_chain[chain][4] = \ 304 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 305 RSSI_EXT80_LOW20_CHAIN##chain); \ 306 ppdu_info->rx_status.rssi_chain[chain][5] = \ 307 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 308 RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ 309 ppdu_info->rx_status.rssi_chain[chain][6] = \ 310 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 311 RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ 312 ppdu_info->rx_status.rssi_chain[chain][7] = \ 313 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 314 RSSI_EXT80_HIGH20_CHAIN##chain); \ 315 } \ 316 317 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 318 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, ppdu_info, rssi_info_tlv) \ 319 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, ppdu_info, rssi_info_tlv) \ 320 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, ppdu_info, rssi_info_tlv) \ 321 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, ppdu_info, rssi_info_tlv) \ 322 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, ppdu_info, rssi_info_tlv) \ 323 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, ppdu_info, rssi_info_tlv) \ 324 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, ppdu_info, rssi_info_tlv) \ 325 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, ppdu_info, rssi_info_tlv)} \ 326 327 static inline uint32_t 328 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 329 uint8_t *rssi_info_tlv) 330 { 331 // TODO - Find all these registers for wcn7850 332 #if 0 333 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 334 #endif 335 return 0; 336 } 337 338 #ifdef WLAN_TX_PKT_CAPTURE_ENH 339 static inline void 340 hal_get_qos_control(void *rx_tlv, 341 struct hal_rx_ppdu_info *ppdu_info) 342 { 343 ppdu_info->rx_info.qos_control_info_valid = 344 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 345 QOS_CONTROL_INFO_VALID); 346 347 if (ppdu_info->rx_info.qos_control_info_valid) 348 ppdu_info->rx_info.qos_control = 349 HAL_RX_GET(rx_tlv, 350 RX_PPDU_END_USER_STATS, 351 QOS_CONTROL_FIELD); 352 } 353 354 static inline void 355 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 356 struct hal_rx_ppdu_info *ppdu_info) 357 { 358 if ((ppdu_info->sw_frame_group_id 359 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 360 (ppdu_info->sw_frame_group_id == 361 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 362 ppdu_info->rx_info.mac_addr1_valid = 363 HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start); 364 365 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 366 HAL_RX_GET(rx_mpdu_start, 367 RX_MPDU_INFO, 368 MAC_ADDR_AD1_31_0); 369 if (ppdu_info->sw_frame_group_id == 370 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 371 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 372 HAL_RX_GET(rx_mpdu_start, 373 RX_MPDU_INFO, 374 MAC_ADDR_AD1_47_32); 375 } 376 } 377 } 378 #else 379 static inline void 380 hal_get_qos_control(void *rx_tlv, 381 struct hal_rx_ppdu_info *ppdu_info) 382 { 383 } 384 385 static inline void 386 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 387 struct hal_rx_ppdu_info *ppdu_info) 388 { 389 } 390 #endif 391 392 /** 393 * hal_rx_status_get_tlv_info() - process receive info TLV 394 * @rx_tlv_hdr: pointer to TLV header 395 * @ppdu_info: pointer to ppdu_info 396 * 397 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 398 */ 399 static inline uint32_t 400 hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo, 401 hal_soc_handle_t hal_soc_hdl, 402 qdf_nbuf_t nbuf) 403 { 404 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 405 uint32_t tlv_tag, user_id, tlv_len, value; 406 uint8_t group_id = 0; 407 uint8_t he_dcm = 0; 408 uint8_t he_stbc = 0; 409 uint16_t he_gi = 0; 410 uint16_t he_ltf = 0; 411 void *rx_tlv; 412 bool unhandled = false; 413 struct mon_rx_user_status *mon_rx_user_status; 414 struct hal_rx_ppdu_info *ppdu_info = 415 (struct hal_rx_ppdu_info *)ppduinfo; 416 417 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 418 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 419 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 420 421 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 422 423 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 424 rx_tlv, tlv_len); 425 426 switch (tlv_tag) { 427 case WIFIRX_PPDU_START_E: 428 { 429 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 430 HAL_RX_GET(rx_tlv, RX_PPDU_START, PHY_PPDU_ID))) 431 hal_err("Matching ppdu_id(%u) detected", 432 ppdu_info->com_info.last_ppdu_id); 433 434 /* Reset ppdu_info before processing the ppdu */ 435 qdf_mem_zero(ppdu_info, 436 sizeof(struct hal_rx_ppdu_info)); 437 438 ppdu_info->com_info.last_ppdu_id = 439 ppdu_info->com_info.ppdu_id = 440 HAL_RX_GET(rx_tlv, RX_PPDU_START, 441 PHY_PPDU_ID); 442 443 /* channel number is set in PHY meta data */ 444 ppdu_info->rx_status.chan_num = 445 (HAL_RX_GET(rx_tlv, RX_PPDU_START, 446 SW_PHY_META_DATA) & 0x0000FFFF); 447 ppdu_info->rx_status.chan_freq = 448 (HAL_RX_GET(rx_tlv, RX_PPDU_START, 449 SW_PHY_META_DATA) & 0xFFFF0000) >> 16; 450 if (ppdu_info->rx_status.chan_num && 451 ppdu_info->rx_status.chan_freq) { 452 ppdu_info->rx_status.chan_freq = 453 hal_rx_radiotap_num_to_freq( 454 ppdu_info->rx_status.chan_num, 455 ppdu_info->rx_status.chan_freq); 456 } 457 #ifdef DP_BE_NOTYET_WAR 458 // TODO - timestamp is changed to 64-bit for wcn7850 459 ppdu_info->com_info.ppdu_timestamp = 460 HAL_RX_GET(rx_tlv, RX_PPDU_START, 461 PPDU_START_TIMESTAMP); 462 #endif 463 ppdu_info->rx_status.ppdu_timestamp = 464 ppdu_info->com_info.ppdu_timestamp; 465 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 466 467 break; 468 } 469 470 case WIFIRX_PPDU_START_USER_INFO_E: 471 break; 472 473 case WIFIRX_PPDU_END_E: 474 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 475 "[%s][%d] ppdu_end_e len=%d", 476 __func__, __LINE__, tlv_len); 477 /* This is followed by sub-TLVs of PPDU_END */ 478 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 479 break; 480 481 case WIFIPHYRX_PKT_END_E: 482 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 483 break; 484 485 case WIFIRXPCU_PPDU_END_INFO_E: 486 ppdu_info->rx_status.rx_antenna = 487 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, RX_ANTENNA); 488 ppdu_info->rx_status.tsft = 489 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, 490 WB_TIMESTAMP_UPPER_32); 491 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 492 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, 493 WB_TIMESTAMP_LOWER_32); 494 ppdu_info->rx_status.duration = 495 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 496 RX_PPDU_DURATION); 497 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 498 break; 499 500 /* 501 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 502 * for MU, based on num users we see this tlv that many times. 503 */ 504 case WIFIRX_PPDU_END_USER_STATS_E: 505 { 506 unsigned long tid = 0; 507 uint16_t seq = 0; 508 509 ppdu_info->rx_status.ast_index = 510 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 511 AST_INDEX); 512 513 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 514 RECEIVED_QOS_DATA_TID_BITMAP); 515 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, 516 sizeof(tid) * 8); 517 518 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 519 ppdu_info->rx_status.tid = HAL_TID_INVALID; 520 521 ppdu_info->rx_status.tcp_msdu_count = 522 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 523 TCP_MSDU_COUNT) + 524 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 525 TCP_ACK_MSDU_COUNT); 526 ppdu_info->rx_status.udp_msdu_count = 527 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 528 UDP_MSDU_COUNT); 529 ppdu_info->rx_status.other_msdu_count = 530 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 531 OTHER_MSDU_COUNT); 532 533 if (ppdu_info->sw_frame_group_id 534 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 535 ppdu_info->rx_status.frame_control_info_valid = 536 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 537 FRAME_CONTROL_INFO_VALID); 538 539 if (ppdu_info->rx_status.frame_control_info_valid) 540 ppdu_info->rx_status.frame_control = 541 HAL_RX_GET(rx_tlv, 542 RX_PPDU_END_USER_STATS, 543 FRAME_CONTROL_FIELD); 544 545 hal_get_qos_control(rx_tlv, ppdu_info); 546 } 547 548 ppdu_info->rx_status.data_sequence_control_info_valid = 549 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 550 DATA_SEQUENCE_CONTROL_INFO_VALID); 551 552 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 553 FIRST_DATA_SEQ_CTRL); 554 if (ppdu_info->rx_status.data_sequence_control_info_valid) 555 ppdu_info->rx_status.first_data_seq_ctrl = seq; 556 557 ppdu_info->rx_status.preamble_type = 558 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 559 HT_CONTROL_FIELD_PKT_TYPE); 560 switch (ppdu_info->rx_status.preamble_type) { 561 case HAL_RX_PKT_TYPE_11N: 562 ppdu_info->rx_status.ht_flags = 1; 563 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 564 break; 565 case HAL_RX_PKT_TYPE_11AC: 566 ppdu_info->rx_status.vht_flags = 1; 567 break; 568 case HAL_RX_PKT_TYPE_11AX: 569 ppdu_info->rx_status.he_flags = 1; 570 break; 571 default: 572 break; 573 } 574 575 ppdu_info->com_info.mpdu_cnt_fcs_ok = 576 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 577 MPDU_CNT_FCS_OK); 578 ppdu_info->com_info.mpdu_cnt_fcs_err = 579 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 580 MPDU_CNT_FCS_ERR); 581 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 582 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 583 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 584 else 585 ppdu_info->rx_status.rs_flags &= 586 (~IEEE80211_AMPDU_FLAG); 587 588 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 589 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 590 FCS_OK_BITMAP_31_0); 591 592 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 593 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS, 594 FCS_OK_BITMAP_63_32); 595 596 if (user_id < HAL_MAX_UL_MU_USERS) { 597 mon_rx_user_status = 598 &ppdu_info->rx_user_status[user_id]; 599 600 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 601 602 ppdu_info->com_info.num_users++; 603 604 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 605 user_id, 606 mon_rx_user_status); 607 } 608 break; 609 } 610 611 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 612 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 613 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 614 FCS_OK_BITMAP_95_64); 615 616 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 617 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 618 FCS_OK_BITMAP_127_96); 619 620 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 621 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 622 FCS_OK_BITMAP_159_128); 623 624 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 625 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 626 FCS_OK_BITMAP_191_160); 627 628 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 629 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 630 FCS_OK_BITMAP_223_192); 631 632 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 633 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 634 FCS_OK_BITMAP_255_224); 635 break; 636 637 case WIFIRX_PPDU_END_STATUS_DONE_E: 638 return HAL_TLV_STATUS_PPDU_DONE; 639 640 case WIFIDUMMY_E: 641 return HAL_TLV_STATUS_BUF_DONE; 642 643 case WIFIPHYRX_HT_SIG_E: 644 { 645 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 646 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 647 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 648 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO, 649 FEC_CODING); 650 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 651 1 : 0; 652 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 653 HT_SIG_INFO, MCS); 654 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 655 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 656 HT_SIG_INFO, CBW); 657 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 658 HT_SIG_INFO, SHORT_GI); 659 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 660 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 661 HT_SIG_SU_NSS_SHIFT) + 1; 662 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 663 break; 664 } 665 666 case WIFIPHYRX_L_SIG_B_E: 667 { 668 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 669 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 670 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 671 672 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO, RATE); 673 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 674 switch (value) { 675 case 1: 676 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 677 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 678 break; 679 case 2: 680 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 681 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 682 break; 683 case 3: 684 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 685 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 686 break; 687 case 4: 688 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 689 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 690 break; 691 case 5: 692 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 693 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 694 break; 695 case 6: 696 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 697 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 698 break; 699 case 7: 700 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 701 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 702 break; 703 default: 704 break; 705 } 706 ppdu_info->rx_status.cck_flag = 1; 707 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 708 break; 709 } 710 711 case WIFIPHYRX_L_SIG_A_E: 712 { 713 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 714 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 715 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 716 717 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO, RATE); 718 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 719 switch (value) { 720 case 8: 721 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 722 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 723 break; 724 case 9: 725 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 726 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 727 break; 728 case 10: 729 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 730 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 731 break; 732 case 11: 733 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 734 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 735 break; 736 case 12: 737 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 738 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 739 break; 740 case 13: 741 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 742 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 743 break; 744 case 14: 745 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 746 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 747 break; 748 case 15: 749 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 750 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 751 break; 752 default: 753 break; 754 } 755 ppdu_info->rx_status.ofdm_flag = 1; 756 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 757 break; 758 } 759 760 case WIFIPHYRX_VHT_SIG_A_E: 761 { 762 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 763 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 764 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 765 766 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, 767 SU_MU_CODING); 768 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 769 1 : 0; 770 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, GROUP_ID); 771 ppdu_info->rx_status.vht_flag_values5 = group_id; 772 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 773 VHT_SIG_A_INFO, MCS); 774 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 775 VHT_SIG_A_INFO, GI_SETTING); 776 777 switch (hal->target_type) { 778 case TARGET_TYPE_QCA8074: 779 case TARGET_TYPE_QCA8074V2: 780 case TARGET_TYPE_QCA6018: 781 case TARGET_TYPE_QCA5018: 782 case TARGET_TYPE_QCN9000: 783 case TARGET_TYPE_QCN6122: 784 #ifdef QCA_WIFI_QCA6390 785 case TARGET_TYPE_QCA6390: 786 #endif 787 ppdu_info->rx_status.is_stbc = 788 HAL_RX_GET(vht_sig_a_info, 789 VHT_SIG_A_INFO, STBC); 790 value = HAL_RX_GET(vht_sig_a_info, 791 VHT_SIG_A_INFO, N_STS); 792 value = value & VHT_SIG_SU_NSS_MASK; 793 if (ppdu_info->rx_status.is_stbc && (value > 0)) 794 value = ((value + 1) >> 1) - 1; 795 ppdu_info->rx_status.nss = 796 ((value & VHT_SIG_SU_NSS_MASK) + 1); 797 798 break; 799 case TARGET_TYPE_QCA6290: 800 #if !defined(QCA_WIFI_QCA6290_11AX) 801 ppdu_info->rx_status.is_stbc = 802 HAL_RX_GET(vht_sig_a_info, 803 VHT_SIG_A_INFO, STBC); 804 value = HAL_RX_GET(vht_sig_a_info, 805 VHT_SIG_A_INFO, N_STS); 806 value = value & VHT_SIG_SU_NSS_MASK; 807 if (ppdu_info->rx_status.is_stbc && (value > 0)) 808 value = ((value + 1) >> 1) - 1; 809 ppdu_info->rx_status.nss = 810 ((value & VHT_SIG_SU_NSS_MASK) + 1); 811 #else 812 ppdu_info->rx_status.nss = 0; 813 #endif 814 break; 815 case TARGET_TYPE_QCA6490: 816 case TARGET_TYPE_QCA6750: 817 case TARGET_TYPE_WCN7850: 818 ppdu_info->rx_status.nss = 0; 819 break; 820 default: 821 break; 822 } 823 ppdu_info->rx_status.vht_flag_values3[0] = 824 (((ppdu_info->rx_status.mcs) << 4) 825 | ppdu_info->rx_status.nss); 826 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 827 VHT_SIG_A_INFO, BANDWIDTH); 828 ppdu_info->rx_status.vht_flag_values2 = 829 ppdu_info->rx_status.bw; 830 ppdu_info->rx_status.vht_flag_values4 = 831 HAL_RX_GET(vht_sig_a_info, 832 VHT_SIG_A_INFO, SU_MU_CODING); 833 834 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 835 VHT_SIG_A_INFO, BEAMFORMED); 836 if (group_id == 0 || group_id == 63) 837 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 838 else 839 ppdu_info->rx_status.reception_type = 840 HAL_RX_TYPE_MU_MIMO; 841 842 break; 843 } 844 case WIFIPHYRX_HE_SIG_A_SU_E: 845 { 846 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 847 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 848 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 849 ppdu_info->rx_status.he_flags = 1; 850 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 851 FORMAT_INDICATION); 852 if (value == 0) { 853 ppdu_info->rx_status.he_data1 = 854 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 855 } else { 856 ppdu_info->rx_status.he_data1 = 857 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 858 } 859 860 /* data1 */ 861 ppdu_info->rx_status.he_data1 |= 862 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 863 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 864 QDF_MON_STATUS_HE_DL_UL_KNOWN | 865 QDF_MON_STATUS_HE_MCS_KNOWN | 866 QDF_MON_STATUS_HE_DCM_KNOWN | 867 QDF_MON_STATUS_HE_CODING_KNOWN | 868 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 869 QDF_MON_STATUS_HE_STBC_KNOWN | 870 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 871 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 872 873 /* data2 */ 874 ppdu_info->rx_status.he_data2 = 875 QDF_MON_STATUS_HE_GI_KNOWN; 876 ppdu_info->rx_status.he_data2 |= 877 QDF_MON_STATUS_TXBF_KNOWN | 878 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 879 QDF_MON_STATUS_TXOP_KNOWN | 880 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 881 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 882 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 883 884 /* data3 */ 885 value = HAL_RX_GET(he_sig_a_su_info, 886 HE_SIG_A_SU_INFO, BSS_COLOR_ID); 887 ppdu_info->rx_status.he_data3 = value; 888 value = HAL_RX_GET(he_sig_a_su_info, 889 HE_SIG_A_SU_INFO, BEAM_CHANGE); 890 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 891 ppdu_info->rx_status.he_data3 |= value; 892 value = HAL_RX_GET(he_sig_a_su_info, 893 HE_SIG_A_SU_INFO, DL_UL_FLAG); 894 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 895 ppdu_info->rx_status.he_data3 |= value; 896 897 value = HAL_RX_GET(he_sig_a_su_info, 898 HE_SIG_A_SU_INFO, TRANSMIT_MCS); 899 ppdu_info->rx_status.mcs = value; 900 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 901 ppdu_info->rx_status.he_data3 |= value; 902 903 value = HAL_RX_GET(he_sig_a_su_info, 904 HE_SIG_A_SU_INFO, DCM); 905 he_dcm = value; 906 value = value << QDF_MON_STATUS_DCM_SHIFT; 907 ppdu_info->rx_status.he_data3 |= value; 908 value = HAL_RX_GET(he_sig_a_su_info, 909 HE_SIG_A_SU_INFO, CODING); 910 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 911 1 : 0; 912 value = value << QDF_MON_STATUS_CODING_SHIFT; 913 ppdu_info->rx_status.he_data3 |= value; 914 value = HAL_RX_GET(he_sig_a_su_info, 915 HE_SIG_A_SU_INFO, 916 LDPC_EXTRA_SYMBOL); 917 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 918 ppdu_info->rx_status.he_data3 |= value; 919 value = HAL_RX_GET(he_sig_a_su_info, 920 HE_SIG_A_SU_INFO, STBC); 921 he_stbc = value; 922 value = value << QDF_MON_STATUS_STBC_SHIFT; 923 ppdu_info->rx_status.he_data3 |= value; 924 925 /* data4 */ 926 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 927 SPATIAL_REUSE); 928 ppdu_info->rx_status.he_data4 = value; 929 930 /* data5 */ 931 value = HAL_RX_GET(he_sig_a_su_info, 932 HE_SIG_A_SU_INFO, TRANSMIT_BW); 933 ppdu_info->rx_status.he_data5 = value; 934 ppdu_info->rx_status.bw = value; 935 value = HAL_RX_GET(he_sig_a_su_info, 936 HE_SIG_A_SU_INFO, CP_LTF_SIZE); 937 switch (value) { 938 case 0: 939 he_gi = HE_GI_0_8; 940 he_ltf = HE_LTF_1_X; 941 break; 942 case 1: 943 he_gi = HE_GI_0_8; 944 he_ltf = HE_LTF_2_X; 945 break; 946 case 2: 947 he_gi = HE_GI_1_6; 948 he_ltf = HE_LTF_2_X; 949 break; 950 case 3: 951 if (he_dcm && he_stbc) { 952 he_gi = HE_GI_0_8; 953 he_ltf = HE_LTF_4_X; 954 } else { 955 he_gi = HE_GI_3_2; 956 he_ltf = HE_LTF_4_X; 957 } 958 break; 959 } 960 ppdu_info->rx_status.sgi = he_gi; 961 ppdu_info->rx_status.ltf_size = he_ltf; 962 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 963 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 964 ppdu_info->rx_status.he_data5 |= value; 965 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 966 ppdu_info->rx_status.he_data5 |= value; 967 968 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 969 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 970 ppdu_info->rx_status.he_data5 |= value; 971 972 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 973 PACKET_EXTENSION_A_FACTOR); 974 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 975 ppdu_info->rx_status.he_data5 |= value; 976 977 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, TXBF); 978 value = value << QDF_MON_STATUS_TXBF_SHIFT; 979 ppdu_info->rx_status.he_data5 |= value; 980 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 981 PACKET_EXTENSION_PE_DISAMBIGUITY); 982 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 983 ppdu_info->rx_status.he_data5 |= value; 984 985 /* data6 */ 986 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 987 value++; 988 ppdu_info->rx_status.nss = value; 989 ppdu_info->rx_status.he_data6 = value; 990 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 991 DOPPLER_INDICATION); 992 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 993 ppdu_info->rx_status.he_data6 |= value; 994 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 995 TXOP_DURATION); 996 value = value << QDF_MON_STATUS_TXOP_SHIFT; 997 ppdu_info->rx_status.he_data6 |= value; 998 999 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 1000 HE_SIG_A_SU_INFO, TXBF); 1001 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1002 break; 1003 } 1004 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 1005 { 1006 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 1007 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 1008 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 1009 1010 ppdu_info->rx_status.he_mu_flags = 1; 1011 1012 /* HE Flags */ 1013 /*data1*/ 1014 ppdu_info->rx_status.he_data1 = 1015 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1016 ppdu_info->rx_status.he_data1 |= 1017 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1018 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1019 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1020 QDF_MON_STATUS_HE_STBC_KNOWN | 1021 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1022 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1023 1024 /* data2 */ 1025 ppdu_info->rx_status.he_data2 = 1026 QDF_MON_STATUS_HE_GI_KNOWN; 1027 ppdu_info->rx_status.he_data2 |= 1028 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1029 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1030 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1031 QDF_MON_STATUS_TXOP_KNOWN | 1032 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1033 1034 /*data3*/ 1035 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1036 HE_SIG_A_MU_DL_INFO, BSS_COLOR_ID); 1037 ppdu_info->rx_status.he_data3 = value; 1038 1039 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1040 HE_SIG_A_MU_DL_INFO, DL_UL_FLAG); 1041 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1042 ppdu_info->rx_status.he_data3 |= value; 1043 1044 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1045 HE_SIG_A_MU_DL_INFO, 1046 LDPC_EXTRA_SYMBOL); 1047 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1048 ppdu_info->rx_status.he_data3 |= value; 1049 1050 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1051 HE_SIG_A_MU_DL_INFO, STBC); 1052 he_stbc = value; 1053 value = value << QDF_MON_STATUS_STBC_SHIFT; 1054 ppdu_info->rx_status.he_data3 |= value; 1055 1056 /*data4*/ 1057 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 1058 SPATIAL_REUSE); 1059 ppdu_info->rx_status.he_data4 = value; 1060 1061 /*data5*/ 1062 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1063 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 1064 ppdu_info->rx_status.he_data5 = value; 1065 ppdu_info->rx_status.bw = value; 1066 1067 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1068 HE_SIG_A_MU_DL_INFO, CP_LTF_SIZE); 1069 switch (value) { 1070 case 0: 1071 he_gi = HE_GI_0_8; 1072 he_ltf = HE_LTF_4_X; 1073 break; 1074 case 1: 1075 he_gi = HE_GI_0_8; 1076 he_ltf = HE_LTF_2_X; 1077 break; 1078 case 2: 1079 he_gi = HE_GI_1_6; 1080 he_ltf = HE_LTF_2_X; 1081 break; 1082 case 3: 1083 he_gi = HE_GI_3_2; 1084 he_ltf = HE_LTF_4_X; 1085 break; 1086 } 1087 ppdu_info->rx_status.sgi = he_gi; 1088 ppdu_info->rx_status.ltf_size = he_ltf; 1089 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1090 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1091 ppdu_info->rx_status.he_data5 |= value; 1092 1093 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1094 ppdu_info->rx_status.he_data5 |= value; 1095 1096 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1097 HE_SIG_A_MU_DL_INFO, NUM_LTF_SYMBOLS); 1098 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1099 ppdu_info->rx_status.he_data5 |= value; 1100 1101 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 1102 PACKET_EXTENSION_A_FACTOR); 1103 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1104 ppdu_info->rx_status.he_data5 |= value; 1105 1106 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 1107 PACKET_EXTENSION_PE_DISAMBIGUITY); 1108 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1109 ppdu_info->rx_status.he_data5 |= value; 1110 1111 /*data6*/ 1112 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 1113 DOPPLER_INDICATION); 1114 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1115 ppdu_info->rx_status.he_data6 |= value; 1116 1117 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 1118 TXOP_DURATION); 1119 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1120 ppdu_info->rx_status.he_data6 |= value; 1121 1122 /* HE-MU Flags */ 1123 /* HE-MU-flags1 */ 1124 ppdu_info->rx_status.he_flags1 = 1125 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1126 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1127 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1128 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1129 QDF_MON_STATUS_RU_0_KNOWN; 1130 1131 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1132 HE_SIG_A_MU_DL_INFO, MCS_OF_SIG_B); 1133 ppdu_info->rx_status.he_flags1 |= value; 1134 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1135 HE_SIG_A_MU_DL_INFO, DCM_OF_SIG_B); 1136 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 1137 ppdu_info->rx_status.he_flags1 |= value; 1138 1139 /* HE-MU-flags2 */ 1140 ppdu_info->rx_status.he_flags2 = 1141 QDF_MON_STATUS_BW_KNOWN; 1142 1143 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1144 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 1145 ppdu_info->rx_status.he_flags2 |= value; 1146 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1147 HE_SIG_A_MU_DL_INFO, COMP_MODE_SIG_B); 1148 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1149 ppdu_info->rx_status.he_flags2 |= value; 1150 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1151 HE_SIG_A_MU_DL_INFO, NUM_SIG_B_SYMBOLS); 1152 value = value - 1; 1153 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1154 ppdu_info->rx_status.he_flags2 |= value; 1155 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1156 break; 1157 } 1158 case WIFIPHYRX_HE_SIG_B1_MU_E: 1159 { 1160 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 1161 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 1162 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 1163 1164 ppdu_info->rx_status.he_sig_b_common_known |= 1165 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 1166 /* TODO: Check on the availability of other fields in 1167 * sig_b_common 1168 */ 1169 1170 value = HAL_RX_GET(he_sig_b1_mu_info, 1171 HE_SIG_B1_MU_INFO, RU_ALLOCATION); 1172 ppdu_info->rx_status.he_RU[0] = value; 1173 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1174 break; 1175 } 1176 case WIFIPHYRX_HE_SIG_B2_MU_E: 1177 { 1178 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 1179 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 1180 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 1181 /* 1182 * Not all "HE" fields can be updated from 1183 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1184 * to populate rest of the "HE" fields for MU scenarios. 1185 */ 1186 1187 /* HE-data1 */ 1188 ppdu_info->rx_status.he_data1 |= 1189 QDF_MON_STATUS_HE_MCS_KNOWN | 1190 QDF_MON_STATUS_HE_CODING_KNOWN; 1191 1192 /* HE-data2 */ 1193 1194 /* HE-data3 */ 1195 value = HAL_RX_GET(he_sig_b2_mu_info, 1196 HE_SIG_B2_MU_INFO, STA_MCS); 1197 ppdu_info->rx_status.mcs = value; 1198 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1199 ppdu_info->rx_status.he_data3 |= value; 1200 1201 value = HAL_RX_GET(he_sig_b2_mu_info, 1202 HE_SIG_B2_MU_INFO, STA_CODING); 1203 value = value << QDF_MON_STATUS_CODING_SHIFT; 1204 ppdu_info->rx_status.he_data3 |= value; 1205 1206 /* HE-data4 */ 1207 value = HAL_RX_GET(he_sig_b2_mu_info, 1208 HE_SIG_B2_MU_INFO, STA_ID); 1209 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1210 ppdu_info->rx_status.he_data4 |= value; 1211 1212 /* HE-data5 */ 1213 1214 /* HE-data6 */ 1215 value = HAL_RX_GET(he_sig_b2_mu_info, 1216 HE_SIG_B2_MU_INFO, NSTS); 1217 /* value n indicates n+1 spatial streams */ 1218 value++; 1219 ppdu_info->rx_status.nss = value; 1220 ppdu_info->rx_status.he_data6 |= value; 1221 1222 break; 1223 } 1224 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1225 { 1226 uint8_t *he_sig_b2_ofdma_info = 1227 (uint8_t *)rx_tlv + 1228 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1229 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1230 1231 /* 1232 * Not all "HE" fields can be updated from 1233 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1234 * to populate rest of "HE" fields for MU OFDMA scenarios. 1235 */ 1236 1237 /* HE-data1 */ 1238 ppdu_info->rx_status.he_data1 |= 1239 QDF_MON_STATUS_HE_MCS_KNOWN | 1240 QDF_MON_STATUS_HE_DCM_KNOWN | 1241 QDF_MON_STATUS_HE_CODING_KNOWN; 1242 1243 /* HE-data2 */ 1244 ppdu_info->rx_status.he_data2 |= 1245 QDF_MON_STATUS_TXBF_KNOWN; 1246 1247 /* HE-data3 */ 1248 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1249 HE_SIG_B2_OFDMA_INFO, STA_MCS); 1250 ppdu_info->rx_status.mcs = value; 1251 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1252 ppdu_info->rx_status.he_data3 |= value; 1253 1254 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1255 HE_SIG_B2_OFDMA_INFO, STA_DCM); 1256 he_dcm = value; 1257 value = value << QDF_MON_STATUS_DCM_SHIFT; 1258 ppdu_info->rx_status.he_data3 |= value; 1259 1260 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1261 HE_SIG_B2_OFDMA_INFO, STA_CODING); 1262 value = value << QDF_MON_STATUS_CODING_SHIFT; 1263 ppdu_info->rx_status.he_data3 |= value; 1264 1265 /* HE-data4 */ 1266 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1267 HE_SIG_B2_OFDMA_INFO, STA_ID); 1268 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1269 ppdu_info->rx_status.he_data4 |= value; 1270 1271 /* HE-data5 */ 1272 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1273 HE_SIG_B2_OFDMA_INFO, TXBF); 1274 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1275 ppdu_info->rx_status.he_data5 |= value; 1276 1277 /* HE-data6 */ 1278 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1279 HE_SIG_B2_OFDMA_INFO, NSTS); 1280 /* value n indicates n+1 spatial streams */ 1281 value++; 1282 ppdu_info->rx_status.nss = value; 1283 ppdu_info->rx_status.he_data6 |= value; 1284 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1285 break; 1286 } 1287 case WIFIPHYRX_RSSI_LEGACY_E: 1288 { 1289 uint8_t reception_type; 1290 int8_t rssi_value; 1291 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1292 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1293 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1294 1295 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1296 PHYRX_RSSI_LEGACY, RSSI_COMB); 1297 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1298 ppdu_info->rx_status.he_re = 0; 1299 1300 reception_type = HAL_RX_GET(rx_tlv, 1301 PHYRX_RSSI_LEGACY, 1302 RECEPTION_TYPE); 1303 switch (reception_type) { 1304 case QDF_RECEPTION_TYPE_ULOFMDA: 1305 ppdu_info->rx_status.reception_type = 1306 HAL_RX_TYPE_MU_OFDMA; 1307 ppdu_info->rx_status.ulofdma_flag = 1; 1308 ppdu_info->rx_status.he_data1 = 1309 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1310 break; 1311 case QDF_RECEPTION_TYPE_ULMIMO: 1312 ppdu_info->rx_status.reception_type = 1313 HAL_RX_TYPE_MU_MIMO; 1314 ppdu_info->rx_status.he_data1 = 1315 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1316 break; 1317 default: 1318 ppdu_info->rx_status.reception_type = 1319 HAL_RX_TYPE_SU; 1320 break; 1321 } 1322 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 1323 rssi_value = HAL_RX_GET(rssi_info_tlv, 1324 RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN0); 1325 ppdu_info->rx_status.rssi[0] = rssi_value; 1326 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1327 "RSSI_PRI20_CHAIN0: %d\n", rssi_value); 1328 1329 rssi_value = HAL_RX_GET(rssi_info_tlv, 1330 RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN1); 1331 ppdu_info->rx_status.rssi[1] = rssi_value; 1332 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1333 "RSSI_PRI20_CHAIN1: %d\n", rssi_value); 1334 1335 rssi_value = HAL_RX_GET(rssi_info_tlv, 1336 RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN2); 1337 ppdu_info->rx_status.rssi[2] = rssi_value; 1338 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1339 "RSSI_PRI20_CHAIN2: %d\n", rssi_value); 1340 1341 rssi_value = HAL_RX_GET(rssi_info_tlv, 1342 RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN3); 1343 ppdu_info->rx_status.rssi[3] = rssi_value; 1344 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1345 "RSSI_PRI20_CHAIN3: %d\n", rssi_value); 1346 1347 #ifdef DP_BE_NOTYET_WAR 1348 // TODO - this is not preset for wcn7850 1349 rssi_value = HAL_RX_GET(rssi_info_tlv, 1350 RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN4); 1351 ppdu_info->rx_status.rssi[4] = rssi_value; 1352 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1353 "RSSI_PRI20_CHAIN4: %d\n", rssi_value); 1354 1355 rssi_value = HAL_RX_GET(rssi_info_tlv, 1356 RECEIVE_RSSI_INFO, 1357 RSSI_PRI20_CHAIN5); 1358 ppdu_info->rx_status.rssi[5] = rssi_value; 1359 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1360 "RSSI_PRI20_CHAIN5: %d\n", rssi_value); 1361 1362 rssi_value = HAL_RX_GET(rssi_info_tlv, 1363 RECEIVE_RSSI_INFO, 1364 RSSI_PRI20_CHAIN6); 1365 ppdu_info->rx_status.rssi[6] = rssi_value; 1366 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1367 "RSSI_PRI20_CHAIN6: %d\n", rssi_value); 1368 1369 rssi_value = HAL_RX_GET(rssi_info_tlv, 1370 RECEIVE_RSSI_INFO, 1371 RSSI_PRI20_CHAIN7); 1372 ppdu_info->rx_status.rssi[7] = rssi_value; 1373 #endif 1374 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1375 "RSSI_PRI20_CHAIN7: %d\n", rssi_value); 1376 break; 1377 } 1378 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1379 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1380 ppdu_info); 1381 break; 1382 case WIFIRX_HEADER_E: 1383 { 1384 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 1385 1386 if (ppdu_info->fcs_ok_cnt >= 1387 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 1388 hal_err("Number of MPDUs(%d) per status buff exceeded", 1389 ppdu_info->fcs_ok_cnt); 1390 break; 1391 } 1392 1393 /* Update first_msdu_payload for every mpdu and increment 1394 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 1395 */ 1396 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 1397 rx_tlv; 1398 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 1399 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1400 ppdu_info->msdu_info.payload_len = tlv_len; 1401 ppdu_info->user_id = user_id; 1402 ppdu_info->hdr_len = tlv_len; 1403 ppdu_info->data = rx_tlv; 1404 ppdu_info->data += 4; 1405 1406 /* for every RX_HEADER TLV increment mpdu_cnt */ 1407 com_info->mpdu_cnt++; 1408 return HAL_TLV_STATUS_HEADER; 1409 } 1410 case WIFIRX_MPDU_START_E: 1411 { 1412 uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv; 1413 uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_tlv); 1414 uint8_t filter_category = 0; 1415 1416 ppdu_info->nac_info.fc_valid = 1417 HAL_RX_GET_FC_VALID(rx_tlv); 1418 1419 ppdu_info->nac_info.to_ds_flag = 1420 HAL_RX_GET_TO_DS_FLAG(rx_tlv); 1421 1422 ppdu_info->nac_info.frame_control = 1423 HAL_RX_GET(rx_mpdu_start, 1424 RX_MPDU_INFO, 1425 MPDU_FRAME_CONTROL_FIELD); 1426 1427 ppdu_info->sw_frame_group_id = 1428 HAL_RX_GET_SW_FRAME_GROUP_ID(rx_tlv); 1429 1430 if (ppdu_info->sw_frame_group_id == 1431 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 1432 ppdu_info->rx_status.frame_control_info_valid = 1433 ppdu_info->nac_info.fc_valid; 1434 ppdu_info->rx_status.frame_control = 1435 ppdu_info->nac_info.frame_control; 1436 } 1437 1438 hal_get_mac_addr1(rx_mpdu_start, 1439 ppdu_info); 1440 1441 ppdu_info->nac_info.mac_addr2_valid = 1442 HAL_RX_TLV_MPDU_MAC_ADDR_AD2_VALID_GET(rx_tlv); 1443 1444 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1445 HAL_RX_GET(rx_mpdu_start, 1446 RX_MPDU_INFO, 1447 MAC_ADDR_AD2_15_0); 1448 1449 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1450 HAL_RX_GET(rx_mpdu_start, 1451 RX_MPDU_INFO, 1452 MAC_ADDR_AD2_47_16); 1453 1454 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1455 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1456 ppdu_info->rx_status.ppdu_len = 1457 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, 1458 MPDU_LENGTH); 1459 } else { 1460 ppdu_info->rx_status.ppdu_len += 1461 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, 1462 MPDU_LENGTH); 1463 } 1464 1465 filter_category = 1466 HAL_RX_GET_FILTER_CATEGORY(rx_tlv); 1467 1468 if (filter_category == 0) 1469 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1470 else if (filter_category == 1) 1471 ppdu_info->rx_status.monitor_direct_used = 1; 1472 1473 ppdu_info->nac_info.mcast_bcast = 1474 HAL_RX_GET(rx_mpdu_start, 1475 RX_MPDU_INFO, 1476 MCAST_BCAST); 1477 break; 1478 } 1479 case WIFIRX_MPDU_END_E: 1480 ppdu_info->user_id = user_id; 1481 ppdu_info->fcs_err = 1482 HAL_RX_GET(rx_tlv, RX_MPDU_END, 1483 FCS_ERR); 1484 return HAL_TLV_STATUS_MPDU_END; 1485 case WIFIRX_MSDU_END_E: 1486 if (user_id < HAL_MAX_UL_MU_USERS) { 1487 ppdu_info->rx_msdu_info[user_id].cce_metadata = 1488 HAL_RX_TLV_CCE_METADATA_GET(rx_tlv); 1489 ppdu_info->rx_msdu_info[user_id].fse_metadata = 1490 HAL_RX_TLV_FSE_METADATA_GET(rx_tlv); 1491 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 1492 HAL_RX_TLV_FLOW_IDX_TIMEOUT_GET(rx_tlv); 1493 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 1494 HAL_RX_TLV_FLOW_IDX_INVALID_GET(rx_tlv); 1495 ppdu_info->rx_msdu_info[user_id].flow_idx = 1496 HAL_RX_TLV_FLOW_IDX_GET(rx_tlv); 1497 } 1498 return HAL_TLV_STATUS_MSDU_END; 1499 case 0: 1500 return HAL_TLV_STATUS_PPDU_DONE; 1501 1502 default: 1503 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1504 unhandled = false; 1505 else 1506 unhandled = true; 1507 break; 1508 } 1509 1510 if (!unhandled) 1511 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1512 "%s TLV type: %d, TLV len:%d %s", 1513 __func__, tlv_tag, tlv_len, 1514 unhandled == true ? "unhandled" : ""); 1515 1516 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1517 rx_tlv, tlv_len); 1518 1519 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1520 } 1521 1522 /** 1523 * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table 1524 * @soc: HAL SoC context 1525 * @map: PCP-TID mapping table 1526 * 1527 * PCP are mapped to 8 TID values using TID values programmed 1528 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 1529 * The mapping register has TID mapping for 8 PCP values 1530 * 1531 * Return: none 1532 */ 1533 static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map) 1534 { 1535 uint32_t addr, value; 1536 1537 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 1538 MAC_TCL_REG_REG_BASE); 1539 1540 value = (map[0] | 1541 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 1542 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 1543 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 1544 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 1545 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 1546 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 1547 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 1548 1549 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 1550 } 1551 1552 /** 1553 * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with 1554 * value received from user-space 1555 * @soc: HAL SoC context 1556 * @pcp: pcp value 1557 * @tid : tid value 1558 * 1559 * Return: void 1560 */ 1561 static void 1562 hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc, 1563 uint8_t pcp, uint8_t tid) 1564 { 1565 uint32_t addr, value, regval; 1566 1567 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 1568 MAC_TCL_REG_REG_BASE); 1569 1570 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 1571 1572 /* Read back previous PCP TID config and update 1573 * with new config. 1574 */ 1575 regval = HAL_REG_READ(soc, addr); 1576 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 1577 regval |= value; 1578 1579 HAL_REG_WRITE(soc, addr, 1580 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 1581 } 1582 1583 /** 1584 * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority 1585 * @soc: HAL SoC context 1586 * @val: priority value 1587 * 1588 * Return: void 1589 */ 1590 static 1591 void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value) 1592 { 1593 uint32_t addr; 1594 1595 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 1596 MAC_TCL_REG_REG_BASE); 1597 1598 HAL_REG_WRITE(soc, addr, 1599 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 1600 } 1601 1602 /** 1603 * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size 1604 * @rx_pkt_tlv_size: TLV size for regular RX packets 1605 * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets 1606 * 1607 * Return: size of rx pkt tlv before the actual data 1608 */ 1609 static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size, 1610 uint16_t *rx_mon_pkt_tlv_size) 1611 { 1612 *rx_pkt_tlv_size = RX_PKT_TLVS_LEN; 1613 /* For now mon pkt tlv is same as rx pkt tlv */ 1614 *rx_mon_pkt_tlv_size = RX_PKT_TLVS_LEN; 1615 } 1616 #endif /* _HAL_BE_GENERIC_API_H_ */ 1617