1 /* 2 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HAL_BE_API_MON_H_ 19 #define _HAL_BE_API_MON_H_ 20 21 #include "hal_be_hw_headers.h" 22 #ifdef QCA_MONITOR_2_0_SUPPORT 23 #include <mon_ingress_ring.h> 24 #include <mon_destination_ring.h> 25 #endif 26 #include <hal_be_hw_headers.h> 27 #include "hal_api_mon.h" 28 #include <hal_generic_api.h> 29 #include <hal_generic_api.h> 30 #include <hal_api_mon.h> 31 32 #if defined(QCA_MONITOR_2_0_SUPPORT) || \ 33 defined(QCA_SINGLE_WIFI_3_0) 34 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 35 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 36 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff 37 38 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 39 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 40 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff 41 42 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 43 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 44 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 45 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 46 47 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c 48 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 49 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 50 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 51 52 #define HAL_MON_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 53 ((*(((unsigned int *) buff_addr_info) + \ 54 (HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 55 ((paddr_lo) << HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 56 HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 57 58 #define HAL_MON_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 59 ((*(((unsigned int *) buff_addr_info) + \ 60 (HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 61 ((paddr_hi) << HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 62 HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 63 64 #define HAL_MON_VADDR_LO_SET(buff_addr_info, vaddr_lo) \ 65 ((*(((unsigned int *) buff_addr_info) + \ 66 (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET >> 2))) = \ 67 ((vaddr_lo) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB) & \ 68 HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK) 69 70 #define HAL_MON_VADDR_HI_SET(buff_addr_info, vaddr_hi) \ 71 ((*(((unsigned int *) buff_addr_info) + \ 72 (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET >> 2))) = \ 73 ((vaddr_hi) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB) & \ 74 HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK) 75 76 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 77 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 78 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 79 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 80 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 81 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 82 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 83 PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 84 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 85 PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 86 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 87 PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 88 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 89 PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 90 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 91 PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 92 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 93 PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 94 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 95 PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 96 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 97 PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 98 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 99 PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 100 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 101 PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 102 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 103 PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 104 #endif 105 106 #ifdef CONFIG_MON_WORD_BASED_TLV 107 #ifndef BIG_ENDIAN_HOST 108 struct rx_mpdu_start_mon_data { 109 uint32_t rxpcu_mpdu_filter_in_category : 2, 110 sw_frame_group_id : 7, 111 ndp_frame : 1, 112 phy_err : 1, 113 phy_err_during_mpdu_header : 1, 114 protocol_version_err : 1, 115 ast_based_lookup_valid : 1, 116 reserved_0a : 2, 117 phy_ppdu_id : 16; 118 uint32_t ast_index : 16, 119 sw_peer_id : 16; 120 uint32_t mpdu_frame_control_valid : 1, 121 mpdu_duration_valid : 1, 122 mac_addr_ad1_valid : 1, 123 mac_addr_ad2_valid : 1, 124 mac_addr_ad3_valid : 1, 125 mac_addr_ad4_valid : 1, 126 mpdu_sequence_control_valid : 1, 127 mpdu_qos_control_valid : 1, 128 mpdu_ht_control_valid : 1, 129 frame_encryption_info_valid : 1, 130 mpdu_fragment_number : 4, 131 more_fragment_flag : 1, 132 reserved_11a : 1, 133 fr_ds : 1, 134 to_ds : 1, 135 encrypted : 1, 136 mpdu_retry : 1, 137 mpdu_sequence_number : 12; 138 uint32_t mpdu_length : 14, 139 first_mpdu : 1, 140 mcast_bcast : 1, 141 ast_index_not_found : 1, 142 ast_index_timeout : 1, 143 power_mgmt : 1, 144 non_qos : 1, 145 null_data : 1, 146 mgmt_type : 1, 147 ctrl_type : 1, 148 more_data : 1, 149 eosp : 1, 150 fragment_flag : 1, 151 order : 1, 152 u_apsd_trigger : 1, 153 encrypt_required : 1, 154 directed : 1, 155 amsdu_present : 1, 156 reserved_13 : 1; 157 uint32_t mpdu_frame_control_field : 16, 158 mpdu_duration_field : 16; 159 uint32_t mac_addr_ad1_31_0 : 32; 160 uint32_t mac_addr_ad1_47_32 : 16, 161 mac_addr_ad2_15_0 : 16; 162 }; 163 164 struct rx_msdu_end_mon_data { 165 uint32_t rxpcu_mpdu_filter_in_category : 2, 166 sw_frame_group_id : 7, 167 reserved_0 : 7, 168 phy_ppdu_id : 16; 169 uint32_t tcp_udp_chksum : 16, 170 sa_idx_timeout : 1, 171 da_idx_timeout : 1, 172 msdu_limit_error : 1, 173 flow_idx_timeout : 1, 174 flow_idx_invalid : 1, 175 wifi_parser_error : 1, 176 amsdu_parser_error : 1, 177 sa_is_valid : 1, 178 da_is_valid : 1, 179 da_is_mcbc : 1, 180 l3_header_padding : 2, 181 first_msdu : 1, 182 last_msdu : 1, 183 tcp_udp_chksum_fail : 1, 184 ip_chksum_fail : 1; 185 uint32_t msdu_drop : 1, 186 reo_destination_indication : 5, 187 flow_idx : 20, 188 reserved_12a : 6; 189 uint32_t fse_metadata : 32; 190 uint32_t cce_metadata : 16, 191 sa_sw_peer_id : 16; 192 }; 193 #else 194 struct rx_mpdu_start_mon_data { 195 uint32_t phy_ppdu_id : 16; 196 reserved_0a : 2, 197 ast_based_lookup_valid : 1, 198 protocol_version_err : 1, 199 phy_err_during_mpdu_header : 1, 200 phy_err : 1, 201 ndp_frame : 1, 202 sw_frame_group_id : 7, 203 rxpcu_mpdu_filter_in_category : 2, 204 uint32_t sw_peer_id : 16; 205 ast_index : 16, 206 uint32_t mpdu_sequence_number : 12; 207 mpdu_retry : 1, 208 encrypted : 1, 209 to_ds : 1, 210 fr_ds : 1, 211 reserved_11a : 1, 212 more_fragment_flag : 1, 213 mpdu_fragment_number : 4, 214 frame_encryption_info_valid : 1, 215 mpdu_ht_control_valid : 1, 216 mpdu_qos_control_valid : 1, 217 mpdu_sequence_control_valid : 1, 218 mac_addr_ad4_valid : 1, 219 mac_addr_ad3_valid : 1, 220 mac_addr_ad2_valid : 1, 221 mac_addr_ad1_valid : 1, 222 mpdu_duration_valid : 1, 223 mpdu_frame_control_valid : 1, 224 uint32_t reserved_13 : 1; 225 amsdu_present : 1, 226 directed : 1, 227 encrypt_required : 1, 228 u_apsd_trigger : 1, 229 order : 1, 230 fragment_flag : 1, 231 eosp : 1, 232 more_data : 1, 233 ctrl_type : 1, 234 mgmt_type : 1, 235 null_data : 1, 236 non_qos : 1, 237 power_mgmt : 1, 238 ast_index_timeout : 1, 239 ast_index_not_found : 1, 240 mcast_bcast : 1, 241 first_mpdu : 1, 242 mpdu_length : 14, 243 uint32_t mpdu_duration_field : 16; 244 mpdu_frame_control_field : 16, 245 uint32_t mac_addr_ad1_31_0 : 32; 246 uint32_t mac_addr_ad2_15_0 : 16; 247 mac_addr_ad1_47_32 : 16, 248 }; 249 250 struct rx_msdu_end_mon_data { 251 uint32_t phy_ppdu_id : 16; 252 reserved_0 : 7, 253 sw_frame_group_id : 7, 254 rxpcu_mpdu_filter_in_category : 2, 255 uint32_t ip_chksum_fail : 1; 256 tcp_udp_chksum_fail : 1, 257 last_msdu : 1, 258 first_msdu : 1, 259 l3_header_padding : 2, 260 da_is_mcbc : 1, 261 da_is_valid : 1, 262 sa_is_valid : 1, 263 amsdu_parser_error : 1, 264 wifi_parser_error : 1, 265 flow_idx_invalid : 1, 266 flow_idx_timeout : 1, 267 msdu_limit_error : 1, 268 da_idx_timeout : 1, 269 sa_idx_timeout : 1, 270 tcp_udp_chksum : 16, 271 uint32_t reserved_12a : 6; 272 flow_idx : 20, 273 reo_destination_indication : 5, 274 msdu_drop : 1, 275 uint32_t fse_metadata : 32; 276 uint32_t sa_sw_peer_id : 16; 277 cce_metadata : 16, 278 }; 279 #endif 280 281 /* TLV struct for word based Tlv */ 282 typedef struct rx_mpdu_start_mon_data hal_rx_mon_mpdu_start_t; 283 typedef struct rx_msdu_end_mon_data hal_rx_mon_msdu_end_t; 284 285 #else 286 287 typedef struct rx_mpdu_start hal_rx_mon_mpdu_start_t; 288 typedef struct rx_msdu_end hal_rx_mon_msdu_end_t; 289 #endif 290 291 /* 292 * struct mon_destination_drop - monitor drop descriptor 293 * 294 * @ppdu_drop_cnt: PPDU drop count 295 * @mpdu_drop_cnt: MPDU drop count 296 * @tlv_drop_cnt: TLV drop count 297 * @end_of_ppdu_seen: end of ppdu seen 298 * @reserved_0a: rsvd 299 * @reserved_1a: rsvd 300 * @ppdu_id: PPDU ID 301 * @reserved_3a: rsvd 302 * @initiator: initiator ppdu 303 * @empty_descriptor: empty descriptor 304 * @ring_id: ring id 305 * @looping_count: looping count 306 */ 307 struct mon_destination_drop { 308 uint32_t ppdu_drop_cnt : 10, 309 mpdu_drop_cnt : 10, 310 tlv_drop_cnt : 10, 311 end_of_ppdu_seen : 1, 312 reserved_0a : 1; 313 uint32_t reserved_1a : 32; 314 uint32_t ppdu_id : 32; 315 uint32_t reserved_3a : 18, 316 initiator : 1, 317 empty_descriptor : 1, 318 ring_id : 8, 319 looping_count : 4; 320 }; 321 322 #define HAL_MON_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 323 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 324 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 325 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 326 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 327 328 #define HAL_MON_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 329 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 330 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 331 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 332 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 333 334 /** 335 * struct hal_rx_status_buffer_done - status buffer done tlv 336 * placeholder structure 337 * 338 * @ppdu_start_offset: ppdu start 339 * @first_ppdu_start_user_info_offset: 340 * @mult_ppdu_start_user_info: 341 * @end_offset: 342 * @ppdu_end_detected: 343 * @flush_detected: 344 * @rsvd: 345 */ 346 struct hal_rx_status_buffer_done { 347 uint32_t ppdu_start_offset : 3, 348 first_ppdu_start_user_info_offset : 6, 349 mult_ppdu_start_user_info : 1, 350 end_offset : 13, 351 ppdu_end_detected : 1, 352 flush_detected : 1, 353 rsvd : 7; 354 }; 355 356 /** 357 * hal_mon_status_end_reason : ppdu status buffer end reason 358 * 359 * @HAL_MON_STATUS_BUFFER_FULL: status buffer full 360 * @HAL_MON_FLUSH_DETECTED: flush detected 361 * @HAL_MON_END_OF_PPDU: end of ppdu detected 362 * HAL_MON_PPDU_truncated: truncated ppdu status 363 */ 364 enum hal_mon_status_end_reason { 365 HAL_MON_STATUS_BUFFER_FULL, 366 HAL_MON_FLUSH_DETECTED, 367 HAL_MON_END_OF_PPDU, 368 HAL_MON_PPDU_TRUNCATED, 369 }; 370 371 /** 372 * struct hal_mon_desc () - HAL Monitor descriptor 373 * 374 * @buf_addr: virtual buffer address 375 * @ppdu_id: ppdu id 376 * - TxMon fills scheduler id 377 * - RxMON fills phy_ppdu_id 378 * @end_offset: offset (units in 4 bytes) where status buffer ended 379 * i.e offset of TLV + last TLV size 380 * @end_reason: 0 - status buffer is full 381 * 1 - flush detected 382 * 2 - TX_FES_STATUS_END or RX_PPDU_END 383 * 3 - PPDU truncated due to system error 384 * @initiator: 1 - descriptor belongs to TX FES 385 * 0 - descriptor belongs to TX RESPONSE 386 * @empty_descriptor: 0 - this descriptor is written on a flush 387 * or end of ppdu or end of status buffer 388 * 1 - descriptor provided to indicate drop 389 * @ring_id: ring id for debugging 390 * @looping_count: count to indicate number of times producer 391 * of entries has looped around the ring 392 * @flush_detected: if flush detected 393 * @end_reason: ppdu end reason 394 * @end_of_ppdu_dropped: if end_of_ppdu is dropped 395 * @ppdu_drop_count: PPDU drop count 396 * @mpdu_drop_count: MPDU drop count 397 * @tlv_drop_count: TLV drop count 398 */ 399 struct hal_mon_desc { 400 uint64_t buf_addr; 401 uint32_t ppdu_id; 402 uint32_t end_offset:12, 403 reserved_3a:4, 404 end_reason:2, 405 initiator:1, 406 empty_descriptor:1, 407 ring_id:8, 408 looping_count:4; 409 uint16_t flush_detected:1, 410 end_of_ppdu_dropped:1; 411 uint32_t ppdu_drop_count; 412 uint32_t mpdu_drop_count; 413 uint32_t tlv_drop_count; 414 }; 415 416 typedef struct hal_mon_desc *hal_mon_desc_t; 417 418 /** 419 * struct hal_mon_buf_addr_status () - HAL buffer address tlv get status 420 * 421 * @buf_addr_31_0: Lower 32 bits of virtual address of status buffer 422 * @buf_addr_63_32: Upper 32 bits of virtual address of status buffer 423 * @dma_length: DMA length 424 * @msdu_continuation: is msdu size more than fragment size 425 * @truncated: is msdu got truncated 426 * @tlv_padding: tlv paddding 427 */ 428 struct hal_mon_buf_addr_status { 429 uint32_t buffer_virt_addr_31_0; 430 uint32_t buffer_virt_addr_63_32; 431 uint32_t dma_length:12, 432 reserved_2a:4, 433 msdu_continuation:1, 434 truncated:1, 435 reserved_2b:14; 436 uint32_t tlv64_padding; 437 }; 438 439 #ifdef QCA_MONITOR_2_0_SUPPORT 440 /** 441 * hal_be_get_mon_dest_status() - Get monitor descriptor 442 * @hal_soc_hdl: HAL Soc handle 443 * @desc: HAL monitor descriptor 444 * 445 * Return: none 446 */ 447 static inline void 448 hal_be_get_mon_dest_status(hal_soc_handle_t hal_soc, 449 void *hw_desc, 450 struct hal_mon_desc *status) 451 { 452 struct mon_destination_ring *desc = hw_desc; 453 454 status->empty_descriptor = desc->empty_descriptor; 455 if (status->empty_descriptor) { 456 struct mon_destination_drop *drop_desc = hw_desc; 457 458 status->buf_addr = 0; 459 status->ppdu_drop_count = drop_desc->ppdu_drop_cnt; 460 status->mpdu_drop_count = drop_desc->mpdu_drop_cnt; 461 status->tlv_drop_count = drop_desc->tlv_drop_cnt; 462 status->end_of_ppdu_dropped = drop_desc->end_of_ppdu_seen; 463 } else { 464 status->buf_addr = HAL_RX_GET(desc, MON_DESTINATION_RING_STAT,BUF_VIRT_ADDR_31_0) | 465 (((uint64_t)HAL_RX_GET(desc, 466 MON_DESTINATION_RING_STAT, 467 BUF_VIRT_ADDR_63_32)) << 32); 468 status->end_reason = desc->end_reason; 469 status->end_offset = desc->end_offset; 470 } 471 status->ppdu_id = desc->ppdu_id; 472 status->initiator = desc->initiator; 473 status->looping_count = desc->looping_count; 474 } 475 #endif 476 477 #if defined(RX_PPDU_END_USER_STATS_OFDMA_INFO_VALID_OFFSET) && \ 478 defined(RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 479 480 static inline void 481 hal_rx_handle_mu_ul_info(void *rx_tlv, 482 struct mon_rx_user_status *mon_rx_user_status) 483 { 484 mon_rx_user_status->mu_ul_user_v0_word0 = 485 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 486 SW_RESPONSE_REFERENCE_PTR); 487 488 mon_rx_user_status->mu_ul_user_v0_word1 = 489 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 490 SW_RESPONSE_REFERENCE_PTR_EXT); 491 } 492 #else 493 static inline void 494 hal_rx_handle_mu_ul_info(void *rx_tlv, 495 struct mon_rx_user_status *mon_rx_user_status) 496 { 497 } 498 #endif 499 500 static inline void 501 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 502 struct mon_rx_user_status *mon_rx_user_status) 503 { 504 uint32_t mpdu_ok_byte_count; 505 uint32_t mpdu_err_byte_count; 506 507 mpdu_ok_byte_count = HAL_RX_GET_64(rx_tlv, 508 RX_PPDU_END_USER_STATS, 509 MPDU_OK_BYTE_COUNT); 510 mpdu_err_byte_count = HAL_RX_GET_64(rx_tlv, 511 RX_PPDU_END_USER_STATS, 512 MPDU_ERR_BYTE_COUNT); 513 514 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 515 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 516 } 517 518 static inline void 519 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id, 520 struct mon_rx_user_status *mon_rx_user_status) 521 { 522 struct mon_rx_info *mon_rx_info; 523 struct mon_rx_user_info *mon_rx_user_info; 524 struct hal_rx_ppdu_info *ppdu_info = 525 (struct hal_rx_ppdu_info *)ppduinfo; 526 527 mon_rx_info = &ppdu_info->rx_info; 528 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 529 mon_rx_user_info->qos_control_info_valid = 530 mon_rx_info->qos_control_info_valid; 531 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 532 533 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 534 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 535 mon_rx_user_status->tcp_msdu_count = 536 ppdu_info->rx_status.tcp_msdu_count; 537 mon_rx_user_status->udp_msdu_count = 538 ppdu_info->rx_status.udp_msdu_count; 539 mon_rx_user_status->other_msdu_count = 540 ppdu_info->rx_status.other_msdu_count; 541 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 542 mon_rx_user_status->frame_control_info_valid = 543 ppdu_info->rx_status.frame_control_info_valid; 544 mon_rx_user_status->data_sequence_control_info_valid = 545 ppdu_info->rx_status.data_sequence_control_info_valid; 546 mon_rx_user_status->first_data_seq_ctrl = 547 ppdu_info->rx_status.first_data_seq_ctrl; 548 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 549 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 550 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 551 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 552 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 553 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 554 555 mon_rx_user_status->mpdu_cnt_fcs_ok = 556 ppdu_info->com_info.mpdu_cnt_fcs_ok; 557 mon_rx_user_status->mpdu_cnt_fcs_err = 558 ppdu_info->com_info.mpdu_cnt_fcs_err; 559 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 560 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 561 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 562 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 563 mon_rx_user_status->retry_mpdu = 564 ppdu_info->rx_status.mpdu_retry_cnt; 565 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 566 } 567 568 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, \ 569 ppdu_info, rssi_info_tlv) \ 570 { \ 571 ppdu_info->rx_status.rssi_chain[chain][0] = \ 572 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 573 RSSI_PRI20_CHAIN##chain); \ 574 ppdu_info->rx_status.rssi_chain[chain][1] = \ 575 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 576 RSSI_EXT20_CHAIN##chain); \ 577 ppdu_info->rx_status.rssi_chain[chain][2] = \ 578 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 579 RSSI_EXT40_LOW20_CHAIN##chain); \ 580 ppdu_info->rx_status.rssi_chain[chain][3] = \ 581 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 582 RSSI_EXT40_HIGH20_CHAIN##chain); \ 583 } \ 584 585 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 586 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, ppdu_info, rssi_info_tlv) \ 587 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, ppdu_info, rssi_info_tlv) \ 588 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, ppdu_info, rssi_info_tlv) \ 589 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, ppdu_info, rssi_info_tlv) \ 590 } \ 591 592 static inline uint32_t 593 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 594 uint8_t *rssi_info_tlv) 595 { 596 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 597 return 0; 598 } 599 600 #ifdef WLAN_TX_PKT_CAPTURE_ENH 601 static inline void 602 hal_get_qos_control(void *rx_tlv, 603 struct hal_rx_ppdu_info *ppdu_info) 604 { 605 ppdu_info->rx_info.qos_control_info_valid = 606 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 607 QOS_CONTROL_INFO_VALID); 608 609 if (ppdu_info->rx_info.qos_control_info_valid) 610 ppdu_info->rx_info.qos_control = 611 HAL_RX_GET_64(rx_tlv, 612 RX_PPDU_END_USER_STATS, 613 QOS_CONTROL_FIELD); 614 } 615 616 static inline void 617 hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 618 struct hal_rx_ppdu_info *ppdu_info) 619 { 620 if ((ppdu_info->sw_frame_group_id 621 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 622 (ppdu_info->sw_frame_group_id == 623 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 624 ppdu_info->rx_info.mac_addr1_valid = 625 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_valid; 626 627 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 628 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_31_0; 629 if (ppdu_info->sw_frame_group_id == 630 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 631 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 632 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_47_32; 633 } 634 } 635 } 636 #else 637 static inline void 638 hal_get_qos_control(void *rx_tlv, 639 struct hal_rx_ppdu_info *ppdu_info) 640 { 641 } 642 643 static inline void 644 hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 645 struct hal_rx_ppdu_info *ppdu_info) 646 { 647 } 648 #endif 649 650 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 651 static inline void 652 hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 653 struct hal_rx_ppdu_info *ppdu_info) 654 { 655 uint16_t frame_ctrl; 656 uint8_t fc_type; 657 658 if (rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid) { 659 frame_ctrl = rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field; 660 fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl); 661 if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT) 662 ppdu_info->frm_type_info.rx_mgmt_cnt++; 663 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL) 664 ppdu_info->frm_type_info.rx_ctrl_cnt++; 665 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA) 666 ppdu_info->frm_type_info.rx_data_cnt++; 667 } 668 } 669 #else 670 static inline void 671 hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 672 struct hal_rx_ppdu_info *ppdu_info) 673 { 674 } 675 #endif 676 677 #ifdef QCA_MONITOR_2_0_SUPPORT 678 /** 679 * hal_mon_buff_addr_info_set() - set desc address in cookie 680 * @hal_soc_hdl: HAL Soc handle 681 * @mon_entry: monitor srng 682 * @desc: HAL monitor descriptor 683 * 684 * Return: none 685 */ 686 static inline 687 void hal_mon_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 688 void *mon_entry, 689 void *mon_desc_addr, 690 qdf_dma_addr_t phy_addr) 691 { 692 uint32_t paddr_lo = ((uintptr_t)phy_addr & 0x00000000ffffffff); 693 uint32_t paddr_hi = ((uintptr_t)phy_addr & 0xffffffff00000000) >> 32; 694 uint32_t vaddr_lo = ((uintptr_t)mon_desc_addr & 0x00000000ffffffff); 695 uint32_t vaddr_hi = ((uintptr_t)mon_desc_addr & 0xffffffff00000000) >> 32; 696 697 HAL_MON_PADDR_LO_SET(mon_entry, paddr_lo); 698 HAL_MON_PADDR_HI_SET(mon_entry, paddr_hi); 699 HAL_MON_VADDR_LO_SET(mon_entry, vaddr_lo); 700 HAL_MON_VADDR_HI_SET(mon_entry, vaddr_hi); 701 } 702 703 /* TX monitor */ 704 #define TX_MON_STATUS_BUF_SIZE 2048 705 706 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 707 708 #define HAL_MAX_DL_MU_USERS 37 709 #define HAL_MAX_RU_INDEX 7 710 711 enum hal_tx_tlv_status { 712 HAL_MON_TX_FES_SETUP, 713 HAL_MON_TX_FES_STATUS_END, 714 HAL_MON_RX_RESPONSE_REQUIRED_INFO, 715 HAL_MON_RESPONSE_END_STATUS_INFO, 716 717 HAL_MON_TX_PCU_PPDU_SETUP_INIT, 718 719 HAL_MON_TX_MPDU_START, 720 HAL_MON_TX_MSDU_START, 721 HAL_MON_TX_BUFFER_ADDR, 722 HAL_MON_TX_DATA, 723 724 HAL_MON_TX_FES_STATUS_START, 725 726 HAL_MON_TX_FES_STATUS_PROT, 727 HAL_MON_TX_FES_STATUS_START_PROT, 728 729 HAL_MON_TX_FES_STATUS_START_PPDU, 730 HAL_MON_TX_FES_STATUS_USER_PPDU, 731 HAL_MON_TX_QUEUE_EXTENSION, 732 733 HAL_MON_RX_FRAME_BITMAP_ACK, 734 HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_256, 735 HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K, 736 HAL_MON_COEX_TX_STATUS, 737 738 HAL_MON_MACTX_HE_SIG_A_SU, 739 HAL_MON_MACTX_HE_SIG_A_MU_DL, 740 HAL_MON_MACTX_HE_SIG_B1_MU, 741 HAL_MON_MACTX_HE_SIG_B2_MU, 742 HAL_MON_MACTX_HE_SIG_B2_OFDMA, 743 HAL_MON_MACTX_L_SIG_A, 744 HAL_MON_MACTX_L_SIG_B, 745 HAL_MON_MACTX_HT_SIG, 746 HAL_MON_MACTX_VHT_SIG_A, 747 748 HAL_MON_MACTX_USER_DESC_PER_USER, 749 HAL_MON_MACTX_USER_DESC_COMMON, 750 HAL_MON_MACTX_PHY_DESC, 751 752 HAL_MON_TX_STATUS_PPDU_NOT_DONE, 753 }; 754 755 enum txmon_coex_tx_status_reason { 756 COEX_FES_TX_START, 757 COEX_FES_TX_END, 758 COEX_FES_END, 759 COEX_RESPONSE_TX_START, 760 COEX_RESPONSE_TX_END, 761 COEX_NO_TX_ONGOING, 762 }; 763 764 enum txmon_transmission_type { 765 TXMON_SU_TRANSMISSION = 0, 766 TXMON_MU_TRANSMISSION, 767 TXMON_MU_SU_TRANSMISSION, 768 TXMON_MU_MIMO_TRANSMISSION = 1, 769 TXMON_MU_OFDMA_TRANMISSION 770 }; 771 772 enum txmon_he_ppdu_subtype { 773 TXMON_HE_SUBTYPE_SU = 0, 774 TXMON_HE_SUBTYPE_TRIG, 775 TXMON_HE_SUBTYPE_MU, 776 TXMON_HE_SUBTYPE_EXT_SU 777 }; 778 779 enum txmon_pkt_type { 780 TXMON_PKT_TYPE_11A = 0, 781 TXMON_PKT_TYPE_11B, 782 TXMON_PKT_TYPE_11N_MM, 783 TXMON_PKT_TYPE_11AC, 784 TXMON_PKT_TYPE_11AX, 785 TXMON_PKT_TYPE_11BA, 786 TXMON_PKT_TYPE_11BE, 787 TXMON_PKT_TYPE_11AZ 788 }; 789 790 enum txmon_generated_response { 791 TXMON_GEN_RESP_SELFGEN_ACK = 0, 792 TXMON_GEN_RESP_SELFGEN_CTS, 793 TXMON_GEN_RESP_SELFGEN_BA, 794 TXMON_GEN_RESP_SELFGEN_MBA, 795 TXMON_GEN_RESP_SELFGEN_CBF, 796 TXMON_GEN_RESP_SELFGEN_TRIG, 797 TXMON_GEN_RESP_SELFGEN_NDP_LMR 798 }; 799 800 #define IS_MULTI_USERS(num_users) (!!(0xFFFE & num_users)) 801 802 #define TXMON_HAL(hal_tx_ppdu_info, field) \ 803 hal_tx_ppdu_info->field 804 #define TXMON_HAL_STATUS(hal_tx_ppdu_info, field) \ 805 hal_tx_ppdu_info->rx_status.field 806 #define TXMON_HAL_USER(hal_tx_ppdu_info, user_id, field) \ 807 hal_tx_ppdu_info->rx_user_status[user_id].field 808 809 #define TXMON_STATUS_INFO(hal_tx_status_info, field) \ 810 hal_tx_status_info->field 811 812 /** 813 * struct hal_tx_status_info - status info that wasn't populated in rx_status 814 * @reception_type: su or uplink mu reception type 815 * @transmission_type: su or mu transmission type 816 * @medium_prot_type: medium protection type 817 * @generated_response: Generated frame in response window 818 * @no_bitmap_avail: Bitmap available flag 819 * @explicit_ack: Explicit Acknowledge flag 820 * @explicit_ack_type: Explicit Acknowledge type 821 * @r2r_end_status_follow: Response to Response status flag 822 * @response_type: Response type in response window 823 * @ndp_frame: NDP frame 824 * @num_users: number of users 825 * @sw_frame_group_id: software frame group ID 826 * @r2r_to_follow: Response to Response follow flag 827 * @buffer: Packet buffer pointer address 828 * @offset: Packet buffer offset 829 * @length: Packet buffer length 830 * @protection_addr: Protection Address flag 831 * @addr1: MAC address 1 832 * @addr2: MAC address 2 833 * @addr3: MAC address 3 834 * @addr4: MAC address 4 835 */ 836 struct hal_tx_status_info { 837 uint8_t reception_type; 838 uint8_t transmission_type; 839 uint8_t medium_prot_type; 840 uint8_t generated_response; 841 842 uint32_t no_bitmap_avail :1, 843 explicit_ack :1, 844 explicit_ack_type :4, 845 r2r_end_status_follow :1, 846 response_type :5, 847 ndp_frame :2, 848 num_users :8, 849 reserved :10; 850 851 uint8_t mba_count; 852 uint8_t mba_fake_bitmap_count; 853 854 uint8_t sw_frame_group_id; 855 uint32_t r2r_to_follow; 856 857 uint16_t phy_abort_reason; 858 uint8_t phy_abort_user_number; 859 860 void *buffer; 861 uint32_t offset; 862 uint32_t length; 863 864 uint8_t protection_addr; 865 uint8_t addr1[QDF_MAC_ADDR_SIZE]; 866 uint8_t addr2[QDF_MAC_ADDR_SIZE]; 867 uint8_t addr3[QDF_MAC_ADDR_SIZE]; 868 uint8_t addr4[QDF_MAC_ADDR_SIZE]; 869 }; 870 871 /** 872 * struct hal_tx_ppdu_info - tx monitor ppdu information 873 * @ppdu_id: Id of the PLCP protocol data unit 874 * @num_users: number of users 875 * @is_used: boolean flag to identify valid ppdu info 876 * @is_data: boolean flag to identify data frame 877 * @cur_usr_idx: Current user index of the PPDU 878 * @reserved: for furture purpose 879 * @prot_tlv_status: protection tlv status 880 * @packet_info: packet information 881 * @rx_status: monitor mode rx status information 882 * @rx_user_status: monitor mode rx user status information 883 */ 884 struct hal_tx_ppdu_info { 885 uint32_t ppdu_id; 886 uint32_t num_users :8, 887 is_used :1, 888 is_data :1, 889 cur_usr_idx :8, 890 reserved :15; 891 892 uint32_t prot_tlv_status; 893 894 /* placeholder to hold packet buffer info */ 895 struct hal_mon_packet_info packet_info; 896 struct mon_rx_status rx_status; 897 struct mon_rx_user_status rx_user_status[]; 898 }; 899 900 /** 901 * hal_tx_status_get_next_tlv() - get next tx status TLV 902 * @tx_tlv: pointer to TLV header 903 * 904 * Return: pointer to next tlv info 905 */ 906 static inline uint8_t* 907 hal_tx_status_get_next_tlv(uint8_t *tx_tlv) { 908 uint32_t tlv_len, tlv_tag; 909 910 tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv); 911 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv); 912 913 return (uint8_t *)(((unsigned long)(tx_tlv + tlv_len + 914 HAL_RX_TLV32_HDR_SIZE + 7)) & (~7)); 915 } 916 917 /** 918 * hal_txmon_status_parse_tlv() - process transmit info TLV 919 * @hal_soc: HAL soc handle 920 * @data_ppdu_info: pointer to hal data ppdu info 921 * @prot_ppdu_info: pointer to hal prot ppdu info 922 * @data_status_info: pointer to data status info 923 * @prot_status_info: pointer to prot status info 924 * @tx_tlv_hdr: pointer to TLV header 925 * @status_frag: pointer to status frag 926 * 927 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE 928 */ 929 static inline uint32_t 930 hal_txmon_status_parse_tlv(hal_soc_handle_t hal_soc_hdl, 931 void *data_ppdu_info, 932 void *prot_ppdu_info, 933 void *data_status_info, 934 void *prot_status_info, 935 void *tx_tlv_hdr, 936 qdf_frag_t status_frag) 937 { 938 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 939 940 return hal_soc->ops->hal_txmon_status_parse_tlv(data_ppdu_info, 941 prot_ppdu_info, 942 data_status_info, 943 prot_status_info, 944 tx_tlv_hdr, 945 status_frag); 946 } 947 948 /** 949 * hal_txmon_status_get_num_users() - api to get num users from start of fes 950 * window 951 * @hal_soc: HAL soc handle 952 * @tx_tlv_hdr: pointer to TLV header 953 * @num_users: reference to number of user 954 * 955 * Return: status 956 */ 957 static inline uint32_t 958 hal_txmon_status_get_num_users(hal_soc_handle_t hal_soc_hdl, 959 void *tx_tlv_hdr, uint8_t *num_users) 960 { 961 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 962 963 return hal_soc->ops->hal_txmon_status_get_num_users(tx_tlv_hdr, 964 num_users); 965 } 966 967 /** 968 * hal_tx_status_get_tlv_tag() - api to get tlv tag 969 * @tx_tlv_hdr: pointer to TLV header 970 * 971 * Return tlv_tag 972 */ 973 static inline uint32_t 974 hal_tx_status_get_tlv_tag(void *tx_tlv_hdr) 975 { 976 uint32_t tlv_tag = 0; 977 978 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr); 979 980 return tlv_tag; 981 } 982 #endif 983 984 /** 985 * hal_txmon_is_mon_buf_addr_tlv() - api to find packet buffer addr tlv 986 * @hal_soc: HAL soc handle 987 * @tx_tlv_hdr: pointer to TLV header 988 * 989 * Return: bool 990 */ 991 static inline bool 992 hal_txmon_is_mon_buf_addr_tlv(hal_soc_handle_t hal_soc_hdl, void *tx_tlv_hdr) 993 { 994 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 995 996 if (qdf_unlikely(!hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv)) 997 return false; 998 999 return hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv(tx_tlv_hdr); 1000 } 1001 1002 /** 1003 * hal_txmon_populate_packet_info() - api to populate packet info 1004 * @hal_soc: HAL soc handle 1005 * @tx_tlv_hdr: pointer to TLV header 1006 * @packet_info: pointer to placeholder for packet info 1007 * 1008 * Return void 1009 */ 1010 static inline void 1011 hal_txmon_populate_packet_info(hal_soc_handle_t hal_soc_hdl, 1012 void *tx_tlv_hdr, 1013 void *packet_info) 1014 { 1015 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1016 1017 if (qdf_unlikely(!hal_soc->ops->hal_txmon_populate_packet_info)) 1018 return; 1019 1020 hal_soc->ops->hal_txmon_populate_packet_info(tx_tlv_hdr, packet_info); 1021 } 1022 1023 static inline uint32_t 1024 hal_rx_parse_u_sig_cmn(struct hal_soc *hal_soc, void *rx_tlv, 1025 struct hal_rx_ppdu_info *ppdu_info) 1026 { 1027 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1028 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 1029 uint8_t bad_usig_crc; 1030 1031 bad_usig_crc = HAL_RX_MON_USIG_GET_RX_INTEGRITY_CHECK_PASSED(rx_tlv) ? 1032 0 : 1; 1033 ppdu_info->rx_status.usig_common |= 1034 QDF_MON_STATUS_USIG_PHY_VERSION_KNOWN | 1035 QDF_MON_STATUS_USIG_BW_KNOWN | 1036 QDF_MON_STATUS_USIG_UL_DL_KNOWN | 1037 QDF_MON_STATUS_USIG_BSS_COLOR_KNOWN | 1038 QDF_MON_STATUS_USIG_TXOP_KNOWN; 1039 1040 ppdu_info->rx_status.usig_common |= (usig_1->phy_version << 1041 QDF_MON_STATUS_USIG_PHY_VERSION_SHIFT); 1042 ppdu_info->rx_status.usig_common |= (usig_1->bw << 1043 QDF_MON_STATUS_USIG_BW_SHIFT); 1044 ppdu_info->rx_status.usig_common |= (usig_1->ul_dl << 1045 QDF_MON_STATUS_USIG_UL_DL_SHIFT); 1046 ppdu_info->rx_status.usig_common |= (usig_1->bss_color << 1047 QDF_MON_STATUS_USIG_BSS_COLOR_SHIFT); 1048 ppdu_info->rx_status.usig_common |= (usig_1->txop << 1049 QDF_MON_STATUS_USIG_TXOP_SHIFT); 1050 ppdu_info->rx_status.usig_common |= bad_usig_crc; 1051 1052 ppdu_info->u_sig_info.ul_dl = usig_1->ul_dl; 1053 ppdu_info->u_sig_info.bw = usig_1->bw; 1054 ppdu_info->rx_status.bw = usig_1->bw; 1055 1056 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1057 } 1058 1059 static inline uint32_t 1060 hal_rx_parse_u_sig_tb(struct hal_soc *hal_soc, void *rx_tlv, 1061 struct hal_rx_ppdu_info *ppdu_info) 1062 { 1063 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1064 struct hal_mon_usig_tb *usig_tb = &usig->usig_2.tb; 1065 1066 ppdu_info->rx_status.usig_mask |= 1067 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 1068 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 1069 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 1070 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_KNOWN | 1071 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_KNOWN | 1072 QDF_MON_STATUS_USIG_TB_DISREGARD1_KNOWN | 1073 QDF_MON_STATUS_USIG_CRC_KNOWN | 1074 QDF_MON_STATUS_USIG_TAIL_KNOWN; 1075 1076 ppdu_info->rx_status.usig_value |= (0x3F << 1077 QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 1078 ppdu_info->rx_status.usig_value |= (usig_tb->ppdu_type_comp_mode << 1079 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 1080 ppdu_info->rx_status.usig_value |= (0x1 << 1081 QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 1082 ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_1 << 1083 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_SHIFT); 1084 ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_2 << 1085 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_SHIFT); 1086 ppdu_info->rx_status.usig_value |= (0x1F << 1087 QDF_MON_STATUS_USIG_TB_DISREGARD1_SHIFT); 1088 ppdu_info->rx_status.usig_value |= (usig_tb->crc << 1089 QDF_MON_STATUS_USIG_CRC_SHIFT); 1090 ppdu_info->rx_status.usig_value |= (usig_tb->tail << 1091 QDF_MON_STATUS_USIG_TAIL_SHIFT); 1092 1093 ppdu_info->u_sig_info.ppdu_type_comp_mode = 1094 usig_tb->ppdu_type_comp_mode; 1095 1096 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1097 } 1098 1099 static inline uint32_t 1100 hal_rx_parse_u_sig_mu(struct hal_soc *hal_soc, void *rx_tlv, 1101 struct hal_rx_ppdu_info *ppdu_info) 1102 { 1103 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1104 struct hal_mon_usig_mu *usig_mu = &usig->usig_2.mu; 1105 1106 ppdu_info->rx_status.usig_mask |= 1107 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 1108 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 1109 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 1110 QDF_MON_STATUS_USIG_MU_VALIDATE1_KNOWN | 1111 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_KNOWN | 1112 QDF_MON_STATUS_USIG_MU_VALIDATE2_KNOWN | 1113 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_KNOWN | 1114 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_KNOWN | 1115 QDF_MON_STATUS_USIG_CRC_KNOWN | 1116 QDF_MON_STATUS_USIG_TAIL_KNOWN; 1117 1118 ppdu_info->rx_status.usig_value |= (0x1F << 1119 QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 1120 ppdu_info->rx_status.usig_value |= (0x1 << 1121 QDF_MON_STATUS_USIG_MU_VALIDATE1_SHIFT); 1122 ppdu_info->rx_status.usig_value |= (usig_mu->ppdu_type_comp_mode << 1123 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 1124 ppdu_info->rx_status.usig_value |= (0x1 << 1125 QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 1126 ppdu_info->rx_status.usig_value |= (usig_mu->punc_ch_info << 1127 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_SHIFT); 1128 ppdu_info->rx_status.usig_value |= (0x1 << 1129 QDF_MON_STATUS_USIG_MU_VALIDATE2_SHIFT); 1130 ppdu_info->rx_status.usig_value |= (usig_mu->eht_sig_mcs << 1131 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_SHIFT); 1132 ppdu_info->rx_status.usig_value |= (usig_mu->num_eht_sig_sym << 1133 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_SHIFT); 1134 ppdu_info->rx_status.usig_value |= (usig_mu->crc << 1135 QDF_MON_STATUS_USIG_CRC_SHIFT); 1136 ppdu_info->rx_status.usig_value |= (usig_mu->tail << 1137 QDF_MON_STATUS_USIG_TAIL_SHIFT); 1138 1139 ppdu_info->u_sig_info.ppdu_type_comp_mode = 1140 usig_mu->ppdu_type_comp_mode; 1141 ppdu_info->u_sig_info.eht_sig_mcs = usig_mu->eht_sig_mcs; 1142 ppdu_info->u_sig_info.num_eht_sig_sym = usig_mu->num_eht_sig_sym; 1143 1144 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1145 } 1146 1147 static inline uint32_t 1148 hal_rx_parse_u_sig_hdr(struct hal_soc *hal_soc, void *rx_tlv, 1149 struct hal_rx_ppdu_info *ppdu_info) 1150 { 1151 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1152 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 1153 1154 ppdu_info->rx_status.usig_flags = 1; 1155 1156 hal_rx_parse_u_sig_cmn(hal_soc, rx_tlv, ppdu_info); 1157 1158 if (HAL_RX_MON_USIG_GET_PPDU_TYPE_N_COMP_MODE(rx_tlv) == 0 && 1159 usig_1->ul_dl == 1) 1160 return hal_rx_parse_u_sig_tb(hal_soc, rx_tlv, ppdu_info); 1161 else 1162 return hal_rx_parse_u_sig_mu(hal_soc, rx_tlv, ppdu_info); 1163 } 1164 1165 static inline uint32_t 1166 hal_rx_parse_usig_overflow(struct hal_soc *hal_soc, void *tlv, 1167 struct hal_rx_ppdu_info *ppdu_info) 1168 { 1169 struct hal_eht_sig_cc_usig_overflow *usig_ovflow = 1170 (struct hal_eht_sig_cc_usig_overflow *)tlv; 1171 1172 ppdu_info->rx_status.eht_known |= 1173 QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1174 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1175 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_KNOWN | 1176 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_KNOWN | 1177 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_KNOWN | 1178 QDF_MON_STATUS_EHT_DISREARD_KNOWN; 1179 1180 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->spatial_reuse << 1181 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1182 /* 1183 * GI and LTF size are separately indicated in radiotap header 1184 * and hence will be parsed from other TLV 1185 **/ 1186 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->num_ltf_sym << 1187 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1188 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->ldpc_extra_sym << 1189 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_SHIFT); 1190 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pre_fec_pad_factor << 1191 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_SHIFT); 1192 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pe_disambiguity << 1193 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_SHIFT); 1194 ppdu_info->rx_status.eht_data[0] |= (0xF << 1195 QDF_MON_STATUS_EHT_DISREGARD_SHIFT); 1196 1197 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1198 } 1199 1200 static inline uint32_t 1201 hal_rx_parse_non_ofdma_users(struct hal_soc *hal_soc, void *tlv, 1202 struct hal_rx_ppdu_info *ppdu_info) 1203 { 1204 struct hal_eht_sig_non_ofdma_cmn_eb *non_ofdma_cmn_eb = 1205 (struct hal_eht_sig_non_ofdma_cmn_eb *)tlv; 1206 1207 ppdu_info->rx_status.eht_known |= 1208 QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_KNOWN; 1209 1210 ppdu_info->rx_status.eht_data[4] |= (non_ofdma_cmn_eb->num_users << 1211 QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_SHIFT); 1212 1213 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1214 } 1215 1216 static inline uint32_t 1217 hal_rx_parse_ru_allocation(struct hal_soc *hal_soc, void *tlv, 1218 struct hal_rx_ppdu_info *ppdu_info) 1219 { 1220 uint64_t *ehtsig_tlv = (uint64_t *)tlv; 1221 struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cmn_eb1; 1222 struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cmn_eb2; 1223 uint8_t num_ru_allocation_known = 0; 1224 1225 ofdma_cmn_eb1 = (struct hal_eht_sig_ofdma_cmn_eb1 *)ehtsig_tlv; 1226 ofdma_cmn_eb2 = (struct hal_eht_sig_ofdma_cmn_eb2 *)(ehtsig_tlv + 1); 1227 1228 switch (ppdu_info->u_sig_info.bw) { 1229 case HAL_EHT_BW_320_2: 1230 case HAL_EHT_BW_320_1: 1231 num_ru_allocation_known += 4; 1232 1233 ppdu_info->rx_status.eht_data[3] |= 1234 (ofdma_cmn_eb2->ru_allocation2_6 << 1235 QDF_MON_STATUS_EHT_RU_ALLOCATION2_6_SHIFT); 1236 ppdu_info->rx_status.eht_data[3] |= 1237 (ofdma_cmn_eb2->ru_allocation2_5 << 1238 QDF_MON_STATUS_EHT_RU_ALLOCATION2_5_SHIFT); 1239 ppdu_info->rx_status.eht_data[3] |= 1240 (ofdma_cmn_eb2->ru_allocation2_4 << 1241 QDF_MON_STATUS_EHT_RU_ALLOCATION2_4_SHIFT); 1242 ppdu_info->rx_status.eht_data[2] |= 1243 (ofdma_cmn_eb2->ru_allocation2_3 << 1244 QDF_MON_STATUS_EHT_RU_ALLOCATION2_3_SHIFT); 1245 fallthrough; 1246 case HAL_EHT_BW_160: 1247 num_ru_allocation_known += 2; 1248 1249 ppdu_info->rx_status.eht_data[2] |= 1250 (ofdma_cmn_eb2->ru_allocation2_2 << 1251 QDF_MON_STATUS_EHT_RU_ALLOCATION2_2_SHIFT); 1252 ppdu_info->rx_status.eht_data[2] |= 1253 (ofdma_cmn_eb2->ru_allocation2_1 << 1254 QDF_MON_STATUS_EHT_RU_ALLOCATION2_1_SHIFT); 1255 fallthrough; 1256 case HAL_EHT_BW_80: 1257 num_ru_allocation_known += 1; 1258 1259 ppdu_info->rx_status.eht_data[1] |= 1260 (ofdma_cmn_eb1->ru_allocation1_2 << 1261 QDF_MON_STATUS_EHT_RU_ALLOCATION1_2_SHIFT); 1262 fallthrough; 1263 case HAL_EHT_BW_40: 1264 case HAL_EHT_BW_20: 1265 num_ru_allocation_known += 1; 1266 1267 ppdu_info->rx_status.eht_data[1] |= 1268 (ofdma_cmn_eb1->ru_allocation1_1 << 1269 QDF_MON_STATUS_EHT_RU_ALLOCATION1_1_SHIFT); 1270 break; 1271 default: 1272 break; 1273 } 1274 1275 ppdu_info->rx_status.eht_known |= (num_ru_allocation_known << 1276 QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT); 1277 1278 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1279 } 1280 1281 static inline uint32_t 1282 hal_rx_parse_eht_sig_mumimo_user_info(struct hal_soc *hal_soc, void *tlv, 1283 struct hal_rx_ppdu_info *ppdu_info) 1284 { 1285 struct hal_eht_sig_mu_mimo_user_info *user_info; 1286 uint32_t user_idx = ppdu_info->rx_status.num_eht_user_info_valid; 1287 1288 user_info = (struct hal_eht_sig_mu_mimo_user_info *)tlv; 1289 1290 ppdu_info->rx_status.eht_user_info[user_idx] |= 1291 QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1292 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1293 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1294 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_KNOWN; 1295 1296 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->sta_id << 1297 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1298 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->mcs << 1299 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1300 ppdu_info->rx_status.mcs = user_info->mcs; 1301 1302 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->coding << 1303 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1304 ppdu_info->rx_status.eht_user_info[user_idx] |= 1305 (user_info->spatial_coding << 1306 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_SHIFT); 1307 1308 /* CRC for matched user block */ 1309 ppdu_info->rx_status.eht_known |= 1310 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN | 1311 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN; 1312 ppdu_info->rx_status.eht_data[4] |= (user_info->crc << 1313 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT); 1314 1315 ppdu_info->rx_status.num_eht_user_info_valid++; 1316 1317 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1318 } 1319 1320 static inline uint32_t 1321 hal_rx_parse_eht_sig_non_mumimo_user_info(struct hal_soc *hal_soc, void *tlv, 1322 struct hal_rx_ppdu_info *ppdu_info) 1323 { 1324 struct hal_eht_sig_non_mu_mimo_user_info *user_info; 1325 uint32_t user_idx = ppdu_info->rx_status.num_eht_user_info_valid; 1326 1327 user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tlv; 1328 1329 ppdu_info->rx_status.eht_user_info[user_idx] |= 1330 QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1331 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1332 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1333 QDF_MON_STATUS_EHT_USER_NSS_KNOWN | 1334 QDF_MON_STATUS_EHT_USER_BEAMFORMING_KNOWN; 1335 1336 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->sta_id << 1337 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1338 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->mcs << 1339 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1340 ppdu_info->rx_status.mcs = user_info->mcs; 1341 1342 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->nss << 1343 QDF_MON_STATUS_EHT_USER_NSS_SHIFT); 1344 ppdu_info->rx_status.nss = user_info->nss + 1; 1345 1346 ppdu_info->rx_status.eht_user_info[user_idx] |= 1347 (user_info->beamformed << 1348 QDF_MON_STATUS_EHT_USER_BEAMFORMING_SHIFT); 1349 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->coding << 1350 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1351 1352 /* CRC for matched user block */ 1353 ppdu_info->rx_status.eht_known |= 1354 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN | 1355 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN; 1356 ppdu_info->rx_status.eht_data[4] |= (user_info->crc << 1357 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT); 1358 1359 ppdu_info->rx_status.num_eht_user_info_valid++; 1360 1361 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1362 } 1363 1364 static inline bool hal_rx_is_ofdma(struct hal_soc *hal_soc, 1365 struct hal_rx_ppdu_info *ppdu_info) 1366 { 1367 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 0 && 1368 ppdu_info->u_sig_info.ul_dl == 0) 1369 return true; 1370 1371 return false; 1372 } 1373 1374 static inline bool hal_rx_is_non_ofdma(struct hal_soc *hal_soc, 1375 struct hal_rx_ppdu_info *ppdu_info) 1376 { 1377 uint32_t ppdu_type_comp_mode = 1378 ppdu_info->u_sig_info.ppdu_type_comp_mode; 1379 uint32_t ul_dl = ppdu_info->u_sig_info.ul_dl; 1380 1381 if ((ppdu_type_comp_mode == 1 && ul_dl == 0) || 1382 (ppdu_type_comp_mode == 2 && ul_dl == 0) || 1383 (ppdu_type_comp_mode == 1 && ul_dl == 1)) 1384 return true; 1385 1386 return false; 1387 } 1388 1389 static inline bool hal_rx_is_mu_mimo_user(struct hal_soc *hal_soc, 1390 struct hal_rx_ppdu_info *ppdu_info) 1391 { 1392 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 0 && 1393 ppdu_info->u_sig_info.ul_dl == 2) 1394 return true; 1395 1396 return false; 1397 } 1398 1399 static inline bool 1400 hal_rx_is_frame_type_ndp(struct hal_soc *hal_soc, 1401 struct hal_rx_ppdu_info *ppdu_info) 1402 { 1403 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 1 && 1404 ppdu_info->u_sig_info.eht_sig_mcs == 0 && 1405 ppdu_info->u_sig_info.num_eht_sig_sym == 0) 1406 return true; 1407 1408 return false; 1409 } 1410 1411 static inline uint32_t 1412 hal_rx_parse_eht_sig_ndp(struct hal_soc *hal_soc, void *tlv, 1413 struct hal_rx_ppdu_info *ppdu_info) 1414 { 1415 struct hal_eht_sig_ndp_cmn_eb *eht_sig_ndp = 1416 (struct hal_eht_sig_ndp_cmn_eb *)tlv; 1417 1418 ppdu_info->rx_status.eht_known |= 1419 QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1420 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1421 QDF_MON_STATUS_EHT_NDP_NSS_KNOWN | 1422 QDF_MON_STATUS_EHT_NDP_BEAMFORMED_KNOWN | 1423 QDF_MON_STATUS_EHT_NDP_DISREGARD_KNOWN | 1424 QDF_MON_STATUS_EHT_CRC1_KNOWN | 1425 QDF_MON_STATUS_EHT_TAIL1_KNOWN; 1426 1427 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->spatial_reuse << 1428 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1429 /* 1430 * GI and LTF size are separately indicated in radiotap header 1431 * and hence will be parsed from other TLV 1432 **/ 1433 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->num_ltf_sym << 1434 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1435 ppdu_info->rx_status.eht_data[0] |= (0xF << 1436 QDF_MON_STATUS_EHT_NDP_DISREGARD_SHIFT); 1437 1438 ppdu_info->rx_status.eht_data[4] |= (eht_sig_ndp->nss << 1439 QDF_MON_STATUS_EHT_NDP_NSS_SHIFT); 1440 ppdu_info->rx_status.eht_data[4] |= (eht_sig_ndp->beamformed << 1441 QDF_MON_STATUS_EHT_NDP_BEAMFORMED_SHIFT); 1442 1443 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->crc << 1444 QDF_MON_STATUS_EHT_CRC1_SHIFT); 1445 1446 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1447 } 1448 1449 static inline uint32_t 1450 hal_rx_parse_eht_sig_non_ofdma(struct hal_soc *hal_soc, void *tlv, 1451 struct hal_rx_ppdu_info *ppdu_info) 1452 { 1453 void *user_info = (void *)((uint8_t *)tlv + 4); 1454 1455 hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info); 1456 hal_rx_parse_non_ofdma_users(hal_soc, tlv, ppdu_info); 1457 1458 if (hal_rx_is_mu_mimo_user(hal_soc, ppdu_info)) 1459 hal_rx_parse_eht_sig_mumimo_user_info(hal_soc, user_info, 1460 ppdu_info); 1461 else 1462 hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, user_info, 1463 ppdu_info); 1464 1465 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1466 } 1467 1468 static inline uint32_t 1469 hal_rx_parse_eht_sig_ofdma(struct hal_soc *hal_soc, void *tlv, 1470 struct hal_rx_ppdu_info *ppdu_info) 1471 { 1472 uint64_t *eht_sig_tlv = (uint64_t *)tlv; 1473 void *user_info = (void *)(eht_sig_tlv + 2); 1474 1475 hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info); 1476 hal_rx_parse_ru_allocation(hal_soc, tlv, ppdu_info); 1477 hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, user_info, 1478 ppdu_info); 1479 1480 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1481 } 1482 1483 static inline uint32_t 1484 hal_rx_parse_eht_sig_hdr(struct hal_soc *hal_soc, uint8_t *tlv, 1485 struct hal_rx_ppdu_info *ppdu_info) 1486 { 1487 ppdu_info->rx_status.eht_flags = 1; 1488 1489 if (hal_rx_is_frame_type_ndp(hal_soc, ppdu_info)) 1490 hal_rx_parse_eht_sig_ndp(hal_soc, tlv, ppdu_info); 1491 else if (hal_rx_is_non_ofdma(hal_soc, ppdu_info)) 1492 hal_rx_parse_eht_sig_non_ofdma(hal_soc, tlv, ppdu_info); 1493 else if (hal_rx_is_ofdma(hal_soc, ppdu_info)) 1494 hal_rx_parse_eht_sig_ofdma(hal_soc, tlv, ppdu_info); 1495 1496 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1497 } 1498 1499 #ifdef WLAN_FEATURE_11BE 1500 static inline void 1501 hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info, 1502 struct hal_rx_ppdu_info *ppdu_info) 1503 { 1504 ppdu_info->rx_status.punctured_pattern = cmn_usr_info->puncture_bitmap; 1505 } 1506 #else 1507 static inline void 1508 hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info, 1509 struct hal_rx_ppdu_info *ppdu_info) 1510 { 1511 } 1512 #endif 1513 static inline uint32_t 1514 hal_rx_parse_cmn_usr_info(struct hal_soc *hal_soc, uint8_t *tlv, 1515 struct hal_rx_ppdu_info *ppdu_info) 1516 { 1517 struct phyrx_common_user_info *cmn_usr_info = 1518 (struct phyrx_common_user_info *)tlv; 1519 1520 ppdu_info->rx_status.eht_known |= 1521 QDF_MON_STATUS_EHT_GUARD_INTERVAL_KNOWN | 1522 QDF_MON_STATUS_EHT_LTF_KNOWN; 1523 1524 ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->cp_setting << 1525 QDF_MON_STATUS_EHT_GI_SHIFT); 1526 if (!ppdu_info->rx_status.sgi) 1527 ppdu_info->rx_status.sgi = cmn_usr_info->cp_setting; 1528 1529 ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->ltf_size << 1530 QDF_MON_STATUS_EHT_LTF_SHIFT); 1531 if (!ppdu_info->rx_status.ltf_size) 1532 ppdu_info->rx_status.ltf_size = cmn_usr_info->ltf_size; 1533 1534 hal_rx_parse_punctured_pattern(cmn_usr_info, ppdu_info); 1535 1536 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1537 } 1538 1539 #ifdef WLAN_FEATURE_11BE 1540 static inline void 1541 hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size, 1542 uint32_t *ru_width) 1543 { 1544 uint32_t width; 1545 1546 width = 0; 1547 switch (ru_size) { 1548 case IEEE80211_EHT_RU_26: 1549 width = RU_26; 1550 break; 1551 case IEEE80211_EHT_RU_52: 1552 width = RU_52; 1553 break; 1554 case IEEE80211_EHT_RU_52_26: 1555 width = RU_52_26; 1556 break; 1557 case IEEE80211_EHT_RU_106: 1558 width = RU_106; 1559 break; 1560 case IEEE80211_EHT_RU_106_26: 1561 width = RU_106_26; 1562 break; 1563 case IEEE80211_EHT_RU_242: 1564 width = RU_242; 1565 break; 1566 case IEEE80211_EHT_RU_484: 1567 width = RU_484; 1568 break; 1569 case IEEE80211_EHT_RU_484_242: 1570 width = RU_484_242; 1571 break; 1572 case IEEE80211_EHT_RU_996: 1573 width = RU_996; 1574 break; 1575 case IEEE80211_EHT_RU_996_484: 1576 width = RU_996_484; 1577 break; 1578 case IEEE80211_EHT_RU_996_484_242: 1579 width = RU_996_484_242; 1580 break; 1581 case IEEE80211_EHT_RU_996x2: 1582 width = RU_2X996; 1583 break; 1584 case IEEE80211_EHT_RU_996x2_484: 1585 width = RU_2X996_484; 1586 break; 1587 case IEEE80211_EHT_RU_996x3: 1588 width = RU_3X996; 1589 break; 1590 case IEEE80211_EHT_RU_996x3_484: 1591 width = RU_3X996_484; 1592 break; 1593 case IEEE80211_EHT_RU_996x4: 1594 width = RU_4X996; 1595 break; 1596 default: 1597 hal_err_rl("RU size(%d) to width convert err", ru_size); 1598 break; 1599 } 1600 *ru_width = width; 1601 } 1602 #else 1603 static inline void 1604 hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size, 1605 uint32_t *ru_width) 1606 { 1607 *ru_width = 0; 1608 } 1609 #endif 1610 1611 static inline enum ieee80211_eht_ru_size 1612 hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(struct hal_soc *hal_soc, 1613 uint32_t hal_ru_size) 1614 { 1615 switch (hal_ru_size) { 1616 case HAL_EHT_RU_26: 1617 return IEEE80211_EHT_RU_26; 1618 case HAL_EHT_RU_52: 1619 return IEEE80211_EHT_RU_52; 1620 case HAL_EHT_RU_78: 1621 return IEEE80211_EHT_RU_52_26; 1622 case HAL_EHT_RU_106: 1623 return IEEE80211_EHT_RU_106; 1624 case HAL_EHT_RU_132: 1625 return IEEE80211_EHT_RU_106_26; 1626 case HAL_EHT_RU_242: 1627 return IEEE80211_EHT_RU_242; 1628 case HAL_EHT_RU_484: 1629 return IEEE80211_EHT_RU_484; 1630 case HAL_EHT_RU_726: 1631 return IEEE80211_EHT_RU_484_242; 1632 case HAL_EHT_RU_996: 1633 return IEEE80211_EHT_RU_996; 1634 case HAL_EHT_RU_996x2: 1635 return IEEE80211_EHT_RU_996x2; 1636 case HAL_EHT_RU_996x3: 1637 return IEEE80211_EHT_RU_996x3; 1638 case HAL_EHT_RU_996x4: 1639 return IEEE80211_EHT_RU_996x4; 1640 case HAL_EHT_RU_NONE: 1641 return IEEE80211_EHT_RU_INVALID; 1642 case HAL_EHT_RU_996_484: 1643 return IEEE80211_EHT_RU_996_484; 1644 case HAL_EHT_RU_996x2_484: 1645 return IEEE80211_EHT_RU_996x2_484; 1646 case HAL_EHT_RU_996x3_484: 1647 return IEEE80211_EHT_RU_996x3_484; 1648 case HAL_EHT_RU_996_484_242: 1649 return IEEE80211_EHT_RU_996_484_242; 1650 default: 1651 return IEEE80211_EHT_RU_INVALID; 1652 } 1653 } 1654 1655 #define HAL_SET_RU_PER80(ru_320mhz, ru_per80, ru_idx_per80mhz, num_80mhz) \ 1656 ((ru_320mhz) |= ((uint64_t)(ru_per80) << \ 1657 (((num_80mhz) * NUM_RU_BITS_PER80) + \ 1658 ((ru_idx_per80mhz) * NUM_RU_BITS_PER20)))) 1659 1660 static inline uint32_t 1661 hal_rx_parse_receive_user_info(struct hal_soc *hal_soc, uint8_t *tlv, 1662 struct hal_rx_ppdu_info *ppdu_info, 1663 uint32_t user_id) 1664 { 1665 struct receive_user_info *rx_usr_info = (struct receive_user_info *)tlv; 1666 struct mon_rx_user_status *mon_rx_user_status = NULL; 1667 uint64_t ru_index_320mhz = 0; 1668 uint16_t ru_index_per80mhz; 1669 uint32_t ru_size = 0, num_80mhz_with_ru = 0; 1670 uint32_t ru_index = HAL_EHT_RU_INVALID; 1671 uint32_t rtap_ru_size = IEEE80211_EHT_RU_INVALID; 1672 uint32_t ru_width; 1673 1674 ppdu_info->rx_status.eht_known |= 1675 QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_KNOWN; 1676 ppdu_info->rx_status.eht_data[0] |= 1677 (rx_usr_info->dl_ofdma_content_channel << 1678 QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_SHIFT); 1679 1680 switch (rx_usr_info->reception_type) { 1681 case HAL_RECEPTION_TYPE_SU: 1682 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1683 break; 1684 case HAL_RECEPTION_TYPE_DL_MU_MIMO: 1685 case HAL_RECEPTION_TYPE_UL_MU_MIMO: 1686 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1687 break; 1688 case HAL_RECEPTION_TYPE_DL_MU_OFMA: 1689 case HAL_RECEPTION_TYPE_UL_MU_OFDMA: 1690 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1691 break; 1692 case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO: 1693 case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO: 1694 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA_MIMO; 1695 } 1696 1697 ppdu_info->rx_status.is_stbc = rx_usr_info->stbc; 1698 ppdu_info->rx_status.ldpc = rx_usr_info->ldpc; 1699 ppdu_info->rx_status.dcm = rx_usr_info->sta_dcm; 1700 ppdu_info->rx_status.mcs = rx_usr_info->rate_mcs; 1701 ppdu_info->rx_status.nss = rx_usr_info->nss + 1; 1702 1703 if (user_id < HAL_MAX_UL_MU_USERS) { 1704 mon_rx_user_status = 1705 &ppdu_info->rx_user_status[user_id]; 1706 mon_rx_user_status->mcs = ppdu_info->rx_status.mcs; 1707 mon_rx_user_status->nss = ppdu_info->rx_status.nss; 1708 } 1709 1710 if (!(ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_MIMO || 1711 ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA || 1712 ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA_MIMO)) 1713 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1714 1715 /* RU allocation present only for OFDMA reception */ 1716 if (rx_usr_info->ru_type_80_0 != HAL_EHT_RU_NONE) { 1717 ru_size += rx_usr_info->ru_type_80_0; 1718 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_0; 1719 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_0, 1720 ru_index_per80mhz, 0); 1721 num_80mhz_with_ru++; 1722 } 1723 1724 if (rx_usr_info->ru_type_80_1 != HAL_EHT_RU_NONE) { 1725 ru_size += rx_usr_info->ru_type_80_1; 1726 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_1; 1727 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_1, 1728 ru_index_per80mhz, 1); 1729 num_80mhz_with_ru++; 1730 } 1731 1732 if (rx_usr_info->ru_type_80_2 != HAL_EHT_RU_NONE) { 1733 ru_size += rx_usr_info->ru_type_80_2; 1734 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_2; 1735 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_2, 1736 ru_index_per80mhz, 2); 1737 num_80mhz_with_ru++; 1738 } 1739 1740 if (rx_usr_info->ru_type_80_3 != HAL_EHT_RU_NONE) { 1741 ru_size += rx_usr_info->ru_type_80_3; 1742 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_3; 1743 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_3, 1744 ru_index_per80mhz, 3); 1745 num_80mhz_with_ru++; 1746 } 1747 1748 if (num_80mhz_with_ru > 1) { 1749 /* Calculate the MRU index */ 1750 switch (ru_index_320mhz) { 1751 case HAL_EHT_RU_996_484_0: 1752 case HAL_EHT_RU_996x2_484_0: 1753 case HAL_EHT_RU_996x3_484_0: 1754 ru_index = 0; 1755 break; 1756 case HAL_EHT_RU_996_484_1: 1757 case HAL_EHT_RU_996x2_484_1: 1758 case HAL_EHT_RU_996x3_484_1: 1759 ru_index = 1; 1760 break; 1761 case HAL_EHT_RU_996_484_2: 1762 case HAL_EHT_RU_996x2_484_2: 1763 case HAL_EHT_RU_996x3_484_2: 1764 ru_index = 2; 1765 break; 1766 case HAL_EHT_RU_996_484_3: 1767 case HAL_EHT_RU_996x2_484_3: 1768 case HAL_EHT_RU_996x3_484_3: 1769 ru_index = 3; 1770 break; 1771 case HAL_EHT_RU_996_484_4: 1772 case HAL_EHT_RU_996x2_484_4: 1773 case HAL_EHT_RU_996x3_484_4: 1774 ru_index = 4; 1775 break; 1776 case HAL_EHT_RU_996_484_5: 1777 case HAL_EHT_RU_996x2_484_5: 1778 case HAL_EHT_RU_996x3_484_5: 1779 ru_index = 5; 1780 break; 1781 case HAL_EHT_RU_996_484_6: 1782 case HAL_EHT_RU_996x2_484_6: 1783 case HAL_EHT_RU_996x3_484_6: 1784 ru_index = 6; 1785 break; 1786 case HAL_EHT_RU_996_484_7: 1787 case HAL_EHT_RU_996x2_484_7: 1788 case HAL_EHT_RU_996x3_484_7: 1789 ru_index = 7; 1790 break; 1791 case HAL_EHT_RU_996x2_484_8: 1792 ru_index = 8; 1793 break; 1794 case HAL_EHT_RU_996x2_484_9: 1795 ru_index = 9; 1796 break; 1797 case HAL_EHT_RU_996x2_484_10: 1798 ru_index = 10; 1799 break; 1800 case HAL_EHT_RU_996x2_484_11: 1801 ru_index = 11; 1802 break; 1803 default: 1804 ru_index = HAL_EHT_RU_INVALID; 1805 dp_debug("Invalid RU index"); 1806 qdf_assert(0); 1807 break; 1808 } 1809 ru_size += 4; 1810 } 1811 1812 rtap_ru_size = hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(hal_soc, 1813 ru_size); 1814 if (rtap_ru_size != IEEE80211_EHT_RU_INVALID) { 1815 ppdu_info->rx_status.eht_known |= 1816 QDF_MON_STATUS_EHT_RU_MRU_SIZE_KNOWN; 1817 ppdu_info->rx_status.eht_data[1] |= (rtap_ru_size << 1818 QDF_MON_STATUS_EHT_RU_MRU_SIZE_SHIFT); 1819 } 1820 1821 if (ru_index != HAL_EHT_RU_INVALID) { 1822 ppdu_info->rx_status.eht_known |= 1823 QDF_MON_STATUS_EHT_RU_MRU_INDEX_KNOWN; 1824 ppdu_info->rx_status.eht_data[1] |= (ru_index << 1825 QDF_MON_STATUS_EHT_RU_MRU_INDEX_SHIFT); 1826 } 1827 1828 if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID && 1829 rtap_ru_size != IEEE80211_EHT_RU_INVALID) { 1830 mon_rx_user_status->ofdma_ru_start_index = ru_index; 1831 mon_rx_user_status->ofdma_ru_size = rtap_ru_size; 1832 hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size, &ru_width); 1833 mon_rx_user_status->ofdma_ru_width = ru_width; 1834 mon_rx_user_status->mu_ul_info_valid = 1; 1835 } 1836 1837 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1838 } 1839 1840 #ifdef QCA_MONITOR_2_0_SUPPORT 1841 static inline void 1842 hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info, 1843 void *rx_tlv) 1844 { 1845 ppdu_info->rx_status.mpdu_retry_cnt = 1846 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 1847 RETRIED_MPDU_COUNT); 1848 } 1849 1850 static inline void 1851 hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv, 1852 struct hal_rx_ppdu_info *ppdu_info) 1853 { 1854 struct mon_buffer_addr *addr = (struct mon_buffer_addr *)rx_tlv; 1855 1856 ppdu_info->packet_info.sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) | 1857 (addr->buffer_virt_addr_31_0)); 1858 /* HW DMA length is '-1' of actual DMA length*/ 1859 ppdu_info->packet_info.dma_length = addr->dma_length + 1; 1860 ppdu_info->packet_info.msdu_continuation = addr->msdu_continuation; 1861 ppdu_info->packet_info.truncated = addr->truncated; 1862 1863 } 1864 #else 1865 static inline void 1866 hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info, 1867 void *rx_tlv) 1868 { 1869 ppdu_info->rx_status.mpdu_retry_cnt = 0; 1870 } 1871 static inline void 1872 hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv, 1873 struct hal_rx_ppdu_info *ppdu_info) 1874 { 1875 } 1876 #endif 1877 1878 /** 1879 * hal_rx_status_get_tlv_info() - process receive info TLV 1880 * @rx_tlv_hdr: pointer to TLV header 1881 * @ppdu_info: pointer to ppdu_info 1882 * 1883 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 1884 */ 1885 static inline uint32_t 1886 hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo, 1887 hal_soc_handle_t hal_soc_hdl, 1888 qdf_nbuf_t nbuf) 1889 { 1890 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1891 uint32_t tlv_tag, user_id, tlv_len, value; 1892 uint8_t group_id = 0; 1893 uint8_t he_dcm = 0; 1894 uint8_t he_stbc = 0; 1895 uint16_t he_gi = 0; 1896 uint16_t he_ltf = 0; 1897 void *rx_tlv; 1898 struct mon_rx_user_status *mon_rx_user_status; 1899 struct hal_rx_ppdu_info *ppdu_info = 1900 (struct hal_rx_ppdu_info *)ppduinfo; 1901 1902 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 1903 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 1904 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 1905 1906 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 1907 1908 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1909 rx_tlv, tlv_len); 1910 1911 ppdu_info->user_id = user_id; 1912 switch (tlv_tag) { 1913 case WIFIRX_PPDU_START_E: 1914 { 1915 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 1916 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, PHY_PPDU_ID))) 1917 hal_err("Matching ppdu_id(%u) detected", 1918 ppdu_info->com_info.last_ppdu_id); 1919 1920 /* Reset ppdu_info before processing the ppdu */ 1921 qdf_mem_zero(ppdu_info, 1922 sizeof(struct hal_rx_ppdu_info)); 1923 1924 ppdu_info->com_info.last_ppdu_id = 1925 ppdu_info->com_info.ppdu_id = 1926 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 1927 PHY_PPDU_ID); 1928 1929 /* channel number is set in PHY meta data */ 1930 ppdu_info->rx_status.chan_num = 1931 (HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 1932 SW_PHY_META_DATA) & 0x0000FFFF); 1933 ppdu_info->rx_status.chan_freq = 1934 (HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 1935 SW_PHY_META_DATA) & 0xFFFF0000) >> 16; 1936 if (ppdu_info->rx_status.chan_num && 1937 ppdu_info->rx_status.chan_freq) { 1938 ppdu_info->rx_status.chan_freq = 1939 hal_rx_radiotap_num_to_freq( 1940 ppdu_info->rx_status.chan_num, 1941 ppdu_info->rx_status.chan_freq); 1942 } 1943 1944 ppdu_info->com_info.ppdu_timestamp = 1945 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 1946 PPDU_START_TIMESTAMP_31_0); 1947 ppdu_info->rx_status.ppdu_timestamp = 1948 ppdu_info->com_info.ppdu_timestamp; 1949 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 1950 1951 break; 1952 } 1953 1954 case WIFIRX_PPDU_START_USER_INFO_E: 1955 hal_rx_parse_receive_user_info(hal, rx_tlv, ppdu_info, user_id); 1956 break; 1957 1958 case WIFIRX_PPDU_END_E: 1959 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1960 "[%s][%d] ppdu_end_e len=%d", 1961 __func__, __LINE__, tlv_len); 1962 /* This is followed by sub-TLVs of PPDU_END */ 1963 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 1964 break; 1965 1966 case WIFIPHYRX_LOCATION_E: 1967 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 1968 break; 1969 1970 case WIFIRXPCU_PPDU_END_INFO_E: 1971 ppdu_info->rx_status.rx_antenna = 1972 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, RX_ANTENNA); 1973 ppdu_info->rx_status.tsft = 1974 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, 1975 WB_TIMESTAMP_UPPER_32); 1976 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 1977 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, 1978 WB_TIMESTAMP_LOWER_32); 1979 ppdu_info->rx_status.duration = 1980 HAL_RX_GET_64(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 1981 RX_PPDU_DURATION); 1982 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 1983 break; 1984 1985 /* 1986 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 1987 * for MU, based on num users we see this tlv that many times. 1988 */ 1989 case WIFIRX_PPDU_END_USER_STATS_E: 1990 { 1991 unsigned long tid = 0; 1992 uint16_t seq = 0; 1993 1994 ppdu_info->rx_status.ast_index = 1995 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 1996 AST_INDEX); 1997 1998 tid = HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 1999 RECEIVED_QOS_DATA_TID_BITMAP); 2000 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, 2001 sizeof(tid) * 8); 2002 2003 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 2004 ppdu_info->rx_status.tid = HAL_TID_INVALID; 2005 2006 ppdu_info->rx_status.tcp_msdu_count = 2007 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2008 TCP_MSDU_COUNT) + 2009 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2010 TCP_ACK_MSDU_COUNT); 2011 ppdu_info->rx_status.udp_msdu_count = 2012 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2013 UDP_MSDU_COUNT); 2014 ppdu_info->rx_status.other_msdu_count = 2015 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2016 OTHER_MSDU_COUNT); 2017 hal_rx_status_get_mpdu_retry_cnt(ppdu_info, rx_tlv); 2018 2019 if (ppdu_info->sw_frame_group_id 2020 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 2021 ppdu_info->rx_status.frame_control_info_valid = 2022 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2023 FRAME_CONTROL_INFO_VALID); 2024 2025 if (ppdu_info->rx_status.frame_control_info_valid) 2026 ppdu_info->rx_status.frame_control = 2027 HAL_RX_GET_64(rx_tlv, 2028 RX_PPDU_END_USER_STATS, 2029 FRAME_CONTROL_FIELD); 2030 2031 hal_get_qos_control(rx_tlv, ppdu_info); 2032 } 2033 2034 ppdu_info->rx_status.data_sequence_control_info_valid = 2035 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2036 DATA_SEQUENCE_CONTROL_INFO_VALID); 2037 2038 seq = HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2039 FIRST_DATA_SEQ_CTRL); 2040 if (ppdu_info->rx_status.data_sequence_control_info_valid) 2041 ppdu_info->rx_status.first_data_seq_ctrl = seq; 2042 2043 ppdu_info->rx_status.preamble_type = 2044 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2045 HT_CONTROL_FIELD_PKT_TYPE); 2046 switch (ppdu_info->rx_status.preamble_type) { 2047 case HAL_RX_PKT_TYPE_11N: 2048 ppdu_info->rx_status.ht_flags = 1; 2049 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 2050 break; 2051 case HAL_RX_PKT_TYPE_11AC: 2052 ppdu_info->rx_status.vht_flags = 1; 2053 break; 2054 case HAL_RX_PKT_TYPE_11AX: 2055 ppdu_info->rx_status.he_flags = 1; 2056 break; 2057 default: 2058 break; 2059 } 2060 2061 ppdu_info->com_info.mpdu_cnt_fcs_ok = 2062 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2063 MPDU_CNT_FCS_OK); 2064 ppdu_info->com_info.mpdu_cnt_fcs_err = 2065 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2066 MPDU_CNT_FCS_ERR); 2067 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 2068 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 2069 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 2070 else 2071 ppdu_info->rx_status.rs_flags &= 2072 (~IEEE80211_AMPDU_FLAG); 2073 2074 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 2075 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2076 FCS_OK_BITMAP_31_0); 2077 2078 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 2079 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2080 FCS_OK_BITMAP_63_32); 2081 2082 if (user_id < HAL_MAX_UL_MU_USERS) { 2083 mon_rx_user_status = 2084 &ppdu_info->rx_user_status[user_id]; 2085 2086 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 2087 2088 ppdu_info->com_info.num_users++; 2089 2090 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 2091 user_id, 2092 mon_rx_user_status); 2093 } 2094 break; 2095 } 2096 2097 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 2098 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 2099 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2100 FCS_OK_BITMAP_95_64); 2101 2102 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 2103 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2104 FCS_OK_BITMAP_127_96); 2105 2106 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 2107 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2108 FCS_OK_BITMAP_159_128); 2109 2110 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 2111 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2112 FCS_OK_BITMAP_191_160); 2113 2114 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 2115 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2116 FCS_OK_BITMAP_223_192); 2117 2118 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 2119 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2120 FCS_OK_BITMAP_255_224); 2121 break; 2122 2123 case WIFIRX_PPDU_END_STATUS_DONE_E: 2124 return HAL_TLV_STATUS_PPDU_DONE; 2125 2126 case WIFIPHYRX_PKT_END_E: 2127 break; 2128 2129 case WIFIDUMMY_E: 2130 return HAL_TLV_STATUS_BUF_DONE; 2131 2132 case WIFIPHYRX_HT_SIG_E: 2133 { 2134 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 2135 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 2136 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 2137 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO, FEC_CODING); 2138 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2139 1 : 0; 2140 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 2141 HT_SIG_INFO, MCS); 2142 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 2143 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 2144 HT_SIG_INFO, CBW); 2145 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 2146 HT_SIG_INFO, SHORT_GI); 2147 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2148 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 2149 HT_SIG_SU_NSS_SHIFT) + 1; 2150 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 2151 break; 2152 } 2153 2154 case WIFIPHYRX_L_SIG_B_E: 2155 { 2156 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 2157 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 2158 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 2159 2160 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO, RATE); 2161 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 2162 switch (value) { 2163 case 1: 2164 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 2165 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 2166 break; 2167 case 2: 2168 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 2169 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 2170 break; 2171 case 3: 2172 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 2173 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 2174 break; 2175 case 4: 2176 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 2177 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 2178 break; 2179 case 5: 2180 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 2181 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 2182 break; 2183 case 6: 2184 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 2185 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 2186 break; 2187 case 7: 2188 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 2189 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 2190 break; 2191 default: 2192 break; 2193 } 2194 ppdu_info->rx_status.cck_flag = 1; 2195 break; 2196 } 2197 2198 case WIFIPHYRX_L_SIG_A_E: 2199 { 2200 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 2201 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 2202 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 2203 2204 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO, RATE); 2205 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 2206 switch (value) { 2207 case 8: 2208 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 2209 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 2210 break; 2211 case 9: 2212 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 2213 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 2214 break; 2215 case 10: 2216 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 2217 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 2218 break; 2219 case 11: 2220 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 2221 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 2222 break; 2223 case 12: 2224 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 2225 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 2226 break; 2227 case 13: 2228 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 2229 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 2230 break; 2231 case 14: 2232 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 2233 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 2234 break; 2235 case 15: 2236 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 2237 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 2238 break; 2239 default: 2240 break; 2241 } 2242 ppdu_info->rx_status.ofdm_flag = 1; 2243 break; 2244 } 2245 2246 case WIFIPHYRX_VHT_SIG_A_E: 2247 { 2248 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 2249 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 2250 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 2251 2252 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, 2253 SU_MU_CODING); 2254 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2255 1 : 0; 2256 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, GROUP_ID); 2257 ppdu_info->rx_status.vht_flag_values5 = group_id; 2258 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 2259 VHT_SIG_A_INFO, MCS); 2260 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 2261 VHT_SIG_A_INFO, 2262 GI_SETTING); 2263 2264 switch (hal->target_type) { 2265 case TARGET_TYPE_QCA8074: 2266 case TARGET_TYPE_QCA8074V2: 2267 case TARGET_TYPE_QCA6018: 2268 case TARGET_TYPE_QCA5018: 2269 case TARGET_TYPE_QCN9000: 2270 case TARGET_TYPE_QCN6122: 2271 #ifdef QCA_WIFI_QCA6390 2272 case TARGET_TYPE_QCA6390: 2273 #endif 2274 ppdu_info->rx_status.is_stbc = 2275 HAL_RX_GET(vht_sig_a_info, 2276 VHT_SIG_A_INFO, STBC); 2277 value = HAL_RX_GET(vht_sig_a_info, 2278 VHT_SIG_A_INFO, N_STS); 2279 value = value & VHT_SIG_SU_NSS_MASK; 2280 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2281 value = ((value + 1) >> 1) - 1; 2282 ppdu_info->rx_status.nss = 2283 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2284 2285 break; 2286 case TARGET_TYPE_QCA6290: 2287 #if !defined(QCA_WIFI_QCA6290_11AX) 2288 ppdu_info->rx_status.is_stbc = 2289 HAL_RX_GET(vht_sig_a_info, 2290 VHT_SIG_A_INFO, STBC); 2291 value = HAL_RX_GET(vht_sig_a_info, 2292 VHT_SIG_A_INFO, N_STS); 2293 value = value & VHT_SIG_SU_NSS_MASK; 2294 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2295 value = ((value + 1) >> 1) - 1; 2296 ppdu_info->rx_status.nss = 2297 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2298 #else 2299 ppdu_info->rx_status.nss = 0; 2300 #endif 2301 break; 2302 case TARGET_TYPE_QCA6490: 2303 case TARGET_TYPE_QCA6750: 2304 case TARGET_TYPE_KIWI: 2305 case TARGET_TYPE_MANGO: 2306 ppdu_info->rx_status.nss = 0; 2307 break; 2308 default: 2309 break; 2310 } 2311 ppdu_info->rx_status.vht_flag_values3[0] = 2312 (((ppdu_info->rx_status.mcs) << 4) 2313 | ppdu_info->rx_status.nss); 2314 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 2315 VHT_SIG_A_INFO, BANDWIDTH); 2316 ppdu_info->rx_status.vht_flag_values2 = 2317 ppdu_info->rx_status.bw; 2318 ppdu_info->rx_status.vht_flag_values4 = 2319 HAL_RX_GET(vht_sig_a_info, 2320 VHT_SIG_A_INFO, SU_MU_CODING); 2321 2322 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 2323 VHT_SIG_A_INFO, 2324 BEAMFORMED); 2325 if (group_id == 0 || group_id == 63) 2326 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2327 else 2328 ppdu_info->rx_status.reception_type = 2329 HAL_RX_TYPE_MU_MIMO; 2330 2331 break; 2332 } 2333 case WIFIPHYRX_HE_SIG_A_SU_E: 2334 { 2335 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 2336 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 2337 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 2338 ppdu_info->rx_status.he_flags = 1; 2339 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2340 FORMAT_INDICATION); 2341 if (value == 0) { 2342 ppdu_info->rx_status.he_data1 = 2343 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 2344 } else { 2345 ppdu_info->rx_status.he_data1 = 2346 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 2347 } 2348 2349 /* data1 */ 2350 ppdu_info->rx_status.he_data1 |= 2351 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 2352 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 2353 QDF_MON_STATUS_HE_DL_UL_KNOWN | 2354 QDF_MON_STATUS_HE_MCS_KNOWN | 2355 QDF_MON_STATUS_HE_DCM_KNOWN | 2356 QDF_MON_STATUS_HE_CODING_KNOWN | 2357 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 2358 QDF_MON_STATUS_HE_STBC_KNOWN | 2359 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 2360 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 2361 2362 /* data2 */ 2363 ppdu_info->rx_status.he_data2 = 2364 QDF_MON_STATUS_HE_GI_KNOWN; 2365 ppdu_info->rx_status.he_data2 |= 2366 QDF_MON_STATUS_TXBF_KNOWN | 2367 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 2368 QDF_MON_STATUS_TXOP_KNOWN | 2369 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 2370 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 2371 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 2372 2373 /* data3 */ 2374 value = HAL_RX_GET(he_sig_a_su_info, 2375 HE_SIG_A_SU_INFO, BSS_COLOR_ID); 2376 ppdu_info->rx_status.he_data3 = value; 2377 value = HAL_RX_GET(he_sig_a_su_info, 2378 HE_SIG_A_SU_INFO, BEAM_CHANGE); 2379 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 2380 ppdu_info->rx_status.he_data3 |= value; 2381 value = HAL_RX_GET(he_sig_a_su_info, 2382 HE_SIG_A_SU_INFO, DL_UL_FLAG); 2383 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 2384 ppdu_info->rx_status.he_data3 |= value; 2385 2386 value = HAL_RX_GET(he_sig_a_su_info, 2387 HE_SIG_A_SU_INFO, TRANSMIT_MCS); 2388 ppdu_info->rx_status.mcs = value; 2389 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2390 ppdu_info->rx_status.he_data3 |= value; 2391 2392 value = HAL_RX_GET(he_sig_a_su_info, 2393 HE_SIG_A_SU_INFO, DCM); 2394 he_dcm = value; 2395 value = value << QDF_MON_STATUS_DCM_SHIFT; 2396 ppdu_info->rx_status.he_data3 |= value; 2397 value = HAL_RX_GET(he_sig_a_su_info, 2398 HE_SIG_A_SU_INFO, CODING); 2399 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2400 1 : 0; 2401 value = value << QDF_MON_STATUS_CODING_SHIFT; 2402 ppdu_info->rx_status.he_data3 |= value; 2403 value = HAL_RX_GET(he_sig_a_su_info, 2404 HE_SIG_A_SU_INFO, 2405 LDPC_EXTRA_SYMBOL); 2406 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 2407 ppdu_info->rx_status.he_data3 |= value; 2408 value = HAL_RX_GET(he_sig_a_su_info, 2409 HE_SIG_A_SU_INFO, STBC); 2410 he_stbc = value; 2411 value = value << QDF_MON_STATUS_STBC_SHIFT; 2412 ppdu_info->rx_status.he_data3 |= value; 2413 2414 /* data4 */ 2415 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2416 SPATIAL_REUSE); 2417 ppdu_info->rx_status.he_data4 = value; 2418 2419 /* data5 */ 2420 value = HAL_RX_GET(he_sig_a_su_info, 2421 HE_SIG_A_SU_INFO, TRANSMIT_BW); 2422 ppdu_info->rx_status.he_data5 = value; 2423 ppdu_info->rx_status.bw = value; 2424 value = HAL_RX_GET(he_sig_a_su_info, 2425 HE_SIG_A_SU_INFO, CP_LTF_SIZE); 2426 switch (value) { 2427 case 0: 2428 he_gi = HE_GI_0_8; 2429 he_ltf = HE_LTF_1_X; 2430 break; 2431 case 1: 2432 he_gi = HE_GI_0_8; 2433 he_ltf = HE_LTF_2_X; 2434 break; 2435 case 2: 2436 he_gi = HE_GI_1_6; 2437 he_ltf = HE_LTF_2_X; 2438 break; 2439 case 3: 2440 if (he_dcm && he_stbc) { 2441 he_gi = HE_GI_0_8; 2442 he_ltf = HE_LTF_4_X; 2443 } else { 2444 he_gi = HE_GI_3_2; 2445 he_ltf = HE_LTF_4_X; 2446 } 2447 break; 2448 } 2449 ppdu_info->rx_status.sgi = he_gi; 2450 ppdu_info->rx_status.ltf_size = he_ltf; 2451 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 2452 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 2453 ppdu_info->rx_status.he_data5 |= value; 2454 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 2455 ppdu_info->rx_status.he_data5 |= value; 2456 2457 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 2458 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 2459 ppdu_info->rx_status.he_data5 |= value; 2460 2461 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2462 PACKET_EXTENSION_A_FACTOR); 2463 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 2464 ppdu_info->rx_status.he_data5 |= value; 2465 2466 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, TXBF); 2467 value = value << QDF_MON_STATUS_TXBF_SHIFT; 2468 ppdu_info->rx_status.he_data5 |= value; 2469 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2470 PACKET_EXTENSION_PE_DISAMBIGUITY); 2471 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 2472 ppdu_info->rx_status.he_data5 |= value; 2473 2474 /* data6 */ 2475 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 2476 value++; 2477 ppdu_info->rx_status.nss = value; 2478 ppdu_info->rx_status.he_data6 = value; 2479 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2480 DOPPLER_INDICATION); 2481 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 2482 ppdu_info->rx_status.he_data6 |= value; 2483 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2484 TXOP_DURATION); 2485 value = value << QDF_MON_STATUS_TXOP_SHIFT; 2486 ppdu_info->rx_status.he_data6 |= value; 2487 2488 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 2489 HE_SIG_A_SU_INFO, 2490 TXBF); 2491 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2492 break; 2493 } 2494 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 2495 { 2496 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 2497 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 2498 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 2499 2500 ppdu_info->rx_status.he_mu_flags = 1; 2501 2502 /* HE Flags */ 2503 /*data1*/ 2504 ppdu_info->rx_status.he_data1 = 2505 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 2506 ppdu_info->rx_status.he_data1 |= 2507 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 2508 QDF_MON_STATUS_HE_DL_UL_KNOWN | 2509 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 2510 QDF_MON_STATUS_HE_STBC_KNOWN | 2511 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 2512 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 2513 2514 /* data2 */ 2515 ppdu_info->rx_status.he_data2 = 2516 QDF_MON_STATUS_HE_GI_KNOWN; 2517 ppdu_info->rx_status.he_data2 |= 2518 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 2519 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 2520 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 2521 QDF_MON_STATUS_TXOP_KNOWN | 2522 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 2523 2524 /*data3*/ 2525 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2526 HE_SIG_A_MU_DL_INFO, BSS_COLOR_ID); 2527 ppdu_info->rx_status.he_data3 = value; 2528 2529 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2530 HE_SIG_A_MU_DL_INFO, DL_UL_FLAG); 2531 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 2532 ppdu_info->rx_status.he_data3 |= value; 2533 2534 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2535 HE_SIG_A_MU_DL_INFO, 2536 LDPC_EXTRA_SYMBOL); 2537 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 2538 ppdu_info->rx_status.he_data3 |= value; 2539 2540 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2541 HE_SIG_A_MU_DL_INFO, STBC); 2542 he_stbc = value; 2543 value = value << QDF_MON_STATUS_STBC_SHIFT; 2544 ppdu_info->rx_status.he_data3 |= value; 2545 2546 /*data4*/ 2547 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2548 SPATIAL_REUSE); 2549 ppdu_info->rx_status.he_data4 = value; 2550 2551 /*data5*/ 2552 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2553 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 2554 ppdu_info->rx_status.he_data5 = value; 2555 ppdu_info->rx_status.bw = value; 2556 2557 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2558 HE_SIG_A_MU_DL_INFO, CP_LTF_SIZE); 2559 switch (value) { 2560 case 0: 2561 he_gi = HE_GI_0_8; 2562 he_ltf = HE_LTF_4_X; 2563 break; 2564 case 1: 2565 he_gi = HE_GI_0_8; 2566 he_ltf = HE_LTF_2_X; 2567 break; 2568 case 2: 2569 he_gi = HE_GI_1_6; 2570 he_ltf = HE_LTF_2_X; 2571 break; 2572 case 3: 2573 he_gi = HE_GI_3_2; 2574 he_ltf = HE_LTF_4_X; 2575 break; 2576 } 2577 ppdu_info->rx_status.sgi = he_gi; 2578 ppdu_info->rx_status.ltf_size = he_ltf; 2579 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 2580 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 2581 ppdu_info->rx_status.he_data5 |= value; 2582 2583 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 2584 ppdu_info->rx_status.he_data5 |= value; 2585 2586 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2587 HE_SIG_A_MU_DL_INFO, NUM_LTF_SYMBOLS); 2588 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 2589 ppdu_info->rx_status.he_data5 |= value; 2590 2591 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2592 PACKET_EXTENSION_A_FACTOR); 2593 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 2594 ppdu_info->rx_status.he_data5 |= value; 2595 2596 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2597 PACKET_EXTENSION_PE_DISAMBIGUITY); 2598 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 2599 ppdu_info->rx_status.he_data5 |= value; 2600 2601 /*data6*/ 2602 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2603 DOPPLER_INDICATION); 2604 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 2605 ppdu_info->rx_status.he_data6 |= value; 2606 2607 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2608 TXOP_DURATION); 2609 value = value << QDF_MON_STATUS_TXOP_SHIFT; 2610 ppdu_info->rx_status.he_data6 |= value; 2611 2612 /* HE-MU Flags */ 2613 /* HE-MU-flags1 */ 2614 ppdu_info->rx_status.he_flags1 = 2615 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 2616 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 2617 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 2618 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 2619 QDF_MON_STATUS_RU_0_KNOWN; 2620 2621 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2622 HE_SIG_A_MU_DL_INFO, MCS_OF_SIG_B); 2623 ppdu_info->rx_status.he_flags1 |= value; 2624 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2625 HE_SIG_A_MU_DL_INFO, DCM_OF_SIG_B); 2626 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 2627 ppdu_info->rx_status.he_flags1 |= value; 2628 2629 /* HE-MU-flags2 */ 2630 ppdu_info->rx_status.he_flags2 = 2631 QDF_MON_STATUS_BW_KNOWN; 2632 2633 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2634 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 2635 ppdu_info->rx_status.he_flags2 |= value; 2636 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2637 HE_SIG_A_MU_DL_INFO, COMP_MODE_SIG_B); 2638 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 2639 ppdu_info->rx_status.he_flags2 |= value; 2640 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2641 HE_SIG_A_MU_DL_INFO, NUM_SIG_B_SYMBOLS); 2642 value = value - 1; 2643 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 2644 ppdu_info->rx_status.he_flags2 |= value; 2645 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 2646 break; 2647 } 2648 case WIFIPHYRX_HE_SIG_B1_MU_E: 2649 { 2650 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 2651 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 2652 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 2653 2654 ppdu_info->rx_status.he_sig_b_common_known |= 2655 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 2656 /* TODO: Check on the availability of other fields in 2657 * sig_b_common 2658 */ 2659 2660 value = HAL_RX_GET(he_sig_b1_mu_info, 2661 HE_SIG_B1_MU_INFO, RU_ALLOCATION); 2662 ppdu_info->rx_status.he_RU[0] = value; 2663 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 2664 break; 2665 } 2666 case WIFIPHYRX_HE_SIG_B2_MU_E: 2667 { 2668 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 2669 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 2670 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 2671 /* 2672 * Not all "HE" fields can be updated from 2673 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 2674 * to populate rest of the "HE" fields for MU scenarios. 2675 */ 2676 2677 /* HE-data1 */ 2678 ppdu_info->rx_status.he_data1 |= 2679 QDF_MON_STATUS_HE_MCS_KNOWN | 2680 QDF_MON_STATUS_HE_CODING_KNOWN; 2681 2682 /* HE-data2 */ 2683 2684 /* HE-data3 */ 2685 value = HAL_RX_GET(he_sig_b2_mu_info, 2686 HE_SIG_B2_MU_INFO, STA_MCS); 2687 ppdu_info->rx_status.mcs = value; 2688 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2689 ppdu_info->rx_status.he_data3 |= value; 2690 2691 value = HAL_RX_GET(he_sig_b2_mu_info, 2692 HE_SIG_B2_MU_INFO, STA_CODING); 2693 value = value << QDF_MON_STATUS_CODING_SHIFT; 2694 ppdu_info->rx_status.he_data3 |= value; 2695 2696 /* HE-data4 */ 2697 value = HAL_RX_GET(he_sig_b2_mu_info, 2698 HE_SIG_B2_MU_INFO, STA_ID); 2699 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 2700 ppdu_info->rx_status.he_data4 |= value; 2701 2702 /* HE-data5 */ 2703 2704 /* HE-data6 */ 2705 value = HAL_RX_GET(he_sig_b2_mu_info, 2706 HE_SIG_B2_MU_INFO, NSTS); 2707 /* value n indicates n+1 spatial streams */ 2708 value++; 2709 ppdu_info->rx_status.nss = value; 2710 ppdu_info->rx_status.he_data6 |= value; 2711 2712 break; 2713 } 2714 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 2715 { 2716 uint8_t *he_sig_b2_ofdma_info = 2717 (uint8_t *)rx_tlv + 2718 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 2719 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 2720 2721 /* 2722 * Not all "HE" fields can be updated from 2723 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 2724 * to populate rest of "HE" fields for MU OFDMA scenarios. 2725 */ 2726 2727 /* HE-data1 */ 2728 ppdu_info->rx_status.he_data1 |= 2729 QDF_MON_STATUS_HE_MCS_KNOWN | 2730 QDF_MON_STATUS_HE_DCM_KNOWN | 2731 QDF_MON_STATUS_HE_CODING_KNOWN; 2732 2733 /* HE-data2 */ 2734 ppdu_info->rx_status.he_data2 |= 2735 QDF_MON_STATUS_TXBF_KNOWN; 2736 2737 /* HE-data3 */ 2738 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2739 HE_SIG_B2_OFDMA_INFO, STA_MCS); 2740 ppdu_info->rx_status.mcs = value; 2741 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2742 ppdu_info->rx_status.he_data3 |= value; 2743 2744 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2745 HE_SIG_B2_OFDMA_INFO, STA_DCM); 2746 he_dcm = value; 2747 value = value << QDF_MON_STATUS_DCM_SHIFT; 2748 ppdu_info->rx_status.he_data3 |= value; 2749 2750 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2751 HE_SIG_B2_OFDMA_INFO, STA_CODING); 2752 value = value << QDF_MON_STATUS_CODING_SHIFT; 2753 ppdu_info->rx_status.he_data3 |= value; 2754 2755 /* HE-data4 */ 2756 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2757 HE_SIG_B2_OFDMA_INFO, STA_ID); 2758 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 2759 ppdu_info->rx_status.he_data4 |= value; 2760 2761 /* HE-data5 */ 2762 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2763 HE_SIG_B2_OFDMA_INFO, TXBF); 2764 value = value << QDF_MON_STATUS_TXBF_SHIFT; 2765 ppdu_info->rx_status.he_data5 |= value; 2766 2767 /* HE-data6 */ 2768 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2769 HE_SIG_B2_OFDMA_INFO, NSTS); 2770 /* value n indicates n+1 spatial streams */ 2771 value++; 2772 ppdu_info->rx_status.nss = value; 2773 ppdu_info->rx_status.he_data6 |= value; 2774 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 2775 break; 2776 } 2777 case WIFIPHYRX_RSSI_LEGACY_E: 2778 { 2779 uint8_t reception_type; 2780 int8_t rssi_value; 2781 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 2782 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 2783 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 2784 2785 ppdu_info->rx_status.rssi_comb = 2786 HAL_RX_GET_64(rx_tlv, 2787 PHYRX_RSSI_LEGACY, RSSI_COMB); 2788 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 2789 ppdu_info->rx_status.he_re = 0; 2790 2791 reception_type = HAL_RX_GET_64(rx_tlv, 2792 PHYRX_RSSI_LEGACY, 2793 RECEPTION_TYPE); 2794 switch (reception_type) { 2795 case QDF_RECEPTION_TYPE_ULOFMDA: 2796 ppdu_info->rx_status.ulofdma_flag = 1; 2797 ppdu_info->rx_status.he_data1 = 2798 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 2799 break; 2800 case QDF_RECEPTION_TYPE_ULMIMO: 2801 ppdu_info->rx_status.he_data1 = 2802 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 2803 break; 2804 default: 2805 break; 2806 } 2807 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 2808 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2809 RECEIVE_RSSI_INFO, 2810 RSSI_PRI20_CHAIN0); 2811 ppdu_info->rx_status.rssi[0] = rssi_value; 2812 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2813 "RSSI_PRI20_CHAIN0: %d\n", rssi_value); 2814 2815 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2816 RECEIVE_RSSI_INFO, 2817 RSSI_PRI20_CHAIN1); 2818 ppdu_info->rx_status.rssi[1] = rssi_value; 2819 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2820 "RSSI_PRI20_CHAIN1: %d\n", rssi_value); 2821 2822 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2823 RECEIVE_RSSI_INFO, 2824 RSSI_PRI20_CHAIN2); 2825 ppdu_info->rx_status.rssi[2] = rssi_value; 2826 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2827 "RSSI_PRI20_CHAIN2: %d\n", rssi_value); 2828 2829 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2830 RECEIVE_RSSI_INFO, 2831 RSSI_PRI20_CHAIN3); 2832 ppdu_info->rx_status.rssi[3] = rssi_value; 2833 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2834 "RSSI_PRI20_CHAIN3: %d\n", rssi_value); 2835 2836 #ifdef DP_BE_NOTYET_WAR 2837 // TODO - this is not preset for kiwi 2838 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2839 RECEIVE_RSSI_INFO, 2840 RSSI_PRI20_CHAIN4); 2841 ppdu_info->rx_status.rssi[4] = rssi_value; 2842 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2843 "RSSI_PRI20_CHAIN4: %d\n", rssi_value); 2844 2845 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2846 RECEIVE_RSSI_INFO, 2847 RSSI_PRI20_CHAIN5); 2848 ppdu_info->rx_status.rssi[5] = rssi_value; 2849 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2850 "RSSI_PRI20_CHAIN5: %d\n", rssi_value); 2851 2852 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2853 RECEIVE_RSSI_INFO, 2854 RSSI_PRI20_CHAIN6); 2855 ppdu_info->rx_status.rssi[6] = rssi_value; 2856 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2857 "RSSI_PRI20_CHAIN6: %d\n", rssi_value); 2858 2859 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2860 RECEIVE_RSSI_INFO, 2861 RSSI_PRI20_CHAIN7); 2862 ppdu_info->rx_status.rssi[7] = rssi_value; 2863 #endif 2864 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2865 "RSSI_PRI20_CHAIN7: %d\n", rssi_value); 2866 break; 2867 } 2868 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 2869 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 2870 ppdu_info); 2871 break; 2872 case WIFIPHYRX_GENERIC_U_SIG_E: 2873 hal_rx_parse_u_sig_hdr(hal, rx_tlv, ppdu_info); 2874 break; 2875 case WIFIPHYRX_COMMON_USER_INFO_E: 2876 hal_rx_parse_cmn_usr_info(hal, rx_tlv, ppdu_info); 2877 break; 2878 case WIFIRX_HEADER_E: 2879 { 2880 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 2881 2882 if (ppdu_info->fcs_ok_cnt >= 2883 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 2884 hal_err("Number of MPDUs(%d) per status buff exceeded", 2885 ppdu_info->fcs_ok_cnt); 2886 break; 2887 } 2888 2889 /* Update first_msdu_payload for every mpdu and increment 2890 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 2891 */ 2892 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 2893 rx_tlv; 2894 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 2895 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 2896 ppdu_info->msdu_info.payload_len = tlv_len; 2897 ppdu_info->user_id = user_id; 2898 ppdu_info->hdr_len = tlv_len; 2899 ppdu_info->data = rx_tlv; 2900 ppdu_info->data += 4; 2901 2902 /* for every RX_HEADER TLV increment mpdu_cnt */ 2903 com_info->mpdu_cnt++; 2904 return HAL_TLV_STATUS_HEADER; 2905 } 2906 case WIFIRX_MPDU_START_E: 2907 { 2908 hal_rx_mon_mpdu_start_t *rx_mpdu_start = rx_tlv; 2909 uint32_t ppdu_id = rx_mpdu_start->rx_mpdu_info_details.phy_ppdu_id; 2910 uint8_t filter_category = 0; 2911 2912 ppdu_info->nac_info.fc_valid = 2913 rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid; 2914 2915 ppdu_info->nac_info.to_ds_flag = 2916 rx_mpdu_start->rx_mpdu_info_details.to_ds; 2917 2918 ppdu_info->nac_info.frame_control = 2919 rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field; 2920 2921 ppdu_info->sw_frame_group_id = 2922 rx_mpdu_start->rx_mpdu_info_details.sw_frame_group_id; 2923 2924 ppdu_info->rx_user_status[user_id].sw_peer_id = 2925 rx_mpdu_start->rx_mpdu_info_details.sw_peer_id; 2926 2927 if (ppdu_info->sw_frame_group_id == 2928 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 2929 ppdu_info->rx_status.frame_control_info_valid = 2930 ppdu_info->nac_info.fc_valid; 2931 ppdu_info->rx_status.frame_control = 2932 ppdu_info->nac_info.frame_control; 2933 } 2934 2935 hal_get_mac_addr1(rx_mpdu_start, 2936 ppdu_info); 2937 2938 ppdu_info->nac_info.mac_addr2_valid = 2939 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_valid; 2940 2941 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 2942 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_15_0; 2943 2944 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 2945 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_47_16; 2946 2947 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 2948 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 2949 ppdu_info->rx_status.ppdu_len = 2950 rx_mpdu_start->rx_mpdu_info_details.mpdu_length; 2951 } else { 2952 ppdu_info->rx_status.ppdu_len += 2953 rx_mpdu_start->rx_mpdu_info_details.mpdu_length; 2954 } 2955 2956 filter_category = 2957 rx_mpdu_start->rx_mpdu_info_details.rxpcu_mpdu_filter_in_category; 2958 2959 if (filter_category == 0) 2960 ppdu_info->rx_status.rxpcu_filter_pass = 1; 2961 else if (filter_category == 1) 2962 ppdu_info->rx_status.monitor_direct_used = 1; 2963 2964 ppdu_info->rx_user_status[user_id].filter_category = filter_category; 2965 2966 ppdu_info->nac_info.mcast_bcast = 2967 rx_mpdu_start->rx_mpdu_info_details.mcast_bcast; 2968 ppdu_info->mpdu_info[user_id].decap_type = 2969 rx_mpdu_start->rx_mpdu_info_details.decap_type; 2970 2971 return HAL_TLV_STATUS_MPDU_START; 2972 } 2973 case WIFIRX_MPDU_END_E: 2974 ppdu_info->user_id = user_id; 2975 ppdu_info->fcs_err = 2976 HAL_RX_GET_64(rx_tlv, RX_MPDU_END, 2977 FCS_ERR); 2978 return HAL_TLV_STATUS_MPDU_END; 2979 case WIFIRX_MSDU_END_E: { 2980 hal_rx_mon_msdu_end_t *rx_msdu_end = rx_tlv; 2981 2982 if (user_id < HAL_MAX_UL_MU_USERS) { 2983 ppdu_info->rx_msdu_info[user_id].cce_metadata = 2984 rx_msdu_end->cce_metadata; 2985 ppdu_info->rx_msdu_info[user_id].fse_metadata = 2986 rx_msdu_end->fse_metadata; 2987 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 2988 rx_msdu_end->flow_idx_timeout; 2989 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 2990 rx_msdu_end->flow_idx_invalid; 2991 ppdu_info->rx_msdu_info[user_id].flow_idx = 2992 rx_msdu_end->flow_idx; 2993 ppdu_info->msdu[user_id].first_msdu = 2994 rx_msdu_end->first_msdu; 2995 ppdu_info->msdu[user_id].last_msdu = 2996 rx_msdu_end->last_msdu; 2997 ppdu_info->msdu[user_id].msdu_len = 2998 rx_msdu_end->msdu_length; 2999 ppdu_info->msdu[user_id].user_rssi = 3000 rx_msdu_end->user_rssi; 3001 ppdu_info->msdu[user_id].reception_type = 3002 rx_msdu_end->reception_type; 3003 } 3004 return HAL_TLV_STATUS_MSDU_END; 3005 } 3006 case WIFIMON_BUFFER_ADDR_E: 3007 hal_rx_status_get_mon_buf_addr(rx_tlv, ppdu_info); 3008 3009 return HAL_TLV_STATUS_MON_BUF_ADDR; 3010 case 0: 3011 return HAL_TLV_STATUS_PPDU_DONE; 3012 case WIFIRX_STATUS_BUFFER_DONE_E: 3013 case WIFIPHYRX_DATA_DONE_E: 3014 case WIFIPHYRX_PKT_END_PART1_E: 3015 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3016 3017 default: 3018 hal_debug("unhandled tlv tag %d", tlv_tag); 3019 } 3020 3021 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3022 rx_tlv, tlv_len); 3023 3024 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3025 } 3026 3027 static uint32_t 3028 hal_rx_status_process_aggr_tlv(struct hal_soc *hal_soc, 3029 struct hal_rx_ppdu_info *ppdu_info) 3030 { 3031 uint32_t aggr_tlv_tag = ppdu_info->tlv_aggr.tlv_tag; 3032 3033 switch (aggr_tlv_tag) { 3034 case WIFIPHYRX_GENERIC_EHT_SIG_E: 3035 hal_rx_parse_eht_sig_hdr(hal_soc, ppdu_info->tlv_aggr.buf, 3036 ppdu_info); 3037 break; 3038 default: 3039 /* Aggregated TLV cannot be handled */ 3040 qdf_assert(0); 3041 break; 3042 } 3043 3044 ppdu_info->tlv_aggr.in_progress = 0; 3045 ppdu_info->tlv_aggr.cur_len = 0; 3046 3047 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3048 } 3049 3050 static inline bool 3051 hal_rx_status_tlv_should_aggregate(struct hal_soc *hal_soc, uint32_t tlv_tag) 3052 { 3053 switch (tlv_tag) { 3054 case WIFIPHYRX_GENERIC_EHT_SIG_E: 3055 return true; 3056 } 3057 3058 return false; 3059 } 3060 3061 static inline uint32_t 3062 hal_rx_status_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr, 3063 struct hal_rx_ppdu_info *ppdu_info, 3064 qdf_nbuf_t nbuf) 3065 { 3066 uint32_t tlv_tag, user_id, tlv_len; 3067 void *rx_tlv; 3068 3069 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 3070 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 3071 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 3072 3073 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 3074 3075 if (tlv_len <= HAL_RX_MON_MAX_AGGR_SIZE - ppdu_info->tlv_aggr.cur_len) { 3076 qdf_mem_copy(ppdu_info->tlv_aggr.buf + 3077 ppdu_info->tlv_aggr.cur_len, 3078 rx_tlv, tlv_len); 3079 ppdu_info->tlv_aggr.cur_len += tlv_len; 3080 } else { 3081 dp_err("Length of TLV exceeds max aggregation length"); 3082 qdf_assert(0); 3083 } 3084 3085 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3086 } 3087 3088 static inline uint32_t 3089 hal_rx_status_start_new_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr, 3090 struct hal_rx_ppdu_info *ppdu_info, 3091 qdf_nbuf_t nbuf) 3092 { 3093 uint32_t tlv_tag, user_id, tlv_len; 3094 3095 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 3096 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 3097 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 3098 3099 ppdu_info->tlv_aggr.in_progress = 1; 3100 ppdu_info->tlv_aggr.tlv_tag = tlv_tag; 3101 ppdu_info->tlv_aggr.cur_len = 0; 3102 3103 return hal_rx_status_aggr_tlv(hal_soc, rx_tlv_hdr, ppdu_info, nbuf); 3104 } 3105 3106 static inline uint32_t 3107 hal_rx_status_get_tlv_info_wrapper_be(void *rx_tlv_hdr, void *ppduinfo, 3108 hal_soc_handle_t hal_soc_hdl, 3109 qdf_nbuf_t nbuf) 3110 { 3111 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3112 uint32_t tlv_tag, user_id, tlv_len; 3113 struct hal_rx_ppdu_info *ppdu_info = 3114 (struct hal_rx_ppdu_info *)ppduinfo; 3115 3116 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 3117 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 3118 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 3119 3120 /* 3121 * Handle the case where aggregation is in progress 3122 * or the current TLV is one of the TLVs which should be 3123 * aggregated 3124 */ 3125 if (ppdu_info->tlv_aggr.in_progress) { 3126 if (ppdu_info->tlv_aggr.tlv_tag == tlv_tag) { 3127 return hal_rx_status_aggr_tlv(hal, rx_tlv_hdr, 3128 ppdu_info, nbuf); 3129 } else { 3130 /* Finish aggregation of current TLV */ 3131 hal_rx_status_process_aggr_tlv(hal, ppdu_info); 3132 } 3133 } 3134 3135 if (hal_rx_status_tlv_should_aggregate(hal, tlv_tag)) { 3136 return hal_rx_status_start_new_aggr_tlv(hal, rx_tlv_hdr, 3137 ppduinfo, nbuf); 3138 } 3139 3140 return hal_rx_status_get_tlv_info_generic_be(rx_tlv_hdr, ppduinfo, 3141 hal_soc_hdl, nbuf); 3142 } 3143 #endif /* _HAL_BE_API_MON_H_ */ 3144