1 /* 2 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HAL_BE_API_MON_H_ 19 #define _HAL_BE_API_MON_H_ 20 21 #include "hal_be_hw_headers.h" 22 #ifdef QCA_MONITOR_2_0_SUPPORT 23 #include <mon_ingress_ring.h> 24 #include <mon_destination_ring.h> 25 #endif 26 #include <hal_be_hw_headers.h> 27 #include "hal_api_mon.h" 28 #include <hal_generic_api.h> 29 #include <hal_generic_api.h> 30 #include <hal_api_mon.h> 31 32 #if defined(QCA_MONITOR_2_0_SUPPORT) || \ 33 defined(QCA_SINGLE_WIFI_3_0) 34 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 35 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 36 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff 37 38 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 39 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 40 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff 41 42 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 43 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 44 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 45 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 46 47 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c 48 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 49 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 50 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 51 52 #define HAL_MON_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 53 ((*(((unsigned int *) buff_addr_info) + \ 54 (HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 55 ((paddr_lo) << HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 56 HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 57 58 #define HAL_MON_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 59 ((*(((unsigned int *) buff_addr_info) + \ 60 (HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 61 ((paddr_hi) << HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 62 HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 63 64 #define HAL_MON_VADDR_LO_SET(buff_addr_info, vaddr_lo) \ 65 ((*(((unsigned int *) buff_addr_info) + \ 66 (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET >> 2))) = \ 67 ((vaddr_lo) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB) & \ 68 HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK) 69 70 #define HAL_MON_VADDR_HI_SET(buff_addr_info, vaddr_hi) \ 71 ((*(((unsigned int *) buff_addr_info) + \ 72 (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET >> 2))) = \ 73 ((vaddr_hi) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB) & \ 74 HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK) 75 76 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 77 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 78 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 79 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 80 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 81 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 82 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 83 PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 84 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 85 PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 86 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 87 PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 88 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 89 PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 90 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 91 PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 92 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 93 PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 94 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 95 PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 96 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 97 PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 98 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 99 PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 100 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 101 PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 102 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 103 PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 104 #endif 105 106 #ifdef CONFIG_MON_WORD_BASED_TLV 107 #ifndef BIG_ENDIAN_HOST 108 struct rx_mpdu_start_mon_data { 109 uint32_t rxpcu_mpdu_filter_in_category : 2, 110 sw_frame_group_id : 7, 111 ndp_frame : 1, 112 phy_err : 1, 113 phy_err_during_mpdu_header : 1, 114 protocol_version_err : 1, 115 ast_based_lookup_valid : 1, 116 reserved_0a : 2, 117 phy_ppdu_id : 16; 118 uint32_t ast_index : 16, 119 sw_peer_id : 16; 120 uint32_t mpdu_frame_control_valid : 1, 121 mpdu_duration_valid : 1, 122 mac_addr_ad1_valid : 1, 123 mac_addr_ad2_valid : 1, 124 mac_addr_ad3_valid : 1, 125 mac_addr_ad4_valid : 1, 126 mpdu_sequence_control_valid : 1, 127 mpdu_qos_control_valid : 1, 128 mpdu_ht_control_valid : 1, 129 frame_encryption_info_valid : 1, 130 mpdu_fragment_number : 4, 131 more_fragment_flag : 1, 132 reserved_11a : 1, 133 fr_ds : 1, 134 to_ds : 1, 135 encrypted : 1, 136 mpdu_retry : 1, 137 mpdu_sequence_number : 12; 138 uint32_t mpdu_length : 14, 139 first_mpdu : 1, 140 mcast_bcast : 1, 141 ast_index_not_found : 1, 142 ast_index_timeout : 1, 143 power_mgmt : 1, 144 non_qos : 1, 145 null_data : 1, 146 mgmt_type : 1, 147 ctrl_type : 1, 148 more_data : 1, 149 eosp : 1, 150 fragment_flag : 1, 151 order : 1, 152 u_apsd_trigger : 1, 153 encrypt_required : 1, 154 directed : 1, 155 amsdu_present : 1, 156 reserved_13 : 1; 157 uint32_t mpdu_frame_control_field : 16, 158 mpdu_duration_field : 16; 159 uint32_t mac_addr_ad1_31_0 : 32; 160 uint32_t mac_addr_ad1_47_32 : 16, 161 mac_addr_ad2_15_0 : 16; 162 }; 163 164 struct rx_msdu_end_mon_data { 165 uint32_t rxpcu_mpdu_filter_in_category : 2, 166 sw_frame_group_id : 7, 167 reserved_0 : 7, 168 phy_ppdu_id : 16; 169 uint32_t tcp_udp_chksum : 16, 170 sa_idx_timeout : 1, 171 da_idx_timeout : 1, 172 msdu_limit_error : 1, 173 flow_idx_timeout : 1, 174 flow_idx_invalid : 1, 175 wifi_parser_error : 1, 176 amsdu_parser_error : 1, 177 sa_is_valid : 1, 178 da_is_valid : 1, 179 da_is_mcbc : 1, 180 l3_header_padding : 2, 181 first_msdu : 1, 182 last_msdu : 1, 183 tcp_udp_chksum_fail : 1, 184 ip_chksum_fail : 1; 185 uint32_t msdu_drop : 1, 186 reo_destination_indication : 5, 187 flow_idx : 20, 188 reserved_12a : 6; 189 uint32_t fse_metadata : 32; 190 uint32_t cce_metadata : 16, 191 sa_sw_peer_id : 16; 192 }; 193 #else 194 struct rx_mpdu_start_mon_data { 195 uint32_t phy_ppdu_id : 16; 196 reserved_0a : 2, 197 ast_based_lookup_valid : 1, 198 protocol_version_err : 1, 199 phy_err_during_mpdu_header : 1, 200 phy_err : 1, 201 ndp_frame : 1, 202 sw_frame_group_id : 7, 203 rxpcu_mpdu_filter_in_category : 2, 204 uint32_t sw_peer_id : 16; 205 ast_index : 16, 206 uint32_t mpdu_sequence_number : 12; 207 mpdu_retry : 1, 208 encrypted : 1, 209 to_ds : 1, 210 fr_ds : 1, 211 reserved_11a : 1, 212 more_fragment_flag : 1, 213 mpdu_fragment_number : 4, 214 frame_encryption_info_valid : 1, 215 mpdu_ht_control_valid : 1, 216 mpdu_qos_control_valid : 1, 217 mpdu_sequence_control_valid : 1, 218 mac_addr_ad4_valid : 1, 219 mac_addr_ad3_valid : 1, 220 mac_addr_ad2_valid : 1, 221 mac_addr_ad1_valid : 1, 222 mpdu_duration_valid : 1, 223 mpdu_frame_control_valid : 1, 224 uint32_t reserved_13 : 1; 225 amsdu_present : 1, 226 directed : 1, 227 encrypt_required : 1, 228 u_apsd_trigger : 1, 229 order : 1, 230 fragment_flag : 1, 231 eosp : 1, 232 more_data : 1, 233 ctrl_type : 1, 234 mgmt_type : 1, 235 null_data : 1, 236 non_qos : 1, 237 power_mgmt : 1, 238 ast_index_timeout : 1, 239 ast_index_not_found : 1, 240 mcast_bcast : 1, 241 first_mpdu : 1, 242 mpdu_length : 14, 243 uint32_t mpdu_duration_field : 16; 244 mpdu_frame_control_field : 16, 245 uint32_t mac_addr_ad1_31_0 : 32; 246 uint32_t mac_addr_ad2_15_0 : 16; 247 mac_addr_ad1_47_32 : 16, 248 }; 249 250 struct rx_msdu_end_mon_data { 251 uint32_t phy_ppdu_id : 16; 252 reserved_0 : 7, 253 sw_frame_group_id : 7, 254 rxpcu_mpdu_filter_in_category : 2, 255 uint32_t ip_chksum_fail : 1; 256 tcp_udp_chksum_fail : 1, 257 last_msdu : 1, 258 first_msdu : 1, 259 l3_header_padding : 2, 260 da_is_mcbc : 1, 261 da_is_valid : 1, 262 sa_is_valid : 1, 263 amsdu_parser_error : 1, 264 wifi_parser_error : 1, 265 flow_idx_invalid : 1, 266 flow_idx_timeout : 1, 267 msdu_limit_error : 1, 268 da_idx_timeout : 1, 269 sa_idx_timeout : 1, 270 tcp_udp_chksum : 16, 271 uint32_t reserved_12a : 6; 272 flow_idx : 20, 273 reo_destination_indication : 5, 274 msdu_drop : 1, 275 uint32_t fse_metadata : 32; 276 uint32_t sa_sw_peer_id : 16; 277 cce_metadata : 16, 278 }; 279 #endif 280 281 /* TLV struct for word based Tlv */ 282 typedef struct rx_mpdu_start_mon_data hal_rx_mon_mpdu_start_t; 283 typedef struct rx_msdu_end_mon_data hal_rx_mon_msdu_end_t; 284 285 #else 286 287 typedef struct rx_mpdu_start hal_rx_mon_mpdu_start_t; 288 typedef struct rx_msdu_end hal_rx_mon_msdu_end_t; 289 #endif 290 291 /* 292 * struct mon_destination_drop - monitor drop descriptor 293 * 294 * @ppdu_drop_cnt: PPDU drop count 295 * @mpdu_drop_cnt: MPDU drop count 296 * @tlv_drop_cnt: TLV drop count 297 * @end_of_ppdu_seen: end of ppdu seen 298 * @reserved_0a: rsvd 299 * @reserved_1a: rsvd 300 * @ppdu_id: PPDU ID 301 * @reserved_3a: rsvd 302 * @initiator: initiator ppdu 303 * @empty_descriptor: empty descriptor 304 * @ring_id: ring id 305 * @looping_count: looping count 306 */ 307 struct mon_destination_drop { 308 uint32_t ppdu_drop_cnt : 10, 309 mpdu_drop_cnt : 10, 310 tlv_drop_cnt : 10, 311 end_of_ppdu_seen : 1, 312 reserved_0a : 1; 313 uint32_t reserved_1a : 32; 314 uint32_t ppdu_id : 32; 315 uint32_t reserved_3a : 18, 316 initiator : 1, 317 empty_descriptor : 1, 318 ring_id : 8, 319 looping_count : 4; 320 }; 321 322 #define HAL_MON_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 323 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 324 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 325 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 326 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 327 328 #define HAL_MON_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 329 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 330 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 331 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 332 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 333 334 /** 335 * struct hal_rx_status_buffer_done - status buffer done tlv 336 * placeholder structure 337 * 338 * @ppdu_start_offset: ppdu start 339 * @first_ppdu_start_user_info_offset: 340 * @mult_ppdu_start_user_info: 341 * @end_offset: 342 * @ppdu_end_detected: 343 * @flush_detected: 344 * @rsvd: 345 */ 346 struct hal_rx_status_buffer_done { 347 uint32_t ppdu_start_offset : 3, 348 first_ppdu_start_user_info_offset : 6, 349 mult_ppdu_start_user_info : 1, 350 end_offset : 13, 351 ppdu_end_detected : 1, 352 flush_detected : 1, 353 rsvd : 7; 354 }; 355 356 /** 357 * hal_mon_status_end_reason : ppdu status buffer end reason 358 * 359 * @HAL_MON_STATUS_BUFFER_FULL: status buffer full 360 * @HAL_MON_FLUSH_DETECTED: flush detected 361 * @HAL_MON_END_OF_PPDU: end of ppdu detected 362 * HAL_MON_PPDU_truncated: truncated ppdu status 363 */ 364 enum hal_mon_status_end_reason { 365 HAL_MON_STATUS_BUFFER_FULL, 366 HAL_MON_FLUSH_DETECTED, 367 HAL_MON_END_OF_PPDU, 368 HAL_MON_PPDU_TRUNCATED, 369 }; 370 371 /** 372 * struct hal_mon_desc () - HAL Monitor descriptor 373 * 374 * @buf_addr: virtual buffer address 375 * @ppdu_id: ppdu id 376 * - TxMon fills scheduler id 377 * - RxMON fills phy_ppdu_id 378 * @end_offset: offset (units in 4 bytes) where status buffer ended 379 * i.e offset of TLV + last TLV size 380 * @end_reason: 0 - status buffer is full 381 * 1 - flush detected 382 * 2 - TX_FES_STATUS_END or RX_PPDU_END 383 * 3 - PPDU truncated due to system error 384 * @initiator: 1 - descriptor belongs to TX FES 385 * 0 - descriptor belongs to TX RESPONSE 386 * @empty_descriptor: 0 - this descriptor is written on a flush 387 * or end of ppdu or end of status buffer 388 * 1 - descriptor provided to indicate drop 389 * @ring_id: ring id for debugging 390 * @looping_count: count to indicate number of times producer 391 * of entries has looped around the ring 392 * @flush_detected: if flush detected 393 * @end_reason: ppdu end reason 394 * @end_of_ppdu_dropped: if end_of_ppdu is dropped 395 * @ppdu_drop_count: PPDU drop count 396 * @mpdu_drop_count: MPDU drop count 397 * @tlv_drop_count: TLV drop count 398 */ 399 struct hal_mon_desc { 400 uint64_t buf_addr; 401 uint32_t ppdu_id; 402 uint32_t end_offset:12, 403 reserved_3a:4, 404 end_reason:2, 405 initiator:1, 406 empty_descriptor:1, 407 ring_id:8, 408 looping_count:4; 409 uint16_t flush_detected:1, 410 end_of_ppdu_dropped:1; 411 uint32_t ppdu_drop_count; 412 uint32_t mpdu_drop_count; 413 uint32_t tlv_drop_count; 414 }; 415 416 typedef struct hal_mon_desc *hal_mon_desc_t; 417 418 /** 419 * struct hal_mon_buf_addr_status () - HAL buffer address tlv get status 420 * 421 * @buf_addr_31_0: Lower 32 bits of virtual address of status buffer 422 * @buf_addr_63_32: Upper 32 bits of virtual address of status buffer 423 * @dma_length: DMA length 424 * @msdu_continuation: is msdu size more than fragment size 425 * @truncated: is msdu got truncated 426 * @tlv_padding: tlv paddding 427 */ 428 struct hal_mon_buf_addr_status { 429 uint32_t buffer_virt_addr_31_0; 430 uint32_t buffer_virt_addr_63_32; 431 uint32_t dma_length:12, 432 reserved_2a:4, 433 msdu_continuation:1, 434 truncated:1, 435 reserved_2b:14; 436 uint32_t tlv64_padding; 437 }; 438 439 #ifdef QCA_MONITOR_2_0_SUPPORT 440 /** 441 * hal_be_get_mon_dest_status() - Get monitor descriptor 442 * @hal_soc_hdl: HAL Soc handle 443 * @desc: HAL monitor descriptor 444 * 445 * Return: none 446 */ 447 static inline void 448 hal_be_get_mon_dest_status(hal_soc_handle_t hal_soc, 449 void *hw_desc, 450 struct hal_mon_desc *status) 451 { 452 struct mon_destination_ring *desc = hw_desc; 453 454 status->empty_descriptor = desc->empty_descriptor; 455 if (status->empty_descriptor) { 456 struct mon_destination_drop *drop_desc = hw_desc; 457 458 status->buf_addr = 0; 459 status->ppdu_drop_count = drop_desc->ppdu_drop_cnt; 460 status->mpdu_drop_count = drop_desc->mpdu_drop_cnt; 461 status->tlv_drop_count = drop_desc->tlv_drop_cnt; 462 status->end_of_ppdu_dropped = drop_desc->end_of_ppdu_seen; 463 } else { 464 status->buf_addr = HAL_RX_GET(desc, MON_DESTINATION_RING_STAT,BUF_VIRT_ADDR_31_0) | 465 (((uint64_t)HAL_RX_GET(desc, 466 MON_DESTINATION_RING_STAT, 467 BUF_VIRT_ADDR_63_32)) << 32); 468 status->end_reason = desc->end_reason; 469 status->end_offset = desc->end_offset; 470 } 471 status->ppdu_id = desc->ppdu_id; 472 status->initiator = desc->initiator; 473 status->looping_count = desc->looping_count; 474 } 475 #endif 476 477 #if defined(RX_PPDU_END_USER_STATS_OFDMA_INFO_VALID_OFFSET) && \ 478 defined(RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 479 480 static inline void 481 hal_rx_handle_mu_ul_info(void *rx_tlv, 482 struct mon_rx_user_status *mon_rx_user_status) 483 { 484 mon_rx_user_status->mu_ul_user_v0_word0 = 485 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 486 SW_RESPONSE_REFERENCE_PTR); 487 488 mon_rx_user_status->mu_ul_user_v0_word1 = 489 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 490 SW_RESPONSE_REFERENCE_PTR_EXT); 491 } 492 #else 493 static inline void 494 hal_rx_handle_mu_ul_info(void *rx_tlv, 495 struct mon_rx_user_status *mon_rx_user_status) 496 { 497 } 498 #endif 499 500 static inline void 501 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 502 struct mon_rx_user_status *mon_rx_user_status) 503 { 504 uint32_t mpdu_ok_byte_count; 505 uint32_t mpdu_err_byte_count; 506 507 mpdu_ok_byte_count = HAL_RX_GET_64(rx_tlv, 508 RX_PPDU_END_USER_STATS, 509 MPDU_OK_BYTE_COUNT); 510 mpdu_err_byte_count = HAL_RX_GET_64(rx_tlv, 511 RX_PPDU_END_USER_STATS, 512 MPDU_ERR_BYTE_COUNT); 513 514 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 515 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 516 } 517 518 static inline void 519 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id, 520 struct mon_rx_user_status *mon_rx_user_status) 521 { 522 struct mon_rx_info *mon_rx_info; 523 struct mon_rx_user_info *mon_rx_user_info; 524 struct hal_rx_ppdu_info *ppdu_info = 525 (struct hal_rx_ppdu_info *)ppduinfo; 526 527 mon_rx_info = &ppdu_info->rx_info; 528 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 529 mon_rx_user_info->qos_control_info_valid = 530 mon_rx_info->qos_control_info_valid; 531 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 532 533 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 534 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 535 mon_rx_user_status->tcp_msdu_count = 536 ppdu_info->rx_status.tcp_msdu_count; 537 mon_rx_user_status->udp_msdu_count = 538 ppdu_info->rx_status.udp_msdu_count; 539 mon_rx_user_status->other_msdu_count = 540 ppdu_info->rx_status.other_msdu_count; 541 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 542 mon_rx_user_status->frame_control_info_valid = 543 ppdu_info->rx_status.frame_control_info_valid; 544 mon_rx_user_status->data_sequence_control_info_valid = 545 ppdu_info->rx_status.data_sequence_control_info_valid; 546 mon_rx_user_status->first_data_seq_ctrl = 547 ppdu_info->rx_status.first_data_seq_ctrl; 548 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 549 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 550 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 551 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 552 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 553 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 554 555 mon_rx_user_status->mpdu_cnt_fcs_ok = 556 ppdu_info->com_info.mpdu_cnt_fcs_ok; 557 mon_rx_user_status->mpdu_cnt_fcs_err = 558 ppdu_info->com_info.mpdu_cnt_fcs_err; 559 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 560 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 561 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 562 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 563 mon_rx_user_status->retry_mpdu = 564 ppdu_info->rx_status.mpdu_retry_cnt; 565 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 566 } 567 568 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, \ 569 ppdu_info, rssi_info_tlv) \ 570 { \ 571 ppdu_info->rx_status.rssi_chain[chain][0] = \ 572 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 573 RSSI_PRI20_CHAIN##chain); \ 574 ppdu_info->rx_status.rssi_chain[chain][1] = \ 575 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 576 RSSI_EXT20_CHAIN##chain); \ 577 ppdu_info->rx_status.rssi_chain[chain][2] = \ 578 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 579 RSSI_EXT40_LOW20_CHAIN##chain); \ 580 ppdu_info->rx_status.rssi_chain[chain][3] = \ 581 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 582 RSSI_EXT40_HIGH20_CHAIN##chain); \ 583 } \ 584 585 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 586 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, ppdu_info, rssi_info_tlv) \ 587 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, ppdu_info, rssi_info_tlv) \ 588 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, ppdu_info, rssi_info_tlv) \ 589 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, ppdu_info, rssi_info_tlv) \ 590 } \ 591 592 static inline uint32_t 593 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 594 uint8_t *rssi_info_tlv) 595 { 596 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 597 return 0; 598 } 599 600 #ifdef WLAN_TX_PKT_CAPTURE_ENH 601 static inline void 602 hal_get_qos_control(void *rx_tlv, 603 struct hal_rx_ppdu_info *ppdu_info) 604 { 605 ppdu_info->rx_info.qos_control_info_valid = 606 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 607 QOS_CONTROL_INFO_VALID); 608 609 if (ppdu_info->rx_info.qos_control_info_valid) 610 ppdu_info->rx_info.qos_control = 611 HAL_RX_GET_64(rx_tlv, 612 RX_PPDU_END_USER_STATS, 613 QOS_CONTROL_FIELD); 614 } 615 616 static inline void 617 hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 618 struct hal_rx_ppdu_info *ppdu_info) 619 { 620 if ((ppdu_info->sw_frame_group_id 621 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 622 (ppdu_info->sw_frame_group_id == 623 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 624 ppdu_info->rx_info.mac_addr1_valid = 625 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_valid; 626 627 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 628 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_31_0; 629 if (ppdu_info->sw_frame_group_id == 630 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 631 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 632 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_47_32; 633 } 634 } 635 } 636 #else 637 static inline void 638 hal_get_qos_control(void *rx_tlv, 639 struct hal_rx_ppdu_info *ppdu_info) 640 { 641 } 642 643 static inline void 644 hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 645 struct hal_rx_ppdu_info *ppdu_info) 646 { 647 } 648 #endif 649 650 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 651 static inline void 652 hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 653 struct hal_rx_ppdu_info *ppdu_info) 654 { 655 uint16_t frame_ctrl; 656 uint8_t fc_type; 657 658 if (rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid) { 659 frame_ctrl = rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field; 660 fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl); 661 if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT) 662 ppdu_info->frm_type_info.rx_mgmt_cnt++; 663 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL) 664 ppdu_info->frm_type_info.rx_ctrl_cnt++; 665 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA) 666 ppdu_info->frm_type_info.rx_data_cnt++; 667 } 668 } 669 #else 670 static inline void 671 hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 672 struct hal_rx_ppdu_info *ppdu_info) 673 { 674 } 675 #endif 676 677 #ifdef QCA_MONITOR_2_0_SUPPORT 678 /** 679 * hal_mon_buff_addr_info_set() - set desc address in cookie 680 * @hal_soc_hdl: HAL Soc handle 681 * @mon_entry: monitor srng 682 * @desc: HAL monitor descriptor 683 * 684 * Return: none 685 */ 686 static inline 687 void hal_mon_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 688 void *mon_entry, 689 void *mon_desc_addr, 690 qdf_dma_addr_t phy_addr) 691 { 692 uint32_t paddr_lo = ((uintptr_t)phy_addr & 0x00000000ffffffff); 693 uint32_t paddr_hi = ((uintptr_t)phy_addr & 0xffffffff00000000) >> 32; 694 uint32_t vaddr_lo = ((uintptr_t)mon_desc_addr & 0x00000000ffffffff); 695 uint32_t vaddr_hi = ((uintptr_t)mon_desc_addr & 0xffffffff00000000) >> 32; 696 697 HAL_MON_PADDR_LO_SET(mon_entry, paddr_lo); 698 HAL_MON_PADDR_HI_SET(mon_entry, paddr_hi); 699 HAL_MON_VADDR_LO_SET(mon_entry, vaddr_lo); 700 HAL_MON_VADDR_HI_SET(mon_entry, vaddr_hi); 701 } 702 703 /* TX monitor */ 704 #define TX_MON_STATUS_BUF_SIZE 2048 705 706 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 707 708 enum hal_tx_tlv_status { 709 HAL_MON_TX_FES_SETUP, 710 HAL_MON_TX_FES_STATUS_END, 711 HAL_MON_RX_RESPONSE_REQUIRED_INFO, 712 HAL_MON_RESPONSE_END_STATUS_INFO, 713 714 HAL_MON_TX_PCU_PPDU_SETUP_INIT, 715 716 HAL_MON_TX_MPDU_START, 717 HAL_MON_TX_MSDU_START, 718 HAL_MON_TX_BUFFER_ADDR, 719 HAL_MON_TX_DATA, 720 721 HAL_MON_TX_FES_STATUS_START, 722 723 HAL_MON_TX_FES_STATUS_PROT, 724 HAL_MON_TX_FES_STATUS_START_PROT, 725 726 HAL_MON_TX_FES_STATUS_START_PPDU, 727 HAL_MON_TX_FES_STATUS_USER_PPDU, 728 HAL_MON_TX_QUEUE_EXTENSION, 729 730 HAL_MON_RX_FRAME_BITMAP_ACK, 731 HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_256, 732 HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K, 733 HAL_MON_COEX_TX_STATUS, 734 735 HAL_MON_MACTX_HE_SIG_A_SU, 736 HAL_MON_MACTX_HE_SIG_A_MU_DL, 737 HAL_MON_MACTX_HE_SIG_B1_MU, 738 HAL_MON_MACTX_HE_SIG_B2_MU, 739 HAL_MON_MACTX_HE_SIG_B2_OFDMA, 740 HAL_MON_MACTX_L_SIG_A, 741 HAL_MON_MACTX_L_SIG_B, 742 HAL_MON_MACTX_HT_SIG, 743 HAL_MON_MACTX_VHT_SIG_A, 744 745 HAL_MON_MACTX_USER_DESC_PER_USER, 746 HAL_MON_MACTX_USER_DESC_COMMON, 747 HAL_MON_MACTX_PHY_DESC, 748 749 HAL_MON_TX_STATUS_PPDU_NOT_DONE, 750 }; 751 752 enum txmon_coex_tx_status_reason { 753 COEX_FES_TX_START, 754 COEX_FES_TX_END, 755 COEX_FES_END, 756 COEX_RESPONSE_TX_START, 757 COEX_RESPONSE_TX_END, 758 COEX_NO_TX_ONGOING, 759 }; 760 761 enum txmon_transmission_type { 762 TXMON_SU_TRANSMISSION = 0, 763 TXMON_MU_TRANSMISSION, 764 TXMON_MU_SU_TRANSMISSION, 765 TXMON_MU_MIMO_TRANSMISSION = 1, 766 TXMON_MU_OFDMA_TRANMISSION 767 }; 768 769 enum txmon_he_ppdu_subtype { 770 TXMON_HE_SUBTYPE_SU = 0, 771 TXMON_HE_SUBTYPE_TRIG, 772 TXMON_HE_SUBTYPE_MU, 773 TXMON_HE_SUBTYPE_EXT_SU 774 }; 775 776 enum txmon_pkt_type { 777 TXMON_PKT_TYPE_11A = 0, 778 TXMON_PKT_TYPE_11B, 779 TXMON_PKT_TYPE_11N_MM, 780 TXMON_PKT_TYPE_11AC, 781 TXMON_PKT_TYPE_11AX, 782 TXMON_PKT_TYPE_11BA, 783 TXMON_PKT_TYPE_11BE, 784 TXMON_PKT_TYPE_11AZ 785 }; 786 787 enum txmon_generated_response { 788 TXMON_GEN_RESP_SELFGEN_ACK = 0, 789 TXMON_GEN_RESP_SELFGEN_CTS, 790 TXMON_GEN_RESP_SELFGEN_BA, 791 TXMON_GEN_RESP_SELFGEN_MBA, 792 TXMON_GEN_RESP_SELFGEN_CBF, 793 TXMON_GEN_RESP_SELFGEN_TRIG, 794 TXMON_GEN_RESP_SELFGEN_NDP_LMR 795 }; 796 797 #define TXMON_HAL(hal_tx_ppdu_info, field) \ 798 hal_tx_ppdu_info->field 799 #define TXMON_HAL_STATUS(hal_tx_ppdu_info, field) \ 800 hal_tx_ppdu_info->rx_status.field 801 #define TXMON_HAL_USER(hal_tx_ppdu_info, user_id, field) \ 802 hal_tx_ppdu_info->rx_user_status[user_id].field 803 804 #define TXMON_STATUS_INFO(hal_tx_status_info, field) \ 805 hal_tx_status_info->field 806 807 /** 808 * struct hal_tx_status_info - status info that wasn't populated in rx_status 809 * @reception_type: su or uplink mu reception type 810 * @transmission_type: su or mu transmission type 811 * @medium_prot_type: medium protection type 812 * @generated_response: Generated frame in response window 813 * @no_bitmap_avail: Bitmap available flag 814 * @explicit_ack: Explicit Acknowledge flag 815 * @explicit_ack_type: Explicit Acknowledge type 816 * @r2r_end_status_follow: Response to Response status flag 817 * @response_type: Response type in response window 818 * @ndp_frame: NDP frame 819 * @num_users: number of users 820 * @sw_frame_group_id: software frame group ID 821 * @r2r_to_follow: Response to Response follow flag 822 * @buffer: Packet buffer pointer address 823 * @offset: Packet buffer offset 824 * @length: Packet buffer length 825 * @protection_addr: Protection Address flag 826 * @addr1: MAC address 1 827 * @addr2: MAC address 2 828 * @addr3: MAC address 3 829 * @addr4: MAC address 4 830 */ 831 struct hal_tx_status_info { 832 uint8_t reception_type; 833 uint8_t transmission_type; 834 uint8_t medium_prot_type; 835 uint8_t generated_response; 836 837 uint32_t no_bitmap_avail :1, 838 explicit_ack :1, 839 explicit_ack_type :4, 840 r2r_end_status_follow :1, 841 response_type :5, 842 ndp_frame :2, 843 num_users :8, 844 reserved :10; 845 846 uint8_t sw_frame_group_id; 847 uint32_t r2r_to_follow; 848 849 void *buffer; 850 uint32_t offset; 851 uint32_t length; 852 853 uint8_t protection_addr; 854 uint8_t addr1[QDF_MAC_ADDR_SIZE]; 855 uint8_t addr2[QDF_MAC_ADDR_SIZE]; 856 uint8_t addr3[QDF_MAC_ADDR_SIZE]; 857 uint8_t addr4[QDF_MAC_ADDR_SIZE]; 858 }; 859 860 /** 861 * struct hal_tx_ppdu_info - tx monitor ppdu information 862 * @ppdu_id: Id of the PLCP protocol data unit 863 * @num_users: number of users 864 * @is_used: boolean flag to identify valid ppdu info 865 * @is_data: boolean flag to identify data frame 866 * @cur_usr_idx: Current user index of the PPDU 867 * @reserved: for furture purpose 868 * @prot_tlv_status: protection tlv status 869 * @packet_info: packet information 870 * @rx_status: monitor mode rx status information 871 * @rx_user_status: monitor mode rx user status information 872 */ 873 struct hal_tx_ppdu_info { 874 uint32_t ppdu_id; 875 uint32_t num_users :8, 876 is_used :1, 877 is_data :1, 878 cur_usr_idx :8, 879 reserved :15; 880 881 uint32_t prot_tlv_status; 882 883 /* placeholder to hold packet buffer info */ 884 struct hal_mon_packet_info packet_info; 885 struct mon_rx_status rx_status; 886 struct mon_rx_user_status rx_user_status[]; 887 }; 888 889 /** 890 * hal_tx_status_get_next_tlv() - get next tx status TLV 891 * @tx_tlv: pointer to TLV header 892 * 893 * Return: pointer to next tlv info 894 */ 895 static inline uint8_t* 896 hal_tx_status_get_next_tlv(uint8_t *tx_tlv) { 897 uint32_t tlv_len, tlv_tag; 898 899 tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv); 900 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv); 901 902 return (uint8_t *)(((unsigned long)(tx_tlv + tlv_len + 903 HAL_RX_TLV32_HDR_SIZE + 7)) & (~7)); 904 } 905 906 /** 907 * hal_txmon_status_parse_tlv() - process transmit info TLV 908 * @hal_soc: HAL soc handle 909 * @data_ppdu_info: pointer to hal data ppdu info 910 * @prot_ppdu_info: pointer to hal prot ppdu info 911 * @data_status_info: pointer to data status info 912 * @prot_status_info: pointer to prot status info 913 * @tx_tlv_hdr: pointer to TLV header 914 * @status_frag: pointer to status frag 915 * 916 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE 917 */ 918 static inline uint32_t 919 hal_txmon_status_parse_tlv(hal_soc_handle_t hal_soc_hdl, 920 void *data_ppdu_info, 921 void *prot_ppdu_info, 922 void *data_status_info, 923 void *prot_status_info, 924 void *tx_tlv_hdr, 925 qdf_frag_t status_frag) 926 { 927 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 928 929 return hal_soc->ops->hal_txmon_status_parse_tlv(data_ppdu_info, 930 prot_ppdu_info, 931 data_status_info, 932 prot_status_info, 933 tx_tlv_hdr, 934 status_frag); 935 } 936 937 /** 938 * hal_txmon_status_get_num_users() - api to get num users from start of fes 939 * window 940 * @hal_soc: HAL soc handle 941 * @tx_tlv_hdr: pointer to TLV header 942 * @num_users: reference to number of user 943 * 944 * Return: status 945 */ 946 static inline uint32_t 947 hal_txmon_status_get_num_users(hal_soc_handle_t hal_soc_hdl, 948 void *tx_tlv_hdr, uint8_t *num_users) 949 { 950 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 951 952 return hal_soc->ops->hal_txmon_status_get_num_users(tx_tlv_hdr, 953 num_users); 954 } 955 956 /** 957 * hal_tx_status_get_tlv_tag() - api to get tlv tag 958 * @tx_tlv_hdr: pointer to TLV header 959 * 960 * Return tlv_tag 961 */ 962 static inline uint32_t 963 hal_tx_status_get_tlv_tag(void *tx_tlv_hdr) 964 { 965 uint32_t tlv_tag = 0; 966 967 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr); 968 969 return tlv_tag; 970 } 971 #endif 972 973 /** 974 * hal_txmon_is_mon_buf_addr_tlv() - api to find packet buffer addr tlv 975 * @hal_soc: HAL soc handle 976 * @tx_tlv_hdr: pointer to TLV header 977 * 978 * Return: bool 979 */ 980 static inline bool 981 hal_txmon_is_mon_buf_addr_tlv(hal_soc_handle_t hal_soc_hdl, void *tx_tlv_hdr) 982 { 983 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 984 985 if (qdf_unlikely(!hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv)) 986 return false; 987 988 return hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv(tx_tlv_hdr); 989 } 990 991 /** 992 * hal_txmon_populate_packet_info() - api to populate packet info 993 * @hal_soc: HAL soc handle 994 * @tx_tlv_hdr: pointer to TLV header 995 * @packet_info: pointer to placeholder for packet info 996 * 997 * Return void 998 */ 999 static inline void 1000 hal_txmon_populate_packet_info(hal_soc_handle_t hal_soc_hdl, 1001 void *tx_tlv_hdr, 1002 void *packet_info) 1003 { 1004 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1005 1006 if (qdf_unlikely(!hal_soc->ops->hal_txmon_populate_packet_info)) 1007 return; 1008 1009 hal_soc->ops->hal_txmon_populate_packet_info(tx_tlv_hdr, packet_info); 1010 } 1011 1012 static inline uint32_t 1013 hal_rx_parse_u_sig_cmn(struct hal_soc *hal_soc, void *rx_tlv, 1014 struct hal_rx_ppdu_info *ppdu_info) 1015 { 1016 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1017 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 1018 uint8_t bad_usig_crc; 1019 1020 bad_usig_crc = HAL_RX_MON_USIG_GET_RX_INTEGRITY_CHECK_PASSED(rx_tlv) ? 1021 0 : 1; 1022 ppdu_info->rx_status.usig_common |= 1023 QDF_MON_STATUS_USIG_PHY_VERSION_KNOWN | 1024 QDF_MON_STATUS_USIG_BW_KNOWN | 1025 QDF_MON_STATUS_USIG_UL_DL_KNOWN | 1026 QDF_MON_STATUS_USIG_BSS_COLOR_KNOWN | 1027 QDF_MON_STATUS_USIG_TXOP_KNOWN; 1028 1029 ppdu_info->rx_status.usig_common |= (usig_1->phy_version << 1030 QDF_MON_STATUS_USIG_PHY_VERSION_SHIFT); 1031 ppdu_info->rx_status.usig_common |= (usig_1->bw << 1032 QDF_MON_STATUS_USIG_BW_SHIFT); 1033 ppdu_info->rx_status.usig_common |= (usig_1->ul_dl << 1034 QDF_MON_STATUS_USIG_UL_DL_SHIFT); 1035 ppdu_info->rx_status.usig_common |= (usig_1->bss_color << 1036 QDF_MON_STATUS_USIG_BSS_COLOR_SHIFT); 1037 ppdu_info->rx_status.usig_common |= (usig_1->txop << 1038 QDF_MON_STATUS_USIG_TXOP_SHIFT); 1039 ppdu_info->rx_status.usig_common |= bad_usig_crc; 1040 1041 ppdu_info->u_sig_info.ul_dl = usig_1->ul_dl; 1042 ppdu_info->u_sig_info.bw = usig_1->bw; 1043 ppdu_info->rx_status.bw = usig_1->bw; 1044 1045 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1046 } 1047 1048 static inline uint32_t 1049 hal_rx_parse_u_sig_tb(struct hal_soc *hal_soc, void *rx_tlv, 1050 struct hal_rx_ppdu_info *ppdu_info) 1051 { 1052 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1053 struct hal_mon_usig_tb *usig_tb = &usig->usig_2.tb; 1054 1055 ppdu_info->rx_status.usig_mask |= 1056 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 1057 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 1058 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 1059 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_KNOWN | 1060 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_KNOWN | 1061 QDF_MON_STATUS_USIG_TB_DISREGARD1_KNOWN | 1062 QDF_MON_STATUS_USIG_CRC_KNOWN | 1063 QDF_MON_STATUS_USIG_TAIL_KNOWN; 1064 1065 ppdu_info->rx_status.usig_value |= (0x3F << 1066 QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 1067 ppdu_info->rx_status.usig_value |= (usig_tb->ppdu_type_comp_mode << 1068 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 1069 ppdu_info->rx_status.usig_value |= (0x1 << 1070 QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 1071 ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_1 << 1072 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_SHIFT); 1073 ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_2 << 1074 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_SHIFT); 1075 ppdu_info->rx_status.usig_value |= (0x1F << 1076 QDF_MON_STATUS_USIG_TB_DISREGARD1_SHIFT); 1077 ppdu_info->rx_status.usig_value |= (usig_tb->crc << 1078 QDF_MON_STATUS_USIG_CRC_SHIFT); 1079 ppdu_info->rx_status.usig_value |= (usig_tb->tail << 1080 QDF_MON_STATUS_USIG_TAIL_SHIFT); 1081 1082 ppdu_info->u_sig_info.ppdu_type_comp_mode = 1083 usig_tb->ppdu_type_comp_mode; 1084 1085 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1086 } 1087 1088 static inline uint32_t 1089 hal_rx_parse_u_sig_mu(struct hal_soc *hal_soc, void *rx_tlv, 1090 struct hal_rx_ppdu_info *ppdu_info) 1091 { 1092 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1093 struct hal_mon_usig_mu *usig_mu = &usig->usig_2.mu; 1094 1095 ppdu_info->rx_status.usig_mask |= 1096 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 1097 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 1098 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 1099 QDF_MON_STATUS_USIG_MU_VALIDATE1_KNOWN | 1100 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_KNOWN | 1101 QDF_MON_STATUS_USIG_MU_VALIDATE2_KNOWN | 1102 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_KNOWN | 1103 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_KNOWN | 1104 QDF_MON_STATUS_USIG_CRC_KNOWN | 1105 QDF_MON_STATUS_USIG_TAIL_KNOWN; 1106 1107 ppdu_info->rx_status.usig_value |= (0x1F << 1108 QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 1109 ppdu_info->rx_status.usig_value |= (0x1 << 1110 QDF_MON_STATUS_USIG_MU_VALIDATE1_SHIFT); 1111 ppdu_info->rx_status.usig_value |= (usig_mu->ppdu_type_comp_mode << 1112 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 1113 ppdu_info->rx_status.usig_value |= (0x1 << 1114 QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 1115 ppdu_info->rx_status.usig_value |= (usig_mu->punc_ch_info << 1116 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_SHIFT); 1117 ppdu_info->rx_status.usig_value |= (0x1 << 1118 QDF_MON_STATUS_USIG_MU_VALIDATE2_SHIFT); 1119 ppdu_info->rx_status.usig_value |= (usig_mu->eht_sig_mcs << 1120 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_SHIFT); 1121 ppdu_info->rx_status.usig_value |= (usig_mu->num_eht_sig_sym << 1122 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_SHIFT); 1123 ppdu_info->rx_status.usig_value |= (usig_mu->crc << 1124 QDF_MON_STATUS_USIG_CRC_SHIFT); 1125 ppdu_info->rx_status.usig_value |= (usig_mu->tail << 1126 QDF_MON_STATUS_USIG_TAIL_SHIFT); 1127 1128 ppdu_info->u_sig_info.ppdu_type_comp_mode = 1129 usig_mu->ppdu_type_comp_mode; 1130 ppdu_info->u_sig_info.eht_sig_mcs = usig_mu->eht_sig_mcs; 1131 ppdu_info->u_sig_info.num_eht_sig_sym = usig_mu->num_eht_sig_sym; 1132 1133 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1134 } 1135 1136 static inline uint32_t 1137 hal_rx_parse_u_sig_hdr(struct hal_soc *hal_soc, void *rx_tlv, 1138 struct hal_rx_ppdu_info *ppdu_info) 1139 { 1140 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1141 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 1142 1143 ppdu_info->rx_status.usig_flags = 1; 1144 1145 hal_rx_parse_u_sig_cmn(hal_soc, rx_tlv, ppdu_info); 1146 1147 if (HAL_RX_MON_USIG_GET_PPDU_TYPE_N_COMP_MODE(rx_tlv) == 0 && 1148 usig_1->ul_dl == 1) 1149 return hal_rx_parse_u_sig_tb(hal_soc, rx_tlv, ppdu_info); 1150 else 1151 return hal_rx_parse_u_sig_mu(hal_soc, rx_tlv, ppdu_info); 1152 } 1153 1154 static inline uint32_t 1155 hal_rx_parse_usig_overflow(struct hal_soc *hal_soc, void *tlv, 1156 struct hal_rx_ppdu_info *ppdu_info) 1157 { 1158 struct hal_eht_sig_cc_usig_overflow *usig_ovflow = 1159 (struct hal_eht_sig_cc_usig_overflow *)tlv; 1160 1161 ppdu_info->rx_status.eht_known |= 1162 QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1163 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1164 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_KNOWN | 1165 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_KNOWN | 1166 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_KNOWN | 1167 QDF_MON_STATUS_EHT_DISREARD_KNOWN; 1168 1169 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->spatial_reuse << 1170 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1171 /* 1172 * GI and LTF size are separately indicated in radiotap header 1173 * and hence will be parsed from other TLV 1174 **/ 1175 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->num_ltf_sym << 1176 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1177 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->ldpc_extra_sym << 1178 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_SHIFT); 1179 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pre_fec_pad_factor << 1180 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_SHIFT); 1181 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pe_disambiguity << 1182 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_SHIFT); 1183 ppdu_info->rx_status.eht_data[0] |= (0xF << 1184 QDF_MON_STATUS_EHT_DISREGARD_SHIFT); 1185 1186 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1187 } 1188 1189 static inline uint32_t 1190 hal_rx_parse_non_ofdma_users(struct hal_soc *hal_soc, void *tlv, 1191 struct hal_rx_ppdu_info *ppdu_info) 1192 { 1193 struct hal_eht_sig_non_ofdma_cmn_eb *non_ofdma_cmn_eb = 1194 (struct hal_eht_sig_non_ofdma_cmn_eb *)tlv; 1195 1196 ppdu_info->rx_status.eht_known |= 1197 QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_KNOWN; 1198 1199 ppdu_info->rx_status.eht_data[4] |= (non_ofdma_cmn_eb->num_users << 1200 QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_SHIFT); 1201 1202 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1203 } 1204 1205 static inline uint32_t 1206 hal_rx_parse_ru_allocation(struct hal_soc *hal_soc, void *tlv, 1207 struct hal_rx_ppdu_info *ppdu_info) 1208 { 1209 uint64_t *ehtsig_tlv = (uint64_t *)tlv; 1210 struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cmn_eb1; 1211 struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cmn_eb2; 1212 uint8_t num_ru_allocation_known = 0; 1213 1214 ofdma_cmn_eb1 = (struct hal_eht_sig_ofdma_cmn_eb1 *)ehtsig_tlv; 1215 ofdma_cmn_eb2 = (struct hal_eht_sig_ofdma_cmn_eb2 *)(ehtsig_tlv + 1); 1216 1217 switch (ppdu_info->u_sig_info.bw) { 1218 case HAL_EHT_BW_320_2: 1219 case HAL_EHT_BW_320_1: 1220 num_ru_allocation_known += 4; 1221 1222 ppdu_info->rx_status.eht_data[3] |= 1223 (ofdma_cmn_eb2->ru_allocation2_6 << 1224 QDF_MON_STATUS_EHT_RU_ALLOCATION2_6_SHIFT); 1225 ppdu_info->rx_status.eht_data[3] |= 1226 (ofdma_cmn_eb2->ru_allocation2_5 << 1227 QDF_MON_STATUS_EHT_RU_ALLOCATION2_5_SHIFT); 1228 ppdu_info->rx_status.eht_data[3] |= 1229 (ofdma_cmn_eb2->ru_allocation2_4 << 1230 QDF_MON_STATUS_EHT_RU_ALLOCATION2_4_SHIFT); 1231 ppdu_info->rx_status.eht_data[2] |= 1232 (ofdma_cmn_eb2->ru_allocation2_3 << 1233 QDF_MON_STATUS_EHT_RU_ALLOCATION2_3_SHIFT); 1234 fallthrough; 1235 case HAL_EHT_BW_160: 1236 num_ru_allocation_known += 2; 1237 1238 ppdu_info->rx_status.eht_data[2] |= 1239 (ofdma_cmn_eb2->ru_allocation2_2 << 1240 QDF_MON_STATUS_EHT_RU_ALLOCATION2_2_SHIFT); 1241 ppdu_info->rx_status.eht_data[2] |= 1242 (ofdma_cmn_eb2->ru_allocation2_1 << 1243 QDF_MON_STATUS_EHT_RU_ALLOCATION2_1_SHIFT); 1244 fallthrough; 1245 case HAL_EHT_BW_80: 1246 num_ru_allocation_known += 1; 1247 1248 ppdu_info->rx_status.eht_data[1] |= 1249 (ofdma_cmn_eb1->ru_allocation1_2 << 1250 QDF_MON_STATUS_EHT_RU_ALLOCATION1_2_SHIFT); 1251 fallthrough; 1252 case HAL_EHT_BW_40: 1253 case HAL_EHT_BW_20: 1254 num_ru_allocation_known += 1; 1255 1256 ppdu_info->rx_status.eht_data[1] |= 1257 (ofdma_cmn_eb1->ru_allocation1_1 << 1258 QDF_MON_STATUS_EHT_RU_ALLOCATION1_1_SHIFT); 1259 break; 1260 default: 1261 break; 1262 } 1263 1264 ppdu_info->rx_status.eht_known |= (num_ru_allocation_known << 1265 QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT); 1266 1267 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1268 } 1269 1270 static inline uint32_t 1271 hal_rx_parse_eht_sig_mumimo_user_info(struct hal_soc *hal_soc, void *tlv, 1272 struct hal_rx_ppdu_info *ppdu_info) 1273 { 1274 struct hal_eht_sig_mu_mimo_user_info *user_info; 1275 uint32_t user_idx = ppdu_info->rx_status.num_eht_user_info_valid; 1276 1277 user_info = (struct hal_eht_sig_mu_mimo_user_info *)tlv; 1278 1279 ppdu_info->rx_status.eht_user_info[user_idx] |= 1280 QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1281 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1282 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1283 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_KNOWN; 1284 1285 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->sta_id << 1286 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1287 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->mcs << 1288 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1289 ppdu_info->rx_status.mcs = user_info->mcs; 1290 1291 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->coding << 1292 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1293 ppdu_info->rx_status.eht_user_info[user_idx] |= 1294 (user_info->spatial_coding << 1295 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_SHIFT); 1296 1297 /* CRC for matched user block */ 1298 ppdu_info->rx_status.eht_known |= 1299 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN | 1300 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN; 1301 ppdu_info->rx_status.eht_data[4] |= (user_info->crc << 1302 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT); 1303 1304 ppdu_info->rx_status.num_eht_user_info_valid++; 1305 1306 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1307 } 1308 1309 static inline uint32_t 1310 hal_rx_parse_eht_sig_non_mumimo_user_info(struct hal_soc *hal_soc, void *tlv, 1311 struct hal_rx_ppdu_info *ppdu_info) 1312 { 1313 struct hal_eht_sig_non_mu_mimo_user_info *user_info; 1314 uint32_t user_idx = ppdu_info->rx_status.num_eht_user_info_valid; 1315 1316 user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tlv; 1317 1318 ppdu_info->rx_status.eht_user_info[user_idx] |= 1319 QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1320 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1321 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1322 QDF_MON_STATUS_EHT_USER_NSS_KNOWN | 1323 QDF_MON_STATUS_EHT_USER_BEAMFORMING_KNOWN; 1324 1325 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->sta_id << 1326 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1327 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->mcs << 1328 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1329 ppdu_info->rx_status.mcs = user_info->mcs; 1330 1331 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->nss << 1332 QDF_MON_STATUS_EHT_USER_NSS_SHIFT); 1333 ppdu_info->rx_status.nss = user_info->nss + 1; 1334 1335 ppdu_info->rx_status.eht_user_info[user_idx] |= 1336 (user_info->beamformed << 1337 QDF_MON_STATUS_EHT_USER_BEAMFORMING_SHIFT); 1338 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->coding << 1339 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1340 1341 /* CRC for matched user block */ 1342 ppdu_info->rx_status.eht_known |= 1343 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN | 1344 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN; 1345 ppdu_info->rx_status.eht_data[4] |= (user_info->crc << 1346 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT); 1347 1348 ppdu_info->rx_status.num_eht_user_info_valid++; 1349 1350 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1351 } 1352 1353 static inline bool hal_rx_is_ofdma(struct hal_soc *hal_soc, 1354 struct hal_rx_ppdu_info *ppdu_info) 1355 { 1356 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 0 && 1357 ppdu_info->u_sig_info.ul_dl == 0) 1358 return true; 1359 1360 return false; 1361 } 1362 1363 static inline bool hal_rx_is_non_ofdma(struct hal_soc *hal_soc, 1364 struct hal_rx_ppdu_info *ppdu_info) 1365 { 1366 uint32_t ppdu_type_comp_mode = 1367 ppdu_info->u_sig_info.ppdu_type_comp_mode; 1368 uint32_t ul_dl = ppdu_info->u_sig_info.ul_dl; 1369 1370 if ((ppdu_type_comp_mode == 1 && ul_dl == 0) || 1371 (ppdu_type_comp_mode == 2 && ul_dl == 0) || 1372 (ppdu_type_comp_mode == 1 && ul_dl == 1)) 1373 return true; 1374 1375 return false; 1376 } 1377 1378 static inline bool hal_rx_is_mu_mimo_user(struct hal_soc *hal_soc, 1379 struct hal_rx_ppdu_info *ppdu_info) 1380 { 1381 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 0 && 1382 ppdu_info->u_sig_info.ul_dl == 2) 1383 return true; 1384 1385 return false; 1386 } 1387 1388 static inline bool 1389 hal_rx_is_frame_type_ndp(struct hal_soc *hal_soc, 1390 struct hal_rx_ppdu_info *ppdu_info) 1391 { 1392 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 1 && 1393 ppdu_info->u_sig_info.eht_sig_mcs == 0 && 1394 ppdu_info->u_sig_info.num_eht_sig_sym == 0) 1395 return true; 1396 1397 return false; 1398 } 1399 1400 static inline uint32_t 1401 hal_rx_parse_eht_sig_ndp(struct hal_soc *hal_soc, void *tlv, 1402 struct hal_rx_ppdu_info *ppdu_info) 1403 { 1404 struct hal_eht_sig_ndp_cmn_eb *eht_sig_ndp = 1405 (struct hal_eht_sig_ndp_cmn_eb *)tlv; 1406 1407 ppdu_info->rx_status.eht_known |= 1408 QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1409 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1410 QDF_MON_STATUS_EHT_NDP_NSS_KNOWN | 1411 QDF_MON_STATUS_EHT_NDP_BEAMFORMED_KNOWN | 1412 QDF_MON_STATUS_EHT_NDP_DISREGARD_KNOWN | 1413 QDF_MON_STATUS_EHT_CRC1_KNOWN | 1414 QDF_MON_STATUS_EHT_TAIL1_KNOWN; 1415 1416 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->spatial_reuse << 1417 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1418 /* 1419 * GI and LTF size are separately indicated in radiotap header 1420 * and hence will be parsed from other TLV 1421 **/ 1422 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->num_ltf_sym << 1423 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1424 ppdu_info->rx_status.eht_data[0] |= (0xF << 1425 QDF_MON_STATUS_EHT_NDP_DISREGARD_SHIFT); 1426 1427 ppdu_info->rx_status.eht_data[4] |= (eht_sig_ndp->nss << 1428 QDF_MON_STATUS_EHT_NDP_NSS_SHIFT); 1429 ppdu_info->rx_status.eht_data[4] |= (eht_sig_ndp->beamformed << 1430 QDF_MON_STATUS_EHT_NDP_BEAMFORMED_SHIFT); 1431 1432 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->crc << 1433 QDF_MON_STATUS_EHT_CRC1_SHIFT); 1434 1435 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1436 } 1437 1438 static inline uint32_t 1439 hal_rx_parse_eht_sig_non_ofdma(struct hal_soc *hal_soc, void *tlv, 1440 struct hal_rx_ppdu_info *ppdu_info) 1441 { 1442 void *user_info = (void *)((uint8_t *)tlv + 4); 1443 1444 hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info); 1445 hal_rx_parse_non_ofdma_users(hal_soc, tlv, ppdu_info); 1446 1447 if (hal_rx_is_mu_mimo_user(hal_soc, ppdu_info)) 1448 hal_rx_parse_eht_sig_mumimo_user_info(hal_soc, user_info, 1449 ppdu_info); 1450 else 1451 hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, user_info, 1452 ppdu_info); 1453 1454 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1455 } 1456 1457 static inline uint32_t 1458 hal_rx_parse_eht_sig_ofdma(struct hal_soc *hal_soc, void *tlv, 1459 struct hal_rx_ppdu_info *ppdu_info) 1460 { 1461 uint64_t *eht_sig_tlv = (uint64_t *)tlv; 1462 void *user_info = (void *)(eht_sig_tlv + 2); 1463 1464 hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info); 1465 hal_rx_parse_ru_allocation(hal_soc, tlv, ppdu_info); 1466 hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, user_info, 1467 ppdu_info); 1468 1469 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1470 } 1471 1472 static inline uint32_t 1473 hal_rx_parse_eht_sig_hdr(struct hal_soc *hal_soc, uint8_t *tlv, 1474 struct hal_rx_ppdu_info *ppdu_info) 1475 { 1476 ppdu_info->rx_status.eht_flags = 1; 1477 1478 if (hal_rx_is_frame_type_ndp(hal_soc, ppdu_info)) 1479 hal_rx_parse_eht_sig_ndp(hal_soc, tlv, ppdu_info); 1480 else if (hal_rx_is_non_ofdma(hal_soc, ppdu_info)) 1481 hal_rx_parse_eht_sig_non_ofdma(hal_soc, tlv, ppdu_info); 1482 else if (hal_rx_is_ofdma(hal_soc, ppdu_info)) 1483 hal_rx_parse_eht_sig_ofdma(hal_soc, tlv, ppdu_info); 1484 1485 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1486 } 1487 1488 #ifdef WLAN_FEATURE_11BE 1489 static inline void 1490 hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info, 1491 struct hal_rx_ppdu_info *ppdu_info) 1492 { 1493 ppdu_info->rx_status.punctured_pattern = cmn_usr_info->puncture_bitmap; 1494 } 1495 #else 1496 static inline void 1497 hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info, 1498 struct hal_rx_ppdu_info *ppdu_info) 1499 { 1500 } 1501 #endif 1502 static inline uint32_t 1503 hal_rx_parse_cmn_usr_info(struct hal_soc *hal_soc, uint8_t *tlv, 1504 struct hal_rx_ppdu_info *ppdu_info) 1505 { 1506 struct phyrx_common_user_info *cmn_usr_info = 1507 (struct phyrx_common_user_info *)tlv; 1508 1509 ppdu_info->rx_status.eht_known |= 1510 QDF_MON_STATUS_EHT_GUARD_INTERVAL_KNOWN | 1511 QDF_MON_STATUS_EHT_LTF_KNOWN; 1512 1513 ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->cp_setting << 1514 QDF_MON_STATUS_EHT_GI_SHIFT); 1515 ppdu_info->rx_status.sgi = cmn_usr_info->cp_setting; 1516 1517 ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->ltf_size << 1518 QDF_MON_STATUS_EHT_LTF_SHIFT); 1519 ppdu_info->rx_status.ltf_size = cmn_usr_info->ltf_size; 1520 1521 hal_rx_parse_punctured_pattern(cmn_usr_info, ppdu_info); 1522 1523 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1524 } 1525 1526 #ifdef WLAN_FEATURE_11BE 1527 static inline void 1528 hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size, 1529 uint32_t *ru_width) 1530 { 1531 uint32_t width; 1532 1533 width = 0; 1534 switch (ru_size) { 1535 case IEEE80211_EHT_RU_26: 1536 width = RU_26; 1537 break; 1538 case IEEE80211_EHT_RU_52: 1539 width = RU_52; 1540 break; 1541 case IEEE80211_EHT_RU_52_26: 1542 width = RU_52_26; 1543 break; 1544 case IEEE80211_EHT_RU_106: 1545 width = RU_106; 1546 break; 1547 case IEEE80211_EHT_RU_106_26: 1548 width = RU_106_26; 1549 break; 1550 case IEEE80211_EHT_RU_242: 1551 width = RU_242; 1552 break; 1553 case IEEE80211_EHT_RU_484: 1554 width = RU_484; 1555 break; 1556 case IEEE80211_EHT_RU_484_242: 1557 width = RU_484_242; 1558 break; 1559 case IEEE80211_EHT_RU_996: 1560 width = RU_996; 1561 break; 1562 case IEEE80211_EHT_RU_996_484: 1563 width = RU_996_484; 1564 break; 1565 case IEEE80211_EHT_RU_996_484_242: 1566 width = RU_996_484_242; 1567 break; 1568 case IEEE80211_EHT_RU_996x2: 1569 width = RU_2X996; 1570 break; 1571 case IEEE80211_EHT_RU_996x2_484: 1572 width = RU_2X996_484; 1573 break; 1574 case IEEE80211_EHT_RU_996x3: 1575 width = RU_3X996; 1576 break; 1577 case IEEE80211_EHT_RU_996x3_484: 1578 width = RU_3X996_484; 1579 break; 1580 case IEEE80211_EHT_RU_996x4: 1581 width = RU_4X996; 1582 break; 1583 default: 1584 hal_err_rl("RU size(%d) to width convert err", ru_size); 1585 break; 1586 } 1587 *ru_width = width; 1588 } 1589 #else 1590 static inline void 1591 hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size, 1592 uint32_t *ru_width) 1593 { 1594 *ru_width = 0; 1595 } 1596 #endif 1597 1598 static inline enum ieee80211_eht_ru_size 1599 hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(struct hal_soc *hal_soc, 1600 uint32_t hal_ru_size) 1601 { 1602 switch (hal_ru_size) { 1603 case HAL_EHT_RU_26: 1604 return IEEE80211_EHT_RU_26; 1605 case HAL_EHT_RU_52: 1606 return IEEE80211_EHT_RU_52; 1607 case HAL_EHT_RU_78: 1608 return IEEE80211_EHT_RU_52_26; 1609 case HAL_EHT_RU_106: 1610 return IEEE80211_EHT_RU_106; 1611 case HAL_EHT_RU_132: 1612 return IEEE80211_EHT_RU_106_26; 1613 case HAL_EHT_RU_242: 1614 return IEEE80211_EHT_RU_242; 1615 case HAL_EHT_RU_484: 1616 return IEEE80211_EHT_RU_484; 1617 case HAL_EHT_RU_726: 1618 return IEEE80211_EHT_RU_484_242; 1619 case HAL_EHT_RU_996: 1620 return IEEE80211_EHT_RU_996; 1621 case HAL_EHT_RU_996x2: 1622 return IEEE80211_EHT_RU_996x2; 1623 case HAL_EHT_RU_996x3: 1624 return IEEE80211_EHT_RU_996x3; 1625 case HAL_EHT_RU_996x4: 1626 return IEEE80211_EHT_RU_996x4; 1627 case HAL_EHT_RU_NONE: 1628 return IEEE80211_EHT_RU_INVALID; 1629 case HAL_EHT_RU_996_484: 1630 return IEEE80211_EHT_RU_996_484; 1631 case HAL_EHT_RU_996x2_484: 1632 return IEEE80211_EHT_RU_996x2_484; 1633 case HAL_EHT_RU_996x3_484: 1634 return IEEE80211_EHT_RU_996x3_484; 1635 case HAL_EHT_RU_996_484_242: 1636 return IEEE80211_EHT_RU_996_484_242; 1637 default: 1638 return IEEE80211_EHT_RU_INVALID; 1639 } 1640 } 1641 1642 #define HAL_SET_RU_PER80(ru_320mhz, ru_per80, ru_idx_per80mhz, num_80mhz) \ 1643 ((ru_320mhz) |= ((uint64_t)(ru_per80) << \ 1644 (((num_80mhz) * NUM_RU_BITS_PER80) + \ 1645 ((ru_idx_per80mhz) * NUM_RU_BITS_PER20)))) 1646 1647 static inline uint32_t 1648 hal_rx_parse_receive_user_info(struct hal_soc *hal_soc, uint8_t *tlv, 1649 struct hal_rx_ppdu_info *ppdu_info, 1650 uint32_t user_id) 1651 { 1652 struct receive_user_info *rx_usr_info = (struct receive_user_info *)tlv; 1653 struct mon_rx_user_status *mon_rx_user_status = NULL; 1654 uint64_t ru_index_320mhz = 0; 1655 uint16_t ru_index_per80mhz; 1656 uint32_t ru_size = 0, num_80mhz_with_ru = 0; 1657 uint32_t ru_index = HAL_EHT_RU_INVALID; 1658 uint32_t rtap_ru_size = IEEE80211_EHT_RU_INVALID; 1659 uint32_t ru_width; 1660 1661 ppdu_info->rx_status.eht_known |= 1662 QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_KNOWN; 1663 ppdu_info->rx_status.eht_data[0] |= 1664 (rx_usr_info->dl_ofdma_content_channel << 1665 QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_SHIFT); 1666 1667 switch (rx_usr_info->reception_type) { 1668 case HAL_RECEPTION_TYPE_SU: 1669 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1670 break; 1671 case HAL_RECEPTION_TYPE_DL_MU_MIMO: 1672 case HAL_RECEPTION_TYPE_UL_MU_MIMO: 1673 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1674 break; 1675 case HAL_RECEPTION_TYPE_DL_MU_OFMA: 1676 case HAL_RECEPTION_TYPE_UL_MU_OFDMA: 1677 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1678 break; 1679 case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO: 1680 case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO: 1681 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA_MIMO; 1682 } 1683 1684 ppdu_info->rx_status.is_stbc = rx_usr_info->stbc; 1685 ppdu_info->rx_status.ldpc = rx_usr_info->ldpc; 1686 ppdu_info->rx_status.dcm = rx_usr_info->sta_dcm; 1687 ppdu_info->rx_status.mcs = rx_usr_info->rate_mcs; 1688 ppdu_info->rx_status.nss = rx_usr_info->nss + 1; 1689 1690 if (user_id < HAL_MAX_UL_MU_USERS) { 1691 mon_rx_user_status = 1692 &ppdu_info->rx_user_status[user_id]; 1693 mon_rx_user_status->mcs = ppdu_info->rx_status.mcs; 1694 mon_rx_user_status->nss = ppdu_info->rx_status.nss; 1695 } 1696 1697 if (!(ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_MIMO || 1698 ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA || 1699 ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA_MIMO)) 1700 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1701 1702 /* RU allocation present only for OFDMA reception */ 1703 if (rx_usr_info->ru_type_80_0 != HAL_EHT_RU_NONE) { 1704 ru_size += rx_usr_info->ru_type_80_0; 1705 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_0; 1706 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_0, 1707 ru_index_per80mhz, 0); 1708 num_80mhz_with_ru++; 1709 } 1710 1711 if (rx_usr_info->ru_type_80_1 != HAL_EHT_RU_NONE) { 1712 ru_size += rx_usr_info->ru_type_80_1; 1713 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_1; 1714 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_1, 1715 ru_index_per80mhz, 1); 1716 num_80mhz_with_ru++; 1717 } 1718 1719 if (rx_usr_info->ru_type_80_2 != HAL_EHT_RU_NONE) { 1720 ru_size += rx_usr_info->ru_type_80_2; 1721 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_2; 1722 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_2, 1723 ru_index_per80mhz, 2); 1724 num_80mhz_with_ru++; 1725 } 1726 1727 if (rx_usr_info->ru_type_80_3 != HAL_EHT_RU_NONE) { 1728 ru_size += rx_usr_info->ru_type_80_3; 1729 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_3; 1730 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_3, 1731 ru_index_per80mhz, 3); 1732 num_80mhz_with_ru++; 1733 } 1734 1735 if (num_80mhz_with_ru > 1) { 1736 /* Calculate the MRU index */ 1737 switch (ru_index_320mhz) { 1738 case HAL_EHT_RU_996_484_0: 1739 case HAL_EHT_RU_996x2_484_0: 1740 case HAL_EHT_RU_996x3_484_0: 1741 ru_index = 0; 1742 break; 1743 case HAL_EHT_RU_996_484_1: 1744 case HAL_EHT_RU_996x2_484_1: 1745 case HAL_EHT_RU_996x3_484_1: 1746 ru_index = 1; 1747 break; 1748 case HAL_EHT_RU_996_484_2: 1749 case HAL_EHT_RU_996x2_484_2: 1750 case HAL_EHT_RU_996x3_484_2: 1751 ru_index = 2; 1752 break; 1753 case HAL_EHT_RU_996_484_3: 1754 case HAL_EHT_RU_996x2_484_3: 1755 case HAL_EHT_RU_996x3_484_3: 1756 ru_index = 3; 1757 break; 1758 case HAL_EHT_RU_996_484_4: 1759 case HAL_EHT_RU_996x2_484_4: 1760 case HAL_EHT_RU_996x3_484_4: 1761 ru_index = 4; 1762 break; 1763 case HAL_EHT_RU_996_484_5: 1764 case HAL_EHT_RU_996x2_484_5: 1765 case HAL_EHT_RU_996x3_484_5: 1766 ru_index = 5; 1767 break; 1768 case HAL_EHT_RU_996_484_6: 1769 case HAL_EHT_RU_996x2_484_6: 1770 case HAL_EHT_RU_996x3_484_6: 1771 ru_index = 6; 1772 break; 1773 case HAL_EHT_RU_996_484_7: 1774 case HAL_EHT_RU_996x2_484_7: 1775 case HAL_EHT_RU_996x3_484_7: 1776 ru_index = 7; 1777 break; 1778 case HAL_EHT_RU_996x2_484_8: 1779 ru_index = 8; 1780 break; 1781 case HAL_EHT_RU_996x2_484_9: 1782 ru_index = 9; 1783 break; 1784 case HAL_EHT_RU_996x2_484_10: 1785 ru_index = 10; 1786 break; 1787 case HAL_EHT_RU_996x2_484_11: 1788 ru_index = 11; 1789 break; 1790 default: 1791 ru_index = HAL_EHT_RU_INVALID; 1792 dp_debug("Invalid RU index"); 1793 qdf_assert(0); 1794 break; 1795 } 1796 ru_size += 4; 1797 } 1798 1799 rtap_ru_size = hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(hal_soc, 1800 ru_size); 1801 if (rtap_ru_size != IEEE80211_EHT_RU_INVALID) { 1802 ppdu_info->rx_status.eht_known |= 1803 QDF_MON_STATUS_EHT_RU_MRU_SIZE_KNOWN; 1804 ppdu_info->rx_status.eht_data[1] |= (rtap_ru_size << 1805 QDF_MON_STATUS_EHT_RU_MRU_SIZE_SHIFT); 1806 } 1807 1808 if (ru_index != HAL_EHT_RU_INVALID) { 1809 ppdu_info->rx_status.eht_known |= 1810 QDF_MON_STATUS_EHT_RU_MRU_INDEX_KNOWN; 1811 ppdu_info->rx_status.eht_data[1] |= (ru_index << 1812 QDF_MON_STATUS_EHT_RU_MRU_INDEX_SHIFT); 1813 } 1814 1815 if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID && 1816 rtap_ru_size != IEEE80211_EHT_RU_INVALID) { 1817 mon_rx_user_status->ofdma_ru_start_index = ru_index; 1818 mon_rx_user_status->ofdma_ru_size = rtap_ru_size; 1819 hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size, &ru_width); 1820 mon_rx_user_status->ofdma_ru_width = ru_width; 1821 mon_rx_user_status->mu_ul_info_valid = 1; 1822 } 1823 1824 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1825 } 1826 1827 #ifdef QCA_MONITOR_2_0_SUPPORT 1828 static inline void 1829 hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info, 1830 void *rx_tlv) 1831 { 1832 ppdu_info->rx_status.mpdu_retry_cnt = 1833 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 1834 RETRIED_MPDU_COUNT); 1835 } 1836 1837 static inline void 1838 hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv, 1839 struct hal_rx_ppdu_info *ppdu_info) 1840 { 1841 struct mon_buffer_addr *addr = (struct mon_buffer_addr *)rx_tlv; 1842 1843 ppdu_info->packet_info.sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) | 1844 (addr->buffer_virt_addr_31_0)); 1845 /* HW DMA length is '-1' of actual DMA length*/ 1846 ppdu_info->packet_info.dma_length = addr->dma_length + 1; 1847 ppdu_info->packet_info.msdu_continuation = addr->msdu_continuation; 1848 ppdu_info->packet_info.truncated = addr->truncated; 1849 1850 } 1851 #else 1852 static inline void 1853 hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info, 1854 void *rx_tlv) 1855 { 1856 ppdu_info->rx_status.mpdu_retry_cnt = 0; 1857 } 1858 static inline void 1859 hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv, 1860 struct hal_rx_ppdu_info *ppdu_info) 1861 { 1862 } 1863 #endif 1864 1865 /** 1866 * hal_rx_status_get_tlv_info() - process receive info TLV 1867 * @rx_tlv_hdr: pointer to TLV header 1868 * @ppdu_info: pointer to ppdu_info 1869 * 1870 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 1871 */ 1872 static inline uint32_t 1873 hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo, 1874 hal_soc_handle_t hal_soc_hdl, 1875 qdf_nbuf_t nbuf) 1876 { 1877 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1878 uint32_t tlv_tag, user_id, tlv_len, value; 1879 uint8_t group_id = 0; 1880 uint8_t he_dcm = 0; 1881 uint8_t he_stbc = 0; 1882 uint16_t he_gi = 0; 1883 uint16_t he_ltf = 0; 1884 void *rx_tlv; 1885 struct mon_rx_user_status *mon_rx_user_status; 1886 struct hal_rx_ppdu_info *ppdu_info = 1887 (struct hal_rx_ppdu_info *)ppduinfo; 1888 1889 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 1890 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 1891 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 1892 1893 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 1894 1895 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1896 rx_tlv, tlv_len); 1897 1898 ppdu_info->user_id = user_id; 1899 switch (tlv_tag) { 1900 case WIFIRX_PPDU_START_E: 1901 { 1902 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 1903 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, PHY_PPDU_ID))) 1904 hal_err("Matching ppdu_id(%u) detected", 1905 ppdu_info->com_info.last_ppdu_id); 1906 1907 /* Reset ppdu_info before processing the ppdu */ 1908 qdf_mem_zero(ppdu_info, 1909 sizeof(struct hal_rx_ppdu_info)); 1910 1911 ppdu_info->com_info.last_ppdu_id = 1912 ppdu_info->com_info.ppdu_id = 1913 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 1914 PHY_PPDU_ID); 1915 1916 /* channel number is set in PHY meta data */ 1917 ppdu_info->rx_status.chan_num = 1918 (HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 1919 SW_PHY_META_DATA) & 0x0000FFFF); 1920 ppdu_info->rx_status.chan_freq = 1921 (HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 1922 SW_PHY_META_DATA) & 0xFFFF0000) >> 16; 1923 if (ppdu_info->rx_status.chan_num && 1924 ppdu_info->rx_status.chan_freq) { 1925 ppdu_info->rx_status.chan_freq = 1926 hal_rx_radiotap_num_to_freq( 1927 ppdu_info->rx_status.chan_num, 1928 ppdu_info->rx_status.chan_freq); 1929 } 1930 1931 ppdu_info->com_info.ppdu_timestamp = 1932 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 1933 PPDU_START_TIMESTAMP_31_0); 1934 ppdu_info->rx_status.ppdu_timestamp = 1935 ppdu_info->com_info.ppdu_timestamp; 1936 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 1937 1938 break; 1939 } 1940 1941 case WIFIRX_PPDU_START_USER_INFO_E: 1942 hal_rx_parse_receive_user_info(hal, rx_tlv, ppdu_info, user_id); 1943 break; 1944 1945 case WIFIRX_PPDU_END_E: 1946 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1947 "[%s][%d] ppdu_end_e len=%d", 1948 __func__, __LINE__, tlv_len); 1949 /* This is followed by sub-TLVs of PPDU_END */ 1950 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 1951 break; 1952 1953 case WIFIPHYRX_LOCATION_E: 1954 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 1955 break; 1956 1957 case WIFIRXPCU_PPDU_END_INFO_E: 1958 ppdu_info->rx_status.rx_antenna = 1959 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, RX_ANTENNA); 1960 ppdu_info->rx_status.tsft = 1961 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, 1962 WB_TIMESTAMP_UPPER_32); 1963 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 1964 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, 1965 WB_TIMESTAMP_LOWER_32); 1966 ppdu_info->rx_status.duration = 1967 HAL_RX_GET_64(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 1968 RX_PPDU_DURATION); 1969 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 1970 break; 1971 1972 /* 1973 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 1974 * for MU, based on num users we see this tlv that many times. 1975 */ 1976 case WIFIRX_PPDU_END_USER_STATS_E: 1977 { 1978 unsigned long tid = 0; 1979 uint16_t seq = 0; 1980 1981 ppdu_info->rx_status.ast_index = 1982 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 1983 AST_INDEX); 1984 1985 tid = HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 1986 RECEIVED_QOS_DATA_TID_BITMAP); 1987 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, 1988 sizeof(tid) * 8); 1989 1990 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 1991 ppdu_info->rx_status.tid = HAL_TID_INVALID; 1992 1993 ppdu_info->rx_status.tcp_msdu_count = 1994 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 1995 TCP_MSDU_COUNT) + 1996 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 1997 TCP_ACK_MSDU_COUNT); 1998 ppdu_info->rx_status.udp_msdu_count = 1999 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2000 UDP_MSDU_COUNT); 2001 ppdu_info->rx_status.other_msdu_count = 2002 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2003 OTHER_MSDU_COUNT); 2004 hal_rx_status_get_mpdu_retry_cnt(ppdu_info, rx_tlv); 2005 2006 if (ppdu_info->sw_frame_group_id 2007 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 2008 ppdu_info->rx_status.frame_control_info_valid = 2009 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2010 FRAME_CONTROL_INFO_VALID); 2011 2012 if (ppdu_info->rx_status.frame_control_info_valid) 2013 ppdu_info->rx_status.frame_control = 2014 HAL_RX_GET_64(rx_tlv, 2015 RX_PPDU_END_USER_STATS, 2016 FRAME_CONTROL_FIELD); 2017 2018 hal_get_qos_control(rx_tlv, ppdu_info); 2019 } 2020 2021 ppdu_info->rx_status.data_sequence_control_info_valid = 2022 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2023 DATA_SEQUENCE_CONTROL_INFO_VALID); 2024 2025 seq = HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2026 FIRST_DATA_SEQ_CTRL); 2027 if (ppdu_info->rx_status.data_sequence_control_info_valid) 2028 ppdu_info->rx_status.first_data_seq_ctrl = seq; 2029 2030 ppdu_info->rx_status.preamble_type = 2031 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2032 HT_CONTROL_FIELD_PKT_TYPE); 2033 switch (ppdu_info->rx_status.preamble_type) { 2034 case HAL_RX_PKT_TYPE_11N: 2035 ppdu_info->rx_status.ht_flags = 1; 2036 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 2037 break; 2038 case HAL_RX_PKT_TYPE_11AC: 2039 ppdu_info->rx_status.vht_flags = 1; 2040 break; 2041 case HAL_RX_PKT_TYPE_11AX: 2042 ppdu_info->rx_status.he_flags = 1; 2043 break; 2044 default: 2045 break; 2046 } 2047 2048 ppdu_info->com_info.mpdu_cnt_fcs_ok = 2049 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2050 MPDU_CNT_FCS_OK); 2051 ppdu_info->com_info.mpdu_cnt_fcs_err = 2052 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2053 MPDU_CNT_FCS_ERR); 2054 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 2055 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 2056 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 2057 else 2058 ppdu_info->rx_status.rs_flags &= 2059 (~IEEE80211_AMPDU_FLAG); 2060 2061 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 2062 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2063 FCS_OK_BITMAP_31_0); 2064 2065 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 2066 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2067 FCS_OK_BITMAP_63_32); 2068 2069 if (user_id < HAL_MAX_UL_MU_USERS) { 2070 mon_rx_user_status = 2071 &ppdu_info->rx_user_status[user_id]; 2072 2073 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 2074 2075 ppdu_info->com_info.num_users++; 2076 2077 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 2078 user_id, 2079 mon_rx_user_status); 2080 } 2081 break; 2082 } 2083 2084 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 2085 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 2086 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2087 FCS_OK_BITMAP_95_64); 2088 2089 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 2090 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2091 FCS_OK_BITMAP_127_96); 2092 2093 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 2094 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2095 FCS_OK_BITMAP_159_128); 2096 2097 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 2098 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2099 FCS_OK_BITMAP_191_160); 2100 2101 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 2102 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2103 FCS_OK_BITMAP_223_192); 2104 2105 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 2106 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2107 FCS_OK_BITMAP_255_224); 2108 break; 2109 2110 case WIFIRX_PPDU_END_STATUS_DONE_E: 2111 return HAL_TLV_STATUS_PPDU_DONE; 2112 2113 case WIFIPHYRX_PKT_END_E: 2114 break; 2115 2116 case WIFIDUMMY_E: 2117 return HAL_TLV_STATUS_BUF_DONE; 2118 2119 case WIFIPHYRX_HT_SIG_E: 2120 { 2121 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 2122 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 2123 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 2124 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO, FEC_CODING); 2125 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2126 1 : 0; 2127 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 2128 HT_SIG_INFO, MCS); 2129 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 2130 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 2131 HT_SIG_INFO, CBW); 2132 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 2133 HT_SIG_INFO, SHORT_GI); 2134 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2135 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 2136 HT_SIG_SU_NSS_SHIFT) + 1; 2137 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 2138 break; 2139 } 2140 2141 case WIFIPHYRX_L_SIG_B_E: 2142 { 2143 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 2144 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 2145 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 2146 2147 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO, RATE); 2148 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 2149 switch (value) { 2150 case 1: 2151 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 2152 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 2153 break; 2154 case 2: 2155 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 2156 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 2157 break; 2158 case 3: 2159 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 2160 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 2161 break; 2162 case 4: 2163 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 2164 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 2165 break; 2166 case 5: 2167 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 2168 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 2169 break; 2170 case 6: 2171 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 2172 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 2173 break; 2174 case 7: 2175 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 2176 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 2177 break; 2178 default: 2179 break; 2180 } 2181 ppdu_info->rx_status.cck_flag = 1; 2182 break; 2183 } 2184 2185 case WIFIPHYRX_L_SIG_A_E: 2186 { 2187 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 2188 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 2189 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 2190 2191 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO, RATE); 2192 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 2193 switch (value) { 2194 case 8: 2195 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 2196 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 2197 break; 2198 case 9: 2199 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 2200 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 2201 break; 2202 case 10: 2203 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 2204 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 2205 break; 2206 case 11: 2207 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 2208 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 2209 break; 2210 case 12: 2211 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 2212 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 2213 break; 2214 case 13: 2215 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 2216 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 2217 break; 2218 case 14: 2219 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 2220 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 2221 break; 2222 case 15: 2223 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 2224 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 2225 break; 2226 default: 2227 break; 2228 } 2229 ppdu_info->rx_status.ofdm_flag = 1; 2230 break; 2231 } 2232 2233 case WIFIPHYRX_VHT_SIG_A_E: 2234 { 2235 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 2236 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 2237 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 2238 2239 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, 2240 SU_MU_CODING); 2241 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2242 1 : 0; 2243 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, GROUP_ID); 2244 ppdu_info->rx_status.vht_flag_values5 = group_id; 2245 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 2246 VHT_SIG_A_INFO, MCS); 2247 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 2248 VHT_SIG_A_INFO, 2249 GI_SETTING); 2250 2251 switch (hal->target_type) { 2252 case TARGET_TYPE_QCA8074: 2253 case TARGET_TYPE_QCA8074V2: 2254 case TARGET_TYPE_QCA6018: 2255 case TARGET_TYPE_QCA5018: 2256 case TARGET_TYPE_QCN9000: 2257 case TARGET_TYPE_QCN6122: 2258 #ifdef QCA_WIFI_QCA6390 2259 case TARGET_TYPE_QCA6390: 2260 #endif 2261 ppdu_info->rx_status.is_stbc = 2262 HAL_RX_GET(vht_sig_a_info, 2263 VHT_SIG_A_INFO, STBC); 2264 value = HAL_RX_GET(vht_sig_a_info, 2265 VHT_SIG_A_INFO, N_STS); 2266 value = value & VHT_SIG_SU_NSS_MASK; 2267 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2268 value = ((value + 1) >> 1) - 1; 2269 ppdu_info->rx_status.nss = 2270 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2271 2272 break; 2273 case TARGET_TYPE_QCA6290: 2274 #if !defined(QCA_WIFI_QCA6290_11AX) 2275 ppdu_info->rx_status.is_stbc = 2276 HAL_RX_GET(vht_sig_a_info, 2277 VHT_SIG_A_INFO, STBC); 2278 value = HAL_RX_GET(vht_sig_a_info, 2279 VHT_SIG_A_INFO, N_STS); 2280 value = value & VHT_SIG_SU_NSS_MASK; 2281 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2282 value = ((value + 1) >> 1) - 1; 2283 ppdu_info->rx_status.nss = 2284 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2285 #else 2286 ppdu_info->rx_status.nss = 0; 2287 #endif 2288 break; 2289 case TARGET_TYPE_QCA6490: 2290 case TARGET_TYPE_QCA6750: 2291 case TARGET_TYPE_KIWI: 2292 case TARGET_TYPE_MANGO: 2293 ppdu_info->rx_status.nss = 0; 2294 break; 2295 default: 2296 break; 2297 } 2298 ppdu_info->rx_status.vht_flag_values3[0] = 2299 (((ppdu_info->rx_status.mcs) << 4) 2300 | ppdu_info->rx_status.nss); 2301 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 2302 VHT_SIG_A_INFO, BANDWIDTH); 2303 ppdu_info->rx_status.vht_flag_values2 = 2304 ppdu_info->rx_status.bw; 2305 ppdu_info->rx_status.vht_flag_values4 = 2306 HAL_RX_GET(vht_sig_a_info, 2307 VHT_SIG_A_INFO, SU_MU_CODING); 2308 2309 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 2310 VHT_SIG_A_INFO, 2311 BEAMFORMED); 2312 if (group_id == 0 || group_id == 63) 2313 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2314 else 2315 ppdu_info->rx_status.reception_type = 2316 HAL_RX_TYPE_MU_MIMO; 2317 2318 break; 2319 } 2320 case WIFIPHYRX_HE_SIG_A_SU_E: 2321 { 2322 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 2323 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 2324 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 2325 ppdu_info->rx_status.he_flags = 1; 2326 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2327 FORMAT_INDICATION); 2328 if (value == 0) { 2329 ppdu_info->rx_status.he_data1 = 2330 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 2331 } else { 2332 ppdu_info->rx_status.he_data1 = 2333 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 2334 } 2335 2336 /* data1 */ 2337 ppdu_info->rx_status.he_data1 |= 2338 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 2339 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 2340 QDF_MON_STATUS_HE_DL_UL_KNOWN | 2341 QDF_MON_STATUS_HE_MCS_KNOWN | 2342 QDF_MON_STATUS_HE_DCM_KNOWN | 2343 QDF_MON_STATUS_HE_CODING_KNOWN | 2344 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 2345 QDF_MON_STATUS_HE_STBC_KNOWN | 2346 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 2347 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 2348 2349 /* data2 */ 2350 ppdu_info->rx_status.he_data2 = 2351 QDF_MON_STATUS_HE_GI_KNOWN; 2352 ppdu_info->rx_status.he_data2 |= 2353 QDF_MON_STATUS_TXBF_KNOWN | 2354 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 2355 QDF_MON_STATUS_TXOP_KNOWN | 2356 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 2357 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 2358 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 2359 2360 /* data3 */ 2361 value = HAL_RX_GET(he_sig_a_su_info, 2362 HE_SIG_A_SU_INFO, BSS_COLOR_ID); 2363 ppdu_info->rx_status.he_data3 = value; 2364 value = HAL_RX_GET(he_sig_a_su_info, 2365 HE_SIG_A_SU_INFO, BEAM_CHANGE); 2366 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 2367 ppdu_info->rx_status.he_data3 |= value; 2368 value = HAL_RX_GET(he_sig_a_su_info, 2369 HE_SIG_A_SU_INFO, DL_UL_FLAG); 2370 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 2371 ppdu_info->rx_status.he_data3 |= value; 2372 2373 value = HAL_RX_GET(he_sig_a_su_info, 2374 HE_SIG_A_SU_INFO, TRANSMIT_MCS); 2375 ppdu_info->rx_status.mcs = value; 2376 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2377 ppdu_info->rx_status.he_data3 |= value; 2378 2379 value = HAL_RX_GET(he_sig_a_su_info, 2380 HE_SIG_A_SU_INFO, DCM); 2381 he_dcm = value; 2382 value = value << QDF_MON_STATUS_DCM_SHIFT; 2383 ppdu_info->rx_status.he_data3 |= value; 2384 value = HAL_RX_GET(he_sig_a_su_info, 2385 HE_SIG_A_SU_INFO, CODING); 2386 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2387 1 : 0; 2388 value = value << QDF_MON_STATUS_CODING_SHIFT; 2389 ppdu_info->rx_status.he_data3 |= value; 2390 value = HAL_RX_GET(he_sig_a_su_info, 2391 HE_SIG_A_SU_INFO, 2392 LDPC_EXTRA_SYMBOL); 2393 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 2394 ppdu_info->rx_status.he_data3 |= value; 2395 value = HAL_RX_GET(he_sig_a_su_info, 2396 HE_SIG_A_SU_INFO, STBC); 2397 he_stbc = value; 2398 value = value << QDF_MON_STATUS_STBC_SHIFT; 2399 ppdu_info->rx_status.he_data3 |= value; 2400 2401 /* data4 */ 2402 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2403 SPATIAL_REUSE); 2404 ppdu_info->rx_status.he_data4 = value; 2405 2406 /* data5 */ 2407 value = HAL_RX_GET(he_sig_a_su_info, 2408 HE_SIG_A_SU_INFO, TRANSMIT_BW); 2409 ppdu_info->rx_status.he_data5 = value; 2410 ppdu_info->rx_status.bw = value; 2411 value = HAL_RX_GET(he_sig_a_su_info, 2412 HE_SIG_A_SU_INFO, CP_LTF_SIZE); 2413 switch (value) { 2414 case 0: 2415 he_gi = HE_GI_0_8; 2416 he_ltf = HE_LTF_1_X; 2417 break; 2418 case 1: 2419 he_gi = HE_GI_0_8; 2420 he_ltf = HE_LTF_2_X; 2421 break; 2422 case 2: 2423 he_gi = HE_GI_1_6; 2424 he_ltf = HE_LTF_2_X; 2425 break; 2426 case 3: 2427 if (he_dcm && he_stbc) { 2428 he_gi = HE_GI_0_8; 2429 he_ltf = HE_LTF_4_X; 2430 } else { 2431 he_gi = HE_GI_3_2; 2432 he_ltf = HE_LTF_4_X; 2433 } 2434 break; 2435 } 2436 ppdu_info->rx_status.sgi = he_gi; 2437 ppdu_info->rx_status.ltf_size = he_ltf; 2438 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 2439 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 2440 ppdu_info->rx_status.he_data5 |= value; 2441 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 2442 ppdu_info->rx_status.he_data5 |= value; 2443 2444 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 2445 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 2446 ppdu_info->rx_status.he_data5 |= value; 2447 2448 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2449 PACKET_EXTENSION_A_FACTOR); 2450 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 2451 ppdu_info->rx_status.he_data5 |= value; 2452 2453 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, TXBF); 2454 value = value << QDF_MON_STATUS_TXBF_SHIFT; 2455 ppdu_info->rx_status.he_data5 |= value; 2456 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2457 PACKET_EXTENSION_PE_DISAMBIGUITY); 2458 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 2459 ppdu_info->rx_status.he_data5 |= value; 2460 2461 /* data6 */ 2462 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 2463 value++; 2464 ppdu_info->rx_status.nss = value; 2465 ppdu_info->rx_status.he_data6 = value; 2466 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2467 DOPPLER_INDICATION); 2468 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 2469 ppdu_info->rx_status.he_data6 |= value; 2470 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2471 TXOP_DURATION); 2472 value = value << QDF_MON_STATUS_TXOP_SHIFT; 2473 ppdu_info->rx_status.he_data6 |= value; 2474 2475 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 2476 HE_SIG_A_SU_INFO, 2477 TXBF); 2478 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2479 break; 2480 } 2481 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 2482 { 2483 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 2484 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 2485 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 2486 2487 ppdu_info->rx_status.he_mu_flags = 1; 2488 2489 /* HE Flags */ 2490 /*data1*/ 2491 ppdu_info->rx_status.he_data1 = 2492 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 2493 ppdu_info->rx_status.he_data1 |= 2494 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 2495 QDF_MON_STATUS_HE_DL_UL_KNOWN | 2496 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 2497 QDF_MON_STATUS_HE_STBC_KNOWN | 2498 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 2499 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 2500 2501 /* data2 */ 2502 ppdu_info->rx_status.he_data2 = 2503 QDF_MON_STATUS_HE_GI_KNOWN; 2504 ppdu_info->rx_status.he_data2 |= 2505 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 2506 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 2507 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 2508 QDF_MON_STATUS_TXOP_KNOWN | 2509 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 2510 2511 /*data3*/ 2512 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2513 HE_SIG_A_MU_DL_INFO, BSS_COLOR_ID); 2514 ppdu_info->rx_status.he_data3 = value; 2515 2516 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2517 HE_SIG_A_MU_DL_INFO, DL_UL_FLAG); 2518 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 2519 ppdu_info->rx_status.he_data3 |= value; 2520 2521 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2522 HE_SIG_A_MU_DL_INFO, 2523 LDPC_EXTRA_SYMBOL); 2524 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 2525 ppdu_info->rx_status.he_data3 |= value; 2526 2527 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2528 HE_SIG_A_MU_DL_INFO, STBC); 2529 he_stbc = value; 2530 value = value << QDF_MON_STATUS_STBC_SHIFT; 2531 ppdu_info->rx_status.he_data3 |= value; 2532 2533 /*data4*/ 2534 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2535 SPATIAL_REUSE); 2536 ppdu_info->rx_status.he_data4 = value; 2537 2538 /*data5*/ 2539 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2540 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 2541 ppdu_info->rx_status.he_data5 = value; 2542 ppdu_info->rx_status.bw = value; 2543 2544 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2545 HE_SIG_A_MU_DL_INFO, CP_LTF_SIZE); 2546 switch (value) { 2547 case 0: 2548 he_gi = HE_GI_0_8; 2549 he_ltf = HE_LTF_4_X; 2550 break; 2551 case 1: 2552 he_gi = HE_GI_0_8; 2553 he_ltf = HE_LTF_2_X; 2554 break; 2555 case 2: 2556 he_gi = HE_GI_1_6; 2557 he_ltf = HE_LTF_2_X; 2558 break; 2559 case 3: 2560 he_gi = HE_GI_3_2; 2561 he_ltf = HE_LTF_4_X; 2562 break; 2563 } 2564 ppdu_info->rx_status.sgi = he_gi; 2565 ppdu_info->rx_status.ltf_size = he_ltf; 2566 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 2567 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 2568 ppdu_info->rx_status.he_data5 |= value; 2569 2570 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 2571 ppdu_info->rx_status.he_data5 |= value; 2572 2573 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2574 HE_SIG_A_MU_DL_INFO, NUM_LTF_SYMBOLS); 2575 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 2576 ppdu_info->rx_status.he_data5 |= value; 2577 2578 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2579 PACKET_EXTENSION_A_FACTOR); 2580 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 2581 ppdu_info->rx_status.he_data5 |= value; 2582 2583 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2584 PACKET_EXTENSION_PE_DISAMBIGUITY); 2585 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 2586 ppdu_info->rx_status.he_data5 |= value; 2587 2588 /*data6*/ 2589 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2590 DOPPLER_INDICATION); 2591 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 2592 ppdu_info->rx_status.he_data6 |= value; 2593 2594 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2595 TXOP_DURATION); 2596 value = value << QDF_MON_STATUS_TXOP_SHIFT; 2597 ppdu_info->rx_status.he_data6 |= value; 2598 2599 /* HE-MU Flags */ 2600 /* HE-MU-flags1 */ 2601 ppdu_info->rx_status.he_flags1 = 2602 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 2603 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 2604 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 2605 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 2606 QDF_MON_STATUS_RU_0_KNOWN; 2607 2608 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2609 HE_SIG_A_MU_DL_INFO, MCS_OF_SIG_B); 2610 ppdu_info->rx_status.he_flags1 |= value; 2611 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2612 HE_SIG_A_MU_DL_INFO, DCM_OF_SIG_B); 2613 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 2614 ppdu_info->rx_status.he_flags1 |= value; 2615 2616 /* HE-MU-flags2 */ 2617 ppdu_info->rx_status.he_flags2 = 2618 QDF_MON_STATUS_BW_KNOWN; 2619 2620 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2621 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 2622 ppdu_info->rx_status.he_flags2 |= value; 2623 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2624 HE_SIG_A_MU_DL_INFO, COMP_MODE_SIG_B); 2625 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 2626 ppdu_info->rx_status.he_flags2 |= value; 2627 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2628 HE_SIG_A_MU_DL_INFO, NUM_SIG_B_SYMBOLS); 2629 value = value - 1; 2630 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 2631 ppdu_info->rx_status.he_flags2 |= value; 2632 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 2633 break; 2634 } 2635 case WIFIPHYRX_HE_SIG_B1_MU_E: 2636 { 2637 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 2638 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 2639 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 2640 2641 ppdu_info->rx_status.he_sig_b_common_known |= 2642 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 2643 /* TODO: Check on the availability of other fields in 2644 * sig_b_common 2645 */ 2646 2647 value = HAL_RX_GET(he_sig_b1_mu_info, 2648 HE_SIG_B1_MU_INFO, RU_ALLOCATION); 2649 ppdu_info->rx_status.he_RU[0] = value; 2650 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 2651 break; 2652 } 2653 case WIFIPHYRX_HE_SIG_B2_MU_E: 2654 { 2655 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 2656 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 2657 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 2658 /* 2659 * Not all "HE" fields can be updated from 2660 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 2661 * to populate rest of the "HE" fields for MU scenarios. 2662 */ 2663 2664 /* HE-data1 */ 2665 ppdu_info->rx_status.he_data1 |= 2666 QDF_MON_STATUS_HE_MCS_KNOWN | 2667 QDF_MON_STATUS_HE_CODING_KNOWN; 2668 2669 /* HE-data2 */ 2670 2671 /* HE-data3 */ 2672 value = HAL_RX_GET(he_sig_b2_mu_info, 2673 HE_SIG_B2_MU_INFO, STA_MCS); 2674 ppdu_info->rx_status.mcs = value; 2675 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2676 ppdu_info->rx_status.he_data3 |= value; 2677 2678 value = HAL_RX_GET(he_sig_b2_mu_info, 2679 HE_SIG_B2_MU_INFO, STA_CODING); 2680 value = value << QDF_MON_STATUS_CODING_SHIFT; 2681 ppdu_info->rx_status.he_data3 |= value; 2682 2683 /* HE-data4 */ 2684 value = HAL_RX_GET(he_sig_b2_mu_info, 2685 HE_SIG_B2_MU_INFO, STA_ID); 2686 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 2687 ppdu_info->rx_status.he_data4 |= value; 2688 2689 /* HE-data5 */ 2690 2691 /* HE-data6 */ 2692 value = HAL_RX_GET(he_sig_b2_mu_info, 2693 HE_SIG_B2_MU_INFO, NSTS); 2694 /* value n indicates n+1 spatial streams */ 2695 value++; 2696 ppdu_info->rx_status.nss = value; 2697 ppdu_info->rx_status.he_data6 |= value; 2698 2699 break; 2700 } 2701 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 2702 { 2703 uint8_t *he_sig_b2_ofdma_info = 2704 (uint8_t *)rx_tlv + 2705 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 2706 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 2707 2708 /* 2709 * Not all "HE" fields can be updated from 2710 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 2711 * to populate rest of "HE" fields for MU OFDMA scenarios. 2712 */ 2713 2714 /* HE-data1 */ 2715 ppdu_info->rx_status.he_data1 |= 2716 QDF_MON_STATUS_HE_MCS_KNOWN | 2717 QDF_MON_STATUS_HE_DCM_KNOWN | 2718 QDF_MON_STATUS_HE_CODING_KNOWN; 2719 2720 /* HE-data2 */ 2721 ppdu_info->rx_status.he_data2 |= 2722 QDF_MON_STATUS_TXBF_KNOWN; 2723 2724 /* HE-data3 */ 2725 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2726 HE_SIG_B2_OFDMA_INFO, STA_MCS); 2727 ppdu_info->rx_status.mcs = value; 2728 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2729 ppdu_info->rx_status.he_data3 |= value; 2730 2731 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2732 HE_SIG_B2_OFDMA_INFO, STA_DCM); 2733 he_dcm = value; 2734 value = value << QDF_MON_STATUS_DCM_SHIFT; 2735 ppdu_info->rx_status.he_data3 |= value; 2736 2737 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2738 HE_SIG_B2_OFDMA_INFO, STA_CODING); 2739 value = value << QDF_MON_STATUS_CODING_SHIFT; 2740 ppdu_info->rx_status.he_data3 |= value; 2741 2742 /* HE-data4 */ 2743 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2744 HE_SIG_B2_OFDMA_INFO, STA_ID); 2745 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 2746 ppdu_info->rx_status.he_data4 |= value; 2747 2748 /* HE-data5 */ 2749 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2750 HE_SIG_B2_OFDMA_INFO, TXBF); 2751 value = value << QDF_MON_STATUS_TXBF_SHIFT; 2752 ppdu_info->rx_status.he_data5 |= value; 2753 2754 /* HE-data6 */ 2755 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2756 HE_SIG_B2_OFDMA_INFO, NSTS); 2757 /* value n indicates n+1 spatial streams */ 2758 value++; 2759 ppdu_info->rx_status.nss = value; 2760 ppdu_info->rx_status.he_data6 |= value; 2761 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 2762 break; 2763 } 2764 case WIFIPHYRX_RSSI_LEGACY_E: 2765 { 2766 uint8_t reception_type; 2767 int8_t rssi_value; 2768 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 2769 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 2770 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 2771 2772 ppdu_info->rx_status.rssi_comb = 2773 HAL_RX_GET_64(rx_tlv, 2774 PHYRX_RSSI_LEGACY, RSSI_COMB); 2775 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 2776 ppdu_info->rx_status.he_re = 0; 2777 2778 reception_type = HAL_RX_GET_64(rx_tlv, 2779 PHYRX_RSSI_LEGACY, 2780 RECEPTION_TYPE); 2781 switch (reception_type) { 2782 case QDF_RECEPTION_TYPE_ULOFMDA: 2783 ppdu_info->rx_status.ulofdma_flag = 1; 2784 ppdu_info->rx_status.he_data1 = 2785 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 2786 break; 2787 case QDF_RECEPTION_TYPE_ULMIMO: 2788 ppdu_info->rx_status.he_data1 = 2789 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 2790 break; 2791 default: 2792 break; 2793 } 2794 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 2795 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2796 RECEIVE_RSSI_INFO, 2797 RSSI_PRI20_CHAIN0); 2798 ppdu_info->rx_status.rssi[0] = rssi_value; 2799 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2800 "RSSI_PRI20_CHAIN0: %d\n", rssi_value); 2801 2802 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2803 RECEIVE_RSSI_INFO, 2804 RSSI_PRI20_CHAIN1); 2805 ppdu_info->rx_status.rssi[1] = rssi_value; 2806 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2807 "RSSI_PRI20_CHAIN1: %d\n", rssi_value); 2808 2809 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2810 RECEIVE_RSSI_INFO, 2811 RSSI_PRI20_CHAIN2); 2812 ppdu_info->rx_status.rssi[2] = rssi_value; 2813 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2814 "RSSI_PRI20_CHAIN2: %d\n", rssi_value); 2815 2816 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2817 RECEIVE_RSSI_INFO, 2818 RSSI_PRI20_CHAIN3); 2819 ppdu_info->rx_status.rssi[3] = rssi_value; 2820 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2821 "RSSI_PRI20_CHAIN3: %d\n", rssi_value); 2822 2823 #ifdef DP_BE_NOTYET_WAR 2824 // TODO - this is not preset for kiwi 2825 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2826 RECEIVE_RSSI_INFO, 2827 RSSI_PRI20_CHAIN4); 2828 ppdu_info->rx_status.rssi[4] = rssi_value; 2829 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2830 "RSSI_PRI20_CHAIN4: %d\n", rssi_value); 2831 2832 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2833 RECEIVE_RSSI_INFO, 2834 RSSI_PRI20_CHAIN5); 2835 ppdu_info->rx_status.rssi[5] = rssi_value; 2836 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2837 "RSSI_PRI20_CHAIN5: %d\n", rssi_value); 2838 2839 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2840 RECEIVE_RSSI_INFO, 2841 RSSI_PRI20_CHAIN6); 2842 ppdu_info->rx_status.rssi[6] = rssi_value; 2843 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2844 "RSSI_PRI20_CHAIN6: %d\n", rssi_value); 2845 2846 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2847 RECEIVE_RSSI_INFO, 2848 RSSI_PRI20_CHAIN7); 2849 ppdu_info->rx_status.rssi[7] = rssi_value; 2850 #endif 2851 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2852 "RSSI_PRI20_CHAIN7: %d\n", rssi_value); 2853 break; 2854 } 2855 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 2856 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 2857 ppdu_info); 2858 break; 2859 case WIFIPHYRX_GENERIC_U_SIG_E: 2860 hal_rx_parse_u_sig_hdr(hal, rx_tlv, ppdu_info); 2861 break; 2862 case WIFIPHYRX_COMMON_USER_INFO_E: 2863 hal_rx_parse_cmn_usr_info(hal, rx_tlv, ppdu_info); 2864 break; 2865 case WIFIRX_HEADER_E: 2866 { 2867 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 2868 2869 if (ppdu_info->fcs_ok_cnt >= 2870 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 2871 hal_err("Number of MPDUs(%d) per status buff exceeded", 2872 ppdu_info->fcs_ok_cnt); 2873 break; 2874 } 2875 2876 /* Update first_msdu_payload for every mpdu and increment 2877 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 2878 */ 2879 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 2880 rx_tlv; 2881 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 2882 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 2883 ppdu_info->msdu_info.payload_len = tlv_len; 2884 ppdu_info->user_id = user_id; 2885 ppdu_info->hdr_len = tlv_len; 2886 ppdu_info->data = rx_tlv; 2887 ppdu_info->data += 4; 2888 2889 /* for every RX_HEADER TLV increment mpdu_cnt */ 2890 com_info->mpdu_cnt++; 2891 return HAL_TLV_STATUS_HEADER; 2892 } 2893 case WIFIRX_MPDU_START_E: 2894 { 2895 hal_rx_mon_mpdu_start_t *rx_mpdu_start = rx_tlv; 2896 uint32_t ppdu_id = rx_mpdu_start->rx_mpdu_info_details.phy_ppdu_id; 2897 uint8_t filter_category = 0; 2898 2899 ppdu_info->nac_info.fc_valid = 2900 rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid; 2901 2902 ppdu_info->nac_info.to_ds_flag = 2903 rx_mpdu_start->rx_mpdu_info_details.to_ds; 2904 2905 ppdu_info->nac_info.frame_control = 2906 rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field; 2907 2908 ppdu_info->sw_frame_group_id = 2909 rx_mpdu_start->rx_mpdu_info_details.sw_frame_group_id; 2910 2911 ppdu_info->rx_user_status[user_id].sw_peer_id = 2912 rx_mpdu_start->rx_mpdu_info_details.sw_peer_id; 2913 2914 if (ppdu_info->sw_frame_group_id == 2915 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 2916 ppdu_info->rx_status.frame_control_info_valid = 2917 ppdu_info->nac_info.fc_valid; 2918 ppdu_info->rx_status.frame_control = 2919 ppdu_info->nac_info.frame_control; 2920 } 2921 2922 hal_get_mac_addr1(rx_mpdu_start, 2923 ppdu_info); 2924 2925 ppdu_info->nac_info.mac_addr2_valid = 2926 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_valid; 2927 2928 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 2929 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_15_0; 2930 2931 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 2932 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_47_16; 2933 2934 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 2935 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 2936 ppdu_info->rx_status.ppdu_len = 2937 rx_mpdu_start->rx_mpdu_info_details.mpdu_length; 2938 } else { 2939 ppdu_info->rx_status.ppdu_len += 2940 rx_mpdu_start->rx_mpdu_info_details.mpdu_length; 2941 } 2942 2943 filter_category = 2944 rx_mpdu_start->rx_mpdu_info_details.rxpcu_mpdu_filter_in_category; 2945 2946 if (filter_category == 0) 2947 ppdu_info->rx_status.rxpcu_filter_pass = 1; 2948 else if (filter_category == 1) 2949 ppdu_info->rx_status.monitor_direct_used = 1; 2950 2951 ppdu_info->rx_user_status[user_id].filter_category = filter_category; 2952 2953 ppdu_info->nac_info.mcast_bcast = 2954 rx_mpdu_start->rx_mpdu_info_details.mcast_bcast; 2955 ppdu_info->mpdu_info[user_id].decap_type = 2956 rx_mpdu_start->rx_mpdu_info_details.decap_type; 2957 2958 return HAL_TLV_STATUS_MPDU_START; 2959 } 2960 case WIFIRX_MPDU_END_E: 2961 ppdu_info->user_id = user_id; 2962 ppdu_info->fcs_err = 2963 HAL_RX_GET_64(rx_tlv, RX_MPDU_END, 2964 FCS_ERR); 2965 return HAL_TLV_STATUS_MPDU_END; 2966 case WIFIRX_MSDU_END_E: { 2967 hal_rx_mon_msdu_end_t *rx_msdu_end = rx_tlv; 2968 2969 if (user_id < HAL_MAX_UL_MU_USERS) { 2970 ppdu_info->rx_msdu_info[user_id].cce_metadata = 2971 rx_msdu_end->cce_metadata; 2972 ppdu_info->rx_msdu_info[user_id].fse_metadata = 2973 rx_msdu_end->fse_metadata; 2974 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 2975 rx_msdu_end->flow_idx_timeout; 2976 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 2977 rx_msdu_end->flow_idx_invalid; 2978 ppdu_info->rx_msdu_info[user_id].flow_idx = 2979 rx_msdu_end->flow_idx; 2980 ppdu_info->msdu[user_id].first_msdu = 2981 rx_msdu_end->first_msdu; 2982 ppdu_info->msdu[user_id].last_msdu = 2983 rx_msdu_end->last_msdu; 2984 ppdu_info->msdu[user_id].msdu_len = 2985 rx_msdu_end->msdu_length; 2986 ppdu_info->msdu[user_id].user_rssi = 2987 rx_msdu_end->user_rssi; 2988 ppdu_info->msdu[user_id].reception_type = 2989 rx_msdu_end->reception_type; 2990 } 2991 return HAL_TLV_STATUS_MSDU_END; 2992 } 2993 case WIFIMON_BUFFER_ADDR_E: 2994 hal_rx_status_get_mon_buf_addr(rx_tlv, ppdu_info); 2995 2996 return HAL_TLV_STATUS_MON_BUF_ADDR; 2997 case 0: 2998 return HAL_TLV_STATUS_PPDU_DONE; 2999 case WIFIRX_STATUS_BUFFER_DONE_E: 3000 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3001 3002 default: 3003 hal_debug("unhandled tlv tag %d", tlv_tag); 3004 } 3005 3006 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3007 rx_tlv, tlv_len); 3008 3009 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3010 } 3011 3012 static uint32_t 3013 hal_rx_status_process_aggr_tlv(struct hal_soc *hal_soc, 3014 struct hal_rx_ppdu_info *ppdu_info) 3015 { 3016 uint32_t aggr_tlv_tag = ppdu_info->tlv_aggr.tlv_tag; 3017 3018 switch (aggr_tlv_tag) { 3019 case WIFIPHYRX_GENERIC_EHT_SIG_E: 3020 hal_rx_parse_eht_sig_hdr(hal_soc, ppdu_info->tlv_aggr.buf, 3021 ppdu_info); 3022 break; 3023 default: 3024 /* Aggregated TLV cannot be handled */ 3025 qdf_assert(0); 3026 break; 3027 } 3028 3029 ppdu_info->tlv_aggr.in_progress = 0; 3030 ppdu_info->tlv_aggr.cur_len = 0; 3031 3032 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3033 } 3034 3035 static inline bool 3036 hal_rx_status_tlv_should_aggregate(struct hal_soc *hal_soc, uint32_t tlv_tag) 3037 { 3038 switch (tlv_tag) { 3039 case WIFIPHYRX_GENERIC_EHT_SIG_E: 3040 return true; 3041 } 3042 3043 return false; 3044 } 3045 3046 static inline uint32_t 3047 hal_rx_status_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr, 3048 struct hal_rx_ppdu_info *ppdu_info, 3049 qdf_nbuf_t nbuf) 3050 { 3051 uint32_t tlv_tag, user_id, tlv_len; 3052 void *rx_tlv; 3053 3054 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 3055 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 3056 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 3057 3058 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 3059 3060 if (tlv_len <= HAL_RX_MON_MAX_AGGR_SIZE - ppdu_info->tlv_aggr.cur_len) { 3061 qdf_mem_copy(ppdu_info->tlv_aggr.buf + 3062 ppdu_info->tlv_aggr.cur_len, 3063 rx_tlv, tlv_len); 3064 ppdu_info->tlv_aggr.cur_len += tlv_len; 3065 } else { 3066 dp_err("Length of TLV exceeds max aggregation length"); 3067 qdf_assert(0); 3068 } 3069 3070 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3071 } 3072 3073 static inline uint32_t 3074 hal_rx_status_start_new_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr, 3075 struct hal_rx_ppdu_info *ppdu_info, 3076 qdf_nbuf_t nbuf) 3077 { 3078 uint32_t tlv_tag, user_id, tlv_len; 3079 3080 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 3081 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 3082 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 3083 3084 ppdu_info->tlv_aggr.in_progress = 1; 3085 ppdu_info->tlv_aggr.tlv_tag = tlv_tag; 3086 ppdu_info->tlv_aggr.cur_len = 0; 3087 3088 return hal_rx_status_aggr_tlv(hal_soc, rx_tlv_hdr, ppdu_info, nbuf); 3089 } 3090 3091 static inline uint32_t 3092 hal_rx_status_get_tlv_info_wrapper_be(void *rx_tlv_hdr, void *ppduinfo, 3093 hal_soc_handle_t hal_soc_hdl, 3094 qdf_nbuf_t nbuf) 3095 { 3096 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3097 uint32_t tlv_tag, user_id, tlv_len; 3098 struct hal_rx_ppdu_info *ppdu_info = 3099 (struct hal_rx_ppdu_info *)ppduinfo; 3100 3101 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 3102 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 3103 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 3104 3105 /* 3106 * Handle the case where aggregation is in progress 3107 * or the current TLV is one of the TLVs which should be 3108 * aggregated 3109 */ 3110 if (ppdu_info->tlv_aggr.in_progress) { 3111 if (ppdu_info->tlv_aggr.tlv_tag == tlv_tag) { 3112 return hal_rx_status_aggr_tlv(hal, rx_tlv_hdr, 3113 ppdu_info, nbuf); 3114 } else { 3115 /* Finish aggregation of current TLV */ 3116 hal_rx_status_process_aggr_tlv(hal, ppdu_info); 3117 } 3118 } 3119 3120 if (hal_rx_status_tlv_should_aggregate(hal, tlv_tag)) { 3121 return hal_rx_status_start_new_aggr_tlv(hal, rx_tlv_hdr, 3122 ppduinfo, nbuf); 3123 } 3124 3125 return hal_rx_status_get_tlv_info_generic_be(rx_tlv_hdr, ppduinfo, 3126 hal_soc_hdl, nbuf); 3127 } 3128 #endif /* _HAL_BE_API_MON_H_ */ 3129