1 /* 2 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HAL_BE_API_MON_H_ 19 #define _HAL_BE_API_MON_H_ 20 21 #include "hal_be_hw_headers.h" 22 #ifdef QCA_MONITOR_2_0_SUPPORT 23 #include <mon_ingress_ring.h> 24 #include <mon_destination_ring.h> 25 #include <mon_drop.h> 26 #endif 27 #include <hal_be_hw_headers.h> 28 #include "hal_api_mon.h" 29 #include <hal_generic_api.h> 30 #include <hal_generic_api.h> 31 #include <hal_api_mon.h> 32 33 #if defined(QCA_MONITOR_2_0_SUPPORT) || \ 34 defined(QCA_SINGLE_WIFI_3_0) 35 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 36 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 37 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff 38 39 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 40 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 41 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff 42 43 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 44 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 45 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 46 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 47 48 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c 49 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 50 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 51 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 52 53 #define HAL_MON_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 54 ((*(((unsigned int *) buff_addr_info) + \ 55 (HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 56 ((paddr_lo) << HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 57 HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 58 59 #define HAL_MON_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 60 ((*(((unsigned int *) buff_addr_info) + \ 61 (HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 62 ((paddr_hi) << HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 63 HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 64 65 #define HAL_MON_VADDR_LO_SET(buff_addr_info, vaddr_lo) \ 66 ((*(((unsigned int *) buff_addr_info) + \ 67 (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET >> 2))) = \ 68 ((vaddr_lo) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB) & \ 69 HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK) 70 71 #define HAL_MON_VADDR_HI_SET(buff_addr_info, vaddr_hi) \ 72 ((*(((unsigned int *) buff_addr_info) + \ 73 (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET >> 2))) = \ 74 ((vaddr_hi) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB) & \ 75 HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK) 76 77 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 78 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 79 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 80 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 81 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 82 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 83 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 84 PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 85 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 86 PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 87 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 88 PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 89 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 90 PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 91 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 92 PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 93 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 94 PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 95 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 96 PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 97 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 98 PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 99 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 100 PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 101 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 102 PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 103 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 104 PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 105 #endif 106 107 #define RX_MON_MPDU_START_WMASK 0x07F0 108 #define RX_MON_MSDU_END_WMASK 0x0AE1 109 #define RX_MON_PPDU_END_USR_STATS_WMASK 0xB7E 110 111 #ifdef CONFIG_MON_WORD_BASED_TLV 112 #ifndef BIG_ENDIAN_HOST 113 struct rx_mpdu_start_mon_data { 114 uint32_t peer_meta_data : 32; 115 uint32_t rxpcu_mpdu_filter_in_category : 2, 116 sw_frame_group_id : 7, 117 ndp_frame : 1, 118 phy_err : 1, 119 phy_err_during_mpdu_header : 1, 120 protocol_version_err : 1, 121 ast_based_lookup_valid : 1, 122 reserved_0a : 2, 123 phy_ppdu_id : 16; 124 uint32_t ast_index : 16, 125 sw_peer_id : 16; 126 uint32_t mpdu_frame_control_valid : 1, 127 mpdu_duration_valid : 1, 128 mac_addr_ad1_valid : 1, 129 mac_addr_ad2_valid : 1, 130 mac_addr_ad3_valid : 1, 131 mac_addr_ad4_valid : 1, 132 mpdu_sequence_control_valid : 1, 133 mpdu_qos_control_valid : 1, 134 mpdu_ht_control_valid : 1, 135 frame_encryption_info_valid : 1, 136 mpdu_fragment_number : 4, 137 more_fragment_flag : 1, 138 reserved_11a : 1, 139 fr_ds : 1, 140 to_ds : 1, 141 encrypted : 1, 142 mpdu_retry : 1, 143 mpdu_sequence_number : 12; 144 uint32_t key_id_octet : 8, 145 new_peer_entry : 1, 146 decrypt_needed : 1, 147 decap_type : 2, 148 rx_insert_vlan_c_tag_padding : 1, 149 rx_insert_vlan_s_tag_padding : 1, 150 strip_vlan_c_tag_decap : 1, 151 strip_vlan_s_tag_decap : 1, 152 pre_delim_count : 12, 153 ampdu_flag : 1, 154 bar_frame : 1, 155 raw_mpdu : 1, 156 reserved_12 : 1; 157 uint32_t mpdu_length : 14, 158 first_mpdu : 1, 159 mcast_bcast : 1, 160 ast_index_not_found : 1, 161 ast_index_timeout : 1, 162 power_mgmt : 1, 163 non_qos : 1, 164 null_data : 1, 165 mgmt_type : 1, 166 ctrl_type : 1, 167 more_data : 1, 168 eosp : 1, 169 fragment_flag : 1, 170 order : 1, 171 u_apsd_trigger : 1, 172 encrypt_required : 1, 173 directed : 1, 174 amsdu_present : 1, 175 reserved_13 : 1; 176 uint32_t mpdu_frame_control_field : 16, 177 mpdu_duration_field : 16; 178 uint32_t mac_addr_ad1_31_0 : 32; 179 uint32_t mac_addr_ad1_47_32 : 16, 180 mac_addr_ad2_15_0 : 16; 181 uint32_t mac_addr_ad2_47_16 : 32; 182 uint32_t mac_addr_ad3_31_0 : 32; 183 uint32_t mac_addr_ad3_47_32 : 16, 184 mpdu_sequence_control_field : 16; 185 uint32_t mac_addr_ad4_31_0 : 32; 186 uint32_t mac_addr_ad4_47_32 : 16, 187 mpdu_qos_control_field : 16; 188 }; 189 190 struct rx_msdu_end_mon_data { 191 uint32_t rxpcu_mpdu_filter_in_category : 2, 192 sw_frame_group_id : 7, 193 reserved_0 : 7, 194 phy_ppdu_id : 16; 195 uint32_t ip_hdr_chksum : 16, 196 reported_mpdu_length : 14, 197 reserved_1a : 2; 198 uint32_t sa_sw_peer_id : 16, 199 sa_idx_timeout : 1, 200 da_idx_timeout : 1, 201 to_ds : 1, 202 tid : 4, 203 sa_is_valid : 1, 204 da_is_valid : 1, 205 da_is_mcbc : 1, 206 l3_header_padding : 2, 207 first_msdu : 1, 208 last_msdu : 1, 209 fr_ds : 1, 210 ip_chksum_fail_copy : 1; 211 uint32_t sa_idx : 16, 212 da_idx_or_sw_peer_id : 16; 213 uint32_t msdu_drop : 1, 214 reo_destination_indication : 5, 215 flow_idx : 20, 216 use_ppe : 1, 217 mesh_sta : 2, 218 vlan_ctag_stripped : 1, 219 vlan_stag_stripped : 1, 220 fragment_flag : 1; 221 uint32_t fse_metadata : 32; 222 uint32_t cce_metadata : 16, 223 tcp_udp_chksum : 16; 224 uint32_t aggregation_count : 8, 225 flow_aggregation_continuation : 1, 226 fisa_timeout : 1, 227 tcp_udp_chksum_fail_copy : 1, 228 msdu_limit_error : 1, 229 flow_idx_timeout : 1, 230 flow_idx_invalid : 1, 231 cce_match : 1, 232 amsdu_parser_error : 1, 233 cumulative_ip_length : 16; 234 uint32_t msdu_length : 14, 235 stbc : 1, 236 ipsec_esp : 1, 237 l3_offset : 7, 238 ipsec_ah : 1, 239 l4_offset : 8; 240 uint32_t msdu_number : 8, 241 decap_format : 2, 242 ipv4_proto : 1, 243 ipv6_proto : 1, 244 tcp_proto : 1, 245 udp_proto : 1, 246 ip_frag : 1, 247 tcp_only_ack : 1, 248 da_is_bcast_mcast : 1, 249 toeplitz_hash_sel : 2, 250 ip_fixed_header_valid : 1, 251 ip_extn_header_valid : 1, 252 tcp_udp_header_valid : 1, 253 mesh_control_present : 1, 254 ldpc : 1, 255 ip4_protocol_ip6_next_header : 8; 256 uint32_t user_rssi : 8, 257 pkt_type : 4, 258 sgi : 2, 259 rate_mcs : 4, 260 receive_bandwidth : 3, 261 reception_type : 3, 262 mimo_ss_bitmap : 7, 263 msdu_done_copy : 1; 264 uint32_t flow_id_toeplitz : 32; 265 }; 266 267 struct rx_ppdu_end_user_mon_data { 268 uint32_t sw_peer_id : 16, 269 mpdu_cnt_fcs_err : 11, 270 sw2rxdma0_buf_source_used : 1, 271 fw2rxdma_pmac0_buf_source_used : 1, 272 sw2rxdma1_buf_source_used : 1, 273 sw2rxdma_exception_buf_source_used: 1, 274 fw2rxdma_pmac1_buf_source_used : 1; 275 uint32_t mpdu_cnt_fcs_ok : 11, 276 frame_control_info_valid : 1, 277 qos_control_info_valid : 1, 278 ht_control_info_valid : 1, 279 data_sequence_control_info_valid : 1, 280 ht_control_info_null_valid : 1, 281 rxdma2fw_pmac1_ring_used : 1, 282 rxdma2reo_ring_used : 1, 283 rxdma2fw_pmac0_ring_used : 1, 284 rxdma2sw_ring_used : 1, 285 rxdma_release_ring_used : 1, 286 ht_control_field_pkt_type : 4, 287 rxdma2reo_remote0_ring_used : 1, 288 rxdma2reo_remote1_ring_used : 1, 289 reserved_3b : 5; 290 uint32_t ast_index : 16, 291 frame_control_field : 16; 292 uint32_t first_data_seq_ctrl : 16, 293 qos_control_field : 16; 294 uint32_t ht_control_field : 32; 295 uint32_t fcs_ok_bitmap_31_0 : 32; 296 uint32_t fcs_ok_bitmap_63_32 : 32; 297 uint32_t udp_msdu_count : 16, 298 tcp_msdu_count : 16; 299 uint32_t other_msdu_count : 16, 300 tcp_ack_msdu_count : 16; 301 uint32_t sw_response_reference_ptr : 32; 302 uint32_t received_qos_data_tid_bitmap : 16, 303 received_qos_data_tid_eosp_bitmap : 16; 304 uint32_t qosctrl_15_8_tid0 : 8, 305 qosctrl_15_8_tid1 : 8, 306 qosctrl_15_8_tid2 : 8, 307 qosctrl_15_8_tid3 : 8; 308 uint32_t qosctrl_15_8_tid12 : 8, 309 qosctrl_15_8_tid13 : 8, 310 qosctrl_15_8_tid14 : 8, 311 qosctrl_15_8_tid15 : 8; 312 uint32_t mpdu_ok_byte_count : 25, 313 ampdu_delim_ok_count_6_0 : 7; 314 uint32_t ampdu_delim_err_count : 25, 315 ampdu_delim_ok_count_13_7 : 7; 316 uint32_t mpdu_err_byte_count : 25, 317 ampdu_delim_ok_count_20_14 : 7; 318 uint32_t sw_response_reference_ptr_ext : 32; 319 uint32_t corrupted_due_to_fifo_delay : 1, 320 frame_control_info_null_valid : 1, 321 frame_control_field_null : 16, 322 retried_mpdu_count : 11, 323 reserved_23a : 3; 324 }; 325 #else 326 struct rx_mpdu_start_mon_data { 327 uint32_t peer_meta_data : 32; 328 uint32_t phy_ppdu_id : 16, 329 reserved_0a : 2, 330 ast_based_lookup_valid : 1, 331 protocol_version_err : 1, 332 phy_err_during_mpdu_header : 1, 333 phy_err : 1, 334 ndp_frame : 1, 335 sw_frame_group_id : 7, 336 rxpcu_mpdu_filter_in_category : 2; 337 uint32_t sw_peer_id : 16, 338 ast_index : 16; 339 uint32_t mpdu_sequence_number : 12, 340 mpdu_retry : 1, 341 encrypted : 1, 342 to_ds : 1, 343 fr_ds : 1, 344 reserved_11a : 1, 345 more_fragment_flag : 1, 346 mpdu_fragment_number : 4, 347 frame_encryption_info_valid : 1, 348 mpdu_ht_control_valid : 1, 349 mpdu_qos_control_valid : 1, 350 mpdu_sequence_control_valid : 1, 351 mac_addr_ad4_valid : 1, 352 mac_addr_ad3_valid : 1, 353 mac_addr_ad2_valid : 1, 354 mac_addr_ad1_valid : 1, 355 mpdu_duration_valid : 1, 356 mpdu_frame_control_valid : 1; 357 uint32_t reserved_12 : 1, 358 raw_mpdu : 1, 359 bar_frame : 1, 360 ampdu_flag : 1, 361 pre_delim_count : 12, 362 strip_vlan_s_tag_decap : 1, 363 strip_vlan_c_tag_decap : 1, 364 rx_insert_vlan_s_tag_padding : 1, 365 rx_insert_vlan_c_tag_padding : 1, 366 decap_type : 2, 367 decrypt_needed : 1, 368 new_peer_entry : 1, 369 key_id_octet : 8; 370 uint32_t reserved_13 : 1; 371 amsdu_present : 1, 372 directed : 1, 373 encrypt_required : 1, 374 u_apsd_trigger : 1, 375 order : 1, 376 fragment_flag : 1, 377 eosp : 1, 378 more_data : 1, 379 ctrl_type : 1, 380 mgmt_type : 1, 381 null_data : 1, 382 non_qos : 1, 383 power_mgmt : 1, 384 ast_index_timeout : 1, 385 ast_index_not_found : 1, 386 mcast_bcast : 1, 387 first_mpdu : 1, 388 mpdu_length : 14, 389 uint32_t mpdu_duration_field : 16, 390 mpdu_frame_control_field : 16; 391 uint32_t mac_addr_ad1_31_0 : 32; 392 uint32_t mac_addr_ad2_15_0 : 16, 393 mac_addr_ad1_47_32 : 16; 394 uint32_t mac_addr_ad2_47_16 : 32; 395 uint32_t mac_addr_ad3_31_0 : 32; 396 uint32_t mpdu_sequence_control_field : 16, 397 mac_addr_ad3_47_32 : 16; 398 uint32_t mac_addr_ad4_31_0 : 32; 399 uint32_t mpdu_qos_control_field : 16, 400 mac_addr_ad4_47_32 : 16; 401 }; 402 403 struct rx_msdu_end_mon_data { 404 uint32_t phy_ppdu_id : 16, 405 reserved_0 : 7, 406 sw_frame_group_id : 7, 407 rxpcu_mpdu_filter_in_category : 2; 408 uint32_t reserved_1a : 2, 409 reported_mpdu_length : 14, 410 ip_hdr_chksum : 16; 411 uint32_t ip_chksum_fail_copy : 1, 412 fr_ds : 1, 413 last_msdu : 1, 414 first_msdu : 1, 415 l3_header_padding : 2, 416 da_is_mcbc : 1, 417 da_is_valid : 1, 418 sa_is_valid : 1, 419 tid : 4, 420 to_ds : 1, 421 da_idx_timeout : 1, 422 sa_idx_timeout : 1, 423 sa_sw_peer_id : 16; 424 uint32_t da_idx_or_sw_peer_id : 16, 425 sa_idx : 16; 426 uint32_t fragment_flag : 1, 427 vlan_stag_stripped : 1, 428 vlan_ctag_stripped : 1, 429 mesh_sta : 2, 430 use_ppe : 1, 431 flow_idx : 20, 432 reo_destination_indication : 5, 433 msdu_drop : 1; 434 uint32_t fse_metadata : 32; 435 uint32_t cce_metadata : 16, 436 tcp_udp_chksum : 16; 437 uint32_t cumulative_ip_length : 16, 438 amsdu_parser_error : 1, 439 cce_match : 1, 440 flow_idx_invalid : 1, 441 flow_idx_timeout : 1, 442 msdu_limit_error : 1, 443 tcp_udp_chksum_fail_copy : 1, 444 fisa_timeout : 1, 445 flow_aggregation_continuation : 1, 446 aggregation_count : 8; 447 uint32_t l4_offset : 8, 448 ipsec_ah : 1, 449 l3_offset : 7, 450 ipsec_esp : 1, 451 stbc : 1, 452 msdu_length : 14; 453 uint32_t ip4_protocol_ip6_next_header : 8, 454 ldpc : 1, 455 mesh_control_present : 1, 456 tcp_udp_header_valid : 1, 457 ip_extn_header_valid : 1, 458 ip_fixed_header_valid : 1, 459 toeplitz_hash_sel : 2, 460 da_is_bcast_mcast : 1, 461 tcp_only_ack : 1, 462 ip_frag : 1, 463 udp_proto : 1, 464 tcp_proto : 1, 465 ipv6_proto : 1, 466 ipv4_proto : 1, 467 decap_format : 2, 468 msdu_number : 8; 469 uint32_t msdu_done_copy : 1, 470 mimo_ss_bitmap : 7, 471 reception_type : 3, 472 receive_bandwidth : 3, 473 rate_mcs : 4, 474 sgi : 2, 475 pkt_type : 4, 476 user_rssi : 8; 477 uint32_t flow_id_toeplitz : 32; 478 }; 479 480 struct rx_ppdu_end_user_mon_data { 481 uint32_t fw2rxdma_pmac1_buf_source_used : 1, 482 sw2rxdma_exception_buf_source_used: 1, 483 sw2rxdma1_buf_source_used : 1, 484 fw2rxdma_pmac0_buf_source_used : 1, 485 sw2rxdma0_buf_source_used : 1, 486 mpdu_cnt_fcs_err : 11, 487 sw_peer_id : 16; 488 uint32_t reserved_3b : 5, 489 rxdma2reo_remote1_ring_used : 1, 490 rxdma2reo_remote0_ring_used : 1, 491 ht_control_field_pkt_type : 4, 492 rxdma_release_ring_used : 1, 493 rxdma2sw_ring_used : 1, 494 rxdma2fw_pmac0_ring_used : 1, 495 rxdma2reo_ring_used : 1, 496 rxdma2fw_pmac1_ring_used : 1, 497 ht_control_info_null_valid : 1, 498 data_sequence_control_info_valid : 1, 499 ht_control_info_valid : 1, 500 qos_control_info_valid : 1, 501 frame_control_info_valid : 1, 502 mpdu_cnt_fcs_ok : 11; 503 uint32_t frame_control_field : 16, 504 ast_index : 16; 505 uint32_t qos_control_field : 16, 506 first_data_seq_ctrl : 16; 507 uint32_t ht_control_field : 32; 508 uint32_t fcs_ok_bitmap_31_0 : 32; 509 uint32_t fcs_ok_bitmap_63_32 : 32; 510 uint32_t tcp_msdu_count : 16, 511 udp_msdu_count : 16; 512 uint32_t tcp_ack_msdu_count : 16, 513 other_msdu_count : 16; 514 uint32_t sw_response_reference_ptr : 32; 515 uint32_t received_qos_data_tid_eosp_bitmap : 16, 516 received_qos_data_tid_bitmap : 16; 517 uint32_t qosctrl_15_8_tid3 : 8, 518 qosctrl_15_8_tid2 : 8, 519 qosctrl_15_8_tid1 : 8, 520 qosctrl_15_8_tid0 : 8; 521 uint32_t qosctrl_15_8_tid15 : 8, 522 qosctrl_15_8_tid14 : 8, 523 qosctrl_15_8_tid13 : 8, 524 qosctrl_15_8_tid12 : 8; 525 uint32_t ampdu_delim_ok_count_6_0 : 7, 526 mpdu_ok_byte_count : 25; 527 uint32_t ampdu_delim_ok_count_13_7 : 7, 528 ampdu_delim_err_count : 25; 529 uint32_t ampdu_delim_ok_count_20_14 : 7, 530 mpdu_err_byte_count : 25; 531 uint32_t sw_response_reference_ptr_ext : 32; 532 uint32_t reserved_23a : 3, 533 retried_mpdu_count : 11, 534 frame_control_field_null : 16, 535 frame_control_info_null_valid : 1, 536 corrupted_due_to_fifo_delay : 1; 537 }; 538 #endif 539 540 struct rx_mpdu_start_mon_data_t { 541 struct rx_mpdu_start_mon_data rx_mpdu_info_details; 542 }; 543 544 struct rx_msdu_end_mon_data_t { 545 struct rx_msdu_end_mon_data rx_mpdu_info_details; 546 }; 547 /* TLV struct for word based Tlv */ 548 typedef struct rx_mpdu_start_mon_data_t hal_rx_mon_mpdu_start_t; 549 typedef struct rx_msdu_end_mon_data hal_rx_mon_msdu_end_t; 550 typedef struct rx_ppdu_end_user_mon_data hal_rx_mon_ppdu_end_user_t; 551 552 #else 553 554 typedef struct rx_mpdu_start hal_rx_mon_mpdu_start_t; 555 typedef struct rx_msdu_end hal_rx_mon_msdu_end_t; 556 typedef struct rx_ppdu_end_user_stats hal_rx_mon_ppdu_end_user_t; 557 #endif 558 559 /* 560 * struct mon_destination_drop - monitor drop descriptor 561 * 562 * @ppdu_drop_cnt: PPDU drop count 563 * @mpdu_drop_cnt: MPDU drop count 564 * @tlv_drop_cnt: TLV drop count 565 * @end_of_ppdu_seen: end of ppdu seen 566 * @reserved_0a: rsvd 567 * @reserved_1a: rsvd 568 * @ppdu_id: PPDU ID 569 * @reserved_3a: rsvd 570 * @initiator: initiator ppdu 571 * @empty_descriptor: empty descriptor 572 * @ring_id: ring id 573 * @looping_count: looping count 574 */ 575 struct mon_destination_drop { 576 uint32_t ppdu_drop_cnt : 10, 577 mpdu_drop_cnt : 10, 578 tlv_drop_cnt : 10, 579 end_of_ppdu_seen : 1, 580 reserved_0a : 1; 581 uint32_t reserved_1a : 32; 582 uint32_t ppdu_id : 32; 583 uint32_t reserved_3a : 18, 584 initiator : 1, 585 empty_descriptor : 1, 586 ring_id : 8, 587 looping_count : 4; 588 }; 589 590 #define HAL_MON_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 591 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 592 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 593 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 594 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 595 596 #define HAL_MON_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 597 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 598 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 599 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 600 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 601 602 /** 603 * struct hal_rx_status_buffer_done - status buffer done tlv 604 * placeholder structure 605 * 606 * @ppdu_start_offset: ppdu start 607 * @first_ppdu_start_user_info_offset: 608 * @mult_ppdu_start_user_info: 609 * @end_offset: 610 * @ppdu_end_detected: 611 * @flush_detected: 612 * @rsvd: 613 */ 614 struct hal_rx_status_buffer_done { 615 uint32_t ppdu_start_offset : 3, 616 first_ppdu_start_user_info_offset : 6, 617 mult_ppdu_start_user_info : 1, 618 end_offset : 13, 619 ppdu_end_detected : 1, 620 flush_detected : 1, 621 rsvd : 7; 622 }; 623 624 /** 625 * hal_mon_status_end_reason : ppdu status buffer end reason 626 * 627 * @HAL_MON_STATUS_BUFFER_FULL: status buffer full 628 * @HAL_MON_FLUSH_DETECTED: flush detected 629 * @HAL_MON_END_OF_PPDU: end of ppdu detected 630 * HAL_MON_PPDU_truncated: truncated ppdu status 631 */ 632 enum hal_mon_status_end_reason { 633 HAL_MON_STATUS_BUFFER_FULL, 634 HAL_MON_FLUSH_DETECTED, 635 HAL_MON_END_OF_PPDU, 636 HAL_MON_PPDU_TRUNCATED, 637 }; 638 639 /** 640 * struct hal_mon_desc () - HAL Monitor descriptor 641 * 642 * @buf_addr: virtual buffer address 643 * @ppdu_id: ppdu id 644 * - TxMon fills scheduler id 645 * - RxMON fills phy_ppdu_id 646 * @end_offset: offset (units in 4 bytes) where status buffer ended 647 * i.e offset of TLV + last TLV size 648 * @end_reason: 0 - status buffer is full 649 * 1 - flush detected 650 * 2 - TX_FES_STATUS_END or RX_PPDU_END 651 * 3 - PPDU truncated due to system error 652 * @initiator: 1 - descriptor belongs to TX FES 653 * 0 - descriptor belongs to TX RESPONSE 654 * @empty_descriptor: 0 - this descriptor is written on a flush 655 * or end of ppdu or end of status buffer 656 * 1 - descriptor provided to indicate drop 657 * @ring_id: ring id for debugging 658 * @looping_count: count to indicate number of times producer 659 * of entries has looped around the ring 660 * @flush_detected: if flush detected 661 * @end_reason: ppdu end reason 662 * @end_of_ppdu_dropped: if end_of_ppdu is dropped 663 * @ppdu_drop_count: PPDU drop count 664 * @mpdu_drop_count: MPDU drop count 665 * @tlv_drop_count: TLV drop count 666 */ 667 struct hal_mon_desc { 668 uint64_t buf_addr; 669 uint32_t ppdu_id; 670 uint32_t end_offset:12, 671 reserved_3a:4, 672 end_reason:2, 673 initiator:1, 674 empty_descriptor:1, 675 ring_id:8, 676 looping_count:4; 677 uint16_t flush_detected:1, 678 end_of_ppdu_dropped:1; 679 uint32_t ppdu_drop_count; 680 uint32_t mpdu_drop_count; 681 uint32_t tlv_drop_count; 682 }; 683 684 typedef struct hal_mon_desc *hal_mon_desc_t; 685 686 /** 687 * struct hal_mon_buf_addr_status () - HAL buffer address tlv get status 688 * 689 * @buf_addr_31_0: Lower 32 bits of virtual address of status buffer 690 * @buf_addr_63_32: Upper 32 bits of virtual address of status buffer 691 * @dma_length: DMA length 692 * @msdu_continuation: is msdu size more than fragment size 693 * @truncated: is msdu got truncated 694 * @tlv_padding: tlv paddding 695 */ 696 struct hal_mon_buf_addr_status { 697 uint32_t buffer_virt_addr_31_0; 698 uint32_t buffer_virt_addr_63_32; 699 uint32_t dma_length:12, 700 reserved_2a:4, 701 msdu_continuation:1, 702 truncated:1, 703 reserved_2b:14; 704 uint32_t tlv64_padding; 705 }; 706 707 #ifdef QCA_MONITOR_2_0_SUPPORT 708 /** 709 * hal_be_get_mon_dest_status() - Get monitor descriptor 710 * @hal_soc_hdl: HAL Soc handle 711 * @desc: HAL monitor descriptor 712 * 713 * Return: none 714 */ 715 static inline void 716 hal_be_get_mon_dest_status(hal_soc_handle_t hal_soc, 717 void *hw_desc, 718 struct hal_mon_desc *status) 719 { 720 struct mon_destination_ring *desc = hw_desc; 721 722 status->empty_descriptor = desc->empty_descriptor; 723 if (status->empty_descriptor) { 724 struct mon_destination_drop *drop_desc = hw_desc; 725 726 status->buf_addr = 0; 727 status->ppdu_drop_count = drop_desc->ppdu_drop_cnt; 728 status->mpdu_drop_count = drop_desc->mpdu_drop_cnt; 729 status->tlv_drop_count = drop_desc->tlv_drop_cnt; 730 status->end_of_ppdu_dropped = drop_desc->end_of_ppdu_seen; 731 } else { 732 status->buf_addr = HAL_RX_GET(desc, MON_DESTINATION_RING_STAT,BUF_VIRT_ADDR_31_0) | 733 (((uint64_t)HAL_RX_GET(desc, 734 MON_DESTINATION_RING_STAT, 735 BUF_VIRT_ADDR_63_32)) << 32); 736 status->end_reason = desc->end_reason; 737 status->end_offset = desc->end_offset; 738 } 739 status->ppdu_id = desc->ppdu_id; 740 status->initiator = desc->initiator; 741 status->looping_count = desc->looping_count; 742 } 743 #endif 744 745 #if defined(RX_PPDU_END_USER_STATS_OFDMA_INFO_VALID_OFFSET) && \ 746 defined(RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 747 748 static inline void 749 hal_rx_handle_mu_ul_info(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 750 struct mon_rx_user_status *mon_rx_user_status) 751 { 752 mon_rx_user_status->mu_ul_user_v0_word0 = 753 rx_ppdu_end_user->sw_response_reference_ptr; 754 755 mon_rx_user_status->mu_ul_user_v0_word1 = 756 rx_ppdu_end_user->sw_response_reference_ptr_ext; 757 } 758 #else 759 static inline void 760 hal_rx_handle_mu_ul_info(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 761 struct mon_rx_user_status *mon_rx_user_status) 762 { 763 } 764 #endif 765 766 static inline void 767 hal_rx_populate_byte_count(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 768 void *ppduinfo, 769 struct mon_rx_user_status *mon_rx_user_status) 770 { 771 mon_rx_user_status->mpdu_ok_byte_count = 772 rx_ppdu_end_user->mpdu_ok_byte_count; 773 mon_rx_user_status->mpdu_err_byte_count = 774 rx_ppdu_end_user->mpdu_err_byte_count; 775 } 776 777 static inline void 778 hal_rx_populate_mu_user_info(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 779 void *ppduinfo, uint32_t user_id, 780 struct mon_rx_user_status *mon_rx_user_status) 781 { 782 struct mon_rx_info *mon_rx_info; 783 struct mon_rx_user_info *mon_rx_user_info; 784 struct hal_rx_ppdu_info *ppdu_info = 785 (struct hal_rx_ppdu_info *)ppduinfo; 786 787 mon_rx_info = &ppdu_info->rx_info; 788 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 789 mon_rx_user_info->qos_control_info_valid = 790 mon_rx_info->qos_control_info_valid; 791 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 792 793 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 794 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 795 mon_rx_user_status->tcp_msdu_count = 796 ppdu_info->rx_status.tcp_msdu_count; 797 mon_rx_user_status->udp_msdu_count = 798 ppdu_info->rx_status.udp_msdu_count; 799 mon_rx_user_status->other_msdu_count = 800 ppdu_info->rx_status.other_msdu_count; 801 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 802 mon_rx_user_status->frame_control_info_valid = 803 ppdu_info->rx_status.frame_control_info_valid; 804 mon_rx_user_status->data_sequence_control_info_valid = 805 ppdu_info->rx_status.data_sequence_control_info_valid; 806 mon_rx_user_status->first_data_seq_ctrl = 807 ppdu_info->rx_status.first_data_seq_ctrl; 808 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 809 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 810 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 811 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 812 if (mon_rx_user_status->vht_flags) { 813 mon_rx_user_status->vht_flag_values2 = 814 ppdu_info->rx_status.vht_flag_values2; 815 qdf_mem_copy(mon_rx_user_status->vht_flag_values3, 816 ppdu_info->rx_status.vht_flag_values3, 817 sizeof(mon_rx_user_status->vht_flag_values3)); 818 mon_rx_user_status->vht_flag_values4 = 819 ppdu_info->rx_status.vht_flag_values4; 820 mon_rx_user_status->vht_flag_values5 = 821 ppdu_info->rx_status.vht_flag_values5; 822 mon_rx_user_status->vht_flag_values6 = 823 ppdu_info->rx_status.vht_flag_values6; 824 } 825 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 826 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 827 828 mon_rx_user_status->mpdu_cnt_fcs_ok = 829 ppdu_info->com_info.mpdu_cnt_fcs_ok; 830 mon_rx_user_status->mpdu_cnt_fcs_err = 831 ppdu_info->com_info.mpdu_cnt_fcs_err; 832 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 833 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 834 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 835 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 836 mon_rx_user_status->retry_mpdu = 837 ppdu_info->rx_status.mpdu_retry_cnt; 838 hal_rx_populate_byte_count(rx_ppdu_end_user, ppdu_info, 839 mon_rx_user_status); 840 } 841 842 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, \ 843 ppdu_info, rssi_info_tlv) \ 844 { \ 845 ppdu_info->rx_status.rssi_chain[chain][0] = \ 846 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 847 RSSI_PRI20_CHAIN##chain); \ 848 ppdu_info->rx_status.rssi_chain[chain][1] = \ 849 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 850 RSSI_EXT20_CHAIN##chain); \ 851 ppdu_info->rx_status.rssi_chain[chain][2] = \ 852 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 853 RSSI_EXT40_LOW20_CHAIN##chain); \ 854 ppdu_info->rx_status.rssi_chain[chain][3] = \ 855 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 856 RSSI_EXT40_HIGH20_CHAIN##chain); \ 857 } \ 858 859 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 860 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, ppdu_info, rssi_info_tlv) \ 861 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, ppdu_info, rssi_info_tlv) \ 862 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, ppdu_info, rssi_info_tlv) \ 863 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, ppdu_info, rssi_info_tlv) \ 864 } \ 865 866 static inline uint32_t 867 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 868 uint8_t *rssi_info_tlv) 869 { 870 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 871 return 0; 872 } 873 874 #ifdef WLAN_TX_PKT_CAPTURE_ENH 875 static inline void 876 hal_get_qos_control(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 877 struct hal_rx_ppdu_info *ppdu_info) 878 { 879 ppdu_info->rx_info.qos_control_info_valid = 880 rx_ppdu_end_user->qos_control_info_valid; 881 882 if (ppdu_info->rx_info.qos_control_info_valid) 883 ppdu_info->rx_info.qos_control = 884 rx_ppdu_end_user->qos_control_field; 885 } 886 887 static inline void 888 hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 889 struct hal_rx_ppdu_info *ppdu_info) 890 { 891 if ((ppdu_info->sw_frame_group_id 892 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 893 (ppdu_info->sw_frame_group_id == 894 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 895 ppdu_info->rx_info.mac_addr1_valid = 896 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_valid; 897 898 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 899 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_31_0; 900 if (ppdu_info->sw_frame_group_id == 901 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 902 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 903 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_47_32; 904 } 905 } 906 } 907 #else 908 static inline void 909 hal_get_qos_control(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 910 struct hal_rx_ppdu_info *ppdu_info) 911 { 912 } 913 914 static inline void 915 hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 916 struct hal_rx_ppdu_info *ppdu_info) 917 { 918 } 919 #endif 920 921 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 922 static inline void 923 hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 924 struct hal_rx_ppdu_info *ppdu_info) 925 { 926 uint16_t frame_ctrl; 927 uint8_t fc_type; 928 929 if (rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid) { 930 frame_ctrl = rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field; 931 fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl); 932 if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT) 933 ppdu_info->frm_type_info.rx_mgmt_cnt++; 934 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL) 935 ppdu_info->frm_type_info.rx_ctrl_cnt++; 936 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA) 937 ppdu_info->frm_type_info.rx_data_cnt++; 938 } 939 } 940 #else 941 static inline void 942 hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 943 struct hal_rx_ppdu_info *ppdu_info) 944 { 945 } 946 #endif 947 948 #ifdef QCA_MONITOR_2_0_SUPPORT 949 /** 950 * hal_mon_buff_addr_info_set() - set desc address in cookie 951 * @hal_soc_hdl: HAL Soc handle 952 * @mon_entry: monitor srng 953 * @desc: HAL monitor descriptor 954 * 955 * Return: none 956 */ 957 static inline 958 void hal_mon_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 959 void *mon_entry, 960 void *mon_desc_addr, 961 qdf_dma_addr_t phy_addr) 962 { 963 uint32_t paddr_lo = ((uintptr_t)phy_addr & 0x00000000ffffffff); 964 uint32_t paddr_hi = ((uintptr_t)phy_addr & 0xffffffff00000000) >> 32; 965 uint32_t vaddr_lo = ((uintptr_t)mon_desc_addr & 0x00000000ffffffff); 966 uint32_t vaddr_hi = ((uintptr_t)mon_desc_addr & 0xffffffff00000000) >> 32; 967 968 HAL_MON_PADDR_LO_SET(mon_entry, paddr_lo); 969 HAL_MON_PADDR_HI_SET(mon_entry, paddr_hi); 970 HAL_MON_VADDR_LO_SET(mon_entry, vaddr_lo); 971 HAL_MON_VADDR_HI_SET(mon_entry, vaddr_hi); 972 } 973 974 /* TX monitor */ 975 #define TX_MON_STATUS_BUF_SIZE 2048 976 977 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 978 979 #define HAL_MAX_DL_MU_USERS 37 980 #define HAL_MAX_RU_INDEX 7 981 982 enum hal_tx_tlv_status { 983 HAL_MON_TX_FES_SETUP, 984 HAL_MON_TX_FES_STATUS_END, 985 HAL_MON_RX_RESPONSE_REQUIRED_INFO, 986 HAL_MON_RESPONSE_END_STATUS_INFO, 987 988 HAL_MON_TX_PCU_PPDU_SETUP_INIT, 989 990 HAL_MON_TX_MPDU_START, 991 HAL_MON_TX_MSDU_START, 992 HAL_MON_TX_BUFFER_ADDR, 993 HAL_MON_TX_DATA, 994 995 HAL_MON_TX_FES_STATUS_START, 996 997 HAL_MON_TX_FES_STATUS_PROT, 998 HAL_MON_TX_FES_STATUS_START_PROT, 999 1000 HAL_MON_TX_FES_STATUS_START_PPDU, 1001 HAL_MON_TX_FES_STATUS_USER_PPDU, 1002 HAL_MON_TX_QUEUE_EXTENSION, 1003 1004 HAL_MON_RX_FRAME_BITMAP_ACK, 1005 HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_256, 1006 HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K, 1007 HAL_MON_COEX_TX_STATUS, 1008 1009 HAL_MON_MACTX_HE_SIG_A_SU, 1010 HAL_MON_MACTX_HE_SIG_A_MU_DL, 1011 HAL_MON_MACTX_HE_SIG_B1_MU, 1012 HAL_MON_MACTX_HE_SIG_B2_MU, 1013 HAL_MON_MACTX_HE_SIG_B2_OFDMA, 1014 HAL_MON_MACTX_L_SIG_A, 1015 HAL_MON_MACTX_L_SIG_B, 1016 HAL_MON_MACTX_HT_SIG, 1017 HAL_MON_MACTX_VHT_SIG_A, 1018 1019 HAL_MON_MACTX_USER_DESC_PER_USER, 1020 HAL_MON_MACTX_USER_DESC_COMMON, 1021 HAL_MON_MACTX_PHY_DESC, 1022 1023 HAL_MON_TX_FW2SW, 1024 HAL_MON_TX_STATUS_PPDU_NOT_DONE, 1025 }; 1026 1027 enum txmon_coex_tx_status_reason { 1028 COEX_FES_TX_START, 1029 COEX_FES_TX_END, 1030 COEX_FES_END, 1031 COEX_RESPONSE_TX_START, 1032 COEX_RESPONSE_TX_END, 1033 COEX_NO_TX_ONGOING, 1034 }; 1035 1036 enum txmon_transmission_type { 1037 TXMON_SU_TRANSMISSION = 0, 1038 TXMON_MU_TRANSMISSION, 1039 TXMON_MU_SU_TRANSMISSION, 1040 TXMON_MU_MIMO_TRANSMISSION = 1, 1041 TXMON_MU_OFDMA_TRANMISSION 1042 }; 1043 1044 enum txmon_he_ppdu_subtype { 1045 TXMON_HE_SUBTYPE_SU = 0, 1046 TXMON_HE_SUBTYPE_TRIG, 1047 TXMON_HE_SUBTYPE_MU, 1048 TXMON_HE_SUBTYPE_EXT_SU 1049 }; 1050 1051 enum txmon_pkt_type { 1052 TXMON_PKT_TYPE_11A = 0, 1053 TXMON_PKT_TYPE_11B, 1054 TXMON_PKT_TYPE_11N_MM, 1055 TXMON_PKT_TYPE_11AC, 1056 TXMON_PKT_TYPE_11AX, 1057 TXMON_PKT_TYPE_11BA, 1058 TXMON_PKT_TYPE_11BE, 1059 TXMON_PKT_TYPE_11AZ 1060 }; 1061 1062 enum txmon_generated_response { 1063 TXMON_GEN_RESP_SELFGEN_ACK = 0, 1064 TXMON_GEN_RESP_SELFGEN_CTS, 1065 TXMON_GEN_RESP_SELFGEN_BA, 1066 TXMON_GEN_RESP_SELFGEN_MBA, 1067 TXMON_GEN_RESP_SELFGEN_CBF, 1068 TXMON_GEN_RESP_SELFGEN_TRIG, 1069 TXMON_GEN_RESP_SELFGEN_NDP_LMR 1070 }; 1071 1072 #define IS_MULTI_USERS(num_users) (!!(0xFFFE & num_users)) 1073 1074 #define TXMON_HAL(hal_tx_ppdu_info, field) \ 1075 hal_tx_ppdu_info->field 1076 #define TXMON_HAL_STATUS(hal_tx_ppdu_info, field) \ 1077 hal_tx_ppdu_info->rx_status.field 1078 #define TXMON_HAL_USER(hal_tx_ppdu_info, user_id, field) \ 1079 hal_tx_ppdu_info->rx_user_status[user_id].field 1080 1081 #define TXMON_STATUS_INFO(hal_tx_status_info, field) \ 1082 hal_tx_status_info->field 1083 1084 /** 1085 * struct hal_tx_status_info - status info that wasn't populated in rx_status 1086 * @reception_type: su or uplink mu reception type 1087 * @transmission_type: su or mu transmission type 1088 * @medium_prot_type: medium protection type 1089 * @generated_response: Generated frame in response window 1090 * @no_bitmap_avail: Bitmap available flag 1091 * @explicit_ack: Explicit Acknowledge flag 1092 * @explicit_ack_type: Explicit Acknowledge type 1093 * @r2r_end_status_follow: Response to Response status flag 1094 * @response_type: Response type in response window 1095 * @ndp_frame: NDP frame 1096 * @num_users: number of users 1097 * @sw_frame_group_id: software frame group ID 1098 * @r2r_to_follow: Response to Response follow flag 1099 * @buffer: Packet buffer pointer address 1100 * @offset: Packet buffer offset 1101 * @length: Packet buffer length 1102 * @protection_addr: Protection Address flag 1103 * @addr1: MAC address 1 1104 * @addr2: MAC address 2 1105 * @addr3: MAC address 3 1106 * @addr4: MAC address 4 1107 */ 1108 struct hal_tx_status_info { 1109 uint8_t reception_type; 1110 uint8_t transmission_type; 1111 uint8_t medium_prot_type; 1112 uint8_t generated_response; 1113 1114 uint16_t band_center_freq1; 1115 uint16_t band_center_freq2; 1116 uint16_t freq; 1117 uint16_t phy_mode; 1118 uint32_t schedule_id; 1119 1120 uint32_t no_bitmap_avail :1, 1121 explicit_ack :1, 1122 explicit_ack_type :4, 1123 r2r_end_status_follow :1, 1124 response_type :5, 1125 ndp_frame :2, 1126 num_users :8, 1127 reserved :10; 1128 1129 uint8_t mba_count; 1130 uint8_t mba_fake_bitmap_count; 1131 1132 uint8_t sw_frame_group_id; 1133 uint32_t r2r_to_follow; 1134 1135 uint16_t phy_abort_reason; 1136 uint8_t phy_abort_user_number; 1137 1138 void *buffer; 1139 uint32_t offset; 1140 uint32_t length; 1141 1142 uint8_t protection_addr; 1143 uint8_t addr1[QDF_MAC_ADDR_SIZE]; 1144 uint8_t addr2[QDF_MAC_ADDR_SIZE]; 1145 uint8_t addr3[QDF_MAC_ADDR_SIZE]; 1146 uint8_t addr4[QDF_MAC_ADDR_SIZE]; 1147 }; 1148 1149 /** 1150 * struct hal_tx_ppdu_info - tx monitor ppdu information 1151 * @ppdu_id: Id of the PLCP protocol data unit 1152 * @num_users: number of users 1153 * @is_used: boolean flag to identify valid ppdu info 1154 * @is_data: boolean flag to identify data frame 1155 * @cur_usr_idx: Current user index of the PPDU 1156 * @reserved: for future purpose 1157 * @prot_tlv_status: protection tlv status 1158 * @packet_info: packet information 1159 * @rx_status: monitor mode rx status information 1160 * @rx_user_status: monitor mode rx user status information 1161 */ 1162 struct hal_tx_ppdu_info { 1163 uint32_t ppdu_id; 1164 uint32_t num_users :8, 1165 is_used :1, 1166 is_data :1, 1167 cur_usr_idx :8, 1168 reserved :15; 1169 1170 uint32_t prot_tlv_status; 1171 1172 /* placeholder to hold packet buffer info */ 1173 struct hal_mon_packet_info packet_info; 1174 struct mon_rx_status rx_status; 1175 struct mon_rx_user_status rx_user_status[]; 1176 }; 1177 1178 /** 1179 * hal_tx_status_get_next_tlv() - get next tx status TLV 1180 * @tx_tlv: pointer to TLV header 1181 * 1182 * Return: pointer to next tlv info 1183 */ 1184 static inline uint8_t* 1185 hal_tx_status_get_next_tlv(uint8_t *tx_tlv) { 1186 uint32_t tlv_len, tlv_tag; 1187 1188 tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv); 1189 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv); 1190 1191 return (uint8_t *)(((unsigned long)(tx_tlv + tlv_len + 1192 HAL_RX_TLV32_HDR_SIZE + 7)) & (~7)); 1193 } 1194 1195 /** 1196 * hal_txmon_status_parse_tlv() - process transmit info TLV 1197 * @hal_soc: HAL soc handle 1198 * @data_ppdu_info: pointer to hal data ppdu info 1199 * @prot_ppdu_info: pointer to hal prot ppdu info 1200 * @data_status_info: pointer to data status info 1201 * @prot_status_info: pointer to prot status info 1202 * @tx_tlv_hdr: pointer to TLV header 1203 * @status_frag: pointer to status frag 1204 * 1205 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE 1206 */ 1207 static inline uint32_t 1208 hal_txmon_status_parse_tlv(hal_soc_handle_t hal_soc_hdl, 1209 void *data_ppdu_info, 1210 void *prot_ppdu_info, 1211 void *data_status_info, 1212 void *prot_status_info, 1213 void *tx_tlv_hdr, 1214 qdf_frag_t status_frag) 1215 { 1216 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1217 1218 return hal_soc->ops->hal_txmon_status_parse_tlv(data_ppdu_info, 1219 prot_ppdu_info, 1220 data_status_info, 1221 prot_status_info, 1222 tx_tlv_hdr, 1223 status_frag); 1224 } 1225 1226 /** 1227 * hal_txmon_status_get_num_users() - api to get num users from start of fes 1228 * window 1229 * @hal_soc: HAL soc handle 1230 * @tx_tlv_hdr: pointer to TLV header 1231 * @num_users: reference to number of user 1232 * 1233 * Return: status 1234 */ 1235 static inline uint32_t 1236 hal_txmon_status_get_num_users(hal_soc_handle_t hal_soc_hdl, 1237 void *tx_tlv_hdr, uint8_t *num_users) 1238 { 1239 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1240 1241 return hal_soc->ops->hal_txmon_status_get_num_users(tx_tlv_hdr, 1242 num_users); 1243 } 1244 1245 /** 1246 * hal_tx_status_get_tlv_tag() - api to get tlv tag 1247 * @tx_tlv_hdr: pointer to TLV header 1248 * 1249 * Return tlv_tag 1250 */ 1251 static inline uint32_t 1252 hal_tx_status_get_tlv_tag(void *tx_tlv_hdr) 1253 { 1254 uint32_t tlv_tag = 0; 1255 1256 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr); 1257 1258 return tlv_tag; 1259 } 1260 #endif 1261 1262 /** 1263 * hal_txmon_is_mon_buf_addr_tlv() - api to find packet buffer addr tlv 1264 * @hal_soc: HAL soc handle 1265 * @tx_tlv_hdr: pointer to TLV header 1266 * 1267 * Return: bool 1268 */ 1269 static inline bool 1270 hal_txmon_is_mon_buf_addr_tlv(hal_soc_handle_t hal_soc_hdl, void *tx_tlv_hdr) 1271 { 1272 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1273 1274 if (qdf_unlikely(!hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv)) 1275 return false; 1276 1277 return hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv(tx_tlv_hdr); 1278 } 1279 1280 /** 1281 * hal_txmon_populate_packet_info() - api to populate packet info 1282 * @hal_soc: HAL soc handle 1283 * @tx_tlv_hdr: pointer to TLV header 1284 * @packet_info: pointer to placeholder for packet info 1285 * 1286 * Return void 1287 */ 1288 static inline void 1289 hal_txmon_populate_packet_info(hal_soc_handle_t hal_soc_hdl, 1290 void *tx_tlv_hdr, 1291 void *packet_info) 1292 { 1293 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1294 1295 if (qdf_unlikely(!hal_soc->ops->hal_txmon_populate_packet_info)) 1296 return; 1297 1298 hal_soc->ops->hal_txmon_populate_packet_info(tx_tlv_hdr, packet_info); 1299 } 1300 1301 static inline uint32_t 1302 hal_rx_parse_u_sig_cmn(struct hal_soc *hal_soc, void *rx_tlv, 1303 struct hal_rx_ppdu_info *ppdu_info) 1304 { 1305 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1306 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 1307 uint8_t bad_usig_crc; 1308 1309 bad_usig_crc = HAL_RX_MON_USIG_GET_RX_INTEGRITY_CHECK_PASSED(rx_tlv) ? 1310 0 : 1; 1311 ppdu_info->rx_status.usig_common |= 1312 QDF_MON_STATUS_USIG_PHY_VERSION_KNOWN | 1313 QDF_MON_STATUS_USIG_BW_KNOWN | 1314 QDF_MON_STATUS_USIG_UL_DL_KNOWN | 1315 QDF_MON_STATUS_USIG_BSS_COLOR_KNOWN | 1316 QDF_MON_STATUS_USIG_TXOP_KNOWN; 1317 1318 ppdu_info->rx_status.usig_common |= (usig_1->phy_version << 1319 QDF_MON_STATUS_USIG_PHY_VERSION_SHIFT); 1320 ppdu_info->rx_status.usig_common |= (usig_1->bw << 1321 QDF_MON_STATUS_USIG_BW_SHIFT); 1322 ppdu_info->rx_status.usig_common |= (usig_1->ul_dl << 1323 QDF_MON_STATUS_USIG_UL_DL_SHIFT); 1324 ppdu_info->rx_status.usig_common |= (usig_1->bss_color << 1325 QDF_MON_STATUS_USIG_BSS_COLOR_SHIFT); 1326 ppdu_info->rx_status.usig_common |= (usig_1->txop << 1327 QDF_MON_STATUS_USIG_TXOP_SHIFT); 1328 ppdu_info->rx_status.usig_common |= bad_usig_crc; 1329 1330 ppdu_info->u_sig_info.ul_dl = usig_1->ul_dl; 1331 ppdu_info->u_sig_info.bw = usig_1->bw; 1332 ppdu_info->rx_status.bw = usig_1->bw; 1333 1334 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1335 } 1336 1337 static inline uint32_t 1338 hal_rx_parse_u_sig_tb(struct hal_soc *hal_soc, void *rx_tlv, 1339 struct hal_rx_ppdu_info *ppdu_info) 1340 { 1341 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1342 struct hal_mon_usig_tb *usig_tb = &usig->usig_2.tb; 1343 1344 ppdu_info->rx_status.usig_mask |= 1345 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 1346 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 1347 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 1348 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_KNOWN | 1349 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_KNOWN | 1350 QDF_MON_STATUS_USIG_TB_DISREGARD1_KNOWN | 1351 QDF_MON_STATUS_USIG_CRC_KNOWN | 1352 QDF_MON_STATUS_USIG_TAIL_KNOWN; 1353 1354 ppdu_info->rx_status.usig_value |= (0x3F << 1355 QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 1356 ppdu_info->rx_status.usig_value |= (usig_tb->ppdu_type_comp_mode << 1357 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 1358 ppdu_info->rx_status.usig_value |= (0x1 << 1359 QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 1360 ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_1 << 1361 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_SHIFT); 1362 ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_2 << 1363 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_SHIFT); 1364 ppdu_info->rx_status.usig_value |= (0x1F << 1365 QDF_MON_STATUS_USIG_TB_DISREGARD1_SHIFT); 1366 ppdu_info->rx_status.usig_value |= (usig_tb->crc << 1367 QDF_MON_STATUS_USIG_CRC_SHIFT); 1368 ppdu_info->rx_status.usig_value |= (usig_tb->tail << 1369 QDF_MON_STATUS_USIG_TAIL_SHIFT); 1370 1371 ppdu_info->u_sig_info.ppdu_type_comp_mode = 1372 usig_tb->ppdu_type_comp_mode; 1373 1374 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1375 } 1376 1377 static inline uint32_t 1378 hal_rx_parse_u_sig_mu(struct hal_soc *hal_soc, void *rx_tlv, 1379 struct hal_rx_ppdu_info *ppdu_info) 1380 { 1381 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1382 struct hal_mon_usig_mu *usig_mu = &usig->usig_2.mu; 1383 1384 ppdu_info->rx_status.usig_mask |= 1385 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 1386 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 1387 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 1388 QDF_MON_STATUS_USIG_MU_VALIDATE1_KNOWN | 1389 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_KNOWN | 1390 QDF_MON_STATUS_USIG_MU_VALIDATE2_KNOWN | 1391 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_KNOWN | 1392 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_KNOWN | 1393 QDF_MON_STATUS_USIG_CRC_KNOWN | 1394 QDF_MON_STATUS_USIG_TAIL_KNOWN; 1395 1396 ppdu_info->rx_status.usig_value |= (0x1F << 1397 QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 1398 ppdu_info->rx_status.usig_value |= (0x1 << 1399 QDF_MON_STATUS_USIG_MU_VALIDATE1_SHIFT); 1400 ppdu_info->rx_status.usig_value |= (usig_mu->ppdu_type_comp_mode << 1401 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 1402 ppdu_info->rx_status.usig_value |= (0x1 << 1403 QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 1404 ppdu_info->rx_status.usig_value |= (usig_mu->punc_ch_info << 1405 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_SHIFT); 1406 ppdu_info->rx_status.usig_value |= (0x1 << 1407 QDF_MON_STATUS_USIG_MU_VALIDATE2_SHIFT); 1408 ppdu_info->rx_status.usig_value |= (usig_mu->eht_sig_mcs << 1409 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_SHIFT); 1410 ppdu_info->rx_status.usig_value |= (usig_mu->num_eht_sig_sym << 1411 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_SHIFT); 1412 ppdu_info->rx_status.usig_value |= (usig_mu->crc << 1413 QDF_MON_STATUS_USIG_CRC_SHIFT); 1414 ppdu_info->rx_status.usig_value |= (usig_mu->tail << 1415 QDF_MON_STATUS_USIG_TAIL_SHIFT); 1416 1417 ppdu_info->u_sig_info.ppdu_type_comp_mode = 1418 usig_mu->ppdu_type_comp_mode; 1419 ppdu_info->u_sig_info.eht_sig_mcs = usig_mu->eht_sig_mcs; 1420 ppdu_info->u_sig_info.num_eht_sig_sym = usig_mu->num_eht_sig_sym; 1421 1422 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1423 } 1424 1425 static inline uint32_t 1426 hal_rx_parse_u_sig_hdr(struct hal_soc *hal_soc, void *rx_tlv, 1427 struct hal_rx_ppdu_info *ppdu_info) 1428 { 1429 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1430 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 1431 1432 ppdu_info->rx_status.usig_flags = 1; 1433 1434 hal_rx_parse_u_sig_cmn(hal_soc, rx_tlv, ppdu_info); 1435 1436 if (HAL_RX_MON_USIG_GET_PPDU_TYPE_N_COMP_MODE(rx_tlv) == 0 && 1437 usig_1->ul_dl == 1) 1438 return hal_rx_parse_u_sig_tb(hal_soc, rx_tlv, ppdu_info); 1439 else 1440 return hal_rx_parse_u_sig_mu(hal_soc, rx_tlv, ppdu_info); 1441 } 1442 1443 static inline uint32_t 1444 hal_rx_parse_usig_overflow(struct hal_soc *hal_soc, void *tlv, 1445 struct hal_rx_ppdu_info *ppdu_info) 1446 { 1447 struct hal_eht_sig_cc_usig_overflow *usig_ovflow = 1448 (struct hal_eht_sig_cc_usig_overflow *)tlv; 1449 1450 ppdu_info->rx_status.eht_known |= 1451 QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1452 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1453 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_KNOWN | 1454 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_KNOWN | 1455 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_KNOWN | 1456 QDF_MON_STATUS_EHT_DISREARD_KNOWN; 1457 1458 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->spatial_reuse << 1459 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1460 /* 1461 * GI and LTF size are separately indicated in radiotap header 1462 * and hence will be parsed from other TLV 1463 **/ 1464 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->num_ltf_sym << 1465 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1466 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->ldpc_extra_sym << 1467 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_SHIFT); 1468 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pre_fec_pad_factor << 1469 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_SHIFT); 1470 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pe_disambiguity << 1471 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_SHIFT); 1472 ppdu_info->rx_status.eht_data[0] |= (0xF << 1473 QDF_MON_STATUS_EHT_DISREGARD_SHIFT); 1474 1475 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1476 } 1477 1478 static inline uint32_t 1479 hal_rx_parse_non_ofdma_users(struct hal_soc *hal_soc, void *tlv, 1480 struct hal_rx_ppdu_info *ppdu_info) 1481 { 1482 struct hal_eht_sig_non_ofdma_cmn_eb *non_ofdma_cmn_eb = 1483 (struct hal_eht_sig_non_ofdma_cmn_eb *)tlv; 1484 1485 ppdu_info->rx_status.eht_known |= 1486 QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_KNOWN; 1487 1488 ppdu_info->rx_status.eht_data[4] |= (non_ofdma_cmn_eb->num_users << 1489 QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_SHIFT); 1490 1491 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1492 } 1493 1494 static inline uint32_t 1495 hal_rx_parse_ru_allocation(struct hal_soc *hal_soc, void *tlv, 1496 struct hal_rx_ppdu_info *ppdu_info) 1497 { 1498 uint64_t *ehtsig_tlv = (uint64_t *)tlv; 1499 struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cmn_eb1; 1500 struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cmn_eb2; 1501 uint8_t num_ru_allocation_known = 0; 1502 1503 ofdma_cmn_eb1 = (struct hal_eht_sig_ofdma_cmn_eb1 *)ehtsig_tlv; 1504 ofdma_cmn_eb2 = (struct hal_eht_sig_ofdma_cmn_eb2 *)(ehtsig_tlv + 1); 1505 1506 switch (ppdu_info->u_sig_info.bw) { 1507 case HAL_EHT_BW_320_2: 1508 case HAL_EHT_BW_320_1: 1509 num_ru_allocation_known += 4; 1510 1511 ppdu_info->rx_status.eht_data[3] |= 1512 (ofdma_cmn_eb2->ru_allocation2_6 << 1513 QDF_MON_STATUS_EHT_RU_ALLOCATION2_6_SHIFT); 1514 ppdu_info->rx_status.eht_data[3] |= 1515 (ofdma_cmn_eb2->ru_allocation2_5 << 1516 QDF_MON_STATUS_EHT_RU_ALLOCATION2_5_SHIFT); 1517 ppdu_info->rx_status.eht_data[3] |= 1518 (ofdma_cmn_eb2->ru_allocation2_4 << 1519 QDF_MON_STATUS_EHT_RU_ALLOCATION2_4_SHIFT); 1520 ppdu_info->rx_status.eht_data[2] |= 1521 (ofdma_cmn_eb2->ru_allocation2_3 << 1522 QDF_MON_STATUS_EHT_RU_ALLOCATION2_3_SHIFT); 1523 fallthrough; 1524 case HAL_EHT_BW_160: 1525 num_ru_allocation_known += 2; 1526 1527 ppdu_info->rx_status.eht_data[2] |= 1528 (ofdma_cmn_eb2->ru_allocation2_2 << 1529 QDF_MON_STATUS_EHT_RU_ALLOCATION2_2_SHIFT); 1530 ppdu_info->rx_status.eht_data[2] |= 1531 (ofdma_cmn_eb2->ru_allocation2_1 << 1532 QDF_MON_STATUS_EHT_RU_ALLOCATION2_1_SHIFT); 1533 fallthrough; 1534 case HAL_EHT_BW_80: 1535 num_ru_allocation_known += 1; 1536 1537 ppdu_info->rx_status.eht_data[1] |= 1538 (ofdma_cmn_eb1->ru_allocation1_2 << 1539 QDF_MON_STATUS_EHT_RU_ALLOCATION1_2_SHIFT); 1540 fallthrough; 1541 case HAL_EHT_BW_40: 1542 case HAL_EHT_BW_20: 1543 num_ru_allocation_known += 1; 1544 1545 ppdu_info->rx_status.eht_data[1] |= 1546 (ofdma_cmn_eb1->ru_allocation1_1 << 1547 QDF_MON_STATUS_EHT_RU_ALLOCATION1_1_SHIFT); 1548 break; 1549 default: 1550 break; 1551 } 1552 1553 ppdu_info->rx_status.eht_known |= (num_ru_allocation_known << 1554 QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT); 1555 1556 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1557 } 1558 1559 static inline uint32_t 1560 hal_rx_parse_eht_sig_mumimo_user_info(struct hal_soc *hal_soc, void *tlv, 1561 struct hal_rx_ppdu_info *ppdu_info) 1562 { 1563 struct hal_eht_sig_mu_mimo_user_info *user_info; 1564 uint32_t user_idx = ppdu_info->rx_status.num_eht_user_info_valid; 1565 1566 user_info = (struct hal_eht_sig_mu_mimo_user_info *)tlv; 1567 1568 ppdu_info->rx_status.eht_user_info[user_idx] |= 1569 QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1570 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1571 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1572 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_KNOWN; 1573 1574 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->sta_id << 1575 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1576 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->mcs << 1577 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1578 ppdu_info->rx_status.mcs = user_info->mcs; 1579 1580 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->coding << 1581 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1582 ppdu_info->rx_status.eht_user_info[user_idx] |= 1583 (user_info->spatial_coding << 1584 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_SHIFT); 1585 1586 /* CRC for matched user block */ 1587 ppdu_info->rx_status.eht_known |= 1588 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN | 1589 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN; 1590 ppdu_info->rx_status.eht_data[4] |= (user_info->crc << 1591 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT); 1592 1593 ppdu_info->rx_status.num_eht_user_info_valid++; 1594 1595 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1596 } 1597 1598 static inline uint32_t 1599 hal_rx_parse_eht_sig_non_mumimo_user_info(struct hal_soc *hal_soc, void *tlv, 1600 struct hal_rx_ppdu_info *ppdu_info) 1601 { 1602 struct hal_eht_sig_non_mu_mimo_user_info *user_info; 1603 uint32_t user_idx = ppdu_info->rx_status.num_eht_user_info_valid; 1604 1605 user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tlv; 1606 1607 ppdu_info->rx_status.eht_user_info[user_idx] |= 1608 QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1609 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1610 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1611 QDF_MON_STATUS_EHT_USER_NSS_KNOWN | 1612 QDF_MON_STATUS_EHT_USER_BEAMFORMING_KNOWN; 1613 1614 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->sta_id << 1615 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1616 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->mcs << 1617 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1618 ppdu_info->rx_status.mcs = user_info->mcs; 1619 1620 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->nss << 1621 QDF_MON_STATUS_EHT_USER_NSS_SHIFT); 1622 ppdu_info->rx_status.nss = user_info->nss + 1; 1623 1624 ppdu_info->rx_status.eht_user_info[user_idx] |= 1625 (user_info->beamformed << 1626 QDF_MON_STATUS_EHT_USER_BEAMFORMING_SHIFT); 1627 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->coding << 1628 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1629 1630 /* CRC for matched user block */ 1631 ppdu_info->rx_status.eht_known |= 1632 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN | 1633 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN; 1634 ppdu_info->rx_status.eht_data[4] |= (user_info->crc << 1635 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT); 1636 1637 ppdu_info->rx_status.num_eht_user_info_valid++; 1638 1639 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1640 } 1641 1642 static inline bool hal_rx_is_ofdma(struct hal_soc *hal_soc, 1643 struct hal_rx_ppdu_info *ppdu_info) 1644 { 1645 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 0 && 1646 ppdu_info->u_sig_info.ul_dl == 0) 1647 return true; 1648 1649 return false; 1650 } 1651 1652 static inline bool hal_rx_is_non_ofdma(struct hal_soc *hal_soc, 1653 struct hal_rx_ppdu_info *ppdu_info) 1654 { 1655 uint32_t ppdu_type_comp_mode = 1656 ppdu_info->u_sig_info.ppdu_type_comp_mode; 1657 uint32_t ul_dl = ppdu_info->u_sig_info.ul_dl; 1658 1659 if ((ppdu_type_comp_mode == 1 && ul_dl == 0) || 1660 (ppdu_type_comp_mode == 2 && ul_dl == 0) || 1661 (ppdu_type_comp_mode == 1 && ul_dl == 1)) 1662 return true; 1663 1664 return false; 1665 } 1666 1667 static inline bool hal_rx_is_mu_mimo_user(struct hal_soc *hal_soc, 1668 struct hal_rx_ppdu_info *ppdu_info) 1669 { 1670 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 2 && 1671 ppdu_info->u_sig_info.ul_dl == 0) 1672 return true; 1673 1674 return false; 1675 } 1676 1677 static inline bool 1678 hal_rx_is_frame_type_ndp(struct hal_soc *hal_soc, 1679 struct hal_rx_ppdu_info *ppdu_info) 1680 { 1681 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 1 && 1682 ppdu_info->u_sig_info.eht_sig_mcs == 0 && 1683 ppdu_info->u_sig_info.num_eht_sig_sym == 0) 1684 return true; 1685 1686 return false; 1687 } 1688 1689 static inline uint32_t 1690 hal_rx_parse_eht_sig_ndp(struct hal_soc *hal_soc, void *tlv, 1691 struct hal_rx_ppdu_info *ppdu_info) 1692 { 1693 struct hal_eht_sig_ndp_cmn_eb *eht_sig_ndp = 1694 (struct hal_eht_sig_ndp_cmn_eb *)tlv; 1695 1696 ppdu_info->rx_status.eht_known |= 1697 QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1698 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1699 QDF_MON_STATUS_EHT_NDP_NSS_KNOWN | 1700 QDF_MON_STATUS_EHT_NDP_BEAMFORMED_KNOWN | 1701 QDF_MON_STATUS_EHT_NDP_DISREGARD_KNOWN | 1702 QDF_MON_STATUS_EHT_CRC1_KNOWN | 1703 QDF_MON_STATUS_EHT_TAIL1_KNOWN; 1704 1705 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->spatial_reuse << 1706 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1707 /* 1708 * GI and LTF size are separately indicated in radiotap header 1709 * and hence will be parsed from other TLV 1710 **/ 1711 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->num_ltf_sym << 1712 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1713 ppdu_info->rx_status.eht_data[0] |= (0xF << 1714 QDF_MON_STATUS_EHT_NDP_DISREGARD_SHIFT); 1715 1716 ppdu_info->rx_status.eht_data[4] |= (eht_sig_ndp->nss << 1717 QDF_MON_STATUS_EHT_NDP_NSS_SHIFT); 1718 ppdu_info->rx_status.eht_data[4] |= (eht_sig_ndp->beamformed << 1719 QDF_MON_STATUS_EHT_NDP_BEAMFORMED_SHIFT); 1720 1721 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->crc << 1722 QDF_MON_STATUS_EHT_CRC1_SHIFT); 1723 1724 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1725 } 1726 1727 static inline uint32_t 1728 hal_rx_parse_eht_sig_non_ofdma(struct hal_soc *hal_soc, void *tlv, 1729 struct hal_rx_ppdu_info *ppdu_info) 1730 { 1731 void *user_info = (void *)((uint8_t *)tlv + 4); 1732 1733 hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info); 1734 hal_rx_parse_non_ofdma_users(hal_soc, tlv, ppdu_info); 1735 1736 if (hal_rx_is_mu_mimo_user(hal_soc, ppdu_info)) 1737 hal_rx_parse_eht_sig_mumimo_user_info(hal_soc, user_info, 1738 ppdu_info); 1739 else 1740 hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, user_info, 1741 ppdu_info); 1742 1743 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1744 } 1745 1746 static inline uint32_t 1747 hal_rx_parse_eht_sig_ofdma(struct hal_soc *hal_soc, void *tlv, 1748 struct hal_rx_ppdu_info *ppdu_info) 1749 { 1750 uint64_t *eht_sig_tlv = (uint64_t *)tlv; 1751 void *user_info = (void *)(eht_sig_tlv + 2); 1752 1753 hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info); 1754 hal_rx_parse_ru_allocation(hal_soc, tlv, ppdu_info); 1755 hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, user_info, 1756 ppdu_info); 1757 1758 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1759 } 1760 1761 static inline uint32_t 1762 hal_rx_parse_eht_sig_hdr(struct hal_soc *hal_soc, uint8_t *tlv, 1763 struct hal_rx_ppdu_info *ppdu_info) 1764 { 1765 ppdu_info->rx_status.eht_flags = 1; 1766 1767 if (hal_rx_is_frame_type_ndp(hal_soc, ppdu_info)) 1768 hal_rx_parse_eht_sig_ndp(hal_soc, tlv, ppdu_info); 1769 else if (hal_rx_is_non_ofdma(hal_soc, ppdu_info)) 1770 hal_rx_parse_eht_sig_non_ofdma(hal_soc, tlv, ppdu_info); 1771 else if (hal_rx_is_ofdma(hal_soc, ppdu_info)) 1772 hal_rx_parse_eht_sig_ofdma(hal_soc, tlv, ppdu_info); 1773 1774 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1775 } 1776 1777 #ifdef WLAN_FEATURE_11BE 1778 static inline void 1779 hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info, 1780 struct hal_rx_ppdu_info *ppdu_info) 1781 { 1782 ppdu_info->rx_status.punctured_pattern = cmn_usr_info->puncture_bitmap; 1783 } 1784 #else 1785 static inline void 1786 hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info, 1787 struct hal_rx_ppdu_info *ppdu_info) 1788 { 1789 } 1790 #endif 1791 static inline uint32_t 1792 hal_rx_parse_cmn_usr_info(struct hal_soc *hal_soc, uint8_t *tlv, 1793 struct hal_rx_ppdu_info *ppdu_info) 1794 { 1795 struct phyrx_common_user_info *cmn_usr_info = 1796 (struct phyrx_common_user_info *)tlv; 1797 1798 ppdu_info->rx_status.eht_known |= 1799 QDF_MON_STATUS_EHT_GUARD_INTERVAL_KNOWN | 1800 QDF_MON_STATUS_EHT_LTF_KNOWN; 1801 1802 ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->cp_setting << 1803 QDF_MON_STATUS_EHT_GI_SHIFT); 1804 if (!ppdu_info->rx_status.sgi) 1805 ppdu_info->rx_status.sgi = cmn_usr_info->cp_setting; 1806 1807 ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->ltf_size << 1808 QDF_MON_STATUS_EHT_LTF_SHIFT); 1809 if (!ppdu_info->rx_status.ltf_size) 1810 ppdu_info->rx_status.ltf_size = cmn_usr_info->ltf_size; 1811 1812 hal_rx_parse_punctured_pattern(cmn_usr_info, ppdu_info); 1813 1814 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1815 } 1816 1817 #ifdef WLAN_FEATURE_11BE 1818 static inline void 1819 hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size, 1820 uint32_t *ru_width) 1821 { 1822 uint32_t width; 1823 1824 width = 0; 1825 switch (ru_size) { 1826 case IEEE80211_EHT_RU_26: 1827 width = RU_26; 1828 break; 1829 case IEEE80211_EHT_RU_52: 1830 width = RU_52; 1831 break; 1832 case IEEE80211_EHT_RU_52_26: 1833 width = RU_52_26; 1834 break; 1835 case IEEE80211_EHT_RU_106: 1836 width = RU_106; 1837 break; 1838 case IEEE80211_EHT_RU_106_26: 1839 width = RU_106_26; 1840 break; 1841 case IEEE80211_EHT_RU_242: 1842 width = RU_242; 1843 break; 1844 case IEEE80211_EHT_RU_484: 1845 width = RU_484; 1846 break; 1847 case IEEE80211_EHT_RU_484_242: 1848 width = RU_484_242; 1849 break; 1850 case IEEE80211_EHT_RU_996: 1851 width = RU_996; 1852 break; 1853 case IEEE80211_EHT_RU_996_484: 1854 width = RU_996_484; 1855 break; 1856 case IEEE80211_EHT_RU_996_484_242: 1857 width = RU_996_484_242; 1858 break; 1859 case IEEE80211_EHT_RU_996x2: 1860 width = RU_2X996; 1861 break; 1862 case IEEE80211_EHT_RU_996x2_484: 1863 width = RU_2X996_484; 1864 break; 1865 case IEEE80211_EHT_RU_996x3: 1866 width = RU_3X996; 1867 break; 1868 case IEEE80211_EHT_RU_996x3_484: 1869 width = RU_3X996_484; 1870 break; 1871 case IEEE80211_EHT_RU_996x4: 1872 width = RU_4X996; 1873 break; 1874 default: 1875 hal_err_rl("RU size(%d) to width convert err", ru_size); 1876 break; 1877 } 1878 *ru_width = width; 1879 } 1880 #else 1881 static inline void 1882 hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size, 1883 uint32_t *ru_width) 1884 { 1885 *ru_width = 0; 1886 } 1887 #endif 1888 1889 static inline enum ieee80211_eht_ru_size 1890 hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(struct hal_soc *hal_soc, 1891 uint32_t hal_ru_size) 1892 { 1893 switch (hal_ru_size) { 1894 case HAL_EHT_RU_26: 1895 return IEEE80211_EHT_RU_26; 1896 case HAL_EHT_RU_52: 1897 return IEEE80211_EHT_RU_52; 1898 case HAL_EHT_RU_78: 1899 return IEEE80211_EHT_RU_52_26; 1900 case HAL_EHT_RU_106: 1901 return IEEE80211_EHT_RU_106; 1902 case HAL_EHT_RU_132: 1903 return IEEE80211_EHT_RU_106_26; 1904 case HAL_EHT_RU_242: 1905 return IEEE80211_EHT_RU_242; 1906 case HAL_EHT_RU_484: 1907 return IEEE80211_EHT_RU_484; 1908 case HAL_EHT_RU_726: 1909 return IEEE80211_EHT_RU_484_242; 1910 case HAL_EHT_RU_996: 1911 return IEEE80211_EHT_RU_996; 1912 case HAL_EHT_RU_996x2: 1913 return IEEE80211_EHT_RU_996x2; 1914 case HAL_EHT_RU_996x3: 1915 return IEEE80211_EHT_RU_996x3; 1916 case HAL_EHT_RU_996x4: 1917 return IEEE80211_EHT_RU_996x4; 1918 case HAL_EHT_RU_NONE: 1919 return IEEE80211_EHT_RU_INVALID; 1920 case HAL_EHT_RU_996_484: 1921 return IEEE80211_EHT_RU_996_484; 1922 case HAL_EHT_RU_996x2_484: 1923 return IEEE80211_EHT_RU_996x2_484; 1924 case HAL_EHT_RU_996x3_484: 1925 return IEEE80211_EHT_RU_996x3_484; 1926 case HAL_EHT_RU_996_484_242: 1927 return IEEE80211_EHT_RU_996_484_242; 1928 default: 1929 return IEEE80211_EHT_RU_INVALID; 1930 } 1931 } 1932 1933 #define HAL_SET_RU_PER80(ru_320mhz, ru_per80, ru_idx_per80mhz, num_80mhz) \ 1934 ((ru_320mhz) |= ((uint64_t)(ru_per80) << \ 1935 (((num_80mhz) * NUM_RU_BITS_PER80) + \ 1936 ((ru_idx_per80mhz) * NUM_RU_BITS_PER20)))) 1937 1938 static inline uint32_t 1939 hal_rx_parse_receive_user_info(struct hal_soc *hal_soc, uint8_t *tlv, 1940 struct hal_rx_ppdu_info *ppdu_info, 1941 uint32_t user_id) 1942 { 1943 struct receive_user_info *rx_usr_info = (struct receive_user_info *)tlv; 1944 struct mon_rx_user_status *mon_rx_user_status = NULL; 1945 uint64_t ru_index_320mhz = 0; 1946 uint16_t ru_index_per80mhz; 1947 uint32_t ru_size = 0, num_80mhz_with_ru = 0; 1948 uint32_t ru_index = HAL_EHT_RU_INVALID; 1949 uint32_t rtap_ru_size = IEEE80211_EHT_RU_INVALID; 1950 uint32_t ru_width; 1951 1952 ppdu_info->rx_status.eht_known |= 1953 QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_KNOWN; 1954 ppdu_info->rx_status.eht_data[0] |= 1955 (rx_usr_info->dl_ofdma_content_channel << 1956 QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_SHIFT); 1957 1958 switch (rx_usr_info->reception_type) { 1959 case HAL_RECEPTION_TYPE_SU: 1960 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1961 break; 1962 case HAL_RECEPTION_TYPE_DL_MU_MIMO: 1963 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 1964 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1965 break; 1966 case HAL_RECEPTION_TYPE_UL_MU_MIMO: 1967 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 1968 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1969 break; 1970 case HAL_RECEPTION_TYPE_DL_MU_OFMA: 1971 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 1972 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1973 break; 1974 case HAL_RECEPTION_TYPE_UL_MU_OFDMA: 1975 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 1976 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1977 break; 1978 case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO: 1979 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 1980 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA_MIMO; 1981 break; 1982 case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO: 1983 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 1984 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA_MIMO; 1985 break; 1986 } 1987 1988 ppdu_info->start_user_info_cnt++; 1989 1990 ppdu_info->rx_status.is_stbc = rx_usr_info->stbc; 1991 ppdu_info->rx_status.ldpc = rx_usr_info->ldpc; 1992 ppdu_info->rx_status.dcm = rx_usr_info->sta_dcm; 1993 ppdu_info->rx_status.mcs = rx_usr_info->rate_mcs; 1994 ppdu_info->rx_status.nss = rx_usr_info->nss + 1; 1995 1996 if (user_id < HAL_MAX_UL_MU_USERS) { 1997 mon_rx_user_status = 1998 &ppdu_info->rx_user_status[user_id]; 1999 mon_rx_user_status->mcs = ppdu_info->rx_status.mcs; 2000 mon_rx_user_status->nss = ppdu_info->rx_status.nss; 2001 } 2002 2003 if (!(ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_MIMO || 2004 ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA || 2005 ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA_MIMO)) 2006 return HAL_TLV_STATUS_PPDU_NOT_DONE; 2007 2008 /* RU allocation present only for OFDMA reception */ 2009 if (rx_usr_info->ru_type_80_0 != HAL_EHT_RU_NONE) { 2010 ru_size += rx_usr_info->ru_type_80_0; 2011 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_0; 2012 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_0, 2013 ru_index_per80mhz, 0); 2014 num_80mhz_with_ru++; 2015 } 2016 2017 if (rx_usr_info->ru_type_80_1 != HAL_EHT_RU_NONE) { 2018 ru_size += rx_usr_info->ru_type_80_1; 2019 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_1; 2020 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_1, 2021 ru_index_per80mhz, 1); 2022 num_80mhz_with_ru++; 2023 } 2024 2025 if (rx_usr_info->ru_type_80_2 != HAL_EHT_RU_NONE) { 2026 ru_size += rx_usr_info->ru_type_80_2; 2027 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_2; 2028 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_2, 2029 ru_index_per80mhz, 2); 2030 num_80mhz_with_ru++; 2031 } 2032 2033 if (rx_usr_info->ru_type_80_3 != HAL_EHT_RU_NONE) { 2034 ru_size += rx_usr_info->ru_type_80_3; 2035 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_3; 2036 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_3, 2037 ru_index_per80mhz, 3); 2038 num_80mhz_with_ru++; 2039 } 2040 2041 if (num_80mhz_with_ru > 1) { 2042 /* Calculate the MRU index */ 2043 switch (ru_index_320mhz) { 2044 case HAL_EHT_RU_996_484_0: 2045 case HAL_EHT_RU_996x2_484_0: 2046 case HAL_EHT_RU_996x3_484_0: 2047 ru_index = 0; 2048 break; 2049 case HAL_EHT_RU_996_484_1: 2050 case HAL_EHT_RU_996x2_484_1: 2051 case HAL_EHT_RU_996x3_484_1: 2052 ru_index = 1; 2053 break; 2054 case HAL_EHT_RU_996_484_2: 2055 case HAL_EHT_RU_996x2_484_2: 2056 case HAL_EHT_RU_996x3_484_2: 2057 ru_index = 2; 2058 break; 2059 case HAL_EHT_RU_996_484_3: 2060 case HAL_EHT_RU_996x2_484_3: 2061 case HAL_EHT_RU_996x3_484_3: 2062 ru_index = 3; 2063 break; 2064 case HAL_EHT_RU_996_484_4: 2065 case HAL_EHT_RU_996x2_484_4: 2066 case HAL_EHT_RU_996x3_484_4: 2067 ru_index = 4; 2068 break; 2069 case HAL_EHT_RU_996_484_5: 2070 case HAL_EHT_RU_996x2_484_5: 2071 case HAL_EHT_RU_996x3_484_5: 2072 ru_index = 5; 2073 break; 2074 case HAL_EHT_RU_996_484_6: 2075 case HAL_EHT_RU_996x2_484_6: 2076 case HAL_EHT_RU_996x3_484_6: 2077 ru_index = 6; 2078 break; 2079 case HAL_EHT_RU_996_484_7: 2080 case HAL_EHT_RU_996x2_484_7: 2081 case HAL_EHT_RU_996x3_484_7: 2082 ru_index = 7; 2083 break; 2084 case HAL_EHT_RU_996x2_484_8: 2085 ru_index = 8; 2086 break; 2087 case HAL_EHT_RU_996x2_484_9: 2088 ru_index = 9; 2089 break; 2090 case HAL_EHT_RU_996x2_484_10: 2091 ru_index = 10; 2092 break; 2093 case HAL_EHT_RU_996x2_484_11: 2094 ru_index = 11; 2095 break; 2096 default: 2097 ru_index = HAL_EHT_RU_INVALID; 2098 dp_debug("Invalid RU index"); 2099 qdf_assert(0); 2100 break; 2101 } 2102 ru_size += 4; 2103 } 2104 2105 rtap_ru_size = hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(hal_soc, 2106 ru_size); 2107 if (rtap_ru_size != IEEE80211_EHT_RU_INVALID) { 2108 ppdu_info->rx_status.eht_known |= 2109 QDF_MON_STATUS_EHT_RU_MRU_SIZE_KNOWN; 2110 ppdu_info->rx_status.eht_data[1] |= (rtap_ru_size << 2111 QDF_MON_STATUS_EHT_RU_MRU_SIZE_SHIFT); 2112 } 2113 2114 if (ru_index != HAL_EHT_RU_INVALID) { 2115 ppdu_info->rx_status.eht_known |= 2116 QDF_MON_STATUS_EHT_RU_MRU_INDEX_KNOWN; 2117 ppdu_info->rx_status.eht_data[1] |= (ru_index << 2118 QDF_MON_STATUS_EHT_RU_MRU_INDEX_SHIFT); 2119 } 2120 2121 if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID && 2122 rtap_ru_size != IEEE80211_EHT_RU_INVALID) { 2123 mon_rx_user_status->ofdma_ru_start_index = ru_index; 2124 mon_rx_user_status->ofdma_ru_size = rtap_ru_size; 2125 hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size, &ru_width); 2126 mon_rx_user_status->ofdma_ru_width = ru_width; 2127 mon_rx_user_status->mu_ul_info_valid = 1; 2128 } 2129 2130 return HAL_TLV_STATUS_PPDU_NOT_DONE; 2131 } 2132 2133 #ifdef QCA_MONITOR_2_0_SUPPORT 2134 static inline void 2135 hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info, 2136 hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user) 2137 { 2138 ppdu_info->rx_status.mpdu_retry_cnt = 2139 rx_ppdu_end_user->retried_mpdu_count; 2140 } 2141 2142 static inline void 2143 hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv, 2144 struct hal_rx_ppdu_info *ppdu_info) 2145 { 2146 struct mon_buffer_addr *addr = (struct mon_buffer_addr *)rx_tlv; 2147 2148 ppdu_info->packet_info.sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) | 2149 (addr->buffer_virt_addr_31_0)); 2150 /* HW DMA length is '-1' of actual DMA length*/ 2151 ppdu_info->packet_info.dma_length = addr->dma_length + 1; 2152 ppdu_info->packet_info.msdu_continuation = addr->msdu_continuation; 2153 ppdu_info->packet_info.truncated = addr->truncated; 2154 2155 } 2156 2157 static inline void 2158 hal_rx_update_ppdu_drop_cnt(uint8_t *rx_tlv, 2159 struct hal_rx_ppdu_info *ppdu_info) 2160 { 2161 struct mon_drop *drop_cnt = (struct mon_drop *)rx_tlv; 2162 2163 ppdu_info->drop_cnt.ppdu_drop_cnt = drop_cnt->ppdu_drop_cnt; 2164 ppdu_info->drop_cnt.mpdu_drop_cnt = drop_cnt->mpdu_drop_cnt; 2165 ppdu_info->drop_cnt.end_of_ppdu_drop_cnt = drop_cnt->end_of_ppdu_seen; 2166 ppdu_info->drop_cnt.tlv_drop_cnt = drop_cnt->tlv_drop_cnt; 2167 } 2168 #else 2169 static inline void 2170 hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info, 2171 hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user) 2172 { 2173 ppdu_info->rx_status.mpdu_retry_cnt = 0; 2174 } 2175 static inline void 2176 hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv, 2177 struct hal_rx_ppdu_info *ppdu_info) 2178 { 2179 } 2180 2181 static inline void 2182 hal_rx_update_ppdu_drop_cnt(uint8_t *rx_tlv, 2183 struct hal_rx_ppdu_info *ppdu_info) 2184 { 2185 } 2186 #endif 2187 2188 #ifdef WLAN_SUPPORT_CTRL_FRAME_STATS 2189 static inline void 2190 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, 2191 uint32_t user_id) 2192 { 2193 uint16_t fc = ppdu_info->nac_info.frame_control; 2194 2195 if (HAL_RX_GET_FRAME_CTRL_TYPE(fc) == HAL_RX_FRAME_CTRL_TYPE_CTRL) { 2196 if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) == 2197 QDF_IEEE80211_FC0_SUBTYPE_VHT_NDP_AN) 2198 ppdu_info->ctrl_frm_info[user_id].ndpa = 1; 2199 if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) == 2200 QDF_IEEE80211_FC0_SUBTYPE_BAR) 2201 ppdu_info->ctrl_frm_info[user_id].bar = 1; 2202 } 2203 } 2204 #else 2205 static inline void 2206 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, 2207 uint32_t user_id) 2208 { 2209 } 2210 #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */ 2211 2212 /** 2213 * hal_rx_status_get_tlv_info() - process receive info TLV 2214 * @rx_tlv_hdr: pointer to TLV header 2215 * @ppdu_info: pointer to ppdu_info 2216 * 2217 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 2218 */ 2219 static inline uint32_t 2220 hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo, 2221 hal_soc_handle_t hal_soc_hdl, 2222 qdf_nbuf_t nbuf) 2223 { 2224 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2225 uint32_t tlv_tag, user_id, tlv_len, value; 2226 uint8_t group_id = 0; 2227 uint8_t he_dcm = 0; 2228 uint8_t he_stbc = 0; 2229 uint16_t he_gi = 0; 2230 uint16_t he_ltf = 0; 2231 void *rx_tlv; 2232 struct mon_rx_user_status *mon_rx_user_status; 2233 struct hal_rx_ppdu_info *ppdu_info = 2234 (struct hal_rx_ppdu_info *)ppduinfo; 2235 2236 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 2237 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 2238 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 2239 2240 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 2241 2242 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2243 rx_tlv, tlv_len); 2244 2245 ppdu_info->user_id = user_id; 2246 switch (tlv_tag) { 2247 case WIFIRX_PPDU_START_E: 2248 { 2249 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 2250 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, PHY_PPDU_ID))) 2251 hal_err("Matching ppdu_id(%u) detected", 2252 ppdu_info->com_info.last_ppdu_id); 2253 2254 /* Reset ppdu_info before processing the ppdu */ 2255 qdf_mem_zero(ppdu_info, 2256 sizeof(struct hal_rx_ppdu_info)); 2257 2258 ppdu_info->com_info.last_ppdu_id = 2259 ppdu_info->com_info.ppdu_id = 2260 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2261 PHY_PPDU_ID); 2262 2263 /* channel number is set in PHY meta data */ 2264 ppdu_info->rx_status.chan_num = 2265 (HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2266 SW_PHY_META_DATA) & 0x0000FFFF); 2267 ppdu_info->rx_status.chan_freq = 2268 (HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2269 SW_PHY_META_DATA) & 0xFFFF0000) >> 16; 2270 if (ppdu_info->rx_status.chan_num && 2271 ppdu_info->rx_status.chan_freq) { 2272 ppdu_info->rx_status.chan_freq = 2273 hal_rx_radiotap_num_to_freq( 2274 ppdu_info->rx_status.chan_num, 2275 ppdu_info->rx_status.chan_freq); 2276 } 2277 2278 ppdu_info->com_info.ppdu_timestamp = 2279 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2280 PPDU_START_TIMESTAMP_31_0); 2281 ppdu_info->rx_status.ppdu_timestamp = 2282 ppdu_info->com_info.ppdu_timestamp; 2283 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 2284 2285 break; 2286 } 2287 2288 case WIFIRX_PPDU_START_USER_INFO_E: 2289 hal_rx_parse_receive_user_info(hal, rx_tlv, ppdu_info, user_id); 2290 break; 2291 2292 case WIFIRX_PPDU_END_E: 2293 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2294 "[%s][%d] ppdu_end_e len=%d", 2295 __func__, __LINE__, tlv_len); 2296 /* This is followed by sub-TLVs of PPDU_END */ 2297 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 2298 break; 2299 2300 case WIFIPHYRX_LOCATION_E: 2301 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 2302 break; 2303 2304 case WIFIRXPCU_PPDU_END_INFO_E: 2305 ppdu_info->rx_status.rx_antenna = 2306 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, RX_ANTENNA); 2307 ppdu_info->rx_status.tsft = 2308 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, 2309 WB_TIMESTAMP_UPPER_32); 2310 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 2311 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, 2312 WB_TIMESTAMP_LOWER_32); 2313 ppdu_info->rx_status.duration = 2314 HAL_RX_GET_64(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 2315 RX_PPDU_DURATION); 2316 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 2317 break; 2318 2319 /* 2320 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 2321 * for MU, based on num users we see this tlv that many times. 2322 */ 2323 case WIFIRX_PPDU_END_USER_STATS_E: 2324 { 2325 hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user = rx_tlv; 2326 unsigned long tid = 0; 2327 uint16_t seq = 0; 2328 2329 ppdu_info->rx_status.ast_index = 2330 rx_ppdu_end_user->ast_index; 2331 2332 tid = rx_ppdu_end_user->received_qos_data_tid_bitmap; 2333 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, 2334 sizeof(tid) * 8); 2335 2336 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 2337 ppdu_info->rx_status.tid = HAL_TID_INVALID; 2338 2339 ppdu_info->rx_status.tcp_msdu_count = 2340 rx_ppdu_end_user->tcp_msdu_count + 2341 rx_ppdu_end_user->tcp_ack_msdu_count; 2342 2343 ppdu_info->rx_status.udp_msdu_count = 2344 rx_ppdu_end_user->udp_msdu_count; 2345 2346 ppdu_info->rx_status.other_msdu_count = 2347 rx_ppdu_end_user->other_msdu_count; 2348 2349 hal_rx_status_get_mpdu_retry_cnt(ppdu_info, rx_ppdu_end_user); 2350 2351 if (ppdu_info->sw_frame_group_id 2352 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 2353 ppdu_info->rx_status.frame_control_info_valid = 2354 rx_ppdu_end_user->frame_control_info_valid; 2355 2356 if (ppdu_info->rx_status.frame_control_info_valid) 2357 ppdu_info->rx_status.frame_control = 2358 rx_ppdu_end_user->frame_control_field; 2359 2360 hal_get_qos_control(rx_ppdu_end_user, ppdu_info); 2361 } 2362 2363 ppdu_info->rx_status.data_sequence_control_info_valid = 2364 rx_ppdu_end_user->data_sequence_control_info_valid; 2365 2366 seq = rx_ppdu_end_user->first_data_seq_ctrl; 2367 2368 if (ppdu_info->rx_status.data_sequence_control_info_valid) 2369 ppdu_info->rx_status.first_data_seq_ctrl = seq; 2370 2371 ppdu_info->rx_status.preamble_type = 2372 rx_ppdu_end_user->ht_control_field_pkt_type; 2373 2374 ppdu_info->end_user_stats_cnt++; 2375 2376 switch (ppdu_info->rx_status.preamble_type) { 2377 case HAL_RX_PKT_TYPE_11N: 2378 ppdu_info->rx_status.ht_flags = 1; 2379 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 2380 break; 2381 case HAL_RX_PKT_TYPE_11AC: 2382 ppdu_info->rx_status.vht_flags = 1; 2383 break; 2384 case HAL_RX_PKT_TYPE_11AX: 2385 ppdu_info->rx_status.he_flags = 1; 2386 break; 2387 default: 2388 break; 2389 } 2390 2391 ppdu_info->com_info.mpdu_cnt_fcs_ok = 2392 rx_ppdu_end_user->mpdu_cnt_fcs_ok; 2393 ppdu_info->com_info.mpdu_cnt_fcs_err = 2394 rx_ppdu_end_user->mpdu_cnt_fcs_err; 2395 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 2396 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 2397 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 2398 else 2399 ppdu_info->rx_status.rs_flags &= 2400 (~IEEE80211_AMPDU_FLAG); 2401 2402 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 2403 rx_ppdu_end_user->fcs_ok_bitmap_31_0; 2404 2405 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 2406 rx_ppdu_end_user->fcs_ok_bitmap_63_32; 2407 2408 if (user_id < HAL_MAX_UL_MU_USERS) { 2409 mon_rx_user_status = 2410 &ppdu_info->rx_user_status[user_id]; 2411 2412 hal_rx_handle_mu_ul_info(rx_ppdu_end_user, 2413 mon_rx_user_status); 2414 2415 ppdu_info->com_info.num_users++; 2416 2417 hal_rx_populate_mu_user_info(rx_ppdu_end_user, ppdu_info, 2418 user_id, 2419 mon_rx_user_status); 2420 } 2421 break; 2422 } 2423 2424 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 2425 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 2426 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2427 FCS_OK_BITMAP_95_64); 2428 2429 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 2430 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2431 FCS_OK_BITMAP_127_96); 2432 2433 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 2434 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2435 FCS_OK_BITMAP_159_128); 2436 2437 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 2438 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2439 FCS_OK_BITMAP_191_160); 2440 2441 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 2442 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2443 FCS_OK_BITMAP_223_192); 2444 2445 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 2446 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2447 FCS_OK_BITMAP_255_224); 2448 break; 2449 2450 case WIFIRX_PPDU_END_STATUS_DONE_E: 2451 return HAL_TLV_STATUS_PPDU_DONE; 2452 2453 case WIFIPHYRX_PKT_END_E: 2454 break; 2455 2456 case WIFIDUMMY_E: 2457 return HAL_TLV_STATUS_BUF_DONE; 2458 2459 case WIFIPHYRX_HT_SIG_E: 2460 { 2461 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 2462 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 2463 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 2464 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO, FEC_CODING); 2465 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2466 1 : 0; 2467 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 2468 HT_SIG_INFO, MCS); 2469 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 2470 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 2471 HT_SIG_INFO, CBW); 2472 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 2473 HT_SIG_INFO, SHORT_GI); 2474 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2475 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 2476 HT_SIG_SU_NSS_SHIFT) + 1; 2477 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 2478 break; 2479 } 2480 2481 case WIFIPHYRX_L_SIG_B_E: 2482 { 2483 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 2484 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 2485 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 2486 2487 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO, RATE); 2488 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 2489 switch (value) { 2490 case 1: 2491 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 2492 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 2493 break; 2494 case 2: 2495 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 2496 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 2497 break; 2498 case 3: 2499 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 2500 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 2501 break; 2502 case 4: 2503 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 2504 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 2505 break; 2506 case 5: 2507 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 2508 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 2509 break; 2510 case 6: 2511 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 2512 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 2513 break; 2514 case 7: 2515 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 2516 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 2517 break; 2518 default: 2519 break; 2520 } 2521 ppdu_info->rx_status.cck_flag = 1; 2522 break; 2523 } 2524 2525 case WIFIPHYRX_L_SIG_A_E: 2526 { 2527 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 2528 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 2529 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 2530 2531 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO, RATE); 2532 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 2533 switch (value) { 2534 case 8: 2535 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 2536 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 2537 break; 2538 case 9: 2539 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 2540 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 2541 break; 2542 case 10: 2543 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 2544 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 2545 break; 2546 case 11: 2547 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 2548 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 2549 break; 2550 case 12: 2551 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 2552 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 2553 break; 2554 case 13: 2555 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 2556 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 2557 break; 2558 case 14: 2559 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 2560 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 2561 break; 2562 case 15: 2563 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 2564 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 2565 break; 2566 default: 2567 break; 2568 } 2569 ppdu_info->rx_status.ofdm_flag = 1; 2570 break; 2571 } 2572 2573 case WIFIPHYRX_VHT_SIG_A_E: 2574 { 2575 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 2576 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 2577 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 2578 2579 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, 2580 SU_MU_CODING); 2581 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2582 1 : 0; 2583 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, GROUP_ID); 2584 ppdu_info->rx_status.vht_flag_values5 = group_id; 2585 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 2586 VHT_SIG_A_INFO, MCS); 2587 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 2588 VHT_SIG_A_INFO, 2589 GI_SETTING); 2590 2591 switch (hal->target_type) { 2592 case TARGET_TYPE_QCA8074: 2593 case TARGET_TYPE_QCA8074V2: 2594 case TARGET_TYPE_QCA6018: 2595 case TARGET_TYPE_QCA5018: 2596 case TARGET_TYPE_QCN9000: 2597 case TARGET_TYPE_QCN6122: 2598 #ifdef QCA_WIFI_QCA6390 2599 case TARGET_TYPE_QCA6390: 2600 #endif 2601 ppdu_info->rx_status.is_stbc = 2602 HAL_RX_GET(vht_sig_a_info, 2603 VHT_SIG_A_INFO, STBC); 2604 value = HAL_RX_GET(vht_sig_a_info, 2605 VHT_SIG_A_INFO, N_STS); 2606 value = value & VHT_SIG_SU_NSS_MASK; 2607 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2608 value = ((value + 1) >> 1) - 1; 2609 ppdu_info->rx_status.nss = 2610 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2611 2612 break; 2613 case TARGET_TYPE_QCA6290: 2614 #if !defined(QCA_WIFI_QCA6290_11AX) 2615 ppdu_info->rx_status.is_stbc = 2616 HAL_RX_GET(vht_sig_a_info, 2617 VHT_SIG_A_INFO, STBC); 2618 value = HAL_RX_GET(vht_sig_a_info, 2619 VHT_SIG_A_INFO, N_STS); 2620 value = value & VHT_SIG_SU_NSS_MASK; 2621 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2622 value = ((value + 1) >> 1) - 1; 2623 ppdu_info->rx_status.nss = 2624 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2625 #else 2626 ppdu_info->rx_status.nss = 0; 2627 #endif 2628 break; 2629 case TARGET_TYPE_KIWI: 2630 case TARGET_TYPE_MANGO: 2631 case TARGET_TYPE_PEACH: 2632 ppdu_info->rx_status.is_stbc = 2633 HAL_RX_GET(vht_sig_a_info, 2634 VHT_SIG_A_INFO, STBC); 2635 value = HAL_RX_GET(vht_sig_a_info, 2636 VHT_SIG_A_INFO, N_STS); 2637 value = value & VHT_SIG_SU_NSS_MASK; 2638 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2639 value = ((value + 1) >> 1) - 1; 2640 ppdu_info->rx_status.nss = 2641 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2642 2643 break; 2644 case TARGET_TYPE_QCA6490: 2645 case TARGET_TYPE_QCA6750: 2646 ppdu_info->rx_status.nss = 0; 2647 break; 2648 default: 2649 break; 2650 } 2651 ppdu_info->rx_status.vht_flag_values3[0] = 2652 (((ppdu_info->rx_status.mcs) << 4) 2653 | ppdu_info->rx_status.nss); 2654 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 2655 VHT_SIG_A_INFO, BANDWIDTH); 2656 ppdu_info->rx_status.vht_flag_values2 = 2657 ppdu_info->rx_status.bw; 2658 ppdu_info->rx_status.vht_flag_values4 = 2659 HAL_RX_GET(vht_sig_a_info, 2660 VHT_SIG_A_INFO, SU_MU_CODING); 2661 2662 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 2663 VHT_SIG_A_INFO, 2664 BEAMFORMED); 2665 if (group_id == 0 || group_id == 63) 2666 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2667 else 2668 ppdu_info->rx_status.reception_type = 2669 HAL_RX_TYPE_MU_MIMO; 2670 2671 break; 2672 } 2673 case WIFIPHYRX_HE_SIG_A_SU_E: 2674 { 2675 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 2676 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 2677 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 2678 ppdu_info->rx_status.he_flags = 1; 2679 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2680 FORMAT_INDICATION); 2681 if (value == 0) { 2682 ppdu_info->rx_status.he_data1 = 2683 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 2684 } else { 2685 ppdu_info->rx_status.he_data1 = 2686 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 2687 } 2688 2689 /* data1 */ 2690 ppdu_info->rx_status.he_data1 |= 2691 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 2692 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 2693 QDF_MON_STATUS_HE_DL_UL_KNOWN | 2694 QDF_MON_STATUS_HE_MCS_KNOWN | 2695 QDF_MON_STATUS_HE_DCM_KNOWN | 2696 QDF_MON_STATUS_HE_CODING_KNOWN | 2697 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 2698 QDF_MON_STATUS_HE_STBC_KNOWN | 2699 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 2700 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 2701 2702 /* data2 */ 2703 ppdu_info->rx_status.he_data2 = 2704 QDF_MON_STATUS_HE_GI_KNOWN; 2705 ppdu_info->rx_status.he_data2 |= 2706 QDF_MON_STATUS_TXBF_KNOWN | 2707 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 2708 QDF_MON_STATUS_TXOP_KNOWN | 2709 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 2710 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 2711 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 2712 2713 /* data3 */ 2714 value = HAL_RX_GET(he_sig_a_su_info, 2715 HE_SIG_A_SU_INFO, BSS_COLOR_ID); 2716 ppdu_info->rx_status.he_data3 = value; 2717 value = HAL_RX_GET(he_sig_a_su_info, 2718 HE_SIG_A_SU_INFO, BEAM_CHANGE); 2719 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 2720 ppdu_info->rx_status.he_data3 |= value; 2721 value = HAL_RX_GET(he_sig_a_su_info, 2722 HE_SIG_A_SU_INFO, DL_UL_FLAG); 2723 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 2724 ppdu_info->rx_status.he_data3 |= value; 2725 2726 value = HAL_RX_GET(he_sig_a_su_info, 2727 HE_SIG_A_SU_INFO, TRANSMIT_MCS); 2728 ppdu_info->rx_status.mcs = value; 2729 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2730 ppdu_info->rx_status.he_data3 |= value; 2731 2732 value = HAL_RX_GET(he_sig_a_su_info, 2733 HE_SIG_A_SU_INFO, DCM); 2734 he_dcm = value; 2735 value = value << QDF_MON_STATUS_DCM_SHIFT; 2736 ppdu_info->rx_status.he_data3 |= value; 2737 value = HAL_RX_GET(he_sig_a_su_info, 2738 HE_SIG_A_SU_INFO, CODING); 2739 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2740 1 : 0; 2741 value = value << QDF_MON_STATUS_CODING_SHIFT; 2742 ppdu_info->rx_status.he_data3 |= value; 2743 value = HAL_RX_GET(he_sig_a_su_info, 2744 HE_SIG_A_SU_INFO, 2745 LDPC_EXTRA_SYMBOL); 2746 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 2747 ppdu_info->rx_status.he_data3 |= value; 2748 value = HAL_RX_GET(he_sig_a_su_info, 2749 HE_SIG_A_SU_INFO, STBC); 2750 he_stbc = value; 2751 value = value << QDF_MON_STATUS_STBC_SHIFT; 2752 ppdu_info->rx_status.he_data3 |= value; 2753 2754 /* data4 */ 2755 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2756 SPATIAL_REUSE); 2757 ppdu_info->rx_status.he_data4 = value; 2758 2759 /* data5 */ 2760 value = HAL_RX_GET(he_sig_a_su_info, 2761 HE_SIG_A_SU_INFO, TRANSMIT_BW); 2762 ppdu_info->rx_status.he_data5 = value; 2763 ppdu_info->rx_status.bw = value; 2764 value = HAL_RX_GET(he_sig_a_su_info, 2765 HE_SIG_A_SU_INFO, CP_LTF_SIZE); 2766 switch (value) { 2767 case 0: 2768 he_gi = HE_GI_0_8; 2769 he_ltf = HE_LTF_1_X; 2770 break; 2771 case 1: 2772 he_gi = HE_GI_0_8; 2773 he_ltf = HE_LTF_2_X; 2774 break; 2775 case 2: 2776 he_gi = HE_GI_1_6; 2777 he_ltf = HE_LTF_2_X; 2778 break; 2779 case 3: 2780 if (he_dcm && he_stbc) { 2781 he_gi = HE_GI_0_8; 2782 he_ltf = HE_LTF_4_X; 2783 } else { 2784 he_gi = HE_GI_3_2; 2785 he_ltf = HE_LTF_4_X; 2786 } 2787 break; 2788 } 2789 ppdu_info->rx_status.sgi = he_gi; 2790 ppdu_info->rx_status.ltf_size = he_ltf; 2791 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 2792 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 2793 ppdu_info->rx_status.he_data5 |= value; 2794 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 2795 ppdu_info->rx_status.he_data5 |= value; 2796 2797 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 2798 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 2799 ppdu_info->rx_status.he_data5 |= value; 2800 2801 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2802 PACKET_EXTENSION_A_FACTOR); 2803 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 2804 ppdu_info->rx_status.he_data5 |= value; 2805 2806 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, TXBF); 2807 value = value << QDF_MON_STATUS_TXBF_SHIFT; 2808 ppdu_info->rx_status.he_data5 |= value; 2809 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2810 PACKET_EXTENSION_PE_DISAMBIGUITY); 2811 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 2812 ppdu_info->rx_status.he_data5 |= value; 2813 2814 /* data6 */ 2815 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 2816 value++; 2817 ppdu_info->rx_status.nss = value; 2818 ppdu_info->rx_status.he_data6 = value; 2819 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2820 DOPPLER_INDICATION); 2821 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 2822 ppdu_info->rx_status.he_data6 |= value; 2823 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2824 TXOP_DURATION); 2825 value = value << QDF_MON_STATUS_TXOP_SHIFT; 2826 ppdu_info->rx_status.he_data6 |= value; 2827 2828 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 2829 HE_SIG_A_SU_INFO, 2830 TXBF); 2831 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2832 break; 2833 } 2834 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 2835 { 2836 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 2837 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 2838 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 2839 2840 ppdu_info->rx_status.he_mu_flags = 1; 2841 2842 /* HE Flags */ 2843 /*data1*/ 2844 ppdu_info->rx_status.he_data1 = 2845 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 2846 ppdu_info->rx_status.he_data1 |= 2847 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 2848 QDF_MON_STATUS_HE_DL_UL_KNOWN | 2849 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 2850 QDF_MON_STATUS_HE_STBC_KNOWN | 2851 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 2852 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 2853 2854 /* data2 */ 2855 ppdu_info->rx_status.he_data2 = 2856 QDF_MON_STATUS_HE_GI_KNOWN; 2857 ppdu_info->rx_status.he_data2 |= 2858 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 2859 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 2860 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 2861 QDF_MON_STATUS_TXOP_KNOWN | 2862 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 2863 2864 /*data3*/ 2865 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2866 HE_SIG_A_MU_DL_INFO, BSS_COLOR_ID); 2867 ppdu_info->rx_status.he_data3 = value; 2868 2869 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2870 HE_SIG_A_MU_DL_INFO, DL_UL_FLAG); 2871 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 2872 ppdu_info->rx_status.he_data3 |= value; 2873 2874 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2875 HE_SIG_A_MU_DL_INFO, 2876 LDPC_EXTRA_SYMBOL); 2877 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 2878 ppdu_info->rx_status.he_data3 |= value; 2879 2880 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2881 HE_SIG_A_MU_DL_INFO, STBC); 2882 he_stbc = value; 2883 value = value << QDF_MON_STATUS_STBC_SHIFT; 2884 ppdu_info->rx_status.he_data3 |= value; 2885 2886 /*data4*/ 2887 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2888 SPATIAL_REUSE); 2889 ppdu_info->rx_status.he_data4 = value; 2890 2891 /*data5*/ 2892 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2893 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 2894 ppdu_info->rx_status.he_data5 = value; 2895 ppdu_info->rx_status.bw = value; 2896 2897 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2898 HE_SIG_A_MU_DL_INFO, CP_LTF_SIZE); 2899 switch (value) { 2900 case 0: 2901 he_gi = HE_GI_0_8; 2902 he_ltf = HE_LTF_4_X; 2903 break; 2904 case 1: 2905 he_gi = HE_GI_0_8; 2906 he_ltf = HE_LTF_2_X; 2907 break; 2908 case 2: 2909 he_gi = HE_GI_1_6; 2910 he_ltf = HE_LTF_2_X; 2911 break; 2912 case 3: 2913 he_gi = HE_GI_3_2; 2914 he_ltf = HE_LTF_4_X; 2915 break; 2916 } 2917 ppdu_info->rx_status.sgi = he_gi; 2918 ppdu_info->rx_status.ltf_size = he_ltf; 2919 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 2920 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 2921 ppdu_info->rx_status.he_data5 |= value; 2922 2923 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 2924 ppdu_info->rx_status.he_data5 |= value; 2925 2926 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2927 HE_SIG_A_MU_DL_INFO, NUM_LTF_SYMBOLS); 2928 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 2929 ppdu_info->rx_status.he_data5 |= value; 2930 2931 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2932 PACKET_EXTENSION_A_FACTOR); 2933 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 2934 ppdu_info->rx_status.he_data5 |= value; 2935 2936 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2937 PACKET_EXTENSION_PE_DISAMBIGUITY); 2938 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 2939 ppdu_info->rx_status.he_data5 |= value; 2940 2941 /*data6*/ 2942 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2943 DOPPLER_INDICATION); 2944 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 2945 ppdu_info->rx_status.he_data6 |= value; 2946 2947 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2948 TXOP_DURATION); 2949 value = value << QDF_MON_STATUS_TXOP_SHIFT; 2950 ppdu_info->rx_status.he_data6 |= value; 2951 2952 /* HE-MU Flags */ 2953 /* HE-MU-flags1 */ 2954 ppdu_info->rx_status.he_flags1 = 2955 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 2956 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 2957 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 2958 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 2959 QDF_MON_STATUS_RU_0_KNOWN; 2960 2961 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2962 HE_SIG_A_MU_DL_INFO, MCS_OF_SIG_B); 2963 ppdu_info->rx_status.he_flags1 |= value; 2964 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2965 HE_SIG_A_MU_DL_INFO, DCM_OF_SIG_B); 2966 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 2967 ppdu_info->rx_status.he_flags1 |= value; 2968 2969 /* HE-MU-flags2 */ 2970 ppdu_info->rx_status.he_flags2 = 2971 QDF_MON_STATUS_BW_KNOWN; 2972 2973 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2974 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 2975 ppdu_info->rx_status.he_flags2 |= value; 2976 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2977 HE_SIG_A_MU_DL_INFO, COMP_MODE_SIG_B); 2978 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 2979 ppdu_info->rx_status.he_flags2 |= value; 2980 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2981 HE_SIG_A_MU_DL_INFO, NUM_SIG_B_SYMBOLS); 2982 value = value - 1; 2983 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 2984 ppdu_info->rx_status.he_flags2 |= value; 2985 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 2986 break; 2987 } 2988 case WIFIPHYRX_HE_SIG_B1_MU_E: 2989 { 2990 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 2991 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 2992 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 2993 2994 ppdu_info->rx_status.he_sig_b_common_known |= 2995 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 2996 /* TODO: Check on the availability of other fields in 2997 * sig_b_common 2998 */ 2999 3000 value = HAL_RX_GET(he_sig_b1_mu_info, 3001 HE_SIG_B1_MU_INFO, RU_ALLOCATION); 3002 ppdu_info->rx_status.he_RU[0] = value; 3003 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 3004 break; 3005 } 3006 case WIFIPHYRX_HE_SIG_B2_MU_E: 3007 { 3008 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 3009 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 3010 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 3011 /* 3012 * Not all "HE" fields can be updated from 3013 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 3014 * to populate rest of the "HE" fields for MU scenarios. 3015 */ 3016 3017 /* HE-data1 */ 3018 ppdu_info->rx_status.he_data1 |= 3019 QDF_MON_STATUS_HE_MCS_KNOWN | 3020 QDF_MON_STATUS_HE_CODING_KNOWN; 3021 3022 /* HE-data2 */ 3023 3024 /* HE-data3 */ 3025 value = HAL_RX_GET(he_sig_b2_mu_info, 3026 HE_SIG_B2_MU_INFO, STA_MCS); 3027 ppdu_info->rx_status.mcs = value; 3028 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 3029 ppdu_info->rx_status.he_data3 |= value; 3030 3031 value = HAL_RX_GET(he_sig_b2_mu_info, 3032 HE_SIG_B2_MU_INFO, STA_CODING); 3033 value = value << QDF_MON_STATUS_CODING_SHIFT; 3034 ppdu_info->rx_status.he_data3 |= value; 3035 3036 /* HE-data4 */ 3037 value = HAL_RX_GET(he_sig_b2_mu_info, 3038 HE_SIG_B2_MU_INFO, STA_ID); 3039 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 3040 ppdu_info->rx_status.he_data4 |= value; 3041 3042 /* HE-data5 */ 3043 3044 /* HE-data6 */ 3045 value = HAL_RX_GET(he_sig_b2_mu_info, 3046 HE_SIG_B2_MU_INFO, NSTS); 3047 /* value n indicates n+1 spatial streams */ 3048 value++; 3049 ppdu_info->rx_status.nss = value; 3050 ppdu_info->rx_status.he_data6 |= value; 3051 3052 break; 3053 } 3054 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 3055 { 3056 uint8_t *he_sig_b2_ofdma_info = 3057 (uint8_t *)rx_tlv + 3058 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 3059 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 3060 3061 /* 3062 * Not all "HE" fields can be updated from 3063 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 3064 * to populate rest of "HE" fields for MU OFDMA scenarios. 3065 */ 3066 3067 /* HE-data1 */ 3068 ppdu_info->rx_status.he_data1 |= 3069 QDF_MON_STATUS_HE_MCS_KNOWN | 3070 QDF_MON_STATUS_HE_DCM_KNOWN | 3071 QDF_MON_STATUS_HE_CODING_KNOWN; 3072 3073 /* HE-data2 */ 3074 ppdu_info->rx_status.he_data2 |= 3075 QDF_MON_STATUS_TXBF_KNOWN; 3076 3077 /* HE-data3 */ 3078 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3079 HE_SIG_B2_OFDMA_INFO, STA_MCS); 3080 ppdu_info->rx_status.mcs = value; 3081 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 3082 ppdu_info->rx_status.he_data3 |= value; 3083 3084 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3085 HE_SIG_B2_OFDMA_INFO, STA_DCM); 3086 he_dcm = value; 3087 value = value << QDF_MON_STATUS_DCM_SHIFT; 3088 ppdu_info->rx_status.he_data3 |= value; 3089 3090 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3091 HE_SIG_B2_OFDMA_INFO, STA_CODING); 3092 value = value << QDF_MON_STATUS_CODING_SHIFT; 3093 ppdu_info->rx_status.he_data3 |= value; 3094 3095 /* HE-data4 */ 3096 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3097 HE_SIG_B2_OFDMA_INFO, STA_ID); 3098 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 3099 ppdu_info->rx_status.he_data4 |= value; 3100 3101 /* HE-data5 */ 3102 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3103 HE_SIG_B2_OFDMA_INFO, TXBF); 3104 value = value << QDF_MON_STATUS_TXBF_SHIFT; 3105 ppdu_info->rx_status.he_data5 |= value; 3106 3107 /* HE-data6 */ 3108 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3109 HE_SIG_B2_OFDMA_INFO, NSTS); 3110 /* value n indicates n+1 spatial streams */ 3111 value++; 3112 ppdu_info->rx_status.nss = value; 3113 ppdu_info->rx_status.he_data6 |= value; 3114 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 3115 break; 3116 } 3117 case WIFIPHYRX_RSSI_LEGACY_E: 3118 { 3119 uint8_t reception_type; 3120 int8_t rssi_value; 3121 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 3122 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 3123 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 3124 3125 ppdu_info->rx_status.rssi_comb = 3126 HAL_RX_GET_64(rx_tlv, 3127 PHYRX_RSSI_LEGACY, RSSI_COMB); 3128 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 3129 ppdu_info->rx_status.he_re = 0; 3130 3131 reception_type = HAL_RX_GET_64(rx_tlv, 3132 PHYRX_RSSI_LEGACY, 3133 RECEPTION_TYPE); 3134 switch (reception_type) { 3135 case QDF_RECEPTION_TYPE_ULOFMDA: 3136 ppdu_info->rx_status.ulofdma_flag = 1; 3137 ppdu_info->rx_status.he_data1 = 3138 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 3139 break; 3140 case QDF_RECEPTION_TYPE_ULMIMO: 3141 ppdu_info->rx_status.he_data1 = 3142 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 3143 break; 3144 default: 3145 break; 3146 } 3147 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 3148 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3149 RECEIVE_RSSI_INFO, 3150 RSSI_PRI20_CHAIN0); 3151 ppdu_info->rx_status.rssi[0] = rssi_value; 3152 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3153 "RSSI_PRI20_CHAIN0: %d\n", rssi_value); 3154 3155 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3156 RECEIVE_RSSI_INFO, 3157 RSSI_PRI20_CHAIN1); 3158 ppdu_info->rx_status.rssi[1] = rssi_value; 3159 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3160 "RSSI_PRI20_CHAIN1: %d\n", rssi_value); 3161 3162 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3163 RECEIVE_RSSI_INFO, 3164 RSSI_PRI20_CHAIN2); 3165 ppdu_info->rx_status.rssi[2] = rssi_value; 3166 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3167 "RSSI_PRI20_CHAIN2: %d\n", rssi_value); 3168 3169 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3170 RECEIVE_RSSI_INFO, 3171 RSSI_PRI20_CHAIN3); 3172 ppdu_info->rx_status.rssi[3] = rssi_value; 3173 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3174 "RSSI_PRI20_CHAIN3: %d\n", rssi_value); 3175 3176 #ifdef DP_BE_NOTYET_WAR 3177 // TODO - this is not preset for kiwi 3178 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3179 RECEIVE_RSSI_INFO, 3180 RSSI_PRI20_CHAIN4); 3181 ppdu_info->rx_status.rssi[4] = rssi_value; 3182 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3183 "RSSI_PRI20_CHAIN4: %d\n", rssi_value); 3184 3185 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3186 RECEIVE_RSSI_INFO, 3187 RSSI_PRI20_CHAIN5); 3188 ppdu_info->rx_status.rssi[5] = rssi_value; 3189 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3190 "RSSI_PRI20_CHAIN5: %d\n", rssi_value); 3191 3192 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3193 RECEIVE_RSSI_INFO, 3194 RSSI_PRI20_CHAIN6); 3195 ppdu_info->rx_status.rssi[6] = rssi_value; 3196 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3197 "RSSI_PRI20_CHAIN6: %d\n", rssi_value); 3198 3199 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3200 RECEIVE_RSSI_INFO, 3201 RSSI_PRI20_CHAIN7); 3202 ppdu_info->rx_status.rssi[7] = rssi_value; 3203 #endif 3204 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3205 "RSSI_PRI20_CHAIN7: %d\n", rssi_value); 3206 break; 3207 } 3208 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 3209 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 3210 ppdu_info); 3211 break; 3212 case WIFIPHYRX_GENERIC_U_SIG_E: 3213 hal_rx_parse_u_sig_hdr(hal, rx_tlv, ppdu_info); 3214 break; 3215 case WIFIPHYRX_COMMON_USER_INFO_E: 3216 hal_rx_parse_cmn_usr_info(hal, rx_tlv, ppdu_info); 3217 break; 3218 case WIFIRX_HEADER_E: 3219 { 3220 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 3221 3222 if (ppdu_info->fcs_ok_cnt >= 3223 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 3224 hal_err("Number of MPDUs(%d) per status buff exceeded", 3225 ppdu_info->fcs_ok_cnt); 3226 break; 3227 } 3228 3229 /* Update first_msdu_payload for every mpdu and increment 3230 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 3231 */ 3232 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 3233 rx_tlv; 3234 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 3235 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 3236 ppdu_info->msdu_info.payload_len = tlv_len; 3237 ppdu_info->user_id = user_id; 3238 ppdu_info->hdr_len = tlv_len; 3239 ppdu_info->data = rx_tlv; 3240 ppdu_info->data += 4; 3241 3242 /* for every RX_HEADER TLV increment mpdu_cnt */ 3243 com_info->mpdu_cnt++; 3244 return HAL_TLV_STATUS_HEADER; 3245 } 3246 case WIFIRX_MPDU_START_E: 3247 { 3248 hal_rx_mon_mpdu_start_t *rx_mpdu_start = rx_tlv; 3249 uint32_t ppdu_id = rx_mpdu_start->rx_mpdu_info_details.phy_ppdu_id; 3250 uint8_t filter_category = 0; 3251 3252 ppdu_info->nac_info.fc_valid = 3253 rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid; 3254 3255 ppdu_info->nac_info.to_ds_flag = 3256 rx_mpdu_start->rx_mpdu_info_details.to_ds; 3257 3258 ppdu_info->nac_info.frame_control = 3259 rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field; 3260 3261 ppdu_info->sw_frame_group_id = 3262 rx_mpdu_start->rx_mpdu_info_details.sw_frame_group_id; 3263 3264 ppdu_info->rx_user_status[user_id].sw_peer_id = 3265 rx_mpdu_start->rx_mpdu_info_details.sw_peer_id; 3266 3267 hal_update_rx_ctrl_frame_stats(ppdu_info, user_id); 3268 3269 if (ppdu_info->sw_frame_group_id == 3270 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 3271 ppdu_info->rx_status.frame_control_info_valid = 3272 ppdu_info->nac_info.fc_valid; 3273 ppdu_info->rx_status.frame_control = 3274 ppdu_info->nac_info.frame_control; 3275 } 3276 3277 hal_get_mac_addr1(rx_mpdu_start, 3278 ppdu_info); 3279 3280 ppdu_info->nac_info.mac_addr2_valid = 3281 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_valid; 3282 3283 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 3284 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_15_0; 3285 3286 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 3287 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_47_16; 3288 3289 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 3290 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 3291 ppdu_info->rx_status.ppdu_len = 3292 rx_mpdu_start->rx_mpdu_info_details.mpdu_length; 3293 } else { 3294 ppdu_info->rx_status.ppdu_len += 3295 rx_mpdu_start->rx_mpdu_info_details.mpdu_length; 3296 } 3297 3298 filter_category = 3299 rx_mpdu_start->rx_mpdu_info_details.rxpcu_mpdu_filter_in_category; 3300 3301 if (filter_category == 0) 3302 ppdu_info->rx_status.rxpcu_filter_pass = 1; 3303 else if (filter_category == 1) 3304 ppdu_info->rx_status.monitor_direct_used = 1; 3305 3306 ppdu_info->rx_user_status[user_id].filter_category = filter_category; 3307 3308 ppdu_info->nac_info.mcast_bcast = 3309 rx_mpdu_start->rx_mpdu_info_details.mcast_bcast; 3310 ppdu_info->mpdu_info[user_id].decap_type = 3311 rx_mpdu_start->rx_mpdu_info_details.decap_type; 3312 3313 return HAL_TLV_STATUS_MPDU_START; 3314 } 3315 case WIFIRX_MPDU_END_E: 3316 ppdu_info->user_id = user_id; 3317 ppdu_info->fcs_err = 3318 HAL_RX_GET_64(rx_tlv, RX_MPDU_END, 3319 FCS_ERR); 3320 return HAL_TLV_STATUS_MPDU_END; 3321 case WIFIRX_MSDU_END_E: { 3322 hal_rx_mon_msdu_end_t *rx_msdu_end = rx_tlv; 3323 3324 if (user_id < HAL_MAX_UL_MU_USERS) { 3325 ppdu_info->rx_msdu_info[user_id].cce_metadata = 3326 rx_msdu_end->cce_metadata; 3327 ppdu_info->rx_msdu_info[user_id].fse_metadata = 3328 rx_msdu_end->fse_metadata; 3329 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 3330 rx_msdu_end->flow_idx_timeout; 3331 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 3332 rx_msdu_end->flow_idx_invalid; 3333 ppdu_info->rx_msdu_info[user_id].flow_idx = 3334 rx_msdu_end->flow_idx; 3335 ppdu_info->msdu[user_id].first_msdu = 3336 rx_msdu_end->first_msdu; 3337 ppdu_info->msdu[user_id].last_msdu = 3338 rx_msdu_end->last_msdu; 3339 ppdu_info->msdu[user_id].msdu_len = 3340 rx_msdu_end->msdu_length; 3341 ppdu_info->msdu[user_id].user_rssi = 3342 rx_msdu_end->user_rssi; 3343 ppdu_info->msdu[user_id].reception_type = 3344 rx_msdu_end->reception_type; 3345 } 3346 return HAL_TLV_STATUS_MSDU_END; 3347 } 3348 case WIFIMON_BUFFER_ADDR_E: 3349 hal_rx_status_get_mon_buf_addr(rx_tlv, ppdu_info); 3350 3351 return HAL_TLV_STATUS_MON_BUF_ADDR; 3352 case WIFIMON_DROP_E: 3353 hal_rx_update_ppdu_drop_cnt(rx_tlv, ppdu_info); 3354 return HAL_TLV_STATUS_MON_DROP; 3355 case 0: 3356 return HAL_TLV_STATUS_PPDU_DONE; 3357 case WIFIRX_STATUS_BUFFER_DONE_E: 3358 case WIFIPHYRX_DATA_DONE_E: 3359 case WIFIPHYRX_PKT_END_PART1_E: 3360 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3361 3362 default: 3363 hal_debug("unhandled tlv tag %d", tlv_tag); 3364 } 3365 3366 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3367 rx_tlv, tlv_len); 3368 3369 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3370 } 3371 3372 static uint32_t 3373 hal_rx_status_process_aggr_tlv(struct hal_soc *hal_soc, 3374 struct hal_rx_ppdu_info *ppdu_info) 3375 { 3376 uint32_t aggr_tlv_tag = ppdu_info->tlv_aggr.tlv_tag; 3377 3378 switch (aggr_tlv_tag) { 3379 case WIFIPHYRX_GENERIC_EHT_SIG_E: 3380 hal_rx_parse_eht_sig_hdr(hal_soc, ppdu_info->tlv_aggr.buf, 3381 ppdu_info); 3382 break; 3383 default: 3384 /* Aggregated TLV cannot be handled */ 3385 qdf_assert(0); 3386 break; 3387 } 3388 3389 ppdu_info->tlv_aggr.in_progress = 0; 3390 ppdu_info->tlv_aggr.cur_len = 0; 3391 3392 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3393 } 3394 3395 static inline bool 3396 hal_rx_status_tlv_should_aggregate(struct hal_soc *hal_soc, uint32_t tlv_tag) 3397 { 3398 switch (tlv_tag) { 3399 case WIFIPHYRX_GENERIC_EHT_SIG_E: 3400 return true; 3401 } 3402 3403 return false; 3404 } 3405 3406 static inline uint32_t 3407 hal_rx_status_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr, 3408 struct hal_rx_ppdu_info *ppdu_info, 3409 qdf_nbuf_t nbuf) 3410 { 3411 uint32_t tlv_tag, user_id, tlv_len; 3412 void *rx_tlv; 3413 3414 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 3415 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 3416 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 3417 3418 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 3419 3420 if (tlv_len <= HAL_RX_MON_MAX_AGGR_SIZE - ppdu_info->tlv_aggr.cur_len) { 3421 qdf_mem_copy(ppdu_info->tlv_aggr.buf + 3422 ppdu_info->tlv_aggr.cur_len, 3423 rx_tlv, tlv_len); 3424 ppdu_info->tlv_aggr.cur_len += tlv_len; 3425 } else { 3426 dp_err("Length of TLV exceeds max aggregation length"); 3427 qdf_assert(0); 3428 } 3429 3430 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3431 } 3432 3433 static inline uint32_t 3434 hal_rx_status_start_new_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr, 3435 struct hal_rx_ppdu_info *ppdu_info, 3436 qdf_nbuf_t nbuf) 3437 { 3438 uint32_t tlv_tag, user_id, tlv_len; 3439 3440 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 3441 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 3442 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 3443 3444 ppdu_info->tlv_aggr.in_progress = 1; 3445 ppdu_info->tlv_aggr.tlv_tag = tlv_tag; 3446 ppdu_info->tlv_aggr.cur_len = 0; 3447 3448 return hal_rx_status_aggr_tlv(hal_soc, rx_tlv_hdr, ppdu_info, nbuf); 3449 } 3450 3451 static inline uint32_t 3452 hal_rx_status_get_tlv_info_wrapper_be(void *rx_tlv_hdr, void *ppduinfo, 3453 hal_soc_handle_t hal_soc_hdl, 3454 qdf_nbuf_t nbuf) 3455 { 3456 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3457 uint32_t tlv_tag, user_id, tlv_len; 3458 struct hal_rx_ppdu_info *ppdu_info = 3459 (struct hal_rx_ppdu_info *)ppduinfo; 3460 3461 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 3462 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 3463 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 3464 3465 /* 3466 * Handle the case where aggregation is in progress 3467 * or the current TLV is one of the TLVs which should be 3468 * aggregated 3469 */ 3470 if (ppdu_info->tlv_aggr.in_progress) { 3471 if (ppdu_info->tlv_aggr.tlv_tag == tlv_tag) { 3472 return hal_rx_status_aggr_tlv(hal, rx_tlv_hdr, 3473 ppdu_info, nbuf); 3474 } else { 3475 /* Finish aggregation of current TLV */ 3476 hal_rx_status_process_aggr_tlv(hal, ppdu_info); 3477 } 3478 } 3479 3480 if (hal_rx_status_tlv_should_aggregate(hal, tlv_tag)) { 3481 return hal_rx_status_start_new_aggr_tlv(hal, rx_tlv_hdr, 3482 ppduinfo, nbuf); 3483 } 3484 3485 return hal_rx_status_get_tlv_info_generic_be(rx_tlv_hdr, ppduinfo, 3486 hal_soc_hdl, nbuf); 3487 } 3488 #endif /* _HAL_BE_API_MON_H_ */ 3489