1 /* 2 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HAL_BE_API_MON_H_ 19 #define _HAL_BE_API_MON_H_ 20 21 #include "hal_be_hw_headers.h" 22 #ifdef QCA_MONITOR_2_0_SUPPORT 23 #include <mon_ingress_ring.h> 24 #include <mon_destination_ring.h> 25 #include <mon_drop.h> 26 #endif 27 #include <hal_be_hw_headers.h> 28 #include "hal_api_mon.h" 29 #include <hal_generic_api.h> 30 #include <hal_generic_api.h> 31 #include <hal_api_mon.h> 32 33 #if defined(QCA_MONITOR_2_0_SUPPORT) || \ 34 defined(QCA_SINGLE_WIFI_3_0) 35 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 36 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 37 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff 38 39 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 40 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 41 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff 42 43 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 44 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 45 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 46 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 47 48 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c 49 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 50 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 51 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 52 53 #define HAL_MON_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 54 ((*(((unsigned int *) buff_addr_info) + \ 55 (HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 56 ((paddr_lo) << HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 57 HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 58 59 #define HAL_MON_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 60 ((*(((unsigned int *) buff_addr_info) + \ 61 (HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 62 ((paddr_hi) << HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 63 HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 64 65 #define HAL_MON_VADDR_LO_SET(buff_addr_info, vaddr_lo) \ 66 ((*(((unsigned int *) buff_addr_info) + \ 67 (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET >> 2))) = \ 68 ((vaddr_lo) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB) & \ 69 HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK) 70 71 #define HAL_MON_VADDR_HI_SET(buff_addr_info, vaddr_hi) \ 72 ((*(((unsigned int *) buff_addr_info) + \ 73 (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET >> 2))) = \ 74 ((vaddr_hi) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB) & \ 75 HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK) 76 77 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 78 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 79 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 80 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 81 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 82 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 83 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 84 PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 85 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 86 PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 87 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 88 PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 89 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 90 PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 91 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 92 PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 93 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 94 PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 95 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 96 PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 97 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 98 PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 99 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 100 PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 101 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 102 PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 103 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 104 PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 105 #endif 106 107 #ifdef CONFIG_MON_WORD_BASED_TLV 108 #ifndef BIG_ENDIAN_HOST 109 struct rx_mpdu_start_mon_data { 110 uint32_t rxpcu_mpdu_filter_in_category : 2, 111 sw_frame_group_id : 7, 112 ndp_frame : 1, 113 phy_err : 1, 114 phy_err_during_mpdu_header : 1, 115 protocol_version_err : 1, 116 ast_based_lookup_valid : 1, 117 reserved_0a : 2, 118 phy_ppdu_id : 16; 119 uint32_t ast_index : 16, 120 sw_peer_id : 16; 121 uint32_t mpdu_frame_control_valid : 1, 122 mpdu_duration_valid : 1, 123 mac_addr_ad1_valid : 1, 124 mac_addr_ad2_valid : 1, 125 mac_addr_ad3_valid : 1, 126 mac_addr_ad4_valid : 1, 127 mpdu_sequence_control_valid : 1, 128 mpdu_qos_control_valid : 1, 129 mpdu_ht_control_valid : 1, 130 frame_encryption_info_valid : 1, 131 mpdu_fragment_number : 4, 132 more_fragment_flag : 1, 133 reserved_11a : 1, 134 fr_ds : 1, 135 to_ds : 1, 136 encrypted : 1, 137 mpdu_retry : 1, 138 mpdu_sequence_number : 12; 139 uint32_t mpdu_length : 14, 140 first_mpdu : 1, 141 mcast_bcast : 1, 142 ast_index_not_found : 1, 143 ast_index_timeout : 1, 144 power_mgmt : 1, 145 non_qos : 1, 146 null_data : 1, 147 mgmt_type : 1, 148 ctrl_type : 1, 149 more_data : 1, 150 eosp : 1, 151 fragment_flag : 1, 152 order : 1, 153 u_apsd_trigger : 1, 154 encrypt_required : 1, 155 directed : 1, 156 amsdu_present : 1, 157 reserved_13 : 1; 158 uint32_t mpdu_frame_control_field : 16, 159 mpdu_duration_field : 16; 160 uint32_t mac_addr_ad1_31_0 : 32; 161 uint32_t mac_addr_ad1_47_32 : 16, 162 mac_addr_ad2_15_0 : 16; 163 }; 164 165 struct rx_msdu_end_mon_data { 166 uint32_t rxpcu_mpdu_filter_in_category : 2, 167 sw_frame_group_id : 7, 168 reserved_0 : 7, 169 phy_ppdu_id : 16; 170 uint32_t tcp_udp_chksum : 16, 171 sa_idx_timeout : 1, 172 da_idx_timeout : 1, 173 msdu_limit_error : 1, 174 flow_idx_timeout : 1, 175 flow_idx_invalid : 1, 176 wifi_parser_error : 1, 177 amsdu_parser_error : 1, 178 sa_is_valid : 1, 179 da_is_valid : 1, 180 da_is_mcbc : 1, 181 l3_header_padding : 2, 182 first_msdu : 1, 183 last_msdu : 1, 184 tcp_udp_chksum_fail : 1, 185 ip_chksum_fail : 1; 186 uint32_t msdu_drop : 1, 187 reo_destination_indication : 5, 188 flow_idx : 20, 189 reserved_12a : 6; 190 uint32_t fse_metadata : 32; 191 uint32_t cce_metadata : 16, 192 sa_sw_peer_id : 16; 193 }; 194 #else 195 struct rx_mpdu_start_mon_data { 196 uint32_t phy_ppdu_id : 16; 197 reserved_0a : 2, 198 ast_based_lookup_valid : 1, 199 protocol_version_err : 1, 200 phy_err_during_mpdu_header : 1, 201 phy_err : 1, 202 ndp_frame : 1, 203 sw_frame_group_id : 7, 204 rxpcu_mpdu_filter_in_category : 2, 205 uint32_t sw_peer_id : 16; 206 ast_index : 16, 207 uint32_t mpdu_sequence_number : 12; 208 mpdu_retry : 1, 209 encrypted : 1, 210 to_ds : 1, 211 fr_ds : 1, 212 reserved_11a : 1, 213 more_fragment_flag : 1, 214 mpdu_fragment_number : 4, 215 frame_encryption_info_valid : 1, 216 mpdu_ht_control_valid : 1, 217 mpdu_qos_control_valid : 1, 218 mpdu_sequence_control_valid : 1, 219 mac_addr_ad4_valid : 1, 220 mac_addr_ad3_valid : 1, 221 mac_addr_ad2_valid : 1, 222 mac_addr_ad1_valid : 1, 223 mpdu_duration_valid : 1, 224 mpdu_frame_control_valid : 1, 225 uint32_t reserved_13 : 1; 226 amsdu_present : 1, 227 directed : 1, 228 encrypt_required : 1, 229 u_apsd_trigger : 1, 230 order : 1, 231 fragment_flag : 1, 232 eosp : 1, 233 more_data : 1, 234 ctrl_type : 1, 235 mgmt_type : 1, 236 null_data : 1, 237 non_qos : 1, 238 power_mgmt : 1, 239 ast_index_timeout : 1, 240 ast_index_not_found : 1, 241 mcast_bcast : 1, 242 first_mpdu : 1, 243 mpdu_length : 14, 244 uint32_t mpdu_duration_field : 16; 245 mpdu_frame_control_field : 16, 246 uint32_t mac_addr_ad1_31_0 : 32; 247 uint32_t mac_addr_ad2_15_0 : 16; 248 mac_addr_ad1_47_32 : 16, 249 }; 250 251 struct rx_msdu_end_mon_data { 252 uint32_t phy_ppdu_id : 16; 253 reserved_0 : 7, 254 sw_frame_group_id : 7, 255 rxpcu_mpdu_filter_in_category : 2, 256 uint32_t ip_chksum_fail : 1; 257 tcp_udp_chksum_fail : 1, 258 last_msdu : 1, 259 first_msdu : 1, 260 l3_header_padding : 2, 261 da_is_mcbc : 1, 262 da_is_valid : 1, 263 sa_is_valid : 1, 264 amsdu_parser_error : 1, 265 wifi_parser_error : 1, 266 flow_idx_invalid : 1, 267 flow_idx_timeout : 1, 268 msdu_limit_error : 1, 269 da_idx_timeout : 1, 270 sa_idx_timeout : 1, 271 tcp_udp_chksum : 16, 272 uint32_t reserved_12a : 6; 273 flow_idx : 20, 274 reo_destination_indication : 5, 275 msdu_drop : 1, 276 uint32_t fse_metadata : 32; 277 uint32_t sa_sw_peer_id : 16; 278 cce_metadata : 16, 279 }; 280 #endif 281 282 /* TLV struct for word based Tlv */ 283 typedef struct rx_mpdu_start_mon_data hal_rx_mon_mpdu_start_t; 284 typedef struct rx_msdu_end_mon_data hal_rx_mon_msdu_end_t; 285 286 #else 287 288 typedef struct rx_mpdu_start hal_rx_mon_mpdu_start_t; 289 typedef struct rx_msdu_end hal_rx_mon_msdu_end_t; 290 #endif 291 292 /* 293 * struct mon_destination_drop - monitor drop descriptor 294 * 295 * @ppdu_drop_cnt: PPDU drop count 296 * @mpdu_drop_cnt: MPDU drop count 297 * @tlv_drop_cnt: TLV drop count 298 * @end_of_ppdu_seen: end of ppdu seen 299 * @reserved_0a: rsvd 300 * @reserved_1a: rsvd 301 * @ppdu_id: PPDU ID 302 * @reserved_3a: rsvd 303 * @initiator: initiator ppdu 304 * @empty_descriptor: empty descriptor 305 * @ring_id: ring id 306 * @looping_count: looping count 307 */ 308 struct mon_destination_drop { 309 uint32_t ppdu_drop_cnt : 10, 310 mpdu_drop_cnt : 10, 311 tlv_drop_cnt : 10, 312 end_of_ppdu_seen : 1, 313 reserved_0a : 1; 314 uint32_t reserved_1a : 32; 315 uint32_t ppdu_id : 32; 316 uint32_t reserved_3a : 18, 317 initiator : 1, 318 empty_descriptor : 1, 319 ring_id : 8, 320 looping_count : 4; 321 }; 322 323 #define HAL_MON_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 324 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 325 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 326 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 327 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 328 329 #define HAL_MON_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 330 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 331 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 332 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 333 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 334 335 /** 336 * struct hal_rx_status_buffer_done - status buffer done tlv 337 * placeholder structure 338 * 339 * @ppdu_start_offset: ppdu start 340 * @first_ppdu_start_user_info_offset: 341 * @mult_ppdu_start_user_info: 342 * @end_offset: 343 * @ppdu_end_detected: 344 * @flush_detected: 345 * @rsvd: 346 */ 347 struct hal_rx_status_buffer_done { 348 uint32_t ppdu_start_offset : 3, 349 first_ppdu_start_user_info_offset : 6, 350 mult_ppdu_start_user_info : 1, 351 end_offset : 13, 352 ppdu_end_detected : 1, 353 flush_detected : 1, 354 rsvd : 7; 355 }; 356 357 /** 358 * hal_mon_status_end_reason : ppdu status buffer end reason 359 * 360 * @HAL_MON_STATUS_BUFFER_FULL: status buffer full 361 * @HAL_MON_FLUSH_DETECTED: flush detected 362 * @HAL_MON_END_OF_PPDU: end of ppdu detected 363 * HAL_MON_PPDU_truncated: truncated ppdu status 364 */ 365 enum hal_mon_status_end_reason { 366 HAL_MON_STATUS_BUFFER_FULL, 367 HAL_MON_FLUSH_DETECTED, 368 HAL_MON_END_OF_PPDU, 369 HAL_MON_PPDU_TRUNCATED, 370 }; 371 372 /** 373 * struct hal_mon_desc () - HAL Monitor descriptor 374 * 375 * @buf_addr: virtual buffer address 376 * @ppdu_id: ppdu id 377 * - TxMon fills scheduler id 378 * - RxMON fills phy_ppdu_id 379 * @end_offset: offset (units in 4 bytes) where status buffer ended 380 * i.e offset of TLV + last TLV size 381 * @end_reason: 0 - status buffer is full 382 * 1 - flush detected 383 * 2 - TX_FES_STATUS_END or RX_PPDU_END 384 * 3 - PPDU truncated due to system error 385 * @initiator: 1 - descriptor belongs to TX FES 386 * 0 - descriptor belongs to TX RESPONSE 387 * @empty_descriptor: 0 - this descriptor is written on a flush 388 * or end of ppdu or end of status buffer 389 * 1 - descriptor provided to indicate drop 390 * @ring_id: ring id for debugging 391 * @looping_count: count to indicate number of times producer 392 * of entries has looped around the ring 393 * @flush_detected: if flush detected 394 * @end_reason: ppdu end reason 395 * @end_of_ppdu_dropped: if end_of_ppdu is dropped 396 * @ppdu_drop_count: PPDU drop count 397 * @mpdu_drop_count: MPDU drop count 398 * @tlv_drop_count: TLV drop count 399 */ 400 struct hal_mon_desc { 401 uint64_t buf_addr; 402 uint32_t ppdu_id; 403 uint32_t end_offset:12, 404 reserved_3a:4, 405 end_reason:2, 406 initiator:1, 407 empty_descriptor:1, 408 ring_id:8, 409 looping_count:4; 410 uint16_t flush_detected:1, 411 end_of_ppdu_dropped:1; 412 uint32_t ppdu_drop_count; 413 uint32_t mpdu_drop_count; 414 uint32_t tlv_drop_count; 415 }; 416 417 typedef struct hal_mon_desc *hal_mon_desc_t; 418 419 /** 420 * struct hal_mon_buf_addr_status () - HAL buffer address tlv get status 421 * 422 * @buf_addr_31_0: Lower 32 bits of virtual address of status buffer 423 * @buf_addr_63_32: Upper 32 bits of virtual address of status buffer 424 * @dma_length: DMA length 425 * @msdu_continuation: is msdu size more than fragment size 426 * @truncated: is msdu got truncated 427 * @tlv_padding: tlv paddding 428 */ 429 struct hal_mon_buf_addr_status { 430 uint32_t buffer_virt_addr_31_0; 431 uint32_t buffer_virt_addr_63_32; 432 uint32_t dma_length:12, 433 reserved_2a:4, 434 msdu_continuation:1, 435 truncated:1, 436 reserved_2b:14; 437 uint32_t tlv64_padding; 438 }; 439 440 #ifdef QCA_MONITOR_2_0_SUPPORT 441 /** 442 * hal_be_get_mon_dest_status() - Get monitor descriptor 443 * @hal_soc_hdl: HAL Soc handle 444 * @desc: HAL monitor descriptor 445 * 446 * Return: none 447 */ 448 static inline void 449 hal_be_get_mon_dest_status(hal_soc_handle_t hal_soc, 450 void *hw_desc, 451 struct hal_mon_desc *status) 452 { 453 struct mon_destination_ring *desc = hw_desc; 454 455 status->empty_descriptor = desc->empty_descriptor; 456 if (status->empty_descriptor) { 457 struct mon_destination_drop *drop_desc = hw_desc; 458 459 status->buf_addr = 0; 460 status->ppdu_drop_count = drop_desc->ppdu_drop_cnt; 461 status->mpdu_drop_count = drop_desc->mpdu_drop_cnt; 462 status->tlv_drop_count = drop_desc->tlv_drop_cnt; 463 status->end_of_ppdu_dropped = drop_desc->end_of_ppdu_seen; 464 } else { 465 status->buf_addr = HAL_RX_GET(desc, MON_DESTINATION_RING_STAT,BUF_VIRT_ADDR_31_0) | 466 (((uint64_t)HAL_RX_GET(desc, 467 MON_DESTINATION_RING_STAT, 468 BUF_VIRT_ADDR_63_32)) << 32); 469 status->end_reason = desc->end_reason; 470 status->end_offset = desc->end_offset; 471 } 472 status->ppdu_id = desc->ppdu_id; 473 status->initiator = desc->initiator; 474 status->looping_count = desc->looping_count; 475 } 476 #endif 477 478 #if defined(RX_PPDU_END_USER_STATS_OFDMA_INFO_VALID_OFFSET) && \ 479 defined(RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 480 481 static inline void 482 hal_rx_handle_mu_ul_info(void *rx_tlv, 483 struct mon_rx_user_status *mon_rx_user_status) 484 { 485 mon_rx_user_status->mu_ul_user_v0_word0 = 486 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 487 SW_RESPONSE_REFERENCE_PTR); 488 489 mon_rx_user_status->mu_ul_user_v0_word1 = 490 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 491 SW_RESPONSE_REFERENCE_PTR_EXT); 492 } 493 #else 494 static inline void 495 hal_rx_handle_mu_ul_info(void *rx_tlv, 496 struct mon_rx_user_status *mon_rx_user_status) 497 { 498 } 499 #endif 500 501 static inline void 502 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 503 struct mon_rx_user_status *mon_rx_user_status) 504 { 505 uint32_t mpdu_ok_byte_count; 506 uint32_t mpdu_err_byte_count; 507 508 mpdu_ok_byte_count = HAL_RX_GET_64(rx_tlv, 509 RX_PPDU_END_USER_STATS, 510 MPDU_OK_BYTE_COUNT); 511 mpdu_err_byte_count = HAL_RX_GET_64(rx_tlv, 512 RX_PPDU_END_USER_STATS, 513 MPDU_ERR_BYTE_COUNT); 514 515 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 516 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 517 } 518 519 static inline void 520 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id, 521 struct mon_rx_user_status *mon_rx_user_status) 522 { 523 struct mon_rx_info *mon_rx_info; 524 struct mon_rx_user_info *mon_rx_user_info; 525 struct hal_rx_ppdu_info *ppdu_info = 526 (struct hal_rx_ppdu_info *)ppduinfo; 527 528 mon_rx_info = &ppdu_info->rx_info; 529 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 530 mon_rx_user_info->qos_control_info_valid = 531 mon_rx_info->qos_control_info_valid; 532 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 533 534 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 535 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 536 mon_rx_user_status->tcp_msdu_count = 537 ppdu_info->rx_status.tcp_msdu_count; 538 mon_rx_user_status->udp_msdu_count = 539 ppdu_info->rx_status.udp_msdu_count; 540 mon_rx_user_status->other_msdu_count = 541 ppdu_info->rx_status.other_msdu_count; 542 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 543 mon_rx_user_status->frame_control_info_valid = 544 ppdu_info->rx_status.frame_control_info_valid; 545 mon_rx_user_status->data_sequence_control_info_valid = 546 ppdu_info->rx_status.data_sequence_control_info_valid; 547 mon_rx_user_status->first_data_seq_ctrl = 548 ppdu_info->rx_status.first_data_seq_ctrl; 549 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 550 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 551 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 552 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 553 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 554 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 555 556 mon_rx_user_status->mpdu_cnt_fcs_ok = 557 ppdu_info->com_info.mpdu_cnt_fcs_ok; 558 mon_rx_user_status->mpdu_cnt_fcs_err = 559 ppdu_info->com_info.mpdu_cnt_fcs_err; 560 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 561 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 562 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 563 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 564 mon_rx_user_status->retry_mpdu = 565 ppdu_info->rx_status.mpdu_retry_cnt; 566 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 567 } 568 569 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, \ 570 ppdu_info, rssi_info_tlv) \ 571 { \ 572 ppdu_info->rx_status.rssi_chain[chain][0] = \ 573 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 574 RSSI_PRI20_CHAIN##chain); \ 575 ppdu_info->rx_status.rssi_chain[chain][1] = \ 576 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 577 RSSI_EXT20_CHAIN##chain); \ 578 ppdu_info->rx_status.rssi_chain[chain][2] = \ 579 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 580 RSSI_EXT40_LOW20_CHAIN##chain); \ 581 ppdu_info->rx_status.rssi_chain[chain][3] = \ 582 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 583 RSSI_EXT40_HIGH20_CHAIN##chain); \ 584 } \ 585 586 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 587 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, ppdu_info, rssi_info_tlv) \ 588 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, ppdu_info, rssi_info_tlv) \ 589 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, ppdu_info, rssi_info_tlv) \ 590 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, ppdu_info, rssi_info_tlv) \ 591 } \ 592 593 static inline uint32_t 594 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 595 uint8_t *rssi_info_tlv) 596 { 597 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 598 return 0; 599 } 600 601 #ifdef WLAN_TX_PKT_CAPTURE_ENH 602 static inline void 603 hal_get_qos_control(void *rx_tlv, 604 struct hal_rx_ppdu_info *ppdu_info) 605 { 606 ppdu_info->rx_info.qos_control_info_valid = 607 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 608 QOS_CONTROL_INFO_VALID); 609 610 if (ppdu_info->rx_info.qos_control_info_valid) 611 ppdu_info->rx_info.qos_control = 612 HAL_RX_GET_64(rx_tlv, 613 RX_PPDU_END_USER_STATS, 614 QOS_CONTROL_FIELD); 615 } 616 617 static inline void 618 hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 619 struct hal_rx_ppdu_info *ppdu_info) 620 { 621 if ((ppdu_info->sw_frame_group_id 622 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 623 (ppdu_info->sw_frame_group_id == 624 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 625 ppdu_info->rx_info.mac_addr1_valid = 626 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_valid; 627 628 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 629 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_31_0; 630 if (ppdu_info->sw_frame_group_id == 631 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 632 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 633 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_47_32; 634 } 635 } 636 } 637 #else 638 static inline void 639 hal_get_qos_control(void *rx_tlv, 640 struct hal_rx_ppdu_info *ppdu_info) 641 { 642 } 643 644 static inline void 645 hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 646 struct hal_rx_ppdu_info *ppdu_info) 647 { 648 } 649 #endif 650 651 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 652 static inline void 653 hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 654 struct hal_rx_ppdu_info *ppdu_info) 655 { 656 uint16_t frame_ctrl; 657 uint8_t fc_type; 658 659 if (rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid) { 660 frame_ctrl = rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field; 661 fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl); 662 if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT) 663 ppdu_info->frm_type_info.rx_mgmt_cnt++; 664 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL) 665 ppdu_info->frm_type_info.rx_ctrl_cnt++; 666 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA) 667 ppdu_info->frm_type_info.rx_data_cnt++; 668 } 669 } 670 #else 671 static inline void 672 hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 673 struct hal_rx_ppdu_info *ppdu_info) 674 { 675 } 676 #endif 677 678 #ifdef QCA_MONITOR_2_0_SUPPORT 679 /** 680 * hal_mon_buff_addr_info_set() - set desc address in cookie 681 * @hal_soc_hdl: HAL Soc handle 682 * @mon_entry: monitor srng 683 * @desc: HAL monitor descriptor 684 * 685 * Return: none 686 */ 687 static inline 688 void hal_mon_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 689 void *mon_entry, 690 void *mon_desc_addr, 691 qdf_dma_addr_t phy_addr) 692 { 693 uint32_t paddr_lo = ((uintptr_t)phy_addr & 0x00000000ffffffff); 694 uint32_t paddr_hi = ((uintptr_t)phy_addr & 0xffffffff00000000) >> 32; 695 uint32_t vaddr_lo = ((uintptr_t)mon_desc_addr & 0x00000000ffffffff); 696 uint32_t vaddr_hi = ((uintptr_t)mon_desc_addr & 0xffffffff00000000) >> 32; 697 698 HAL_MON_PADDR_LO_SET(mon_entry, paddr_lo); 699 HAL_MON_PADDR_HI_SET(mon_entry, paddr_hi); 700 HAL_MON_VADDR_LO_SET(mon_entry, vaddr_lo); 701 HAL_MON_VADDR_HI_SET(mon_entry, vaddr_hi); 702 } 703 704 /* TX monitor */ 705 #define TX_MON_STATUS_BUF_SIZE 2048 706 707 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 708 709 #define HAL_MAX_DL_MU_USERS 37 710 #define HAL_MAX_RU_INDEX 7 711 712 enum hal_tx_tlv_status { 713 HAL_MON_TX_FES_SETUP, 714 HAL_MON_TX_FES_STATUS_END, 715 HAL_MON_RX_RESPONSE_REQUIRED_INFO, 716 HAL_MON_RESPONSE_END_STATUS_INFO, 717 718 HAL_MON_TX_PCU_PPDU_SETUP_INIT, 719 720 HAL_MON_TX_MPDU_START, 721 HAL_MON_TX_MSDU_START, 722 HAL_MON_TX_BUFFER_ADDR, 723 HAL_MON_TX_DATA, 724 725 HAL_MON_TX_FES_STATUS_START, 726 727 HAL_MON_TX_FES_STATUS_PROT, 728 HAL_MON_TX_FES_STATUS_START_PROT, 729 730 HAL_MON_TX_FES_STATUS_START_PPDU, 731 HAL_MON_TX_FES_STATUS_USER_PPDU, 732 HAL_MON_TX_QUEUE_EXTENSION, 733 734 HAL_MON_RX_FRAME_BITMAP_ACK, 735 HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_256, 736 HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K, 737 HAL_MON_COEX_TX_STATUS, 738 739 HAL_MON_MACTX_HE_SIG_A_SU, 740 HAL_MON_MACTX_HE_SIG_A_MU_DL, 741 HAL_MON_MACTX_HE_SIG_B1_MU, 742 HAL_MON_MACTX_HE_SIG_B2_MU, 743 HAL_MON_MACTX_HE_SIG_B2_OFDMA, 744 HAL_MON_MACTX_L_SIG_A, 745 HAL_MON_MACTX_L_SIG_B, 746 HAL_MON_MACTX_HT_SIG, 747 HAL_MON_MACTX_VHT_SIG_A, 748 749 HAL_MON_MACTX_USER_DESC_PER_USER, 750 HAL_MON_MACTX_USER_DESC_COMMON, 751 HAL_MON_MACTX_PHY_DESC, 752 753 HAL_MON_TX_FW2SW, 754 HAL_MON_TX_STATUS_PPDU_NOT_DONE, 755 }; 756 757 enum txmon_coex_tx_status_reason { 758 COEX_FES_TX_START, 759 COEX_FES_TX_END, 760 COEX_FES_END, 761 COEX_RESPONSE_TX_START, 762 COEX_RESPONSE_TX_END, 763 COEX_NO_TX_ONGOING, 764 }; 765 766 enum txmon_transmission_type { 767 TXMON_SU_TRANSMISSION = 0, 768 TXMON_MU_TRANSMISSION, 769 TXMON_MU_SU_TRANSMISSION, 770 TXMON_MU_MIMO_TRANSMISSION = 1, 771 TXMON_MU_OFDMA_TRANMISSION 772 }; 773 774 enum txmon_he_ppdu_subtype { 775 TXMON_HE_SUBTYPE_SU = 0, 776 TXMON_HE_SUBTYPE_TRIG, 777 TXMON_HE_SUBTYPE_MU, 778 TXMON_HE_SUBTYPE_EXT_SU 779 }; 780 781 enum txmon_pkt_type { 782 TXMON_PKT_TYPE_11A = 0, 783 TXMON_PKT_TYPE_11B, 784 TXMON_PKT_TYPE_11N_MM, 785 TXMON_PKT_TYPE_11AC, 786 TXMON_PKT_TYPE_11AX, 787 TXMON_PKT_TYPE_11BA, 788 TXMON_PKT_TYPE_11BE, 789 TXMON_PKT_TYPE_11AZ 790 }; 791 792 enum txmon_generated_response { 793 TXMON_GEN_RESP_SELFGEN_ACK = 0, 794 TXMON_GEN_RESP_SELFGEN_CTS, 795 TXMON_GEN_RESP_SELFGEN_BA, 796 TXMON_GEN_RESP_SELFGEN_MBA, 797 TXMON_GEN_RESP_SELFGEN_CBF, 798 TXMON_GEN_RESP_SELFGEN_TRIG, 799 TXMON_GEN_RESP_SELFGEN_NDP_LMR 800 }; 801 802 #define IS_MULTI_USERS(num_users) (!!(0xFFFE & num_users)) 803 804 #define TXMON_HAL(hal_tx_ppdu_info, field) \ 805 hal_tx_ppdu_info->field 806 #define TXMON_HAL_STATUS(hal_tx_ppdu_info, field) \ 807 hal_tx_ppdu_info->rx_status.field 808 #define TXMON_HAL_USER(hal_tx_ppdu_info, user_id, field) \ 809 hal_tx_ppdu_info->rx_user_status[user_id].field 810 811 #define TXMON_STATUS_INFO(hal_tx_status_info, field) \ 812 hal_tx_status_info->field 813 814 /** 815 * struct hal_tx_status_info - status info that wasn't populated in rx_status 816 * @reception_type: su or uplink mu reception type 817 * @transmission_type: su or mu transmission type 818 * @medium_prot_type: medium protection type 819 * @generated_response: Generated frame in response window 820 * @no_bitmap_avail: Bitmap available flag 821 * @explicit_ack: Explicit Acknowledge flag 822 * @explicit_ack_type: Explicit Acknowledge type 823 * @r2r_end_status_follow: Response to Response status flag 824 * @response_type: Response type in response window 825 * @ndp_frame: NDP frame 826 * @num_users: number of users 827 * @sw_frame_group_id: software frame group ID 828 * @r2r_to_follow: Response to Response follow flag 829 * @buffer: Packet buffer pointer address 830 * @offset: Packet buffer offset 831 * @length: Packet buffer length 832 * @protection_addr: Protection Address flag 833 * @addr1: MAC address 1 834 * @addr2: MAC address 2 835 * @addr3: MAC address 3 836 * @addr4: MAC address 4 837 */ 838 struct hal_tx_status_info { 839 uint8_t reception_type; 840 uint8_t transmission_type; 841 uint8_t medium_prot_type; 842 uint8_t generated_response; 843 844 uint16_t band_center_freq1; 845 uint16_t band_center_freq2; 846 uint16_t freq; 847 uint16_t phy_mode; 848 uint32_t schedule_id; 849 850 uint32_t no_bitmap_avail :1, 851 explicit_ack :1, 852 explicit_ack_type :4, 853 r2r_end_status_follow :1, 854 response_type :5, 855 ndp_frame :2, 856 num_users :8, 857 reserved :10; 858 859 uint8_t mba_count; 860 uint8_t mba_fake_bitmap_count; 861 862 uint8_t sw_frame_group_id; 863 uint32_t r2r_to_follow; 864 865 uint16_t phy_abort_reason; 866 uint8_t phy_abort_user_number; 867 868 void *buffer; 869 uint32_t offset; 870 uint32_t length; 871 872 uint8_t protection_addr; 873 uint8_t addr1[QDF_MAC_ADDR_SIZE]; 874 uint8_t addr2[QDF_MAC_ADDR_SIZE]; 875 uint8_t addr3[QDF_MAC_ADDR_SIZE]; 876 uint8_t addr4[QDF_MAC_ADDR_SIZE]; 877 }; 878 879 /** 880 * struct hal_tx_ppdu_info - tx monitor ppdu information 881 * @ppdu_id: Id of the PLCP protocol data unit 882 * @num_users: number of users 883 * @is_used: boolean flag to identify valid ppdu info 884 * @is_data: boolean flag to identify data frame 885 * @cur_usr_idx: Current user index of the PPDU 886 * @reserved: for future purpose 887 * @prot_tlv_status: protection tlv status 888 * @packet_info: packet information 889 * @rx_status: monitor mode rx status information 890 * @rx_user_status: monitor mode rx user status information 891 */ 892 struct hal_tx_ppdu_info { 893 uint32_t ppdu_id; 894 uint32_t num_users :8, 895 is_used :1, 896 is_data :1, 897 cur_usr_idx :8, 898 reserved :15; 899 900 uint32_t prot_tlv_status; 901 902 /* placeholder to hold packet buffer info */ 903 struct hal_mon_packet_info packet_info; 904 struct mon_rx_status rx_status; 905 struct mon_rx_user_status rx_user_status[]; 906 }; 907 908 /** 909 * hal_tx_status_get_next_tlv() - get next tx status TLV 910 * @tx_tlv: pointer to TLV header 911 * 912 * Return: pointer to next tlv info 913 */ 914 static inline uint8_t* 915 hal_tx_status_get_next_tlv(uint8_t *tx_tlv) { 916 uint32_t tlv_len, tlv_tag; 917 918 tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv); 919 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv); 920 921 return (uint8_t *)(((unsigned long)(tx_tlv + tlv_len + 922 HAL_RX_TLV32_HDR_SIZE + 7)) & (~7)); 923 } 924 925 /** 926 * hal_txmon_status_parse_tlv() - process transmit info TLV 927 * @hal_soc: HAL soc handle 928 * @data_ppdu_info: pointer to hal data ppdu info 929 * @prot_ppdu_info: pointer to hal prot ppdu info 930 * @data_status_info: pointer to data status info 931 * @prot_status_info: pointer to prot status info 932 * @tx_tlv_hdr: pointer to TLV header 933 * @status_frag: pointer to status frag 934 * 935 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE 936 */ 937 static inline uint32_t 938 hal_txmon_status_parse_tlv(hal_soc_handle_t hal_soc_hdl, 939 void *data_ppdu_info, 940 void *prot_ppdu_info, 941 void *data_status_info, 942 void *prot_status_info, 943 void *tx_tlv_hdr, 944 qdf_frag_t status_frag) 945 { 946 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 947 948 return hal_soc->ops->hal_txmon_status_parse_tlv(data_ppdu_info, 949 prot_ppdu_info, 950 data_status_info, 951 prot_status_info, 952 tx_tlv_hdr, 953 status_frag); 954 } 955 956 /** 957 * hal_txmon_status_get_num_users() - api to get num users from start of fes 958 * window 959 * @hal_soc: HAL soc handle 960 * @tx_tlv_hdr: pointer to TLV header 961 * @num_users: reference to number of user 962 * 963 * Return: status 964 */ 965 static inline uint32_t 966 hal_txmon_status_get_num_users(hal_soc_handle_t hal_soc_hdl, 967 void *tx_tlv_hdr, uint8_t *num_users) 968 { 969 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 970 971 return hal_soc->ops->hal_txmon_status_get_num_users(tx_tlv_hdr, 972 num_users); 973 } 974 975 /** 976 * hal_tx_status_get_tlv_tag() - api to get tlv tag 977 * @tx_tlv_hdr: pointer to TLV header 978 * 979 * Return tlv_tag 980 */ 981 static inline uint32_t 982 hal_tx_status_get_tlv_tag(void *tx_tlv_hdr) 983 { 984 uint32_t tlv_tag = 0; 985 986 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr); 987 988 return tlv_tag; 989 } 990 #endif 991 992 /** 993 * hal_txmon_is_mon_buf_addr_tlv() - api to find packet buffer addr tlv 994 * @hal_soc: HAL soc handle 995 * @tx_tlv_hdr: pointer to TLV header 996 * 997 * Return: bool 998 */ 999 static inline bool 1000 hal_txmon_is_mon_buf_addr_tlv(hal_soc_handle_t hal_soc_hdl, void *tx_tlv_hdr) 1001 { 1002 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1003 1004 if (qdf_unlikely(!hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv)) 1005 return false; 1006 1007 return hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv(tx_tlv_hdr); 1008 } 1009 1010 /** 1011 * hal_txmon_populate_packet_info() - api to populate packet info 1012 * @hal_soc: HAL soc handle 1013 * @tx_tlv_hdr: pointer to TLV header 1014 * @packet_info: pointer to placeholder for packet info 1015 * 1016 * Return void 1017 */ 1018 static inline void 1019 hal_txmon_populate_packet_info(hal_soc_handle_t hal_soc_hdl, 1020 void *tx_tlv_hdr, 1021 void *packet_info) 1022 { 1023 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1024 1025 if (qdf_unlikely(!hal_soc->ops->hal_txmon_populate_packet_info)) 1026 return; 1027 1028 hal_soc->ops->hal_txmon_populate_packet_info(tx_tlv_hdr, packet_info); 1029 } 1030 1031 static inline uint32_t 1032 hal_rx_parse_u_sig_cmn(struct hal_soc *hal_soc, void *rx_tlv, 1033 struct hal_rx_ppdu_info *ppdu_info) 1034 { 1035 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1036 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 1037 uint8_t bad_usig_crc; 1038 1039 bad_usig_crc = HAL_RX_MON_USIG_GET_RX_INTEGRITY_CHECK_PASSED(rx_tlv) ? 1040 0 : 1; 1041 ppdu_info->rx_status.usig_common |= 1042 QDF_MON_STATUS_USIG_PHY_VERSION_KNOWN | 1043 QDF_MON_STATUS_USIG_BW_KNOWN | 1044 QDF_MON_STATUS_USIG_UL_DL_KNOWN | 1045 QDF_MON_STATUS_USIG_BSS_COLOR_KNOWN | 1046 QDF_MON_STATUS_USIG_TXOP_KNOWN; 1047 1048 ppdu_info->rx_status.usig_common |= (usig_1->phy_version << 1049 QDF_MON_STATUS_USIG_PHY_VERSION_SHIFT); 1050 ppdu_info->rx_status.usig_common |= (usig_1->bw << 1051 QDF_MON_STATUS_USIG_BW_SHIFT); 1052 ppdu_info->rx_status.usig_common |= (usig_1->ul_dl << 1053 QDF_MON_STATUS_USIG_UL_DL_SHIFT); 1054 ppdu_info->rx_status.usig_common |= (usig_1->bss_color << 1055 QDF_MON_STATUS_USIG_BSS_COLOR_SHIFT); 1056 ppdu_info->rx_status.usig_common |= (usig_1->txop << 1057 QDF_MON_STATUS_USIG_TXOP_SHIFT); 1058 ppdu_info->rx_status.usig_common |= bad_usig_crc; 1059 1060 ppdu_info->u_sig_info.ul_dl = usig_1->ul_dl; 1061 ppdu_info->u_sig_info.bw = usig_1->bw; 1062 ppdu_info->rx_status.bw = usig_1->bw; 1063 1064 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1065 } 1066 1067 static inline uint32_t 1068 hal_rx_parse_u_sig_tb(struct hal_soc *hal_soc, void *rx_tlv, 1069 struct hal_rx_ppdu_info *ppdu_info) 1070 { 1071 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1072 struct hal_mon_usig_tb *usig_tb = &usig->usig_2.tb; 1073 1074 ppdu_info->rx_status.usig_mask |= 1075 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 1076 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 1077 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 1078 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_KNOWN | 1079 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_KNOWN | 1080 QDF_MON_STATUS_USIG_TB_DISREGARD1_KNOWN | 1081 QDF_MON_STATUS_USIG_CRC_KNOWN | 1082 QDF_MON_STATUS_USIG_TAIL_KNOWN; 1083 1084 ppdu_info->rx_status.usig_value |= (0x3F << 1085 QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 1086 ppdu_info->rx_status.usig_value |= (usig_tb->ppdu_type_comp_mode << 1087 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 1088 ppdu_info->rx_status.usig_value |= (0x1 << 1089 QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 1090 ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_1 << 1091 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_SHIFT); 1092 ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_2 << 1093 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_SHIFT); 1094 ppdu_info->rx_status.usig_value |= (0x1F << 1095 QDF_MON_STATUS_USIG_TB_DISREGARD1_SHIFT); 1096 ppdu_info->rx_status.usig_value |= (usig_tb->crc << 1097 QDF_MON_STATUS_USIG_CRC_SHIFT); 1098 ppdu_info->rx_status.usig_value |= (usig_tb->tail << 1099 QDF_MON_STATUS_USIG_TAIL_SHIFT); 1100 1101 ppdu_info->u_sig_info.ppdu_type_comp_mode = 1102 usig_tb->ppdu_type_comp_mode; 1103 1104 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1105 } 1106 1107 static inline uint32_t 1108 hal_rx_parse_u_sig_mu(struct hal_soc *hal_soc, void *rx_tlv, 1109 struct hal_rx_ppdu_info *ppdu_info) 1110 { 1111 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1112 struct hal_mon_usig_mu *usig_mu = &usig->usig_2.mu; 1113 1114 ppdu_info->rx_status.usig_mask |= 1115 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 1116 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 1117 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 1118 QDF_MON_STATUS_USIG_MU_VALIDATE1_KNOWN | 1119 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_KNOWN | 1120 QDF_MON_STATUS_USIG_MU_VALIDATE2_KNOWN | 1121 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_KNOWN | 1122 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_KNOWN | 1123 QDF_MON_STATUS_USIG_CRC_KNOWN | 1124 QDF_MON_STATUS_USIG_TAIL_KNOWN; 1125 1126 ppdu_info->rx_status.usig_value |= (0x1F << 1127 QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 1128 ppdu_info->rx_status.usig_value |= (0x1 << 1129 QDF_MON_STATUS_USIG_MU_VALIDATE1_SHIFT); 1130 ppdu_info->rx_status.usig_value |= (usig_mu->ppdu_type_comp_mode << 1131 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 1132 ppdu_info->rx_status.usig_value |= (0x1 << 1133 QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 1134 ppdu_info->rx_status.usig_value |= (usig_mu->punc_ch_info << 1135 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_SHIFT); 1136 ppdu_info->rx_status.usig_value |= (0x1 << 1137 QDF_MON_STATUS_USIG_MU_VALIDATE2_SHIFT); 1138 ppdu_info->rx_status.usig_value |= (usig_mu->eht_sig_mcs << 1139 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_SHIFT); 1140 ppdu_info->rx_status.usig_value |= (usig_mu->num_eht_sig_sym << 1141 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_SHIFT); 1142 ppdu_info->rx_status.usig_value |= (usig_mu->crc << 1143 QDF_MON_STATUS_USIG_CRC_SHIFT); 1144 ppdu_info->rx_status.usig_value |= (usig_mu->tail << 1145 QDF_MON_STATUS_USIG_TAIL_SHIFT); 1146 1147 ppdu_info->u_sig_info.ppdu_type_comp_mode = 1148 usig_mu->ppdu_type_comp_mode; 1149 ppdu_info->u_sig_info.eht_sig_mcs = usig_mu->eht_sig_mcs; 1150 ppdu_info->u_sig_info.num_eht_sig_sym = usig_mu->num_eht_sig_sym; 1151 1152 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1153 } 1154 1155 static inline uint32_t 1156 hal_rx_parse_u_sig_hdr(struct hal_soc *hal_soc, void *rx_tlv, 1157 struct hal_rx_ppdu_info *ppdu_info) 1158 { 1159 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1160 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 1161 1162 ppdu_info->rx_status.usig_flags = 1; 1163 1164 hal_rx_parse_u_sig_cmn(hal_soc, rx_tlv, ppdu_info); 1165 1166 if (HAL_RX_MON_USIG_GET_PPDU_TYPE_N_COMP_MODE(rx_tlv) == 0 && 1167 usig_1->ul_dl == 1) 1168 return hal_rx_parse_u_sig_tb(hal_soc, rx_tlv, ppdu_info); 1169 else 1170 return hal_rx_parse_u_sig_mu(hal_soc, rx_tlv, ppdu_info); 1171 } 1172 1173 static inline uint32_t 1174 hal_rx_parse_usig_overflow(struct hal_soc *hal_soc, void *tlv, 1175 struct hal_rx_ppdu_info *ppdu_info) 1176 { 1177 struct hal_eht_sig_cc_usig_overflow *usig_ovflow = 1178 (struct hal_eht_sig_cc_usig_overflow *)tlv; 1179 1180 ppdu_info->rx_status.eht_known |= 1181 QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1182 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1183 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_KNOWN | 1184 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_KNOWN | 1185 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_KNOWN | 1186 QDF_MON_STATUS_EHT_DISREARD_KNOWN; 1187 1188 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->spatial_reuse << 1189 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1190 /* 1191 * GI and LTF size are separately indicated in radiotap header 1192 * and hence will be parsed from other TLV 1193 **/ 1194 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->num_ltf_sym << 1195 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1196 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->ldpc_extra_sym << 1197 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_SHIFT); 1198 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pre_fec_pad_factor << 1199 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_SHIFT); 1200 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pe_disambiguity << 1201 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_SHIFT); 1202 ppdu_info->rx_status.eht_data[0] |= (0xF << 1203 QDF_MON_STATUS_EHT_DISREGARD_SHIFT); 1204 1205 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1206 } 1207 1208 static inline uint32_t 1209 hal_rx_parse_non_ofdma_users(struct hal_soc *hal_soc, void *tlv, 1210 struct hal_rx_ppdu_info *ppdu_info) 1211 { 1212 struct hal_eht_sig_non_ofdma_cmn_eb *non_ofdma_cmn_eb = 1213 (struct hal_eht_sig_non_ofdma_cmn_eb *)tlv; 1214 1215 ppdu_info->rx_status.eht_known |= 1216 QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_KNOWN; 1217 1218 ppdu_info->rx_status.eht_data[4] |= (non_ofdma_cmn_eb->num_users << 1219 QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_SHIFT); 1220 1221 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1222 } 1223 1224 static inline uint32_t 1225 hal_rx_parse_ru_allocation(struct hal_soc *hal_soc, void *tlv, 1226 struct hal_rx_ppdu_info *ppdu_info) 1227 { 1228 uint64_t *ehtsig_tlv = (uint64_t *)tlv; 1229 struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cmn_eb1; 1230 struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cmn_eb2; 1231 uint8_t num_ru_allocation_known = 0; 1232 1233 ofdma_cmn_eb1 = (struct hal_eht_sig_ofdma_cmn_eb1 *)ehtsig_tlv; 1234 ofdma_cmn_eb2 = (struct hal_eht_sig_ofdma_cmn_eb2 *)(ehtsig_tlv + 1); 1235 1236 switch (ppdu_info->u_sig_info.bw) { 1237 case HAL_EHT_BW_320_2: 1238 case HAL_EHT_BW_320_1: 1239 num_ru_allocation_known += 4; 1240 1241 ppdu_info->rx_status.eht_data[3] |= 1242 (ofdma_cmn_eb2->ru_allocation2_6 << 1243 QDF_MON_STATUS_EHT_RU_ALLOCATION2_6_SHIFT); 1244 ppdu_info->rx_status.eht_data[3] |= 1245 (ofdma_cmn_eb2->ru_allocation2_5 << 1246 QDF_MON_STATUS_EHT_RU_ALLOCATION2_5_SHIFT); 1247 ppdu_info->rx_status.eht_data[3] |= 1248 (ofdma_cmn_eb2->ru_allocation2_4 << 1249 QDF_MON_STATUS_EHT_RU_ALLOCATION2_4_SHIFT); 1250 ppdu_info->rx_status.eht_data[2] |= 1251 (ofdma_cmn_eb2->ru_allocation2_3 << 1252 QDF_MON_STATUS_EHT_RU_ALLOCATION2_3_SHIFT); 1253 fallthrough; 1254 case HAL_EHT_BW_160: 1255 num_ru_allocation_known += 2; 1256 1257 ppdu_info->rx_status.eht_data[2] |= 1258 (ofdma_cmn_eb2->ru_allocation2_2 << 1259 QDF_MON_STATUS_EHT_RU_ALLOCATION2_2_SHIFT); 1260 ppdu_info->rx_status.eht_data[2] |= 1261 (ofdma_cmn_eb2->ru_allocation2_1 << 1262 QDF_MON_STATUS_EHT_RU_ALLOCATION2_1_SHIFT); 1263 fallthrough; 1264 case HAL_EHT_BW_80: 1265 num_ru_allocation_known += 1; 1266 1267 ppdu_info->rx_status.eht_data[1] |= 1268 (ofdma_cmn_eb1->ru_allocation1_2 << 1269 QDF_MON_STATUS_EHT_RU_ALLOCATION1_2_SHIFT); 1270 fallthrough; 1271 case HAL_EHT_BW_40: 1272 case HAL_EHT_BW_20: 1273 num_ru_allocation_known += 1; 1274 1275 ppdu_info->rx_status.eht_data[1] |= 1276 (ofdma_cmn_eb1->ru_allocation1_1 << 1277 QDF_MON_STATUS_EHT_RU_ALLOCATION1_1_SHIFT); 1278 break; 1279 default: 1280 break; 1281 } 1282 1283 ppdu_info->rx_status.eht_known |= (num_ru_allocation_known << 1284 QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT); 1285 1286 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1287 } 1288 1289 static inline uint32_t 1290 hal_rx_parse_eht_sig_mumimo_user_info(struct hal_soc *hal_soc, void *tlv, 1291 struct hal_rx_ppdu_info *ppdu_info) 1292 { 1293 struct hal_eht_sig_mu_mimo_user_info *user_info; 1294 uint32_t user_idx = ppdu_info->rx_status.num_eht_user_info_valid; 1295 1296 user_info = (struct hal_eht_sig_mu_mimo_user_info *)tlv; 1297 1298 ppdu_info->rx_status.eht_user_info[user_idx] |= 1299 QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1300 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1301 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1302 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_KNOWN; 1303 1304 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->sta_id << 1305 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1306 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->mcs << 1307 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1308 ppdu_info->rx_status.mcs = user_info->mcs; 1309 1310 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->coding << 1311 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1312 ppdu_info->rx_status.eht_user_info[user_idx] |= 1313 (user_info->spatial_coding << 1314 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_SHIFT); 1315 1316 /* CRC for matched user block */ 1317 ppdu_info->rx_status.eht_known |= 1318 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN | 1319 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN; 1320 ppdu_info->rx_status.eht_data[4] |= (user_info->crc << 1321 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT); 1322 1323 ppdu_info->rx_status.num_eht_user_info_valid++; 1324 1325 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1326 } 1327 1328 static inline uint32_t 1329 hal_rx_parse_eht_sig_non_mumimo_user_info(struct hal_soc *hal_soc, void *tlv, 1330 struct hal_rx_ppdu_info *ppdu_info) 1331 { 1332 struct hal_eht_sig_non_mu_mimo_user_info *user_info; 1333 uint32_t user_idx = ppdu_info->rx_status.num_eht_user_info_valid; 1334 1335 user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tlv; 1336 1337 ppdu_info->rx_status.eht_user_info[user_idx] |= 1338 QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1339 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1340 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1341 QDF_MON_STATUS_EHT_USER_NSS_KNOWN | 1342 QDF_MON_STATUS_EHT_USER_BEAMFORMING_KNOWN; 1343 1344 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->sta_id << 1345 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1346 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->mcs << 1347 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1348 ppdu_info->rx_status.mcs = user_info->mcs; 1349 1350 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->nss << 1351 QDF_MON_STATUS_EHT_USER_NSS_SHIFT); 1352 ppdu_info->rx_status.nss = user_info->nss + 1; 1353 1354 ppdu_info->rx_status.eht_user_info[user_idx] |= 1355 (user_info->beamformed << 1356 QDF_MON_STATUS_EHT_USER_BEAMFORMING_SHIFT); 1357 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->coding << 1358 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1359 1360 /* CRC for matched user block */ 1361 ppdu_info->rx_status.eht_known |= 1362 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN | 1363 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN; 1364 ppdu_info->rx_status.eht_data[4] |= (user_info->crc << 1365 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT); 1366 1367 ppdu_info->rx_status.num_eht_user_info_valid++; 1368 1369 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1370 } 1371 1372 static inline bool hal_rx_is_ofdma(struct hal_soc *hal_soc, 1373 struct hal_rx_ppdu_info *ppdu_info) 1374 { 1375 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 0 && 1376 ppdu_info->u_sig_info.ul_dl == 0) 1377 return true; 1378 1379 return false; 1380 } 1381 1382 static inline bool hal_rx_is_non_ofdma(struct hal_soc *hal_soc, 1383 struct hal_rx_ppdu_info *ppdu_info) 1384 { 1385 uint32_t ppdu_type_comp_mode = 1386 ppdu_info->u_sig_info.ppdu_type_comp_mode; 1387 uint32_t ul_dl = ppdu_info->u_sig_info.ul_dl; 1388 1389 if ((ppdu_type_comp_mode == 1 && ul_dl == 0) || 1390 (ppdu_type_comp_mode == 2 && ul_dl == 0) || 1391 (ppdu_type_comp_mode == 1 && ul_dl == 1)) 1392 return true; 1393 1394 return false; 1395 } 1396 1397 static inline bool hal_rx_is_mu_mimo_user(struct hal_soc *hal_soc, 1398 struct hal_rx_ppdu_info *ppdu_info) 1399 { 1400 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 2 && 1401 ppdu_info->u_sig_info.ul_dl == 0) 1402 return true; 1403 1404 return false; 1405 } 1406 1407 static inline bool 1408 hal_rx_is_frame_type_ndp(struct hal_soc *hal_soc, 1409 struct hal_rx_ppdu_info *ppdu_info) 1410 { 1411 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 1 && 1412 ppdu_info->u_sig_info.eht_sig_mcs == 0 && 1413 ppdu_info->u_sig_info.num_eht_sig_sym == 0) 1414 return true; 1415 1416 return false; 1417 } 1418 1419 static inline uint32_t 1420 hal_rx_parse_eht_sig_ndp(struct hal_soc *hal_soc, void *tlv, 1421 struct hal_rx_ppdu_info *ppdu_info) 1422 { 1423 struct hal_eht_sig_ndp_cmn_eb *eht_sig_ndp = 1424 (struct hal_eht_sig_ndp_cmn_eb *)tlv; 1425 1426 ppdu_info->rx_status.eht_known |= 1427 QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1428 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1429 QDF_MON_STATUS_EHT_NDP_NSS_KNOWN | 1430 QDF_MON_STATUS_EHT_NDP_BEAMFORMED_KNOWN | 1431 QDF_MON_STATUS_EHT_NDP_DISREGARD_KNOWN | 1432 QDF_MON_STATUS_EHT_CRC1_KNOWN | 1433 QDF_MON_STATUS_EHT_TAIL1_KNOWN; 1434 1435 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->spatial_reuse << 1436 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1437 /* 1438 * GI and LTF size are separately indicated in radiotap header 1439 * and hence will be parsed from other TLV 1440 **/ 1441 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->num_ltf_sym << 1442 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1443 ppdu_info->rx_status.eht_data[0] |= (0xF << 1444 QDF_MON_STATUS_EHT_NDP_DISREGARD_SHIFT); 1445 1446 ppdu_info->rx_status.eht_data[4] |= (eht_sig_ndp->nss << 1447 QDF_MON_STATUS_EHT_NDP_NSS_SHIFT); 1448 ppdu_info->rx_status.eht_data[4] |= (eht_sig_ndp->beamformed << 1449 QDF_MON_STATUS_EHT_NDP_BEAMFORMED_SHIFT); 1450 1451 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->crc << 1452 QDF_MON_STATUS_EHT_CRC1_SHIFT); 1453 1454 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1455 } 1456 1457 static inline uint32_t 1458 hal_rx_parse_eht_sig_non_ofdma(struct hal_soc *hal_soc, void *tlv, 1459 struct hal_rx_ppdu_info *ppdu_info) 1460 { 1461 void *user_info = (void *)((uint8_t *)tlv + 4); 1462 1463 hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info); 1464 hal_rx_parse_non_ofdma_users(hal_soc, tlv, ppdu_info); 1465 1466 if (hal_rx_is_mu_mimo_user(hal_soc, ppdu_info)) 1467 hal_rx_parse_eht_sig_mumimo_user_info(hal_soc, user_info, 1468 ppdu_info); 1469 else 1470 hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, user_info, 1471 ppdu_info); 1472 1473 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1474 } 1475 1476 static inline uint32_t 1477 hal_rx_parse_eht_sig_ofdma(struct hal_soc *hal_soc, void *tlv, 1478 struct hal_rx_ppdu_info *ppdu_info) 1479 { 1480 uint64_t *eht_sig_tlv = (uint64_t *)tlv; 1481 void *user_info = (void *)(eht_sig_tlv + 2); 1482 1483 hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info); 1484 hal_rx_parse_ru_allocation(hal_soc, tlv, ppdu_info); 1485 hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, user_info, 1486 ppdu_info); 1487 1488 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1489 } 1490 1491 static inline uint32_t 1492 hal_rx_parse_eht_sig_hdr(struct hal_soc *hal_soc, uint8_t *tlv, 1493 struct hal_rx_ppdu_info *ppdu_info) 1494 { 1495 ppdu_info->rx_status.eht_flags = 1; 1496 1497 if (hal_rx_is_frame_type_ndp(hal_soc, ppdu_info)) 1498 hal_rx_parse_eht_sig_ndp(hal_soc, tlv, ppdu_info); 1499 else if (hal_rx_is_non_ofdma(hal_soc, ppdu_info)) 1500 hal_rx_parse_eht_sig_non_ofdma(hal_soc, tlv, ppdu_info); 1501 else if (hal_rx_is_ofdma(hal_soc, ppdu_info)) 1502 hal_rx_parse_eht_sig_ofdma(hal_soc, tlv, ppdu_info); 1503 1504 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1505 } 1506 1507 #ifdef WLAN_FEATURE_11BE 1508 static inline void 1509 hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info, 1510 struct hal_rx_ppdu_info *ppdu_info) 1511 { 1512 ppdu_info->rx_status.punctured_pattern = cmn_usr_info->puncture_bitmap; 1513 } 1514 #else 1515 static inline void 1516 hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info, 1517 struct hal_rx_ppdu_info *ppdu_info) 1518 { 1519 } 1520 #endif 1521 static inline uint32_t 1522 hal_rx_parse_cmn_usr_info(struct hal_soc *hal_soc, uint8_t *tlv, 1523 struct hal_rx_ppdu_info *ppdu_info) 1524 { 1525 struct phyrx_common_user_info *cmn_usr_info = 1526 (struct phyrx_common_user_info *)tlv; 1527 1528 ppdu_info->rx_status.eht_known |= 1529 QDF_MON_STATUS_EHT_GUARD_INTERVAL_KNOWN | 1530 QDF_MON_STATUS_EHT_LTF_KNOWN; 1531 1532 ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->cp_setting << 1533 QDF_MON_STATUS_EHT_GI_SHIFT); 1534 if (!ppdu_info->rx_status.sgi) 1535 ppdu_info->rx_status.sgi = cmn_usr_info->cp_setting; 1536 1537 ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->ltf_size << 1538 QDF_MON_STATUS_EHT_LTF_SHIFT); 1539 if (!ppdu_info->rx_status.ltf_size) 1540 ppdu_info->rx_status.ltf_size = cmn_usr_info->ltf_size; 1541 1542 hal_rx_parse_punctured_pattern(cmn_usr_info, ppdu_info); 1543 1544 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1545 } 1546 1547 #ifdef WLAN_FEATURE_11BE 1548 static inline void 1549 hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size, 1550 uint32_t *ru_width) 1551 { 1552 uint32_t width; 1553 1554 width = 0; 1555 switch (ru_size) { 1556 case IEEE80211_EHT_RU_26: 1557 width = RU_26; 1558 break; 1559 case IEEE80211_EHT_RU_52: 1560 width = RU_52; 1561 break; 1562 case IEEE80211_EHT_RU_52_26: 1563 width = RU_52_26; 1564 break; 1565 case IEEE80211_EHT_RU_106: 1566 width = RU_106; 1567 break; 1568 case IEEE80211_EHT_RU_106_26: 1569 width = RU_106_26; 1570 break; 1571 case IEEE80211_EHT_RU_242: 1572 width = RU_242; 1573 break; 1574 case IEEE80211_EHT_RU_484: 1575 width = RU_484; 1576 break; 1577 case IEEE80211_EHT_RU_484_242: 1578 width = RU_484_242; 1579 break; 1580 case IEEE80211_EHT_RU_996: 1581 width = RU_996; 1582 break; 1583 case IEEE80211_EHT_RU_996_484: 1584 width = RU_996_484; 1585 break; 1586 case IEEE80211_EHT_RU_996_484_242: 1587 width = RU_996_484_242; 1588 break; 1589 case IEEE80211_EHT_RU_996x2: 1590 width = RU_2X996; 1591 break; 1592 case IEEE80211_EHT_RU_996x2_484: 1593 width = RU_2X996_484; 1594 break; 1595 case IEEE80211_EHT_RU_996x3: 1596 width = RU_3X996; 1597 break; 1598 case IEEE80211_EHT_RU_996x3_484: 1599 width = RU_3X996_484; 1600 break; 1601 case IEEE80211_EHT_RU_996x4: 1602 width = RU_4X996; 1603 break; 1604 default: 1605 hal_err_rl("RU size(%d) to width convert err", ru_size); 1606 break; 1607 } 1608 *ru_width = width; 1609 } 1610 #else 1611 static inline void 1612 hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size, 1613 uint32_t *ru_width) 1614 { 1615 *ru_width = 0; 1616 } 1617 #endif 1618 1619 static inline enum ieee80211_eht_ru_size 1620 hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(struct hal_soc *hal_soc, 1621 uint32_t hal_ru_size) 1622 { 1623 switch (hal_ru_size) { 1624 case HAL_EHT_RU_26: 1625 return IEEE80211_EHT_RU_26; 1626 case HAL_EHT_RU_52: 1627 return IEEE80211_EHT_RU_52; 1628 case HAL_EHT_RU_78: 1629 return IEEE80211_EHT_RU_52_26; 1630 case HAL_EHT_RU_106: 1631 return IEEE80211_EHT_RU_106; 1632 case HAL_EHT_RU_132: 1633 return IEEE80211_EHT_RU_106_26; 1634 case HAL_EHT_RU_242: 1635 return IEEE80211_EHT_RU_242; 1636 case HAL_EHT_RU_484: 1637 return IEEE80211_EHT_RU_484; 1638 case HAL_EHT_RU_726: 1639 return IEEE80211_EHT_RU_484_242; 1640 case HAL_EHT_RU_996: 1641 return IEEE80211_EHT_RU_996; 1642 case HAL_EHT_RU_996x2: 1643 return IEEE80211_EHT_RU_996x2; 1644 case HAL_EHT_RU_996x3: 1645 return IEEE80211_EHT_RU_996x3; 1646 case HAL_EHT_RU_996x4: 1647 return IEEE80211_EHT_RU_996x4; 1648 case HAL_EHT_RU_NONE: 1649 return IEEE80211_EHT_RU_INVALID; 1650 case HAL_EHT_RU_996_484: 1651 return IEEE80211_EHT_RU_996_484; 1652 case HAL_EHT_RU_996x2_484: 1653 return IEEE80211_EHT_RU_996x2_484; 1654 case HAL_EHT_RU_996x3_484: 1655 return IEEE80211_EHT_RU_996x3_484; 1656 case HAL_EHT_RU_996_484_242: 1657 return IEEE80211_EHT_RU_996_484_242; 1658 default: 1659 return IEEE80211_EHT_RU_INVALID; 1660 } 1661 } 1662 1663 #define HAL_SET_RU_PER80(ru_320mhz, ru_per80, ru_idx_per80mhz, num_80mhz) \ 1664 ((ru_320mhz) |= ((uint64_t)(ru_per80) << \ 1665 (((num_80mhz) * NUM_RU_BITS_PER80) + \ 1666 ((ru_idx_per80mhz) * NUM_RU_BITS_PER20)))) 1667 1668 static inline uint32_t 1669 hal_rx_parse_receive_user_info(struct hal_soc *hal_soc, uint8_t *tlv, 1670 struct hal_rx_ppdu_info *ppdu_info, 1671 uint32_t user_id) 1672 { 1673 struct receive_user_info *rx_usr_info = (struct receive_user_info *)tlv; 1674 struct mon_rx_user_status *mon_rx_user_status = NULL; 1675 uint64_t ru_index_320mhz = 0; 1676 uint16_t ru_index_per80mhz; 1677 uint32_t ru_size = 0, num_80mhz_with_ru = 0; 1678 uint32_t ru_index = HAL_EHT_RU_INVALID; 1679 uint32_t rtap_ru_size = IEEE80211_EHT_RU_INVALID; 1680 uint32_t ru_width; 1681 1682 ppdu_info->rx_status.eht_known |= 1683 QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_KNOWN; 1684 ppdu_info->rx_status.eht_data[0] |= 1685 (rx_usr_info->dl_ofdma_content_channel << 1686 QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_SHIFT); 1687 1688 switch (rx_usr_info->reception_type) { 1689 case HAL_RECEPTION_TYPE_SU: 1690 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1691 break; 1692 case HAL_RECEPTION_TYPE_DL_MU_MIMO: 1693 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 1694 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1695 break; 1696 case HAL_RECEPTION_TYPE_UL_MU_MIMO: 1697 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 1698 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1699 break; 1700 case HAL_RECEPTION_TYPE_DL_MU_OFMA: 1701 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 1702 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1703 break; 1704 case HAL_RECEPTION_TYPE_UL_MU_OFDMA: 1705 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 1706 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1707 break; 1708 case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO: 1709 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 1710 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA_MIMO; 1711 break; 1712 case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO: 1713 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 1714 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA_MIMO; 1715 break; 1716 } 1717 1718 ppdu_info->start_user_info_cnt++; 1719 1720 ppdu_info->rx_status.is_stbc = rx_usr_info->stbc; 1721 ppdu_info->rx_status.ldpc = rx_usr_info->ldpc; 1722 ppdu_info->rx_status.dcm = rx_usr_info->sta_dcm; 1723 ppdu_info->rx_status.mcs = rx_usr_info->rate_mcs; 1724 ppdu_info->rx_status.nss = rx_usr_info->nss + 1; 1725 1726 if (user_id < HAL_MAX_UL_MU_USERS) { 1727 mon_rx_user_status = 1728 &ppdu_info->rx_user_status[user_id]; 1729 mon_rx_user_status->mcs = ppdu_info->rx_status.mcs; 1730 mon_rx_user_status->nss = ppdu_info->rx_status.nss; 1731 } 1732 1733 if (!(ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_MIMO || 1734 ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA || 1735 ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA_MIMO)) 1736 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1737 1738 /* RU allocation present only for OFDMA reception */ 1739 if (rx_usr_info->ru_type_80_0 != HAL_EHT_RU_NONE) { 1740 ru_size += rx_usr_info->ru_type_80_0; 1741 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_0; 1742 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_0, 1743 ru_index_per80mhz, 0); 1744 num_80mhz_with_ru++; 1745 } 1746 1747 if (rx_usr_info->ru_type_80_1 != HAL_EHT_RU_NONE) { 1748 ru_size += rx_usr_info->ru_type_80_1; 1749 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_1; 1750 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_1, 1751 ru_index_per80mhz, 1); 1752 num_80mhz_with_ru++; 1753 } 1754 1755 if (rx_usr_info->ru_type_80_2 != HAL_EHT_RU_NONE) { 1756 ru_size += rx_usr_info->ru_type_80_2; 1757 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_2; 1758 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_2, 1759 ru_index_per80mhz, 2); 1760 num_80mhz_with_ru++; 1761 } 1762 1763 if (rx_usr_info->ru_type_80_3 != HAL_EHT_RU_NONE) { 1764 ru_size += rx_usr_info->ru_type_80_3; 1765 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_3; 1766 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_3, 1767 ru_index_per80mhz, 3); 1768 num_80mhz_with_ru++; 1769 } 1770 1771 if (num_80mhz_with_ru > 1) { 1772 /* Calculate the MRU index */ 1773 switch (ru_index_320mhz) { 1774 case HAL_EHT_RU_996_484_0: 1775 case HAL_EHT_RU_996x2_484_0: 1776 case HAL_EHT_RU_996x3_484_0: 1777 ru_index = 0; 1778 break; 1779 case HAL_EHT_RU_996_484_1: 1780 case HAL_EHT_RU_996x2_484_1: 1781 case HAL_EHT_RU_996x3_484_1: 1782 ru_index = 1; 1783 break; 1784 case HAL_EHT_RU_996_484_2: 1785 case HAL_EHT_RU_996x2_484_2: 1786 case HAL_EHT_RU_996x3_484_2: 1787 ru_index = 2; 1788 break; 1789 case HAL_EHT_RU_996_484_3: 1790 case HAL_EHT_RU_996x2_484_3: 1791 case HAL_EHT_RU_996x3_484_3: 1792 ru_index = 3; 1793 break; 1794 case HAL_EHT_RU_996_484_4: 1795 case HAL_EHT_RU_996x2_484_4: 1796 case HAL_EHT_RU_996x3_484_4: 1797 ru_index = 4; 1798 break; 1799 case HAL_EHT_RU_996_484_5: 1800 case HAL_EHT_RU_996x2_484_5: 1801 case HAL_EHT_RU_996x3_484_5: 1802 ru_index = 5; 1803 break; 1804 case HAL_EHT_RU_996_484_6: 1805 case HAL_EHT_RU_996x2_484_6: 1806 case HAL_EHT_RU_996x3_484_6: 1807 ru_index = 6; 1808 break; 1809 case HAL_EHT_RU_996_484_7: 1810 case HAL_EHT_RU_996x2_484_7: 1811 case HAL_EHT_RU_996x3_484_7: 1812 ru_index = 7; 1813 break; 1814 case HAL_EHT_RU_996x2_484_8: 1815 ru_index = 8; 1816 break; 1817 case HAL_EHT_RU_996x2_484_9: 1818 ru_index = 9; 1819 break; 1820 case HAL_EHT_RU_996x2_484_10: 1821 ru_index = 10; 1822 break; 1823 case HAL_EHT_RU_996x2_484_11: 1824 ru_index = 11; 1825 break; 1826 default: 1827 ru_index = HAL_EHT_RU_INVALID; 1828 dp_debug("Invalid RU index"); 1829 qdf_assert(0); 1830 break; 1831 } 1832 ru_size += 4; 1833 } 1834 1835 rtap_ru_size = hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(hal_soc, 1836 ru_size); 1837 if (rtap_ru_size != IEEE80211_EHT_RU_INVALID) { 1838 ppdu_info->rx_status.eht_known |= 1839 QDF_MON_STATUS_EHT_RU_MRU_SIZE_KNOWN; 1840 ppdu_info->rx_status.eht_data[1] |= (rtap_ru_size << 1841 QDF_MON_STATUS_EHT_RU_MRU_SIZE_SHIFT); 1842 } 1843 1844 if (ru_index != HAL_EHT_RU_INVALID) { 1845 ppdu_info->rx_status.eht_known |= 1846 QDF_MON_STATUS_EHT_RU_MRU_INDEX_KNOWN; 1847 ppdu_info->rx_status.eht_data[1] |= (ru_index << 1848 QDF_MON_STATUS_EHT_RU_MRU_INDEX_SHIFT); 1849 } 1850 1851 if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID && 1852 rtap_ru_size != IEEE80211_EHT_RU_INVALID) { 1853 mon_rx_user_status->ofdma_ru_start_index = ru_index; 1854 mon_rx_user_status->ofdma_ru_size = rtap_ru_size; 1855 hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size, &ru_width); 1856 mon_rx_user_status->ofdma_ru_width = ru_width; 1857 mon_rx_user_status->mu_ul_info_valid = 1; 1858 } 1859 1860 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1861 } 1862 1863 #ifdef QCA_MONITOR_2_0_SUPPORT 1864 static inline void 1865 hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info, 1866 void *rx_tlv) 1867 { 1868 ppdu_info->rx_status.mpdu_retry_cnt = 1869 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 1870 RETRIED_MPDU_COUNT); 1871 } 1872 1873 static inline void 1874 hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv, 1875 struct hal_rx_ppdu_info *ppdu_info) 1876 { 1877 struct mon_buffer_addr *addr = (struct mon_buffer_addr *)rx_tlv; 1878 1879 ppdu_info->packet_info.sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) | 1880 (addr->buffer_virt_addr_31_0)); 1881 /* HW DMA length is '-1' of actual DMA length*/ 1882 ppdu_info->packet_info.dma_length = addr->dma_length + 1; 1883 ppdu_info->packet_info.msdu_continuation = addr->msdu_continuation; 1884 ppdu_info->packet_info.truncated = addr->truncated; 1885 1886 } 1887 1888 static inline void 1889 hal_rx_update_ppdu_drop_cnt(uint8_t *rx_tlv, 1890 struct hal_rx_ppdu_info *ppdu_info) 1891 { 1892 struct mon_drop *drop_cnt = (struct mon_drop *)rx_tlv; 1893 1894 ppdu_info->drop_cnt.ppdu_drop_cnt = drop_cnt->ppdu_drop_cnt; 1895 ppdu_info->drop_cnt.mpdu_drop_cnt = drop_cnt->mpdu_drop_cnt; 1896 ppdu_info->drop_cnt.end_of_ppdu_drop_cnt = drop_cnt->end_of_ppdu_seen; 1897 ppdu_info->drop_cnt.tlv_drop_cnt = drop_cnt->tlv_drop_cnt; 1898 } 1899 #else 1900 static inline void 1901 hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info, 1902 void *rx_tlv) 1903 { 1904 ppdu_info->rx_status.mpdu_retry_cnt = 0; 1905 } 1906 static inline void 1907 hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv, 1908 struct hal_rx_ppdu_info *ppdu_info) 1909 { 1910 } 1911 1912 static inline void 1913 hal_rx_update_ppdu_drop_cnt(uint8_t *rx_tlv, 1914 struct hal_rx_ppdu_info *ppdu_info) 1915 { 1916 } 1917 #endif 1918 1919 #ifdef WLAN_SUPPORT_CTRL_FRAME_STATS 1920 static inline void 1921 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, 1922 uint32_t user_id) 1923 { 1924 uint16_t fc = ppdu_info->nac_info.frame_control; 1925 1926 if (HAL_RX_GET_FRAME_CTRL_TYPE(fc) == HAL_RX_FRAME_CTRL_TYPE_CTRL) { 1927 if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) == 1928 QDF_IEEE80211_FC0_SUBTYPE_VHT_NDP_AN) 1929 ppdu_info->ctrl_frm_info[user_id].ndpa = 1; 1930 if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) == 1931 QDF_IEEE80211_FC0_SUBTYPE_BAR) 1932 ppdu_info->ctrl_frm_info[user_id].bar = 1; 1933 } 1934 } 1935 #else 1936 static inline void 1937 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, 1938 uint32_t user_id) 1939 { 1940 } 1941 #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */ 1942 1943 /** 1944 * hal_rx_status_get_tlv_info() - process receive info TLV 1945 * @rx_tlv_hdr: pointer to TLV header 1946 * @ppdu_info: pointer to ppdu_info 1947 * 1948 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 1949 */ 1950 static inline uint32_t 1951 hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo, 1952 hal_soc_handle_t hal_soc_hdl, 1953 qdf_nbuf_t nbuf) 1954 { 1955 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1956 uint32_t tlv_tag, user_id, tlv_len, value; 1957 uint8_t group_id = 0; 1958 uint8_t he_dcm = 0; 1959 uint8_t he_stbc = 0; 1960 uint16_t he_gi = 0; 1961 uint16_t he_ltf = 0; 1962 void *rx_tlv; 1963 struct mon_rx_user_status *mon_rx_user_status; 1964 struct hal_rx_ppdu_info *ppdu_info = 1965 (struct hal_rx_ppdu_info *)ppduinfo; 1966 1967 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 1968 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 1969 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 1970 1971 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 1972 1973 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1974 rx_tlv, tlv_len); 1975 1976 ppdu_info->user_id = user_id; 1977 switch (tlv_tag) { 1978 case WIFIRX_PPDU_START_E: 1979 { 1980 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 1981 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, PHY_PPDU_ID))) 1982 hal_err("Matching ppdu_id(%u) detected", 1983 ppdu_info->com_info.last_ppdu_id); 1984 1985 /* Reset ppdu_info before processing the ppdu */ 1986 qdf_mem_zero(ppdu_info, 1987 sizeof(struct hal_rx_ppdu_info)); 1988 1989 ppdu_info->com_info.last_ppdu_id = 1990 ppdu_info->com_info.ppdu_id = 1991 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 1992 PHY_PPDU_ID); 1993 1994 /* channel number is set in PHY meta data */ 1995 ppdu_info->rx_status.chan_num = 1996 (HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 1997 SW_PHY_META_DATA) & 0x0000FFFF); 1998 ppdu_info->rx_status.chan_freq = 1999 (HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2000 SW_PHY_META_DATA) & 0xFFFF0000) >> 16; 2001 if (ppdu_info->rx_status.chan_num && 2002 ppdu_info->rx_status.chan_freq) { 2003 ppdu_info->rx_status.chan_freq = 2004 hal_rx_radiotap_num_to_freq( 2005 ppdu_info->rx_status.chan_num, 2006 ppdu_info->rx_status.chan_freq); 2007 } 2008 2009 ppdu_info->com_info.ppdu_timestamp = 2010 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2011 PPDU_START_TIMESTAMP_31_0); 2012 ppdu_info->rx_status.ppdu_timestamp = 2013 ppdu_info->com_info.ppdu_timestamp; 2014 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 2015 2016 break; 2017 } 2018 2019 case WIFIRX_PPDU_START_USER_INFO_E: 2020 hal_rx_parse_receive_user_info(hal, rx_tlv, ppdu_info, user_id); 2021 break; 2022 2023 case WIFIRX_PPDU_END_E: 2024 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2025 "[%s][%d] ppdu_end_e len=%d", 2026 __func__, __LINE__, tlv_len); 2027 /* This is followed by sub-TLVs of PPDU_END */ 2028 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 2029 break; 2030 2031 case WIFIPHYRX_LOCATION_E: 2032 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 2033 break; 2034 2035 case WIFIRXPCU_PPDU_END_INFO_E: 2036 ppdu_info->rx_status.rx_antenna = 2037 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, RX_ANTENNA); 2038 ppdu_info->rx_status.tsft = 2039 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, 2040 WB_TIMESTAMP_UPPER_32); 2041 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 2042 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, 2043 WB_TIMESTAMP_LOWER_32); 2044 ppdu_info->rx_status.duration = 2045 HAL_RX_GET_64(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 2046 RX_PPDU_DURATION); 2047 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 2048 break; 2049 2050 /* 2051 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 2052 * for MU, based on num users we see this tlv that many times. 2053 */ 2054 case WIFIRX_PPDU_END_USER_STATS_E: 2055 { 2056 unsigned long tid = 0; 2057 uint16_t seq = 0; 2058 2059 ppdu_info->rx_status.ast_index = 2060 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2061 AST_INDEX); 2062 2063 tid = HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2064 RECEIVED_QOS_DATA_TID_BITMAP); 2065 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, 2066 sizeof(tid) * 8); 2067 2068 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 2069 ppdu_info->rx_status.tid = HAL_TID_INVALID; 2070 2071 ppdu_info->rx_status.tcp_msdu_count = 2072 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2073 TCP_MSDU_COUNT) + 2074 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2075 TCP_ACK_MSDU_COUNT); 2076 ppdu_info->rx_status.udp_msdu_count = 2077 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2078 UDP_MSDU_COUNT); 2079 ppdu_info->rx_status.other_msdu_count = 2080 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2081 OTHER_MSDU_COUNT); 2082 hal_rx_status_get_mpdu_retry_cnt(ppdu_info, rx_tlv); 2083 2084 if (ppdu_info->sw_frame_group_id 2085 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 2086 ppdu_info->rx_status.frame_control_info_valid = 2087 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2088 FRAME_CONTROL_INFO_VALID); 2089 2090 if (ppdu_info->rx_status.frame_control_info_valid) 2091 ppdu_info->rx_status.frame_control = 2092 HAL_RX_GET_64(rx_tlv, 2093 RX_PPDU_END_USER_STATS, 2094 FRAME_CONTROL_FIELD); 2095 2096 hal_get_qos_control(rx_tlv, ppdu_info); 2097 } 2098 2099 ppdu_info->rx_status.data_sequence_control_info_valid = 2100 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2101 DATA_SEQUENCE_CONTROL_INFO_VALID); 2102 2103 seq = HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2104 FIRST_DATA_SEQ_CTRL); 2105 if (ppdu_info->rx_status.data_sequence_control_info_valid) 2106 ppdu_info->rx_status.first_data_seq_ctrl = seq; 2107 2108 ppdu_info->rx_status.preamble_type = 2109 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2110 HT_CONTROL_FIELD_PKT_TYPE); 2111 2112 ppdu_info->end_user_stats_cnt++; 2113 2114 switch (ppdu_info->rx_status.preamble_type) { 2115 case HAL_RX_PKT_TYPE_11N: 2116 ppdu_info->rx_status.ht_flags = 1; 2117 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 2118 break; 2119 case HAL_RX_PKT_TYPE_11AC: 2120 ppdu_info->rx_status.vht_flags = 1; 2121 break; 2122 case HAL_RX_PKT_TYPE_11AX: 2123 ppdu_info->rx_status.he_flags = 1; 2124 break; 2125 default: 2126 break; 2127 } 2128 2129 ppdu_info->com_info.mpdu_cnt_fcs_ok = 2130 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2131 MPDU_CNT_FCS_OK); 2132 ppdu_info->com_info.mpdu_cnt_fcs_err = 2133 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2134 MPDU_CNT_FCS_ERR); 2135 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 2136 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 2137 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 2138 else 2139 ppdu_info->rx_status.rs_flags &= 2140 (~IEEE80211_AMPDU_FLAG); 2141 2142 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 2143 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2144 FCS_OK_BITMAP_31_0); 2145 2146 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 2147 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS, 2148 FCS_OK_BITMAP_63_32); 2149 2150 if (user_id < HAL_MAX_UL_MU_USERS) { 2151 mon_rx_user_status = 2152 &ppdu_info->rx_user_status[user_id]; 2153 2154 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 2155 2156 ppdu_info->com_info.num_users++; 2157 2158 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 2159 user_id, 2160 mon_rx_user_status); 2161 } 2162 break; 2163 } 2164 2165 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 2166 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 2167 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2168 FCS_OK_BITMAP_95_64); 2169 2170 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 2171 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2172 FCS_OK_BITMAP_127_96); 2173 2174 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 2175 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2176 FCS_OK_BITMAP_159_128); 2177 2178 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 2179 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2180 FCS_OK_BITMAP_191_160); 2181 2182 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 2183 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2184 FCS_OK_BITMAP_223_192); 2185 2186 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 2187 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2188 FCS_OK_BITMAP_255_224); 2189 break; 2190 2191 case WIFIRX_PPDU_END_STATUS_DONE_E: 2192 return HAL_TLV_STATUS_PPDU_DONE; 2193 2194 case WIFIPHYRX_PKT_END_E: 2195 break; 2196 2197 case WIFIDUMMY_E: 2198 return HAL_TLV_STATUS_BUF_DONE; 2199 2200 case WIFIPHYRX_HT_SIG_E: 2201 { 2202 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 2203 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 2204 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 2205 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO, FEC_CODING); 2206 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2207 1 : 0; 2208 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 2209 HT_SIG_INFO, MCS); 2210 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 2211 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 2212 HT_SIG_INFO, CBW); 2213 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 2214 HT_SIG_INFO, SHORT_GI); 2215 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2216 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 2217 HT_SIG_SU_NSS_SHIFT) + 1; 2218 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 2219 break; 2220 } 2221 2222 case WIFIPHYRX_L_SIG_B_E: 2223 { 2224 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 2225 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 2226 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 2227 2228 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO, RATE); 2229 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 2230 switch (value) { 2231 case 1: 2232 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 2233 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 2234 break; 2235 case 2: 2236 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 2237 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 2238 break; 2239 case 3: 2240 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 2241 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 2242 break; 2243 case 4: 2244 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 2245 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 2246 break; 2247 case 5: 2248 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 2249 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 2250 break; 2251 case 6: 2252 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 2253 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 2254 break; 2255 case 7: 2256 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 2257 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 2258 break; 2259 default: 2260 break; 2261 } 2262 ppdu_info->rx_status.cck_flag = 1; 2263 break; 2264 } 2265 2266 case WIFIPHYRX_L_SIG_A_E: 2267 { 2268 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 2269 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 2270 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 2271 2272 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO, RATE); 2273 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 2274 switch (value) { 2275 case 8: 2276 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 2277 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 2278 break; 2279 case 9: 2280 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 2281 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 2282 break; 2283 case 10: 2284 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 2285 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 2286 break; 2287 case 11: 2288 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 2289 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 2290 break; 2291 case 12: 2292 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 2293 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 2294 break; 2295 case 13: 2296 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 2297 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 2298 break; 2299 case 14: 2300 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 2301 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 2302 break; 2303 case 15: 2304 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 2305 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 2306 break; 2307 default: 2308 break; 2309 } 2310 ppdu_info->rx_status.ofdm_flag = 1; 2311 break; 2312 } 2313 2314 case WIFIPHYRX_VHT_SIG_A_E: 2315 { 2316 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 2317 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 2318 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 2319 2320 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, 2321 SU_MU_CODING); 2322 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2323 1 : 0; 2324 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, GROUP_ID); 2325 ppdu_info->rx_status.vht_flag_values5 = group_id; 2326 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 2327 VHT_SIG_A_INFO, MCS); 2328 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 2329 VHT_SIG_A_INFO, 2330 GI_SETTING); 2331 2332 switch (hal->target_type) { 2333 case TARGET_TYPE_QCA8074: 2334 case TARGET_TYPE_QCA8074V2: 2335 case TARGET_TYPE_QCA6018: 2336 case TARGET_TYPE_QCA5018: 2337 case TARGET_TYPE_QCN9000: 2338 case TARGET_TYPE_QCN6122: 2339 #ifdef QCA_WIFI_QCA6390 2340 case TARGET_TYPE_QCA6390: 2341 #endif 2342 ppdu_info->rx_status.is_stbc = 2343 HAL_RX_GET(vht_sig_a_info, 2344 VHT_SIG_A_INFO, STBC); 2345 value = HAL_RX_GET(vht_sig_a_info, 2346 VHT_SIG_A_INFO, N_STS); 2347 value = value & VHT_SIG_SU_NSS_MASK; 2348 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2349 value = ((value + 1) >> 1) - 1; 2350 ppdu_info->rx_status.nss = 2351 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2352 2353 break; 2354 case TARGET_TYPE_QCA6290: 2355 #if !defined(QCA_WIFI_QCA6290_11AX) 2356 ppdu_info->rx_status.is_stbc = 2357 HAL_RX_GET(vht_sig_a_info, 2358 VHT_SIG_A_INFO, STBC); 2359 value = HAL_RX_GET(vht_sig_a_info, 2360 VHT_SIG_A_INFO, N_STS); 2361 value = value & VHT_SIG_SU_NSS_MASK; 2362 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2363 value = ((value + 1) >> 1) - 1; 2364 ppdu_info->rx_status.nss = 2365 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2366 #else 2367 ppdu_info->rx_status.nss = 0; 2368 #endif 2369 break; 2370 case TARGET_TYPE_KIWI: 2371 case TARGET_TYPE_MANGO: 2372 ppdu_info->rx_status.is_stbc = 2373 HAL_RX_GET(vht_sig_a_info, 2374 VHT_SIG_A_INFO, STBC); 2375 value = HAL_RX_GET(vht_sig_a_info, 2376 VHT_SIG_A_INFO, N_STS); 2377 value = value & VHT_SIG_SU_NSS_MASK; 2378 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2379 value = ((value + 1) >> 1) - 1; 2380 ppdu_info->rx_status.nss = 2381 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2382 2383 break; 2384 case TARGET_TYPE_QCA6490: 2385 case TARGET_TYPE_QCA6750: 2386 ppdu_info->rx_status.nss = 0; 2387 break; 2388 default: 2389 break; 2390 } 2391 ppdu_info->rx_status.vht_flag_values3[0] = 2392 (((ppdu_info->rx_status.mcs) << 4) 2393 | ppdu_info->rx_status.nss); 2394 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 2395 VHT_SIG_A_INFO, BANDWIDTH); 2396 ppdu_info->rx_status.vht_flag_values2 = 2397 ppdu_info->rx_status.bw; 2398 ppdu_info->rx_status.vht_flag_values4 = 2399 HAL_RX_GET(vht_sig_a_info, 2400 VHT_SIG_A_INFO, SU_MU_CODING); 2401 2402 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 2403 VHT_SIG_A_INFO, 2404 BEAMFORMED); 2405 if (group_id == 0 || group_id == 63) 2406 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2407 else 2408 ppdu_info->rx_status.reception_type = 2409 HAL_RX_TYPE_MU_MIMO; 2410 2411 break; 2412 } 2413 case WIFIPHYRX_HE_SIG_A_SU_E: 2414 { 2415 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 2416 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 2417 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 2418 ppdu_info->rx_status.he_flags = 1; 2419 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2420 FORMAT_INDICATION); 2421 if (value == 0) { 2422 ppdu_info->rx_status.he_data1 = 2423 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 2424 } else { 2425 ppdu_info->rx_status.he_data1 = 2426 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 2427 } 2428 2429 /* data1 */ 2430 ppdu_info->rx_status.he_data1 |= 2431 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 2432 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 2433 QDF_MON_STATUS_HE_DL_UL_KNOWN | 2434 QDF_MON_STATUS_HE_MCS_KNOWN | 2435 QDF_MON_STATUS_HE_DCM_KNOWN | 2436 QDF_MON_STATUS_HE_CODING_KNOWN | 2437 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 2438 QDF_MON_STATUS_HE_STBC_KNOWN | 2439 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 2440 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 2441 2442 /* data2 */ 2443 ppdu_info->rx_status.he_data2 = 2444 QDF_MON_STATUS_HE_GI_KNOWN; 2445 ppdu_info->rx_status.he_data2 |= 2446 QDF_MON_STATUS_TXBF_KNOWN | 2447 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 2448 QDF_MON_STATUS_TXOP_KNOWN | 2449 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 2450 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 2451 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 2452 2453 /* data3 */ 2454 value = HAL_RX_GET(he_sig_a_su_info, 2455 HE_SIG_A_SU_INFO, BSS_COLOR_ID); 2456 ppdu_info->rx_status.he_data3 = value; 2457 value = HAL_RX_GET(he_sig_a_su_info, 2458 HE_SIG_A_SU_INFO, BEAM_CHANGE); 2459 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 2460 ppdu_info->rx_status.he_data3 |= value; 2461 value = HAL_RX_GET(he_sig_a_su_info, 2462 HE_SIG_A_SU_INFO, DL_UL_FLAG); 2463 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 2464 ppdu_info->rx_status.he_data3 |= value; 2465 2466 value = HAL_RX_GET(he_sig_a_su_info, 2467 HE_SIG_A_SU_INFO, TRANSMIT_MCS); 2468 ppdu_info->rx_status.mcs = value; 2469 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2470 ppdu_info->rx_status.he_data3 |= value; 2471 2472 value = HAL_RX_GET(he_sig_a_su_info, 2473 HE_SIG_A_SU_INFO, DCM); 2474 he_dcm = value; 2475 value = value << QDF_MON_STATUS_DCM_SHIFT; 2476 ppdu_info->rx_status.he_data3 |= value; 2477 value = HAL_RX_GET(he_sig_a_su_info, 2478 HE_SIG_A_SU_INFO, CODING); 2479 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2480 1 : 0; 2481 value = value << QDF_MON_STATUS_CODING_SHIFT; 2482 ppdu_info->rx_status.he_data3 |= value; 2483 value = HAL_RX_GET(he_sig_a_su_info, 2484 HE_SIG_A_SU_INFO, 2485 LDPC_EXTRA_SYMBOL); 2486 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 2487 ppdu_info->rx_status.he_data3 |= value; 2488 value = HAL_RX_GET(he_sig_a_su_info, 2489 HE_SIG_A_SU_INFO, STBC); 2490 he_stbc = value; 2491 value = value << QDF_MON_STATUS_STBC_SHIFT; 2492 ppdu_info->rx_status.he_data3 |= value; 2493 2494 /* data4 */ 2495 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2496 SPATIAL_REUSE); 2497 ppdu_info->rx_status.he_data4 = value; 2498 2499 /* data5 */ 2500 value = HAL_RX_GET(he_sig_a_su_info, 2501 HE_SIG_A_SU_INFO, TRANSMIT_BW); 2502 ppdu_info->rx_status.he_data5 = value; 2503 ppdu_info->rx_status.bw = value; 2504 value = HAL_RX_GET(he_sig_a_su_info, 2505 HE_SIG_A_SU_INFO, CP_LTF_SIZE); 2506 switch (value) { 2507 case 0: 2508 he_gi = HE_GI_0_8; 2509 he_ltf = HE_LTF_1_X; 2510 break; 2511 case 1: 2512 he_gi = HE_GI_0_8; 2513 he_ltf = HE_LTF_2_X; 2514 break; 2515 case 2: 2516 he_gi = HE_GI_1_6; 2517 he_ltf = HE_LTF_2_X; 2518 break; 2519 case 3: 2520 if (he_dcm && he_stbc) { 2521 he_gi = HE_GI_0_8; 2522 he_ltf = HE_LTF_4_X; 2523 } else { 2524 he_gi = HE_GI_3_2; 2525 he_ltf = HE_LTF_4_X; 2526 } 2527 break; 2528 } 2529 ppdu_info->rx_status.sgi = he_gi; 2530 ppdu_info->rx_status.ltf_size = he_ltf; 2531 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 2532 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 2533 ppdu_info->rx_status.he_data5 |= value; 2534 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 2535 ppdu_info->rx_status.he_data5 |= value; 2536 2537 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 2538 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 2539 ppdu_info->rx_status.he_data5 |= value; 2540 2541 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2542 PACKET_EXTENSION_A_FACTOR); 2543 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 2544 ppdu_info->rx_status.he_data5 |= value; 2545 2546 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, TXBF); 2547 value = value << QDF_MON_STATUS_TXBF_SHIFT; 2548 ppdu_info->rx_status.he_data5 |= value; 2549 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2550 PACKET_EXTENSION_PE_DISAMBIGUITY); 2551 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 2552 ppdu_info->rx_status.he_data5 |= value; 2553 2554 /* data6 */ 2555 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 2556 value++; 2557 ppdu_info->rx_status.nss = value; 2558 ppdu_info->rx_status.he_data6 = value; 2559 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2560 DOPPLER_INDICATION); 2561 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 2562 ppdu_info->rx_status.he_data6 |= value; 2563 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2564 TXOP_DURATION); 2565 value = value << QDF_MON_STATUS_TXOP_SHIFT; 2566 ppdu_info->rx_status.he_data6 |= value; 2567 2568 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 2569 HE_SIG_A_SU_INFO, 2570 TXBF); 2571 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2572 break; 2573 } 2574 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 2575 { 2576 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 2577 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 2578 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 2579 2580 ppdu_info->rx_status.he_mu_flags = 1; 2581 2582 /* HE Flags */ 2583 /*data1*/ 2584 ppdu_info->rx_status.he_data1 = 2585 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 2586 ppdu_info->rx_status.he_data1 |= 2587 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 2588 QDF_MON_STATUS_HE_DL_UL_KNOWN | 2589 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 2590 QDF_MON_STATUS_HE_STBC_KNOWN | 2591 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 2592 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 2593 2594 /* data2 */ 2595 ppdu_info->rx_status.he_data2 = 2596 QDF_MON_STATUS_HE_GI_KNOWN; 2597 ppdu_info->rx_status.he_data2 |= 2598 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 2599 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 2600 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 2601 QDF_MON_STATUS_TXOP_KNOWN | 2602 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 2603 2604 /*data3*/ 2605 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2606 HE_SIG_A_MU_DL_INFO, BSS_COLOR_ID); 2607 ppdu_info->rx_status.he_data3 = value; 2608 2609 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2610 HE_SIG_A_MU_DL_INFO, DL_UL_FLAG); 2611 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 2612 ppdu_info->rx_status.he_data3 |= value; 2613 2614 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2615 HE_SIG_A_MU_DL_INFO, 2616 LDPC_EXTRA_SYMBOL); 2617 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 2618 ppdu_info->rx_status.he_data3 |= value; 2619 2620 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2621 HE_SIG_A_MU_DL_INFO, STBC); 2622 he_stbc = value; 2623 value = value << QDF_MON_STATUS_STBC_SHIFT; 2624 ppdu_info->rx_status.he_data3 |= value; 2625 2626 /*data4*/ 2627 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2628 SPATIAL_REUSE); 2629 ppdu_info->rx_status.he_data4 = value; 2630 2631 /*data5*/ 2632 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2633 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 2634 ppdu_info->rx_status.he_data5 = value; 2635 ppdu_info->rx_status.bw = value; 2636 2637 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2638 HE_SIG_A_MU_DL_INFO, CP_LTF_SIZE); 2639 switch (value) { 2640 case 0: 2641 he_gi = HE_GI_0_8; 2642 he_ltf = HE_LTF_4_X; 2643 break; 2644 case 1: 2645 he_gi = HE_GI_0_8; 2646 he_ltf = HE_LTF_2_X; 2647 break; 2648 case 2: 2649 he_gi = HE_GI_1_6; 2650 he_ltf = HE_LTF_2_X; 2651 break; 2652 case 3: 2653 he_gi = HE_GI_3_2; 2654 he_ltf = HE_LTF_4_X; 2655 break; 2656 } 2657 ppdu_info->rx_status.sgi = he_gi; 2658 ppdu_info->rx_status.ltf_size = he_ltf; 2659 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 2660 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 2661 ppdu_info->rx_status.he_data5 |= value; 2662 2663 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 2664 ppdu_info->rx_status.he_data5 |= value; 2665 2666 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2667 HE_SIG_A_MU_DL_INFO, NUM_LTF_SYMBOLS); 2668 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 2669 ppdu_info->rx_status.he_data5 |= value; 2670 2671 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2672 PACKET_EXTENSION_A_FACTOR); 2673 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 2674 ppdu_info->rx_status.he_data5 |= value; 2675 2676 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2677 PACKET_EXTENSION_PE_DISAMBIGUITY); 2678 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 2679 ppdu_info->rx_status.he_data5 |= value; 2680 2681 /*data6*/ 2682 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2683 DOPPLER_INDICATION); 2684 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 2685 ppdu_info->rx_status.he_data6 |= value; 2686 2687 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 2688 TXOP_DURATION); 2689 value = value << QDF_MON_STATUS_TXOP_SHIFT; 2690 ppdu_info->rx_status.he_data6 |= value; 2691 2692 /* HE-MU Flags */ 2693 /* HE-MU-flags1 */ 2694 ppdu_info->rx_status.he_flags1 = 2695 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 2696 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 2697 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 2698 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 2699 QDF_MON_STATUS_RU_0_KNOWN; 2700 2701 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2702 HE_SIG_A_MU_DL_INFO, MCS_OF_SIG_B); 2703 ppdu_info->rx_status.he_flags1 |= value; 2704 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2705 HE_SIG_A_MU_DL_INFO, DCM_OF_SIG_B); 2706 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 2707 ppdu_info->rx_status.he_flags1 |= value; 2708 2709 /* HE-MU-flags2 */ 2710 ppdu_info->rx_status.he_flags2 = 2711 QDF_MON_STATUS_BW_KNOWN; 2712 2713 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2714 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 2715 ppdu_info->rx_status.he_flags2 |= value; 2716 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2717 HE_SIG_A_MU_DL_INFO, COMP_MODE_SIG_B); 2718 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 2719 ppdu_info->rx_status.he_flags2 |= value; 2720 value = HAL_RX_GET(he_sig_a_mu_dl_info, 2721 HE_SIG_A_MU_DL_INFO, NUM_SIG_B_SYMBOLS); 2722 value = value - 1; 2723 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 2724 ppdu_info->rx_status.he_flags2 |= value; 2725 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 2726 break; 2727 } 2728 case WIFIPHYRX_HE_SIG_B1_MU_E: 2729 { 2730 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 2731 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 2732 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 2733 2734 ppdu_info->rx_status.he_sig_b_common_known |= 2735 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 2736 /* TODO: Check on the availability of other fields in 2737 * sig_b_common 2738 */ 2739 2740 value = HAL_RX_GET(he_sig_b1_mu_info, 2741 HE_SIG_B1_MU_INFO, RU_ALLOCATION); 2742 ppdu_info->rx_status.he_RU[0] = value; 2743 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 2744 break; 2745 } 2746 case WIFIPHYRX_HE_SIG_B2_MU_E: 2747 { 2748 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 2749 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 2750 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 2751 /* 2752 * Not all "HE" fields can be updated from 2753 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 2754 * to populate rest of the "HE" fields for MU scenarios. 2755 */ 2756 2757 /* HE-data1 */ 2758 ppdu_info->rx_status.he_data1 |= 2759 QDF_MON_STATUS_HE_MCS_KNOWN | 2760 QDF_MON_STATUS_HE_CODING_KNOWN; 2761 2762 /* HE-data2 */ 2763 2764 /* HE-data3 */ 2765 value = HAL_RX_GET(he_sig_b2_mu_info, 2766 HE_SIG_B2_MU_INFO, STA_MCS); 2767 ppdu_info->rx_status.mcs = value; 2768 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2769 ppdu_info->rx_status.he_data3 |= value; 2770 2771 value = HAL_RX_GET(he_sig_b2_mu_info, 2772 HE_SIG_B2_MU_INFO, STA_CODING); 2773 value = value << QDF_MON_STATUS_CODING_SHIFT; 2774 ppdu_info->rx_status.he_data3 |= value; 2775 2776 /* HE-data4 */ 2777 value = HAL_RX_GET(he_sig_b2_mu_info, 2778 HE_SIG_B2_MU_INFO, STA_ID); 2779 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 2780 ppdu_info->rx_status.he_data4 |= value; 2781 2782 /* HE-data5 */ 2783 2784 /* HE-data6 */ 2785 value = HAL_RX_GET(he_sig_b2_mu_info, 2786 HE_SIG_B2_MU_INFO, NSTS); 2787 /* value n indicates n+1 spatial streams */ 2788 value++; 2789 ppdu_info->rx_status.nss = value; 2790 ppdu_info->rx_status.he_data6 |= value; 2791 2792 break; 2793 } 2794 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 2795 { 2796 uint8_t *he_sig_b2_ofdma_info = 2797 (uint8_t *)rx_tlv + 2798 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 2799 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 2800 2801 /* 2802 * Not all "HE" fields can be updated from 2803 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 2804 * to populate rest of "HE" fields for MU OFDMA scenarios. 2805 */ 2806 2807 /* HE-data1 */ 2808 ppdu_info->rx_status.he_data1 |= 2809 QDF_MON_STATUS_HE_MCS_KNOWN | 2810 QDF_MON_STATUS_HE_DCM_KNOWN | 2811 QDF_MON_STATUS_HE_CODING_KNOWN; 2812 2813 /* HE-data2 */ 2814 ppdu_info->rx_status.he_data2 |= 2815 QDF_MON_STATUS_TXBF_KNOWN; 2816 2817 /* HE-data3 */ 2818 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2819 HE_SIG_B2_OFDMA_INFO, STA_MCS); 2820 ppdu_info->rx_status.mcs = value; 2821 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2822 ppdu_info->rx_status.he_data3 |= value; 2823 2824 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2825 HE_SIG_B2_OFDMA_INFO, STA_DCM); 2826 he_dcm = value; 2827 value = value << QDF_MON_STATUS_DCM_SHIFT; 2828 ppdu_info->rx_status.he_data3 |= value; 2829 2830 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2831 HE_SIG_B2_OFDMA_INFO, STA_CODING); 2832 value = value << QDF_MON_STATUS_CODING_SHIFT; 2833 ppdu_info->rx_status.he_data3 |= value; 2834 2835 /* HE-data4 */ 2836 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2837 HE_SIG_B2_OFDMA_INFO, STA_ID); 2838 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 2839 ppdu_info->rx_status.he_data4 |= value; 2840 2841 /* HE-data5 */ 2842 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2843 HE_SIG_B2_OFDMA_INFO, TXBF); 2844 value = value << QDF_MON_STATUS_TXBF_SHIFT; 2845 ppdu_info->rx_status.he_data5 |= value; 2846 2847 /* HE-data6 */ 2848 value = HAL_RX_GET(he_sig_b2_ofdma_info, 2849 HE_SIG_B2_OFDMA_INFO, NSTS); 2850 /* value n indicates n+1 spatial streams */ 2851 value++; 2852 ppdu_info->rx_status.nss = value; 2853 ppdu_info->rx_status.he_data6 |= value; 2854 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 2855 break; 2856 } 2857 case WIFIPHYRX_RSSI_LEGACY_E: 2858 { 2859 uint8_t reception_type; 2860 int8_t rssi_value; 2861 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 2862 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 2863 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 2864 2865 ppdu_info->rx_status.rssi_comb = 2866 HAL_RX_GET_64(rx_tlv, 2867 PHYRX_RSSI_LEGACY, RSSI_COMB); 2868 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 2869 ppdu_info->rx_status.he_re = 0; 2870 2871 reception_type = HAL_RX_GET_64(rx_tlv, 2872 PHYRX_RSSI_LEGACY, 2873 RECEPTION_TYPE); 2874 switch (reception_type) { 2875 case QDF_RECEPTION_TYPE_ULOFMDA: 2876 ppdu_info->rx_status.ulofdma_flag = 1; 2877 ppdu_info->rx_status.he_data1 = 2878 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 2879 break; 2880 case QDF_RECEPTION_TYPE_ULMIMO: 2881 ppdu_info->rx_status.he_data1 = 2882 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 2883 break; 2884 default: 2885 break; 2886 } 2887 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 2888 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2889 RECEIVE_RSSI_INFO, 2890 RSSI_PRI20_CHAIN0); 2891 ppdu_info->rx_status.rssi[0] = rssi_value; 2892 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2893 "RSSI_PRI20_CHAIN0: %d\n", rssi_value); 2894 2895 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2896 RECEIVE_RSSI_INFO, 2897 RSSI_PRI20_CHAIN1); 2898 ppdu_info->rx_status.rssi[1] = rssi_value; 2899 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2900 "RSSI_PRI20_CHAIN1: %d\n", rssi_value); 2901 2902 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2903 RECEIVE_RSSI_INFO, 2904 RSSI_PRI20_CHAIN2); 2905 ppdu_info->rx_status.rssi[2] = rssi_value; 2906 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2907 "RSSI_PRI20_CHAIN2: %d\n", rssi_value); 2908 2909 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2910 RECEIVE_RSSI_INFO, 2911 RSSI_PRI20_CHAIN3); 2912 ppdu_info->rx_status.rssi[3] = rssi_value; 2913 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2914 "RSSI_PRI20_CHAIN3: %d\n", rssi_value); 2915 2916 #ifdef DP_BE_NOTYET_WAR 2917 // TODO - this is not preset for kiwi 2918 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2919 RECEIVE_RSSI_INFO, 2920 RSSI_PRI20_CHAIN4); 2921 ppdu_info->rx_status.rssi[4] = rssi_value; 2922 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2923 "RSSI_PRI20_CHAIN4: %d\n", rssi_value); 2924 2925 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2926 RECEIVE_RSSI_INFO, 2927 RSSI_PRI20_CHAIN5); 2928 ppdu_info->rx_status.rssi[5] = rssi_value; 2929 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2930 "RSSI_PRI20_CHAIN5: %d\n", rssi_value); 2931 2932 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2933 RECEIVE_RSSI_INFO, 2934 RSSI_PRI20_CHAIN6); 2935 ppdu_info->rx_status.rssi[6] = rssi_value; 2936 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2937 "RSSI_PRI20_CHAIN6: %d\n", rssi_value); 2938 2939 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 2940 RECEIVE_RSSI_INFO, 2941 RSSI_PRI20_CHAIN7); 2942 ppdu_info->rx_status.rssi[7] = rssi_value; 2943 #endif 2944 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2945 "RSSI_PRI20_CHAIN7: %d\n", rssi_value); 2946 break; 2947 } 2948 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 2949 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 2950 ppdu_info); 2951 break; 2952 case WIFIPHYRX_GENERIC_U_SIG_E: 2953 hal_rx_parse_u_sig_hdr(hal, rx_tlv, ppdu_info); 2954 break; 2955 case WIFIPHYRX_COMMON_USER_INFO_E: 2956 hal_rx_parse_cmn_usr_info(hal, rx_tlv, ppdu_info); 2957 break; 2958 case WIFIRX_HEADER_E: 2959 { 2960 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 2961 2962 if (ppdu_info->fcs_ok_cnt >= 2963 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 2964 hal_err("Number of MPDUs(%d) per status buff exceeded", 2965 ppdu_info->fcs_ok_cnt); 2966 break; 2967 } 2968 2969 /* Update first_msdu_payload for every mpdu and increment 2970 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 2971 */ 2972 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 2973 rx_tlv; 2974 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 2975 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 2976 ppdu_info->msdu_info.payload_len = tlv_len; 2977 ppdu_info->user_id = user_id; 2978 ppdu_info->hdr_len = tlv_len; 2979 ppdu_info->data = rx_tlv; 2980 ppdu_info->data += 4; 2981 2982 /* for every RX_HEADER TLV increment mpdu_cnt */ 2983 com_info->mpdu_cnt++; 2984 return HAL_TLV_STATUS_HEADER; 2985 } 2986 case WIFIRX_MPDU_START_E: 2987 { 2988 hal_rx_mon_mpdu_start_t *rx_mpdu_start = rx_tlv; 2989 uint32_t ppdu_id = rx_mpdu_start->rx_mpdu_info_details.phy_ppdu_id; 2990 uint8_t filter_category = 0; 2991 2992 ppdu_info->nac_info.fc_valid = 2993 rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid; 2994 2995 ppdu_info->nac_info.to_ds_flag = 2996 rx_mpdu_start->rx_mpdu_info_details.to_ds; 2997 2998 ppdu_info->nac_info.frame_control = 2999 rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field; 3000 3001 ppdu_info->sw_frame_group_id = 3002 rx_mpdu_start->rx_mpdu_info_details.sw_frame_group_id; 3003 3004 ppdu_info->rx_user_status[user_id].sw_peer_id = 3005 rx_mpdu_start->rx_mpdu_info_details.sw_peer_id; 3006 3007 hal_update_rx_ctrl_frame_stats(ppdu_info, user_id); 3008 3009 if (ppdu_info->sw_frame_group_id == 3010 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 3011 ppdu_info->rx_status.frame_control_info_valid = 3012 ppdu_info->nac_info.fc_valid; 3013 ppdu_info->rx_status.frame_control = 3014 ppdu_info->nac_info.frame_control; 3015 } 3016 3017 hal_get_mac_addr1(rx_mpdu_start, 3018 ppdu_info); 3019 3020 ppdu_info->nac_info.mac_addr2_valid = 3021 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_valid; 3022 3023 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 3024 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_15_0; 3025 3026 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 3027 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_47_16; 3028 3029 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 3030 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 3031 ppdu_info->rx_status.ppdu_len = 3032 rx_mpdu_start->rx_mpdu_info_details.mpdu_length; 3033 } else { 3034 ppdu_info->rx_status.ppdu_len += 3035 rx_mpdu_start->rx_mpdu_info_details.mpdu_length; 3036 } 3037 3038 filter_category = 3039 rx_mpdu_start->rx_mpdu_info_details.rxpcu_mpdu_filter_in_category; 3040 3041 if (filter_category == 0) 3042 ppdu_info->rx_status.rxpcu_filter_pass = 1; 3043 else if (filter_category == 1) 3044 ppdu_info->rx_status.monitor_direct_used = 1; 3045 3046 ppdu_info->rx_user_status[user_id].filter_category = filter_category; 3047 3048 ppdu_info->nac_info.mcast_bcast = 3049 rx_mpdu_start->rx_mpdu_info_details.mcast_bcast; 3050 ppdu_info->mpdu_info[user_id].decap_type = 3051 rx_mpdu_start->rx_mpdu_info_details.decap_type; 3052 3053 return HAL_TLV_STATUS_MPDU_START; 3054 } 3055 case WIFIRX_MPDU_END_E: 3056 ppdu_info->user_id = user_id; 3057 ppdu_info->fcs_err = 3058 HAL_RX_GET_64(rx_tlv, RX_MPDU_END, 3059 FCS_ERR); 3060 return HAL_TLV_STATUS_MPDU_END; 3061 case WIFIRX_MSDU_END_E: { 3062 hal_rx_mon_msdu_end_t *rx_msdu_end = rx_tlv; 3063 3064 if (user_id < HAL_MAX_UL_MU_USERS) { 3065 ppdu_info->rx_msdu_info[user_id].cce_metadata = 3066 rx_msdu_end->cce_metadata; 3067 ppdu_info->rx_msdu_info[user_id].fse_metadata = 3068 rx_msdu_end->fse_metadata; 3069 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 3070 rx_msdu_end->flow_idx_timeout; 3071 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 3072 rx_msdu_end->flow_idx_invalid; 3073 ppdu_info->rx_msdu_info[user_id].flow_idx = 3074 rx_msdu_end->flow_idx; 3075 ppdu_info->msdu[user_id].first_msdu = 3076 rx_msdu_end->first_msdu; 3077 ppdu_info->msdu[user_id].last_msdu = 3078 rx_msdu_end->last_msdu; 3079 ppdu_info->msdu[user_id].msdu_len = 3080 rx_msdu_end->msdu_length; 3081 ppdu_info->msdu[user_id].user_rssi = 3082 rx_msdu_end->user_rssi; 3083 ppdu_info->msdu[user_id].reception_type = 3084 rx_msdu_end->reception_type; 3085 } 3086 return HAL_TLV_STATUS_MSDU_END; 3087 } 3088 case WIFIMON_BUFFER_ADDR_E: 3089 hal_rx_status_get_mon_buf_addr(rx_tlv, ppdu_info); 3090 3091 return HAL_TLV_STATUS_MON_BUF_ADDR; 3092 case WIFIMON_DROP_E: 3093 hal_rx_update_ppdu_drop_cnt(rx_tlv, ppdu_info); 3094 return HAL_TLV_STATUS_MON_DROP; 3095 case 0: 3096 return HAL_TLV_STATUS_PPDU_DONE; 3097 case WIFIRX_STATUS_BUFFER_DONE_E: 3098 case WIFIPHYRX_DATA_DONE_E: 3099 case WIFIPHYRX_PKT_END_PART1_E: 3100 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3101 3102 default: 3103 hal_debug("unhandled tlv tag %d", tlv_tag); 3104 } 3105 3106 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3107 rx_tlv, tlv_len); 3108 3109 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3110 } 3111 3112 static uint32_t 3113 hal_rx_status_process_aggr_tlv(struct hal_soc *hal_soc, 3114 struct hal_rx_ppdu_info *ppdu_info) 3115 { 3116 uint32_t aggr_tlv_tag = ppdu_info->tlv_aggr.tlv_tag; 3117 3118 switch (aggr_tlv_tag) { 3119 case WIFIPHYRX_GENERIC_EHT_SIG_E: 3120 hal_rx_parse_eht_sig_hdr(hal_soc, ppdu_info->tlv_aggr.buf, 3121 ppdu_info); 3122 break; 3123 default: 3124 /* Aggregated TLV cannot be handled */ 3125 qdf_assert(0); 3126 break; 3127 } 3128 3129 ppdu_info->tlv_aggr.in_progress = 0; 3130 ppdu_info->tlv_aggr.cur_len = 0; 3131 3132 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3133 } 3134 3135 static inline bool 3136 hal_rx_status_tlv_should_aggregate(struct hal_soc *hal_soc, uint32_t tlv_tag) 3137 { 3138 switch (tlv_tag) { 3139 case WIFIPHYRX_GENERIC_EHT_SIG_E: 3140 return true; 3141 } 3142 3143 return false; 3144 } 3145 3146 static inline uint32_t 3147 hal_rx_status_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr, 3148 struct hal_rx_ppdu_info *ppdu_info, 3149 qdf_nbuf_t nbuf) 3150 { 3151 uint32_t tlv_tag, user_id, tlv_len; 3152 void *rx_tlv; 3153 3154 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 3155 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 3156 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 3157 3158 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 3159 3160 if (tlv_len <= HAL_RX_MON_MAX_AGGR_SIZE - ppdu_info->tlv_aggr.cur_len) { 3161 qdf_mem_copy(ppdu_info->tlv_aggr.buf + 3162 ppdu_info->tlv_aggr.cur_len, 3163 rx_tlv, tlv_len); 3164 ppdu_info->tlv_aggr.cur_len += tlv_len; 3165 } else { 3166 dp_err("Length of TLV exceeds max aggregation length"); 3167 qdf_assert(0); 3168 } 3169 3170 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3171 } 3172 3173 static inline uint32_t 3174 hal_rx_status_start_new_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr, 3175 struct hal_rx_ppdu_info *ppdu_info, 3176 qdf_nbuf_t nbuf) 3177 { 3178 uint32_t tlv_tag, user_id, tlv_len; 3179 3180 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 3181 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 3182 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 3183 3184 ppdu_info->tlv_aggr.in_progress = 1; 3185 ppdu_info->tlv_aggr.tlv_tag = tlv_tag; 3186 ppdu_info->tlv_aggr.cur_len = 0; 3187 3188 return hal_rx_status_aggr_tlv(hal_soc, rx_tlv_hdr, ppdu_info, nbuf); 3189 } 3190 3191 static inline uint32_t 3192 hal_rx_status_get_tlv_info_wrapper_be(void *rx_tlv_hdr, void *ppduinfo, 3193 hal_soc_handle_t hal_soc_hdl, 3194 qdf_nbuf_t nbuf) 3195 { 3196 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3197 uint32_t tlv_tag, user_id, tlv_len; 3198 struct hal_rx_ppdu_info *ppdu_info = 3199 (struct hal_rx_ppdu_info *)ppduinfo; 3200 3201 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr); 3202 user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr); 3203 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 3204 3205 /* 3206 * Handle the case where aggregation is in progress 3207 * or the current TLV is one of the TLVs which should be 3208 * aggregated 3209 */ 3210 if (ppdu_info->tlv_aggr.in_progress) { 3211 if (ppdu_info->tlv_aggr.tlv_tag == tlv_tag) { 3212 return hal_rx_status_aggr_tlv(hal, rx_tlv_hdr, 3213 ppdu_info, nbuf); 3214 } else { 3215 /* Finish aggregation of current TLV */ 3216 hal_rx_status_process_aggr_tlv(hal, ppdu_info); 3217 } 3218 } 3219 3220 if (hal_rx_status_tlv_should_aggregate(hal, tlv_tag)) { 3221 return hal_rx_status_start_new_aggr_tlv(hal, rx_tlv_hdr, 3222 ppduinfo, nbuf); 3223 } 3224 3225 return hal_rx_status_get_tlv_info_generic_be(rx_tlv_hdr, ppduinfo, 3226 hal_soc_hdl, nbuf); 3227 } 3228 #endif /* _HAL_BE_API_MON_H_ */ 3229