xref: /wlan-dirver/qca-wifi-host-cmn/hal/wifi3.0/be/hal_be_api.h (revision d0c05845839e5f2ba5a8dcebe0cd3e4cd4e8dfcf)
1 /*
2  * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef _HAL_BE_API_H_
21 #define _HAL_BE_API_H_
22 
23 #include "hal_hw_headers.h"
24 #include "hal_rx.h"
25 
26 #define HAL_RX_MSDU_EXT_DESC_INFO_GET(msdu_details_ptr) \
27 	((struct rx_msdu_ext_desc_info *) \
28 	_OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
29 RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
30 
31 /**
32  * hal_reo_setup_generic_be - Initialize HW REO block
33  *
34  * @hal_soc: Opaque HAL SOC handle
35  * @reo_params: parameters needed by HAL for REO config
36  */
37 void hal_reo_setup_generic_be(struct hal_soc *soc,
38 			      void *reoparams);
39 
40 /**
41  * hal_rx_msdu_ext_desc_info_get_ptr_be() - Get the msdu extension
42  *			descriptor pointer.
43  * @msdu_details_ptr: msdu details
44  *
45  * Return: msdu exntension descriptor pointer.
46  */
47 void *hal_rx_msdu_ext_desc_info_get_ptr_be(void *msdu_details_ptr);
48 
49 /**
50  * hal_set_link_desc_addr_be - Setup link descriptor in a buffer_addr_info
51  * HW structure
52  *
53  * @desc: Descriptor entry (from WBM_IDLE_LINK ring)
54  * @cookie: SW cookie for the buffer/descriptor
55  * @link_desc_paddr: Physical address of link descriptor entry
56  * @bm_id: idle link BM id
57  *
58  */
59 void hal_set_link_desc_addr_be(void *desc, uint32_t cookie,
60 			       qdf_dma_addr_t link_desc_paddr,
61 			       uint8_t bm_id);
62 
63 /**
64  * hal_hw_txrx_default_ops_attach_be(): Add default ops for BE chips
65  * @ hal_soc_hdl: hal_soc handle
66  *
67  * Return: None
68  */
69 void hal_hw_txrx_default_ops_attach_be(struct hal_soc *soc);
70 
71 uint32_t hal_tx_comp_get_buffer_source_generic_be(void *hal_desc);
72 uint8_t hal_rx_ret_buf_manager_get_be(hal_ring_desc_t ring_desc);
73 void hal_rx_wbm_err_info_get_generic_be(void *wbm_desc, void *wbm_er_info1);
74 
75 /**
76  * hal_reo_qdesc_setup - Setup HW REO queue descriptor
77  *
78  * @hal_soc: Opaque HAL SOC handle
79  * @ba_window_size: BlockAck window size
80  * @start_seq: Starting sequence number
81  * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
82  * @hw_qdesc_paddr: Physical address of REO queue descriptor memory
83  * @pn_type: PN type (one of the types defined in 'enum hal_pn_type')
84  * @vdev_stats_id: vdev_stats_id to be programmed in REO Queue Descriptor
85  */
86 void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl,
87 			    int tid, uint32_t ba_window_size,
88 			    uint32_t start_seq, void *hw_qdesc_vaddr,
89 			    qdf_dma_addr_t hw_qdesc_paddr,
90 			    int pn_type, uint8_t vdev_stats_id);
91 
92 /**
93  * hal_cookie_conversion_reg_cfg_be() - set cookie conversion relevant register
94  *					for REO/WBM
95  * @soc: HAL soc handle
96  * @cc_cfg: structure pointer for HW cookie conversion configuration
97  *
98  * Return: None
99  */
100 void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl,
101 				      struct hal_hw_cc_config *cc_cfg);
102 
103 /**
104  * hal_reo_ix_remap_value_get() - Calculate reo remap register value from
105  *				  ring_id_mask which is used for hash based
106  *				  reo distribution
107  *
108  * @hal_soc: Handle to HAL SoC structure
109  * @ring_id_mask: mask value indicating the rx rings 0th bit set indicate
110  * REO2SW1 is included in hash distribution
111  *
112  * Return: REO remap value
113  */
114 uint32_t
115 hal_reo_ix_remap_value_get_be(hal_soc_handle_t hal_soc_hdl,
116 			      uint8_t rx_ring_mask);
117 
118 /**
119  * hal_reo_ring_remap_value_get_be() - return REO remap value
120  *
121  * @ring_id: REO2SW ring id
122  *
123  * Return: REO remap value
124  */
125 uint8_t
126 hal_reo_ring_remap_value_get_be(uint8_t rx_ring_id);
127 
128 /**
129  * hal_setup_reo_swap() - Set the swap flag for big endian machines
130  * @soc: HAL soc handle
131  *
132  * Return: None
133  */
134 void hal_setup_reo_swap(struct hal_soc *soc);
135 
136 /**
137  * hal_get_idle_link_bm_id_be() - Get idle link BM id from chid_id
138  * @chip_id: mlo chip_id
139  *
140  * Returns: RBM ID
141  */
142 uint8_t hal_get_idle_link_bm_id_be(uint8_t chip_id);
143 #endif /* _HAL_BE_API_H_ */
144