1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_BE_API_H_ 21 #define _HAL_BE_API_H_ 22 23 #include "hal_hw_headers.h" 24 #include "hal_rx.h" 25 26 struct hal_hw_cc_config { 27 uint32_t lut_base_addr_31_0; 28 uint32_t cc_global_en:1, 29 page_4k_align:1, 30 cookie_offset_msb:5, 31 cookie_page_msb:5, 32 lut_base_addr_39_32:8, 33 wbm2sw6_cc_en:1, 34 wbm2sw5_cc_en:1, 35 wbm2sw4_cc_en:1, 36 wbm2sw3_cc_en:1, 37 wbm2sw2_cc_en:1, 38 wbm2sw1_cc_en:1, 39 wbm2sw0_cc_en:1, 40 wbm2fw_cc_en:1, 41 error_path_cookie_conv_en:1, 42 release_path_cookie_conv_en:1, 43 reserved:2; 44 }; 45 46 #define HAL_RX_MSDU_EXT_DESC_INFO_GET(msdu_details_ptr) \ 47 ((struct rx_msdu_ext_desc_info *) \ 48 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 49 RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET)) 50 51 /** 52 * hal_reo_setup_generic_be - Initialize HW REO block 53 * 54 * @hal_soc: Opaque HAL SOC handle 55 * @reo_params: parameters needed by HAL for REO config 56 */ 57 void hal_reo_setup_generic_be(struct hal_soc *soc, 58 void *reoparams); 59 60 /** 61 * hal_rx_msdu_ext_desc_info_get_ptr_be() - Get the msdu extension 62 * descriptor pointer. 63 * @msdu_details_ptr: msdu details 64 * 65 * Return: msdu exntension descriptor pointer. 66 */ 67 void *hal_rx_msdu_ext_desc_info_get_ptr_be(void *msdu_details_ptr); 68 69 /** 70 * hal_set_link_desc_addr_be - Setup link descriptor in a buffer_addr_info 71 * HW structure 72 * 73 * @desc: Descriptor entry (from WBM_IDLE_LINK ring) 74 * @cookie: SW cookie for the buffer/descriptor 75 * @link_desc_paddr: Physical address of link descriptor entry 76 * @bm_id: idle link BM id 77 * 78 */ 79 void hal_set_link_desc_addr_be(void *desc, uint32_t cookie, 80 qdf_dma_addr_t link_desc_paddr, 81 uint8_t bm_id); 82 83 /** 84 * hal_hw_txrx_default_ops_attach_be(): Add default ops for BE chips 85 * @ hal_soc_hdl: hal_soc handle 86 * 87 * Return: None 88 */ 89 void hal_hw_txrx_default_ops_attach_be(struct hal_soc *soc); 90 91 uint32_t hal_tx_comp_get_buffer_source_generic_be(void *hal_desc); 92 uint8_t hal_rx_ret_buf_manager_get_be(hal_ring_desc_t ring_desc); 93 void hal_rx_wbm_err_info_get_generic_be(void *wbm_desc, void *wbm_er_info1); 94 95 /** 96 * hal_reo_qdesc_setup - Setup HW REO queue descriptor 97 * 98 * @hal_soc: Opaque HAL SOC handle 99 * @ba_window_size: BlockAck window size 100 * @start_seq: Starting sequence number 101 * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory 102 * @hw_qdesc_paddr: Physical address of REO queue descriptor memory 103 * @pn_type: PN type (one of the types defined in 'enum hal_pn_type') 104 * 105 */ 106 void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl, 107 int tid, uint32_t ba_window_size, 108 uint32_t start_seq, void *hw_qdesc_vaddr, 109 qdf_dma_addr_t hw_qdesc_paddr, 110 int pn_type); 111 112 /** 113 * hal_cookie_conversion_reg_cfg_be() - set cookie conversion relevant register 114 * for REO/WBM 115 * @soc: HAL soc handle 116 * @cc_cfg: structure pointer for HW cookie conversion configuration 117 * 118 * Return: None 119 */ 120 void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl, 121 struct hal_hw_cc_config *cc_cfg); 122 123 /** 124 * hal_reo_ix_remap_value_get() - Calculate reo remap register value from 125 * ring_id_mask which is used for hash based 126 * reo distribution 127 * 128 * @hal_soc: Handle to HAL SoC structure 129 * @ring_id_mask: mask value indicating the rx rings 0th bit set indicate 130 * REO2SW1 is included in hash distribution 131 * 132 * Return: REO remap value 133 */ 134 uint32_t 135 hal_reo_ix_remap_value_get_be(hal_soc_handle_t hal_soc_hdl, 136 uint8_t rx_ring_mask); 137 138 /** 139 * hal_reo_ring_remap_value_get_be() - return REO remap value 140 * 141 * @ring_id: REO2SW ring id 142 * 143 * Return: REO remap value 144 */ 145 uint8_t 146 hal_reo_ring_remap_value_get_be(uint8_t rx_ring_id); 147 148 /** 149 * hal_setup_reo_swap() - Set the swap flag for big endian machines 150 * @soc: HAL soc handle 151 * 152 * Return: None 153 */ 154 void hal_setup_reo_swap(struct hal_soc *soc); 155 #endif /* _HAL_BE_API_H_ */ 156