1 /* 2 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _DP_UMAC_RESET_H_ 18 #define _DP_UMAC_RESET_H_ 19 20 #include <qdf_types.h> 21 struct dp_soc; 22 23 /** 24 * enum umac_reset_action - Actions supported by the UMAC reset 25 * @UMAC_RESET_ACTION_NONE: No action 26 * @UMAC_RESET_ACTION_DO_TRIGGER_RECOVERY: Trigger umac recovery 27 * @UMAC_RESET_ACTION_DO_PRE_RESET: DO_PRE_RESET 28 * @UMAC_RESET_ACTION_DO_POST_RESET_START: DO_POST_RESET_START 29 * @UMAC_RESET_ACTION_DO_POST_RESET_COMPLETE: DO_POST_RESET_COMPLETE 30 * @UMAC_RESET_ACTION_ABORT: Abort the current Umac reset session 31 * @UMAC_RESET_ACTION_MAX: Maximum actions 32 */ 33 enum umac_reset_action { 34 UMAC_RESET_ACTION_NONE, 35 UMAC_RESET_ACTION_DO_TRIGGER_RECOVERY, 36 UMAC_RESET_ACTION_DO_PRE_RESET, 37 UMAC_RESET_ACTION_DO_POST_RESET_START, 38 UMAC_RESET_ACTION_DO_POST_RESET_COMPLETE, 39 UMAC_RESET_ACTION_ABORT, 40 UMAC_RESET_ACTION_MAX 41 }; 42 43 #ifdef DP_UMAC_HW_RESET_SUPPORT 44 45 #define dp_umac_reset_alert(params...) \ 46 QDF_TRACE_FATAL(QDF_MODULE_ID_DP_UMAC_RESET, params) 47 #define dp_umac_reset_err(params...) \ 48 QDF_TRACE_ERROR(QDF_MODULE_ID_DP_UMAC_RESET, params) 49 #define dp_umac_reset_warn(params...) \ 50 QDF_TRACE_WARN(QDF_MODULE_ID_DP_UMAC_RESET, params) 51 #define dp_umac_reset_notice(params...) \ 52 QDF_TRACE_INFO(QDF_MODULE_ID_DP_UMAC_RESET, params) 53 #define dp_umac_reset_info(params...) \ 54 QDF_TRACE_INFO(QDF_MODULE_ID_DP_UMAC_RESET, params) 55 #define dp_umac_reset_debug(params...) \ 56 QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_UMAC_RESET, params) 57 58 #define DP_UMAC_RESET_PRINT_STATS(fmt, args ...)\ 59 QDF_TRACE(QDF_MODULE_ID_DP_UMAC_RESET, QDF_TRACE_LEVEL_FATAL,\ 60 fmt, ## args) 61 62 #define DP_UMAC_RESET_SHMEM_ALIGN 8 63 #define DP_UMAC_RESET_SHMEM_MAGIC_NUM (0xDEADBEEF) 64 65 /** 66 * enum umac_reset_state - States required by the UMAC reset state machine 67 * @UMAC_RESET_STATE_WAIT_FOR_TRIGGER: Waiting for trigger event 68 * @UMAC_RESET_STATE_DO_TRIGGER_RECEIVED: Receivd the DO_TRIGGER event 69 * @UMAC_RESET_STATE_HOST_TRIGGER_DONE: Host completed handling Trigger event 70 * @UMAC_RESET_STATE_WAIT_FOR_DO_PRE_RESET: Waiting for the DO_PRE_RESET event 71 * @UMAC_RESET_STATE_DO_PRE_RESET_RECEIVED: Received the DO_PRE_RESET event 72 * @UMAC_RESET_STATE_HOST_PRE_RESET_DONE: Host has completed handling the 73 * PRE_RESET event 74 * @UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_START: Waiting for the 75 * DO_POST_RESET_START event 76 * @UMAC_RESET_STATE_DO_POST_RESET_START_RECEIVED: Received the 77 * DO_POST_RESET_START event 78 * @UMAC_RESET_STATE_HOST_POST_RESET_START_DONE: Host has completed handling the 79 * POST_RESET_START event 80 * @UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_COMPLETE: Waiting for the 81 * DO_POST_RESET_COMPLETE event 82 * @UMAC_RESET_STATE_DO_POST_RESET_COMPLETE_RECEIVED: Received the 83 * DO_POST_RESET_COMPLETE event 84 * @UMAC_RESET_STATE_HOST_POST_RESET_COMPLETE_DONE: Host has completed handling 85 * the DO_POST_RESET_COMPLETE event 86 */ 87 enum umac_reset_state { 88 UMAC_RESET_STATE_WAIT_FOR_TRIGGER = 0, 89 UMAC_RESET_STATE_DO_TRIGGER_RECEIVED, 90 UMAC_RESET_STATE_HOST_TRIGGER_DONE, 91 92 UMAC_RESET_STATE_WAIT_FOR_DO_PRE_RESET, 93 UMAC_RESET_STATE_DO_PRE_RESET_RECEIVED, 94 UMAC_RESET_STATE_HOST_PRE_RESET_DONE, 95 96 UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_START, 97 UMAC_RESET_STATE_DO_POST_RESET_START_RECEIVED, 98 UMAC_RESET_STATE_HOST_POST_RESET_START_DONE, 99 100 UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_COMPLETE, 101 UMAC_RESET_STATE_DO_POST_RESET_COMPLETE_RECEIVED, 102 UMAC_RESET_STATE_HOST_POST_RESET_COMPLETE_DONE, 103 }; 104 105 /** 106 * enum umac_reset_rx_event - Rx events deduced by the UMAC reset 107 * @UMAC_RESET_RX_EVENT_NONE: No event 108 * @UMAC_RESET_RX_EVENT_DO_TRIGGER_RECOVERY: ACTION_DO_TRIGGER_RECOVERY event 109 * @UMAC_RESET_RX_EVENT_DO_TRIGGER_TR_SYNC: ACTION_DO_TRIGGER_RECOVERY event 110 * @UMAC_RESET_RX_EVENT_DO_PRE_RESET: DO_PRE_RESET event 111 * @UMAC_RESET_RX_EVENT_DO_POST_RESET_START: DO_POST_RESET_START event 112 * @UMAC_RESET_RX_EVENT_DO_POST_RESET_COMPELTE: DO_POST_RESET_COMPELTE event 113 * @UMAC_RESET_RX_EVENT_ERROR: Error while processing the Rx event 114 */ 115 enum umac_reset_rx_event { 116 UMAC_RESET_RX_EVENT_NONE = 0x0, 117 UMAC_RESET_RX_EVENT_DO_TRIGGER_RECOVERY, 118 UMAC_RESET_RX_EVENT_DO_TRIGGER_TR_SYNC, 119 UMAC_RESET_RX_EVENT_DO_PRE_RESET, 120 UMAC_RESET_RX_EVENT_DO_POST_RESET_START, 121 UMAC_RESET_RX_EVENT_DO_POST_RESET_COMPELTE, 122 123 UMAC_RESET_RX_EVENT_ERROR = 0xFFFFFFFF, 124 }; 125 126 /** 127 * enum umac_reset_tx_cmd: UMAC reset Tx command 128 * @UMAC_RESET_TX_CMD_TRIGGER_DONE: TRIGGER_DONE 129 * @UMAC_RESET_TX_CMD_PRE_RESET_DONE: PRE_RESET_DONE 130 * @UMAC_RESET_TX_CMD_POST_RESET_START_DONE: POST_RESET_START_DONE 131 * @UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE: POST_RESET_COMPLETE_DONE 132 */ 133 enum umac_reset_tx_cmd { 134 UMAC_RESET_TX_CMD_TRIGGER_DONE, 135 UMAC_RESET_TX_CMD_PRE_RESET_DONE, 136 UMAC_RESET_TX_CMD_POST_RESET_START_DONE, 137 UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE, 138 }; 139 140 /** 141 * struct umac_reset_rx_actions - callbacks for handling UMAC reset actions 142 * @cb: Array of pointers where each pointer contains callback for each UMAC 143 * reset action for that index 144 */ 145 struct umac_reset_rx_actions { 146 QDF_STATUS (*cb[UMAC_RESET_ACTION_MAX])(struct dp_soc *soc); 147 }; 148 149 /** 150 * struct reset_ts - timestamps of for umac reset events for debug 151 * @trigger_start: Umac reset trigger event timestamp 152 * @trigger_done: Umac reset trigger done timestamp 153 * @pre_reset_start: Umac prereset start event timestamp 154 * @pre_reset_done: Umac prereset done timestamp 155 * @post_reset_start: Umac postreset start event timestamp 156 * @post_reset_done: Umac postreset done timestamp 157 * @post_reset_complete_start: Umac postreset complete event timestamp 158 * @post_reset_complete_done: Umac postreset complete done timestamp 159 */ 160 struct reset_ts { 161 uint64_t trigger_start; 162 uint64_t trigger_done; 163 uint64_t pre_reset_start; 164 uint64_t pre_reset_done; 165 uint64_t post_reset_start; 166 uint64_t post_reset_done; 167 uint64_t post_reset_complete_start; 168 uint64_t post_reset_complete_done; 169 }; 170 171 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 172 /** 173 * struct dp_soc_mlo_umac_reset_ctx - UMAC reset context at mlo group level 174 * @partner_map: Partner soc map 175 * @request_map: Partner soc request map 176 * @response_map: Partner soc response map 177 * @grp_ctx_lock: lock for accessing group level umac reset context 178 * @umac_reset_in_progress: Flag to indicate if umac reset is in progress 179 * @is_target_recovery: Flag to indicate if this is for target recovery 180 * @initiator_chip_id: chip id of the Umac reset initiator 181 * @umac_reset_count: Number of times Umac reset happened on this MLO group 182 */ 183 struct dp_soc_mlo_umac_reset_ctx { 184 unsigned long partner_map; 185 unsigned long request_map; 186 unsigned long response_map; 187 qdf_spinlock_t grp_ctx_lock; 188 uint8_t umac_reset_in_progress:1, 189 is_target_recovery:1; 190 uint8_t initiator_chip_id; 191 uint32_t umac_reset_count; 192 }; 193 #endif 194 195 /** 196 * struct dp_soc_umac_reset_ctx - UMAC reset context at soc level 197 * @shmem_paddr_unaligned: Physical address of the shared memory (unaligned) 198 * @shmem_vaddr_unaligned: Virtual address of the shared memory (unaligned) 199 * @shmem_paddr_aligned: Physical address of the shared memory (aligned) 200 * @shmem_vaddr_aligned: Virtual address of the shared memory (aligned) 201 * @shmem_size: Size of the shared memory 202 * @intr_offset: Offset of the UMAC reset interrupt w.r.t DP base interrupt 203 * @current_state: current state of the UMAC reset state machine 204 * @shmem_exp_magic_num: Expected magic number in the shared memory 205 * @rx_actions: callbacks for handling UMAC reset actions 206 * @pending_action: Action pending to be executed. 207 * @intr_ctx_bkp: DP Interrupts ring masks backup 208 * @nbuf_list: skb list for delayed free 209 * @skel_enable: Enable skeleton code for umac reset 210 * @ts: timestamps debug 211 */ 212 struct dp_soc_umac_reset_ctx { 213 qdf_dma_addr_t shmem_paddr_unaligned; 214 void *shmem_vaddr_unaligned; 215 qdf_dma_addr_t shmem_paddr_aligned; 216 htt_umac_hang_recovery_msg_shmem_t *shmem_vaddr_aligned; 217 size_t shmem_size; 218 int intr_offset; 219 enum umac_reset_state current_state; 220 uint32_t shmem_exp_magic_num; 221 struct umac_reset_rx_actions rx_actions; 222 enum umac_reset_rx_event pending_action; 223 struct dp_intr_bkp *intr_ctx_bkp; 224 qdf_nbuf_t nbuf_list; 225 bool skel_enable; 226 struct reset_ts ts; 227 }; 228 229 /** 230 * dp_soc_umac_reset_init() - Initialize UMAC reset context 231 * @txrx_soc: DP soc object 232 * 233 * Return: QDF status of operation 234 */ 235 QDF_STATUS dp_soc_umac_reset_init(struct cdp_soc_t *txrx_soc); 236 237 /** 238 * dp_soc_umac_reset_deinit() - De-initialize UMAC reset context 239 * @txrx_soc: DP soc object 240 * 241 * Return: QDF status of operation 242 */ 243 QDF_STATUS dp_soc_umac_reset_deinit(struct cdp_soc_t *txrx_soc); 244 245 /** 246 * dp_umac_reset_interrupt_attach() - Register handlers for UMAC reset interrupt 247 * @soc: DP soc object 248 * 249 * Return: QDF status of operation 250 */ 251 QDF_STATUS dp_umac_reset_interrupt_attach(struct dp_soc *soc); 252 253 /** 254 * dp_umac_reset_interrupt_detach() - Unregister UMAC reset interrupt handlers 255 * @soc: DP soc object 256 * 257 * Return: QDF status of operation 258 */ 259 QDF_STATUS dp_umac_reset_interrupt_detach(struct dp_soc *soc); 260 261 /** 262 * dp_umac_reset_register_rx_action_callback() - Register a callback for a given 263 * UMAC reset action 264 * @soc: DP soc object 265 * @handler: callback handler to be registered 266 * @action: UMAC reset action for which @handler needs to be registered 267 * 268 * Return: QDF status of operation 269 */ 270 QDF_STATUS dp_umac_reset_register_rx_action_callback( 271 struct dp_soc *soc, 272 QDF_STATUS (*handler)(struct dp_soc *soc), 273 enum umac_reset_action action); 274 275 /** 276 * dp_umac_reset_notify_action_completion() - Notify that a given action has 277 * been completed 278 * @soc: DP soc object 279 * @action: UMAC reset action that got completed 280 * 281 * Return: QDF status of operation 282 */ 283 QDF_STATUS dp_umac_reset_notify_action_completion( 284 struct dp_soc *soc, 285 enum umac_reset_action action); 286 287 /** 288 * dp_umac_reset_post_tx_cmd_via_shmem() - Post Tx command using shared memory 289 * @soc: DP soc object 290 * @ctxt: Tx command to be posted 291 * @chip_id: Chip id of the mlo soc 292 * 293 * Return: None 294 */ 295 void dp_umac_reset_post_tx_cmd_via_shmem(struct dp_soc *soc, void *ctxt, 296 int chip_id); 297 298 /** 299 * dp_check_umac_reset_in_progress() - Check if Umac reset is in progress 300 * @soc: dp soc handle 301 * 302 * Return: true if Umac reset is in progress or false otherwise 303 */ 304 bool dp_check_umac_reset_in_progress(struct dp_soc *soc); 305 306 /** 307 * dp_umac_reset_stats_print - API to print UMAC reset stats 308 * @soc: dp soc handle 309 * 310 * Return: QDF_STATUS 311 */ 312 QDF_STATUS dp_umac_reset_stats_print(struct dp_soc *soc); 313 #else 314 static inline bool dp_check_umac_reset_in_progress(struct dp_soc *soc) 315 { 316 return false; 317 } 318 319 static inline 320 QDF_STATUS dp_soc_umac_reset_init(struct cdp_soc_t *txrx_soc) 321 { 322 return QDF_STATUS_SUCCESS; 323 } 324 325 static inline 326 QDF_STATUS dp_soc_umac_reset_deinit(struct cdp_soc_t *txrx_soc) 327 { 328 return QDF_STATUS_SUCCESS; 329 } 330 331 static inline 332 QDF_STATUS dp_umac_reset_register_rx_action_callback( 333 struct dp_soc *soc, 334 QDF_STATUS (*handler)(struct dp_soc *soc), 335 enum umac_reset_action action) 336 { 337 return QDF_STATUS_SUCCESS; 338 } 339 340 static inline 341 QDF_STATUS dp_umac_reset_notify_action_completion( 342 struct dp_soc *soc, 343 enum umac_reset_action action) 344 { 345 return QDF_STATUS_SUCCESS; 346 } 347 348 static inline 349 QDF_STATUS dp_umac_reset_stats_print(struct dp_soc *soc) 350 { 351 return QDF_STATUS_SUCCESS; 352 } 353 #endif /* DP_UMAC_HW_RESET_SUPPORT */ 354 #endif /* _DP_UMAC_RESET_H_ */ 355