1 /* 2 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _DP_UMAC_RESET_H_ 18 #define _DP_UMAC_RESET_H_ 19 20 #include <qdf_types.h> 21 struct dp_soc; 22 23 /** 24 * enum umac_reset_action - Actions supported by the UMAC reset 25 * @UMAC_RESET_ACTION_DO_PRE_RESET: DO_PRE_RESET 26 * @UMAC_RESET_ACTION_DO_POST_RESET_START: DO_POST_RESET_START 27 * @UMAC_RESET_ACTION_DO_POST_RESET_COMPLETE: DO_POST_RESET_COMPLETE 28 * @UMAC_RESET_ACTION_MAX: Maximum actions 29 */ 30 enum umac_reset_action { 31 UMAC_RESET_ACTION_DO_PRE_RESET = 0, 32 UMAC_RESET_ACTION_DO_POST_RESET_START = 1, 33 UMAC_RESET_ACTION_DO_POST_RESET_COMPLETE = 2, 34 UMAC_RESET_ACTION_MAX 35 }; 36 37 #ifdef DP_UMAC_HW_RESET_SUPPORT 38 39 #define dp_umac_reset_alert(params...) \ 40 QDF_TRACE_FATAL(QDF_MODULE_ID_DP_UMAC_RESET, params) 41 #define dp_umac_reset_err(params...) \ 42 QDF_TRACE_ERROR(QDF_MODULE_ID_DP_UMAC_RESET, params) 43 #define dp_umac_reset_warn(params...) \ 44 QDF_TRACE_WARN(QDF_MODULE_ID_DP_UMAC_RESET, params) 45 #define dp_umac_reset_notice(params...) \ 46 QDF_TRACE_INFO(QDF_MODULE_ID_DP_UMAC_RESET, params) 47 #define dp_umac_reset_info(params...) \ 48 QDF_TRACE_INFO(QDF_MODULE_ID_DP_UMAC_RESET, params) 49 #define dp_umac_reset_debug(params...) \ 50 QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_UMAC_RESET, params) 51 52 #define DP_UMAC_RESET_SHMEM_ALIGN 8 53 #define DP_UMAC_RESET_SHMEM_MAGIC_NUM (0xDEADBEEF) 54 55 /** 56 * enum umac_reset_state - States required by the UMAC reset state machine 57 * @UMAC_RESET_STATE_WAIT_FOR_DO_PRE_RESET: Waiting for the DO_PRE_RESET event 58 * @UMAC_RESET_STATE_DO_PRE_RESET_RECEIVED: Received the DO_PRE_RESET event 59 * @UMAC_RESET_STATE_HOST_PRE_RESET_DONE: Host has completed handling the 60 * PRE_RESET event 61 * @UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_START: Waiting for the 62 * DO_POST_RESET_START event 63 * @UMAC_RESET_STATE_DO_POST_RESET_START_RECEIVED: Received the 64 * DO_POST_RESET_START event 65 * @UMAC_RESET_STATE_HOST_POST_RESET_START_DONE: Host has completed handling the 66 * POST_RESET_START event 67 * @UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_COMPLETE: Waiting for the 68 * DO_POST_RESET_COMPLETE event 69 * @UMAC_RESET_STATE_DO_POST_RESET_COMPLETE_RECEIVED: Received the 70 * DO_POST_RESET_COMPLETE event 71 * @UMAC_RESET_STATE_HOST_POST_RESET_COMPLETE_DONE: Host has completed handling 72 * the DO_POST_RESET_COMPLETE event 73 */ 74 enum umac_reset_state { 75 UMAC_RESET_STATE_WAIT_FOR_DO_PRE_RESET = 0, 76 UMAC_RESET_STATE_DO_PRE_RESET_RECEIVED, 77 UMAC_RESET_STATE_HOST_PRE_RESET_DONE, 78 79 UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_START, 80 UMAC_RESET_STATE_DO_POST_RESET_START_RECEIVED, 81 UMAC_RESET_STATE_HOST_POST_RESET_START_DONE, 82 83 UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_COMPLETE, 84 UMAC_RESET_STATE_DO_POST_RESET_COMPLETE_RECEIVED, 85 UMAC_RESET_STATE_HOST_POST_RESET_COMPLETE_DONE, 86 }; 87 88 /** 89 * enum umac_reset_rx_event - Rx events deduced by the UMAC reset 90 * @UMAC_RESET_RX_EVENT_NONE: No event 91 * @UMAC_RESET_RX_EVENT_DO_PRE_RESET: DO_PRE_RESET event 92 * @UMAC_RESET_RX_EVENT_DO_POST_RESET_START: DO_POST_RESET_START event 93 * @UMAC_RESET_RX_EVENT_DO_POST_RESET_COMPELTE: DO_POST_RESET_COMPELTE event 94 * @UMAC_RESET_RX_EVENT_ERROR: Error while processing the Rx event 95 */ 96 enum umac_reset_rx_event { 97 UMAC_RESET_RX_EVENT_NONE = 0x0, 98 UMAC_RESET_RX_EVENT_DO_PRE_RESET = 0x1, 99 UMAC_RESET_RX_EVENT_DO_POST_RESET_START = 0x2, 100 UMAC_RESET_RX_EVENT_DO_POST_RESET_COMPELTE = 0x4, 101 102 UMAC_RESET_RX_EVENT_ERROR = 0xFFFFFFFF, 103 }; 104 105 /** 106 * enum umac_reset_tx_cmd: UMAC reset Tx command 107 * @UMAC_RESET_TX_CMD_PRE_RESET_DONE: PRE_RESET_DONE 108 * @UMAC_RESET_TX_CMD_POST_RESET_START_DONE: POST_RESET_START_DONE 109 * @UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE: POST_RESET_COMPLETE_DONE 110 */ 111 enum umac_reset_tx_cmd { 112 UMAC_RESET_TX_CMD_PRE_RESET_DONE, 113 UMAC_RESET_TX_CMD_POST_RESET_START_DONE, 114 UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE, 115 }; 116 117 /** 118 * struct umac_reset_rx_actions - callbacks for handling UMAC reset actions 119 * @cb: Array of pointers where each pointer contains callback for each UMAC 120 * reset action for that index 121 */ 122 struct umac_reset_rx_actions { 123 QDF_STATUS (*cb[UMAC_RESET_ACTION_MAX])(struct dp_soc *soc); 124 }; 125 126 /** 127 * struct reset_ts - timestamps of for umac reset events for debug 128 * @pre_reset_start: Umac prereset start event timestamp 129 * @pre_reset_done: Umac prereset done timestamp 130 * @post_reset_start: Umac postreset start event timestamp 131 * @post_reset_done: Umac postreset done timestamp 132 * @post_reset_complete_start: Umac postreset complete event timestamp 133 * @post_reset_complete_done: Umac postreset complete done timestamp 134 */ 135 struct reset_ts { 136 uint64_t pre_reset_start; 137 uint64_t pre_reset_done; 138 uint64_t post_reset_start; 139 uint64_t post_reset_done; 140 uint64_t post_reset_complete_start; 141 uint64_t post_reset_complete_done; 142 }; 143 144 /** 145 * struct dp_soc_umac_reset_ctx - UMAC reset context at soc level 146 * @shmem_paddr_unaligned: Physical address of the shared memory (unaligned) 147 * @shmem_vaddr_unaligned: Virtual address of the shared memory (unaligned) 148 * @shmem_paddr_aligned: Physical address of the shared memory (aligned) 149 * @shmem_vaddr_aligned: Virtual address of the shared memory (aligned) 150 * @shmem_size: Size of the shared memory 151 * @intr_offset: Offset of the UMAC reset interrupt w.r.t DP base interrupt 152 * @current_state: current state of the UMAC reset state machine 153 * @shmem_exp_magic_num: Expected magic number in the shared memory 154 * @rx_actions: callbacks for handling UMAC reset actions 155 * @intr_ctx_bkp: DP Interrupts ring masks backup 156 * @nbuf_list: skb list for delayed free 157 * @skel_enable: Enable skeleton code for umac reset 158 * @ts: timestamps debug 159 */ 160 struct dp_soc_umac_reset_ctx { 161 qdf_dma_addr_t shmem_paddr_unaligned; 162 void *shmem_vaddr_unaligned; 163 qdf_dma_addr_t shmem_paddr_aligned; 164 htt_umac_hang_recovery_msg_shmem_t *shmem_vaddr_aligned; 165 size_t shmem_size; 166 int intr_offset; 167 enum umac_reset_state current_state; 168 uint32_t shmem_exp_magic_num; 169 struct umac_reset_rx_actions rx_actions; 170 struct dp_intr_bkp *intr_ctx_bkp; 171 qdf_nbuf_t nbuf_list; 172 bool skel_enable; 173 struct reset_ts ts; 174 }; 175 176 /** 177 * dp_soc_umac_reset_init() - Initialize UMAC reset context 178 * @soc: DP soc object 179 * 180 * Return: QDF status of operation 181 */ 182 QDF_STATUS dp_soc_umac_reset_init(struct dp_soc *soc); 183 184 /** 185 * dp_soc_umac_reset_deinit() - De-initialize UMAC reset context 186 * @txrx_soc: DP soc object 187 * 188 * Return: QDF status of operation 189 */ 190 QDF_STATUS dp_soc_umac_reset_deinit(struct cdp_soc_t *txrx_soc); 191 192 /** 193 * dp_umac_reset_interrupt_attach() - Register handlers for UMAC reset interrupt 194 * @soc: DP soc object 195 * 196 * Return: QDF status of operation 197 */ 198 QDF_STATUS dp_umac_reset_interrupt_attach(struct dp_soc *soc); 199 200 /** 201 * dp_umac_reset_interrupt_detach() - Unregister UMAC reset interrupt handlers 202 * @soc: DP soc object 203 * 204 * Return: QDF status of operation 205 */ 206 QDF_STATUS dp_umac_reset_interrupt_detach(struct dp_soc *soc); 207 208 /** 209 * dp_umac_reset_register_rx_action_callback() - Register a callback for a given 210 * UMAC reset action 211 * @soc: DP soc object 212 * @handler: callback handler to be registered 213 * @action: UMAC reset action for which @handler needs to be registered 214 * 215 * Return: QDF status of operation 216 */ 217 QDF_STATUS dp_umac_reset_register_rx_action_callback( 218 struct dp_soc *soc, 219 QDF_STATUS (*handler)(struct dp_soc *soc), 220 enum umac_reset_action action); 221 222 /** 223 * dp_umac_reset_notify_action_completion() - Notify that a given action has 224 * been completed 225 * @soc: DP soc object 226 * @action: UMAC reset action that got completed 227 * 228 * Return: QDF status of operation 229 */ 230 QDF_STATUS dp_umac_reset_notify_action_completion( 231 struct dp_soc *soc, 232 enum umac_reset_action action); 233 #else 234 static inline 235 QDF_STATUS dp_soc_umac_reset_init(struct dp_soc *soc) 236 { 237 return QDF_STATUS_SUCCESS; 238 } 239 240 static inline 241 QDF_STATUS dp_soc_umac_reset_deinit(struct cdp_soc_t *txrx_soc) 242 { 243 return QDF_STATUS_SUCCESS; 244 } 245 246 static inline 247 QDF_STATUS dp_umac_reset_register_rx_action_callback( 248 struct dp_soc *soc, 249 QDF_STATUS (*handler)(struct dp_soc *soc), 250 enum umac_reset_action action) 251 { 252 return QDF_STATUS_SUCCESS; 253 } 254 255 static inline 256 QDF_STATUS dp_umac_reset_notify_action_completion( 257 struct dp_soc *soc, 258 enum umac_reset_action action) 259 { 260 return QDF_STATUS_SUCCESS; 261 } 262 #endif /* DP_UMAC_HW_RESET_SUPPORT */ 263 #endif /* _DP_UMAC_RESET_H_ */ 264