1 /* 2 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _DP_UMAC_RESET_H_ 18 #define _DP_UMAC_RESET_H_ 19 20 #include <qdf_types.h> 21 struct dp_soc; 22 23 /** 24 * enum umac_reset_action - Actions supported by the UMAC reset 25 * @UMAC_RESET_ACTION_NONE: No action 26 * @UMAC_RESET_ACTION_DO_TRIGGER_RECOVERY: Trigger umac recovery 27 * @UMAC_RESET_ACTION_DO_PRE_RESET: DO_PRE_RESET 28 * @UMAC_RESET_ACTION_DO_POST_RESET_START: DO_POST_RESET_START 29 * @UMAC_RESET_ACTION_DO_POST_RESET_COMPLETE: DO_POST_RESET_COMPLETE 30 * @UMAC_RESET_ACTION_ABORT: Abort the current Umac reset session 31 * @UMAC_RESET_ACTION_MAX: Maximum actions 32 */ 33 enum umac_reset_action { 34 UMAC_RESET_ACTION_NONE, 35 UMAC_RESET_ACTION_DO_TRIGGER_RECOVERY, 36 UMAC_RESET_ACTION_DO_PRE_RESET, 37 UMAC_RESET_ACTION_DO_POST_RESET_START, 38 UMAC_RESET_ACTION_DO_POST_RESET_COMPLETE, 39 UMAC_RESET_ACTION_ABORT, 40 UMAC_RESET_ACTION_MAX 41 }; 42 43 #ifdef DP_UMAC_HW_RESET_SUPPORT 44 45 #define dp_umac_reset_alert(params...) \ 46 QDF_TRACE_FATAL(QDF_MODULE_ID_DP_UMAC_RESET, params) 47 #define dp_umac_reset_err(params...) \ 48 QDF_TRACE_ERROR(QDF_MODULE_ID_DP_UMAC_RESET, params) 49 #define dp_umac_reset_warn(params...) \ 50 QDF_TRACE_WARN(QDF_MODULE_ID_DP_UMAC_RESET, params) 51 #define dp_umac_reset_notice(params...) \ 52 QDF_TRACE_INFO(QDF_MODULE_ID_DP_UMAC_RESET, params) 53 #define dp_umac_reset_info(params...) \ 54 QDF_TRACE_INFO(QDF_MODULE_ID_DP_UMAC_RESET, params) 55 #define dp_umac_reset_debug(params...) \ 56 QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_UMAC_RESET, params) 57 58 #define DP_UMAC_RESET_SHMEM_ALIGN 8 59 #define DP_UMAC_RESET_SHMEM_MAGIC_NUM (0xDEADBEEF) 60 61 /** 62 * enum umac_reset_state - States required by the UMAC reset state machine 63 * @UMAC_RESET_STATE_WAIT_FOR_TRIGGER: Waiting for trigger event 64 * @UMAC_RESET_STATE_DO_TRIGGER_RECEIVED: Receivd the DO_TRIGGER event 65 * @UMAC_RESET_STATE_HOST_TRIGGER_DONE: Host completed handling Trigger event 66 * @UMAC_RESET_STATE_WAIT_FOR_DO_PRE_RESET: Waiting for the DO_PRE_RESET event 67 * @UMAC_RESET_STATE_DO_PRE_RESET_RECEIVED: Received the DO_PRE_RESET event 68 * @UMAC_RESET_STATE_HOST_PRE_RESET_DONE: Host has completed handling the 69 * PRE_RESET event 70 * @UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_START: Waiting for the 71 * DO_POST_RESET_START event 72 * @UMAC_RESET_STATE_DO_POST_RESET_START_RECEIVED: Received the 73 * DO_POST_RESET_START event 74 * @UMAC_RESET_STATE_HOST_POST_RESET_START_DONE: Host has completed handling the 75 * POST_RESET_START event 76 * @UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_COMPLETE: Waiting for the 77 * DO_POST_RESET_COMPLETE event 78 * @UMAC_RESET_STATE_DO_POST_RESET_COMPLETE_RECEIVED: Received the 79 * DO_POST_RESET_COMPLETE event 80 * @UMAC_RESET_STATE_HOST_POST_RESET_COMPLETE_DONE: Host has completed handling 81 * the DO_POST_RESET_COMPLETE event 82 */ 83 enum umac_reset_state { 84 UMAC_RESET_STATE_WAIT_FOR_TRIGGER = 0, 85 UMAC_RESET_STATE_DO_TRIGGER_RECEIVED, 86 UMAC_RESET_STATE_HOST_TRIGGER_DONE, 87 88 UMAC_RESET_STATE_WAIT_FOR_DO_PRE_RESET, 89 UMAC_RESET_STATE_DO_PRE_RESET_RECEIVED, 90 UMAC_RESET_STATE_HOST_PRE_RESET_DONE, 91 92 UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_START, 93 UMAC_RESET_STATE_DO_POST_RESET_START_RECEIVED, 94 UMAC_RESET_STATE_HOST_POST_RESET_START_DONE, 95 96 UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_COMPLETE, 97 UMAC_RESET_STATE_DO_POST_RESET_COMPLETE_RECEIVED, 98 UMAC_RESET_STATE_HOST_POST_RESET_COMPLETE_DONE, 99 }; 100 101 /** 102 * enum umac_reset_rx_event - Rx events deduced by the UMAC reset 103 * @UMAC_RESET_RX_EVENT_NONE: No event 104 * @UMAC_RESET_RX_EVENT_DO_TRIGGER_RECOVERY: ACTION_DO_TRIGGER_RECOVERY event 105 * @UMAC_RESET_RX_EVENT_DO_TRIGGER_TR_SYNC: ACTION_DO_TRIGGER_RECOVERY event 106 * @UMAC_RESET_RX_EVENT_DO_PRE_RESET: DO_PRE_RESET event 107 * @UMAC_RESET_RX_EVENT_DO_POST_RESET_START: DO_POST_RESET_START event 108 * @UMAC_RESET_RX_EVENT_DO_POST_RESET_COMPELTE: DO_POST_RESET_COMPELTE event 109 * @UMAC_RESET_RX_EVENT_ERROR: Error while processing the Rx event 110 */ 111 enum umac_reset_rx_event { 112 UMAC_RESET_RX_EVENT_NONE = 0x0, 113 UMAC_RESET_RX_EVENT_DO_TRIGGER_RECOVERY, 114 UMAC_RESET_RX_EVENT_DO_TRIGGER_TR_SYNC, 115 UMAC_RESET_RX_EVENT_DO_PRE_RESET, 116 UMAC_RESET_RX_EVENT_DO_POST_RESET_START, 117 UMAC_RESET_RX_EVENT_DO_POST_RESET_COMPELTE, 118 119 UMAC_RESET_RX_EVENT_ERROR = 0xFFFFFFFF, 120 }; 121 122 /** 123 * enum umac_reset_tx_cmd: UMAC reset Tx command 124 * @UMAC_RESET_TX_CMD_TRIGGER_DONE: TRIGGER_DONE 125 * @UMAC_RESET_TX_CMD_PRE_RESET_DONE: PRE_RESET_DONE 126 * @UMAC_RESET_TX_CMD_POST_RESET_START_DONE: POST_RESET_START_DONE 127 * @UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE: POST_RESET_COMPLETE_DONE 128 */ 129 enum umac_reset_tx_cmd { 130 UMAC_RESET_TX_CMD_TRIGGER_DONE, 131 UMAC_RESET_TX_CMD_PRE_RESET_DONE, 132 UMAC_RESET_TX_CMD_POST_RESET_START_DONE, 133 UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE, 134 }; 135 136 /** 137 * struct umac_reset_rx_actions - callbacks for handling UMAC reset actions 138 * @cb: Array of pointers where each pointer contains callback for each UMAC 139 * reset action for that index 140 */ 141 struct umac_reset_rx_actions { 142 QDF_STATUS (*cb[UMAC_RESET_ACTION_MAX])(struct dp_soc *soc); 143 }; 144 145 /** 146 * struct reset_ts - timestamps of for umac reset events for debug 147 * @trigger_start: Umac reset trigger event timestamp 148 * @trigger_done: Umac reset trigger done timestamp 149 * @pre_reset_start: Umac prereset start event timestamp 150 * @pre_reset_done: Umac prereset done timestamp 151 * @post_reset_start: Umac postreset start event timestamp 152 * @post_reset_done: Umac postreset done timestamp 153 * @post_reset_complete_start: Umac postreset complete event timestamp 154 * @post_reset_complete_done: Umac postreset complete done timestamp 155 */ 156 struct reset_ts { 157 uint64_t trigger_start; 158 uint64_t trigger_done; 159 uint64_t pre_reset_start; 160 uint64_t pre_reset_done; 161 uint64_t post_reset_start; 162 uint64_t post_reset_done; 163 uint64_t post_reset_complete_start; 164 uint64_t post_reset_complete_done; 165 }; 166 167 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 168 /** 169 * struct dp_soc_mlo_umac_reset_ctx - UMAC reset context at mlo group level 170 * @partner_map: Partner soc map 171 * @request_map: Partner soc request map 172 * @response_map: Partner soc response map 173 * @grp_ctx_lock: lock for accessing group level umac reset context 174 * @umac_reset_in_progress: Flag to indicate if umac reset is in progress 175 * @is_target_recovery: Flag to indicate if this is for target recovery 176 * @initiator_chip_id: chip id of the Umac reset initiator 177 * @umac_reset_count: Number of times Umac reset happened on this MLO group 178 */ 179 struct dp_soc_mlo_umac_reset_ctx { 180 unsigned long partner_map; 181 unsigned long request_map; 182 unsigned long response_map; 183 qdf_spinlock_t grp_ctx_lock; 184 uint8_t umac_reset_in_progress:1, 185 is_target_recovery:1; 186 uint8_t initiator_chip_id; 187 uint32_t umac_reset_count; 188 }; 189 #endif 190 191 /** 192 * struct dp_soc_umac_reset_ctx - UMAC reset context at soc level 193 * @shmem_paddr_unaligned: Physical address of the shared memory (unaligned) 194 * @shmem_vaddr_unaligned: Virtual address of the shared memory (unaligned) 195 * @shmem_paddr_aligned: Physical address of the shared memory (aligned) 196 * @shmem_vaddr_aligned: Virtual address of the shared memory (aligned) 197 * @shmem_size: Size of the shared memory 198 * @intr_offset: Offset of the UMAC reset interrupt w.r.t DP base interrupt 199 * @current_state: current state of the UMAC reset state machine 200 * @shmem_exp_magic_num: Expected magic number in the shared memory 201 * @rx_actions: callbacks for handling UMAC reset actions 202 * @pending_action: Action pending to be executed. 203 * @intr_ctx_bkp: DP Interrupts ring masks backup 204 * @nbuf_list: skb list for delayed free 205 * @skel_enable: Enable skeleton code for umac reset 206 * @ts: timestamps debug 207 */ 208 struct dp_soc_umac_reset_ctx { 209 qdf_dma_addr_t shmem_paddr_unaligned; 210 void *shmem_vaddr_unaligned; 211 qdf_dma_addr_t shmem_paddr_aligned; 212 htt_umac_hang_recovery_msg_shmem_t *shmem_vaddr_aligned; 213 size_t shmem_size; 214 int intr_offset; 215 enum umac_reset_state current_state; 216 uint32_t shmem_exp_magic_num; 217 struct umac_reset_rx_actions rx_actions; 218 enum umac_reset_rx_event pending_action; 219 struct dp_intr_bkp *intr_ctx_bkp; 220 qdf_nbuf_t nbuf_list; 221 bool skel_enable; 222 struct reset_ts ts; 223 }; 224 225 /** 226 * dp_soc_umac_reset_init() - Initialize UMAC reset context 227 * @soc: DP soc object 228 * 229 * Return: QDF status of operation 230 */ 231 QDF_STATUS dp_soc_umac_reset_init(struct dp_soc *soc); 232 233 /** 234 * dp_soc_umac_reset_deinit() - De-initialize UMAC reset context 235 * @txrx_soc: DP soc object 236 * 237 * Return: QDF status of operation 238 */ 239 QDF_STATUS dp_soc_umac_reset_deinit(struct cdp_soc_t *txrx_soc); 240 241 /** 242 * dp_umac_reset_interrupt_attach() - Register handlers for UMAC reset interrupt 243 * @soc: DP soc object 244 * 245 * Return: QDF status of operation 246 */ 247 QDF_STATUS dp_umac_reset_interrupt_attach(struct dp_soc *soc); 248 249 /** 250 * dp_umac_reset_interrupt_detach() - Unregister UMAC reset interrupt handlers 251 * @soc: DP soc object 252 * 253 * Return: QDF status of operation 254 */ 255 QDF_STATUS dp_umac_reset_interrupt_detach(struct dp_soc *soc); 256 257 /** 258 * dp_umac_reset_register_rx_action_callback() - Register a callback for a given 259 * UMAC reset action 260 * @soc: DP soc object 261 * @handler: callback handler to be registered 262 * @action: UMAC reset action for which @handler needs to be registered 263 * 264 * Return: QDF status of operation 265 */ 266 QDF_STATUS dp_umac_reset_register_rx_action_callback( 267 struct dp_soc *soc, 268 QDF_STATUS (*handler)(struct dp_soc *soc), 269 enum umac_reset_action action); 270 271 /** 272 * dp_umac_reset_notify_action_completion() - Notify that a given action has 273 * been completed 274 * @soc: DP soc object 275 * @action: UMAC reset action that got completed 276 * 277 * Return: QDF status of operation 278 */ 279 QDF_STATUS dp_umac_reset_notify_action_completion( 280 struct dp_soc *soc, 281 enum umac_reset_action action); 282 283 /** 284 * dp_umac_reset_post_tx_cmd_via_shmem() - Post Tx command using shared memory 285 * @soc: DP soc object 286 * @ctxt: Tx command to be posted 287 * @chip_id: Chip id of the mlo soc 288 * 289 * Return: None 290 */ 291 void dp_umac_reset_post_tx_cmd_via_shmem(struct dp_soc *soc, void *ctxt, 292 int chip_id); 293 294 /** 295 * dp_check_umac_reset_in_progress() - Check if Umac reset is in progress 296 * @soc: dp soc handle 297 * 298 * Return: true if Umac reset is in progress or false otherwise 299 */ 300 bool dp_check_umac_reset_in_progress(struct dp_soc *soc); 301 #else 302 static inline bool dp_check_umac_reset_in_progress(struct dp_soc *soc) 303 { 304 return false; 305 } 306 307 static inline 308 QDF_STATUS dp_soc_umac_reset_init(struct dp_soc *soc) 309 { 310 return QDF_STATUS_SUCCESS; 311 } 312 313 static inline 314 QDF_STATUS dp_soc_umac_reset_deinit(struct cdp_soc_t *txrx_soc) 315 { 316 return QDF_STATUS_SUCCESS; 317 } 318 319 static inline 320 QDF_STATUS dp_umac_reset_register_rx_action_callback( 321 struct dp_soc *soc, 322 QDF_STATUS (*handler)(struct dp_soc *soc), 323 enum umac_reset_action action) 324 { 325 return QDF_STATUS_SUCCESS; 326 } 327 328 static inline 329 QDF_STATUS dp_umac_reset_notify_action_completion( 330 struct dp_soc *soc, 331 enum umac_reset_action action) 332 { 333 return QDF_STATUS_SUCCESS; 334 } 335 #endif /* DP_UMAC_HW_RESET_SUPPORT */ 336 #endif /* _DP_UMAC_RESET_H_ */ 337