1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DP_TYPES_H_ 20 #define _DP_TYPES_H_ 21 22 #include <qdf_types.h> 23 #include <qdf_nbuf.h> 24 #include <qdf_lock.h> 25 #include <qdf_atomic.h> 26 #include <qdf_util.h> 27 #include <qdf_list.h> 28 #include <qdf_lro.h> 29 #include <queue.h> 30 #include <htt_common.h> 31 32 #include <cdp_txrx_cmn.h> 33 #ifdef DP_MOB_DEFS 34 #include <cds_ieee80211_common.h> 35 #endif 36 #include <wdi_event_api.h> /* WDI subscriber event list */ 37 38 #include "hal_hw_headers.h" 39 #include <hal_tx.h> 40 #include <hal_reo.h> 41 #include "wlan_cfg.h" 42 #include "hal_rx.h" 43 #include <hal_api.h> 44 #include <hal_api_mon.h> 45 #include "hal_rx.h" 46 //#include "hal_rx_flow.h" 47 48 #define MAX_BW 7 49 #define MAX_RETRIES 4 50 #define MAX_RECEPTION_TYPES 4 51 52 #ifndef REMOVE_PKT_LOG 53 #include <pktlog.h> 54 #endif 55 56 #ifdef WLAN_TX_PKT_CAPTURE_ENH 57 #include "dp_tx_capture.h" 58 #endif 59 60 #define REPT_MU_MIMO 1 61 #define REPT_MU_OFDMA_MIMO 3 62 #define DP_VO_TID 6 63 /** MAX TID MAPS AVAILABLE PER PDEV */ 64 #define DP_MAX_TID_MAPS 16 65 /** pad DSCP_TID_MAP_MAX with 6 to fix oob issue */ 66 #define DSCP_TID_MAP_MAX (64 + 6) 67 #define DP_IP_DSCP_SHIFT 2 68 #define DP_IP_DSCP_MASK 0x3f 69 #define DP_FC0_SUBTYPE_QOS 0x80 70 #define DP_QOS_TID 0x0f 71 #define DP_IPV6_PRIORITY_SHIFT 20 72 #define MAX_MON_LINK_DESC_BANKS 2 73 #define DP_VDEV_ALL 0xff 74 75 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 76 #define MAX_PDEV_CNT 1 77 #else 78 #define MAX_PDEV_CNT 3 79 #endif 80 81 /* Max no. of VDEV per PSOC */ 82 #ifdef WLAN_PSOC_MAX_VDEVS 83 #define MAX_VDEV_CNT WLAN_PSOC_MAX_VDEVS 84 #else 85 #define MAX_VDEV_CNT 51 86 #endif 87 88 #define MAX_LINK_DESC_BANKS 8 89 #define MAX_TXDESC_POOLS 4 90 #define MAX_RXDESC_POOLS 4 91 #define MAX_REO_DEST_RINGS 4 92 #define EXCEPTION_DEST_RING_ID 0 93 #define MAX_TCL_DATA_RINGS 4 94 #define MAX_IDLE_SCATTER_BUFS 16 95 #define DP_MAX_IRQ_PER_CONTEXT 12 96 #define DEFAULT_HW_PEER_ID 0xffff 97 98 #define WBM_INT_ERROR_ALL 0 99 #define WBM_INT_ERROR_REO_NULL_BUFFER 1 100 #define WBM_INT_ERROR_REO_NULL_LINK_DESC 2 101 #define WBM_INT_ERROR_REO_NULL_MSDU_BUFF 3 102 #define WBM_INT_ERROR_REO_BUFF_REAPED 4 103 #define MAX_WBM_INT_ERROR_REASONS 5 104 105 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 106 /* Maximum retries for Delba per tid per peer */ 107 #define DP_MAX_DELBA_RETRY 3 108 109 #define PCP_TID_MAP_MAX 8 110 #define MAX_MU_USERS 37 111 112 #define REO_CMD_EVENT_HIST_MAX 64 113 114 #ifndef REMOVE_PKT_LOG 115 enum rx_pktlog_mode { 116 DP_RX_PKTLOG_DISABLED = 0, 117 DP_RX_PKTLOG_FULL, 118 DP_RX_PKTLOG_LITE, 119 }; 120 #endif 121 122 struct msdu_list { 123 qdf_nbuf_t head; 124 qdf_nbuf_t tail; 125 uint32 sum_len; 126 }; 127 128 struct dp_soc_cmn; 129 struct dp_pdev; 130 struct dp_vdev; 131 struct dp_tx_desc_s; 132 struct dp_soc; 133 union dp_rx_desc_list_elem_t; 134 struct cdp_peer_rate_stats_ctx; 135 struct cdp_soc_rate_stats_ctx; 136 struct dp_rx_fst; 137 struct dp_mon_filter; 138 139 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 140 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 141 142 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 143 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 144 145 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 146 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 147 148 #define DP_MUTEX_TYPE qdf_spinlock_t 149 150 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 151 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 152 153 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 154 ((_a)[0] == 0x33 && \ 155 (_a)[1] == 0x33) 156 157 #define DP_FRAME_IS_BROADCAST(_a) \ 158 ((_a)[0] == 0xff && \ 159 (_a)[1] == 0xff && \ 160 (_a)[2] == 0xff && \ 161 (_a)[3] == 0xff && \ 162 (_a)[4] == 0xff && \ 163 (_a)[5] == 0xff) 164 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 165 (_llc)->llc_ssap == 0xaa && \ 166 (_llc)->llc_un.type_snap.control == 0x3) 167 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 168 #define DP_FRAME_FC0_TYPE_MASK 0x0c 169 #define DP_FRAME_FC0_TYPE_DATA 0x08 170 #define DP_FRAME_IS_DATA(_frame) \ 171 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 172 173 /** 174 * macros to convert hw mac id to sw mac id: 175 * mac ids used by hardware start from a value of 1 while 176 * those in host software start from a value of 0. Use the 177 * macros below to convert between mac ids used by software and 178 * hardware 179 */ 180 #define DP_SW2HW_MACID(id) ((id) + 1) 181 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 182 183 /** 184 * Number of Tx Queues 185 * enum and macro to define how many threshold levels is used 186 * for the AC based flow control 187 */ 188 #ifdef QCA_AC_BASED_FLOW_CONTROL 189 enum dp_fl_ctrl_threshold { 190 DP_TH_BE_BK = 0, 191 DP_TH_VI, 192 DP_TH_VO, 193 DP_TH_HI, 194 }; 195 196 #define FL_TH_MAX (4) 197 #define FL_TH_VI_PERCENTAGE (80) 198 #define FL_TH_VO_PERCENTAGE (60) 199 #define FL_TH_HI_PERCENTAGE (40) 200 #endif 201 202 /** 203 * enum dp_intr_mode 204 * @DP_INTR_INTEGRATED: Line interrupts 205 * @DP_INTR_MSI: MSI interrupts 206 * @DP_INTR_POLL: Polling 207 */ 208 enum dp_intr_mode { 209 DP_INTR_INTEGRATED = 0, 210 DP_INTR_MSI, 211 DP_INTR_POLL, 212 }; 213 214 /** 215 * enum dp_tx_frm_type 216 * @dp_tx_frm_std: Regular frame, no added header fragments 217 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 218 * @dp_tx_frm_sg: SG segment 219 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 220 * @dp_tx_frm_me: Multicast to Unicast Converted frame 221 * @dp_tx_frm_raw: Raw Frame 222 */ 223 enum dp_tx_frm_type { 224 dp_tx_frm_std = 0, 225 dp_tx_frm_tso, 226 dp_tx_frm_sg, 227 dp_tx_frm_audio, 228 dp_tx_frm_me, 229 dp_tx_frm_raw, 230 }; 231 232 /** 233 * enum dp_ast_type 234 * @dp_ast_type_wds: WDS peer AST type 235 * @dp_ast_type_static: static ast entry type 236 * @dp_ast_type_mec: Multicast echo ast entry type 237 */ 238 enum dp_ast_type { 239 dp_ast_type_wds = 0, 240 dp_ast_type_static, 241 dp_ast_type_mec, 242 }; 243 244 /** 245 * enum dp_nss_cfg 246 * @dp_nss_cfg_default: No radios are offloaded 247 * @dp_nss_cfg_first_radio: First radio offloaded 248 * @dp_nss_cfg_second_radio: Second radio offloaded 249 * @dp_nss_cfg_dbdc: Dual radios offloaded 250 * @dp_nss_cfg_dbtc: Three radios offloaded 251 */ 252 enum dp_nss_cfg { 253 dp_nss_cfg_default = 0x0, 254 dp_nss_cfg_first_radio = 0x1, 255 dp_nss_cfg_second_radio = 0x2, 256 dp_nss_cfg_dbdc = 0x3, 257 dp_nss_cfg_dbtc = 0x7, 258 dp_nss_cfg_max 259 }; 260 261 #ifdef WLAN_TX_PKT_CAPTURE_ENH 262 #define DP_CPU_RING_MAP_1 1 263 #endif 264 265 /** 266 * dp_cpu_ring_map_type - dp tx cpu ring map 267 * @DP_NSS_DEFAULT_MAP: Default mode with no NSS offloaded 268 * @DP_NSS_FIRST_RADIO_OFFLOADED_MAP: Only First Radio is offloaded 269 * @DP_NSS_SECOND_RADIO_OFFLOADED_MAP: Only second radio is offloaded 270 * @DP_NSS_DBDC_OFFLOADED_MAP: Both radios are offloaded 271 * @DP_NSS_DBTC_OFFLOADED_MAP: All three radios are offloaded 272 * @DP_SINGLE_TX_RING_MAP: to avoid out of order all cpu mapped to single ring 273 * @DP_NSS_CPU_RING_MAP_MAX: Max cpu ring map val 274 */ 275 enum dp_cpu_ring_map_types { 276 DP_NSS_DEFAULT_MAP, 277 DP_NSS_FIRST_RADIO_OFFLOADED_MAP, 278 DP_NSS_SECOND_RADIO_OFFLOADED_MAP, 279 DP_NSS_DBDC_OFFLOADED_MAP, 280 DP_NSS_DBTC_OFFLOADED_MAP, 281 #ifdef WLAN_TX_PKT_CAPTURE_ENH 282 DP_SINGLE_TX_RING_MAP, 283 #endif 284 DP_NSS_CPU_RING_MAP_MAX 285 }; 286 287 /** 288 * struct rx_desc_pool 289 * @pool_size: number of RX descriptor in the pool 290 * @elem_size: Element size 291 * @desc_pages: Multi page descriptors 292 * @array: pointer to array of RX descriptor 293 * @freelist: pointer to free RX descriptor link list 294 * @lock: Protection for the RX descriptor pool 295 * @owner: owner for nbuf 296 * @buf_size: Buffer size 297 * @buf_alignment: Buffer alignment 298 */ 299 struct rx_desc_pool { 300 uint32_t pool_size; 301 #ifdef RX_DESC_MULTI_PAGE_ALLOC 302 uint16_t elem_size; 303 struct qdf_mem_multi_page_t desc_pages; 304 #else 305 union dp_rx_desc_list_elem_t *array; 306 #endif 307 union dp_rx_desc_list_elem_t *freelist; 308 qdf_spinlock_t lock; 309 uint8_t owner; 310 uint16_t buf_size; 311 uint8_t buf_alignment; 312 }; 313 314 /** 315 * struct dp_tx_ext_desc_elem_s 316 * @next: next extension descriptor pointer 317 * @vaddr: hlos virtual address pointer 318 * @paddr: physical address pointer for descriptor 319 */ 320 struct dp_tx_ext_desc_elem_s { 321 struct dp_tx_ext_desc_elem_s *next; 322 void *vaddr; 323 qdf_dma_addr_t paddr; 324 }; 325 326 /** 327 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 328 * @elem_count: Number of descriptors in the pool 329 * @elem_size: Size of each descriptor 330 * @num_free: Number of free descriptors 331 * @msdu_ext_desc: MSDU extension descriptor 332 * @desc_pages: multiple page allocation information for actual descriptors 333 * @link_elem_size: size of the link descriptor in cacheable memory used for 334 * chaining the extension descriptors 335 * @desc_link_pages: multiple page allocation information for link descriptors 336 */ 337 struct dp_tx_ext_desc_pool_s { 338 uint16_t elem_count; 339 int elem_size; 340 uint16_t num_free; 341 struct qdf_mem_multi_page_t desc_pages; 342 int link_elem_size; 343 struct qdf_mem_multi_page_t desc_link_pages; 344 struct dp_tx_ext_desc_elem_s *freelist; 345 qdf_spinlock_t lock; 346 qdf_dma_mem_context(memctx); 347 }; 348 349 /** 350 * struct dp_tx_desc_s - Tx Descriptor 351 * @next: Next in the chain of descriptors in freelist or in the completion list 352 * @nbuf: Buffer Address 353 * @msdu_ext_desc: MSDU extension descriptor 354 * @id: Descriptor ID 355 * @vdev: vdev over which the packet was transmitted 356 * @pdev: Handle to pdev 357 * @pool_id: Pool ID - used when releasing the descriptor 358 * @flags: Flags to track the state of descriptor and special frame handling 359 * @comp: Pool ID - used when releasing the descriptor 360 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 361 * This is maintained in descriptor to allow more efficient 362 * processing in completion event processing code. 363 * This field is filled in with the htt_pkt_type enum. 364 * @frm_type: Frame Type - ToDo check if this is redundant 365 * @pkt_offset: Offset from which the actual packet data starts 366 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 367 * Tx completion of ME packet 368 * @pool: handle to flow_pool this descriptor belongs to. 369 */ 370 struct dp_tx_desc_s { 371 struct dp_tx_desc_s *next; 372 qdf_nbuf_t nbuf; 373 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 374 uint32_t id; 375 struct dp_vdev *vdev; 376 struct dp_pdev *pdev; 377 uint8_t pool_id; 378 uint16_t flags; 379 struct hal_tx_desc_comp_s comp; 380 uint16_t tx_encap_type; 381 uint8_t frm_type; 382 uint8_t pkt_offset; 383 void *me_buffer; 384 void *tso_desc; 385 void *tso_num_desc; 386 uint64_t timestamp; 387 }; 388 389 /** 390 * enum flow_pool_status - flow pool status 391 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 392 * and network queues are unpaused 393 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 394 * and network queues are paused 395 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 396 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 397 */ 398 enum flow_pool_status { 399 FLOW_POOL_ACTIVE_UNPAUSED = 0, 400 FLOW_POOL_ACTIVE_PAUSED = 1, 401 FLOW_POOL_BE_BK_PAUSED = 2, 402 FLOW_POOL_VI_PAUSED = 3, 403 FLOW_POOL_VO_PAUSED = 4, 404 FLOW_POOL_INVALID = 5, 405 FLOW_POOL_INACTIVE = 6, 406 }; 407 408 /** 409 * struct dp_tx_tso_seg_pool_s 410 * @pool_size: total number of pool elements 411 * @num_free: free element count 412 * @freelist: first free element pointer 413 * @desc_pages: multiple page allocation information for actual descriptors 414 * @lock: lock for accessing the pool 415 */ 416 struct dp_tx_tso_seg_pool_s { 417 uint16_t pool_size; 418 uint16_t num_free; 419 struct qdf_tso_seg_elem_t *freelist; 420 struct qdf_mem_multi_page_t desc_pages; 421 qdf_spinlock_t lock; 422 }; 423 424 /** 425 * struct dp_tx_tso_num_seg_pool_s { 426 * @num_seg_pool_size: total number of pool elements 427 * @num_free: free element count 428 * @freelist: first free element pointer 429 * @desc_pages: multiple page allocation information for actual descriptors 430 * @lock: lock for accessing the pool 431 */ 432 433 struct dp_tx_tso_num_seg_pool_s { 434 uint16_t num_seg_pool_size; 435 uint16_t num_free; 436 struct qdf_tso_num_seg_elem_t *freelist; 437 struct qdf_mem_multi_page_t desc_pages; 438 /*tso mutex */ 439 qdf_spinlock_t lock; 440 }; 441 442 /** 443 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 444 * @elem_size: Size of each descriptor in the pool 445 * @pool_size: Total number of descriptors in the pool 446 * @num_free: Number of free descriptors 447 * @num_allocated: Number of used descriptors 448 * @freelist: Chain of free descriptors 449 * @desc_pages: multiple page allocation information for actual descriptors 450 * @num_invalid_bin: Deleted pool with pending Tx completions. 451 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 452 * @flow_pool_array: List of allocated flow pools 453 * @lock- Lock for descriptor allocation/free from/to the pool 454 */ 455 struct dp_tx_desc_pool_s { 456 uint16_t elem_size; 457 uint32_t num_allocated; 458 struct dp_tx_desc_s *freelist; 459 struct qdf_mem_multi_page_t desc_pages; 460 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 461 uint16_t pool_size; 462 uint8_t flow_pool_id; 463 uint8_t num_invalid_bin; 464 uint16_t avail_desc; 465 enum flow_pool_status status; 466 enum htt_flow_type flow_type; 467 #ifdef QCA_AC_BASED_FLOW_CONTROL 468 uint16_t stop_th[FL_TH_MAX]; 469 uint16_t start_th[FL_TH_MAX]; 470 qdf_time_t max_pause_time[FL_TH_MAX]; 471 qdf_time_t latest_pause_time[FL_TH_MAX]; 472 #else 473 uint16_t stop_th; 474 uint16_t start_th; 475 #endif 476 uint16_t pkt_drop_no_desc; 477 qdf_spinlock_t flow_pool_lock; 478 uint8_t pool_create_cnt; 479 void *pool_owner_ctx; 480 #else 481 uint16_t elem_count; 482 uint32_t num_free; 483 qdf_spinlock_t lock; 484 #endif 485 }; 486 487 /** 488 * struct dp_txrx_pool_stats - flow pool related statistics 489 * @pool_map_count: flow pool map received 490 * @pool_unmap_count: flow pool unmap received 491 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 492 */ 493 struct dp_txrx_pool_stats { 494 uint16_t pool_map_count; 495 uint16_t pool_unmap_count; 496 uint16_t pkt_drop_no_pool; 497 }; 498 499 struct dp_srng { 500 hal_ring_handle_t hal_srng; 501 void *base_vaddr_unaligned; 502 qdf_dma_addr_t base_paddr_unaligned; 503 uint32_t alloc_size; 504 uint8_t cached; 505 int irq; 506 uint32_t num_entries; 507 }; 508 509 struct dp_rx_reorder_array_elem { 510 qdf_nbuf_t head; 511 qdf_nbuf_t tail; 512 }; 513 514 #define DP_RX_BA_INACTIVE 0 515 #define DP_RX_BA_ACTIVE 1 516 #define DP_RX_BA_IN_PROGRESS 2 517 struct dp_reo_cmd_info { 518 uint16_t cmd; 519 enum hal_reo_cmd_type cmd_type; 520 void *data; 521 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 522 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 523 }; 524 525 /* Rx TID */ 526 struct dp_rx_tid { 527 /* TID */ 528 int tid; 529 530 /* Num of addba requests */ 531 uint32_t num_of_addba_req; 532 533 /* Num of addba responses */ 534 uint32_t num_of_addba_resp; 535 536 /* Num of delba requests */ 537 uint32_t num_of_delba_req; 538 539 /* Num of addba responses successful */ 540 uint32_t num_addba_rsp_success; 541 542 /* Num of addba responses failed */ 543 uint32_t num_addba_rsp_failed; 544 545 /* pn size */ 546 uint8_t pn_size; 547 /* REO TID queue descriptors */ 548 void *hw_qdesc_vaddr_unaligned; 549 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 550 qdf_dma_addr_t hw_qdesc_paddr; 551 uint32_t hw_qdesc_alloc_size; 552 553 /* RX ADDBA session state */ 554 int ba_status; 555 556 /* RX BA window size */ 557 uint16_t ba_win_size; 558 559 /* Starting sequence number in Addba request */ 560 uint16_t startseqnum; 561 562 /* TODO: Check the following while adding defragmentation support */ 563 struct dp_rx_reorder_array_elem *array; 564 /* base - single rx reorder element used for non-aggr cases */ 565 struct dp_rx_reorder_array_elem base; 566 567 /* only used for defrag right now */ 568 TAILQ_ENTRY(dp_rx_tid) defrag_waitlist_elem; 569 570 /* Store dst desc for reinjection */ 571 hal_ring_desc_t dst_ring_desc; 572 struct dp_rx_desc *head_frag_desc; 573 574 /* rx_tid lock */ 575 qdf_spinlock_t tid_lock; 576 577 /* Sequence and fragments that are being processed currently */ 578 uint32_t curr_seq_num; 579 uint32_t curr_frag_num; 580 581 uint32_t defrag_timeout_ms; 582 uint16_t dialogtoken; 583 uint16_t statuscode; 584 /* user defined ADDBA response status code */ 585 uint16_t userstatuscode; 586 587 /* Store ppdu_id when 2k exception is received */ 588 uint32_t ppdu_id_2k; 589 590 /* Delba Tx completion status */ 591 uint8_t delba_tx_status; 592 593 /* Delba Tx retry count */ 594 uint8_t delba_tx_retry; 595 596 /* Delba stats */ 597 uint32_t delba_tx_success_cnt; 598 uint32_t delba_tx_fail_cnt; 599 600 /* Delba reason code for retries */ 601 uint8_t delba_rcode; 602 603 }; 604 605 /** 606 * struct dp_intr_stats - DP Interrupt Stats for an interrupt context 607 * @num_tx_ring_masks: interrupts with tx_ring_mask set 608 * @num_rx_ring_masks: interrupts with rx_ring_mask set 609 * @num_rx_mon_ring_masks: interrupts with rx_mon_ring_mask set 610 * @num_rx_err_ring_masks: interrupts with rx_err_ring_mask set 611 * @num_rx_wbm_rel_ring_masks: interrupts with rx_wbm_rel_ring_mask set 612 * @num_reo_status_ring_masks: interrupts with reo_status_ring_mask set 613 * @num_rxdma2host_ring_masks: interrupts with rxdma2host_ring_mask set 614 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 615 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 616 * @num_masks: total number of times the interrupt was received 617 * 618 * Counter for individual masks are incremented only if there are any packets 619 * on that ring. 620 */ 621 struct dp_intr_stats { 622 uint32_t num_tx_ring_masks[MAX_TCL_DATA_RINGS]; 623 uint32_t num_rx_ring_masks[MAX_REO_DEST_RINGS]; 624 uint32_t num_rx_mon_ring_masks; 625 uint32_t num_rx_err_ring_masks; 626 uint32_t num_rx_wbm_rel_ring_masks; 627 uint32_t num_reo_status_ring_masks; 628 uint32_t num_rxdma2host_ring_masks; 629 uint32_t num_host2rxdma_ring_masks; 630 uint32_t num_masks; 631 }; 632 633 /* per interrupt context */ 634 struct dp_intr { 635 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 636 associated with this napi context */ 637 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 638 with this interrupt context */ 639 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 640 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 641 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 642 uint8_t reo_status_ring_mask; /* REO command response ring */ 643 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 644 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 645 /* Host to RXDMA monitor buffer ring */ 646 uint8_t host2rxdma_mon_ring_mask; 647 struct dp_soc *soc; /* Reference to SoC structure , 648 to get DMA ring handles */ 649 qdf_lro_ctx_t lro_ctx; 650 uint8_t dp_intr_id; 651 652 /* Interrupt Stats for individual masks */ 653 struct dp_intr_stats intr_stats; 654 }; 655 656 #define REO_DESC_FREELIST_SIZE 64 657 #define REO_DESC_FREE_DEFER_MS 1000 658 struct reo_desc_list_node { 659 qdf_list_node_t node; 660 unsigned long free_ts; 661 struct dp_rx_tid rx_tid; 662 bool resend_update_reo_cmd; 663 }; 664 665 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 666 /** 667 * struct reo_cmd_event_record: Elements to record for each reo command 668 * @cmd_type: reo command type 669 * @cmd_return_status: reo command post status 670 * @timestamp: record timestamp for the reo command 671 */ 672 struct reo_cmd_event_record { 673 enum hal_reo_cmd_type cmd_type; 674 uint8_t cmd_return_status; 675 uint32_t timestamp; 676 }; 677 678 /** 679 * struct reo_cmd_event_history: Account for reo cmd events 680 * @index: record number 681 * @cmd_record: list of records 682 */ 683 struct reo_cmd_event_history { 684 qdf_atomic_t index; 685 struct reo_cmd_event_record cmd_record[REO_CMD_EVENT_HIST_MAX]; 686 }; 687 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 688 689 /* SoC level data path statistics */ 690 struct dp_soc_stats { 691 struct { 692 uint32_t added; 693 uint32_t deleted; 694 uint32_t aged_out; 695 uint32_t map_err; 696 } ast; 697 698 /* SOC level TX stats */ 699 struct { 700 /* packets dropped on tx because of no peer */ 701 struct cdp_pkt_info tx_invalid_peer; 702 /* descriptors in each tcl ring */ 703 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 704 /* Descriptors in use at soc */ 705 uint32_t desc_in_use; 706 /* tqm_release_reason == FW removed */ 707 uint32_t dropped_fw_removed; 708 /* tx completion release_src != TQM or FW */ 709 uint32_t invalid_release_source; 710 /* tx completion wbm_internal_error */ 711 uint32_t wbm_internal_error[MAX_WBM_INT_ERROR_REASONS]; 712 /* tx completion non_wbm_internal_error */ 713 uint32_t non_wbm_internal_err; 714 /* TX Comp loop packet limit hit */ 715 uint32_t tx_comp_loop_pkt_limit_hit; 716 /* Head pointer Out of sync at the end of dp_tx_comp_handler */ 717 uint32_t hp_oos2; 718 } tx; 719 720 /* SOC level RX stats */ 721 struct { 722 /* Rx errors */ 723 /* Total Packets in Rx Error ring */ 724 uint32_t err_ring_pkts; 725 /* No of Fragments */ 726 uint32_t rx_frags; 727 /* No of incomplete fragments in waitlist */ 728 uint32_t rx_frag_wait; 729 /* Fragments dropped due to errors */ 730 uint32_t rx_frag_err; 731 /* Fragments dropped due to len errors in skb */ 732 uint32_t rx_frag_err_len_error; 733 /* Fragments dropped due to no peer found */ 734 uint32_t rx_frag_err_no_peer; 735 /* No of reinjected packets */ 736 uint32_t reo_reinject; 737 /* Reap loop packet limit hit */ 738 uint32_t reap_loop_pkt_limit_hit; 739 /* Head pointer Out of sync at the end of dp_rx_process */ 740 uint32_t hp_oos2; 741 /* Rx ring near full */ 742 uint32_t near_full; 743 /* Break ring reaping as not all scattered msdu received */ 744 uint32_t msdu_scatter_wait_break; 745 746 struct { 747 /* Invalid RBM error count */ 748 uint32_t invalid_rbm; 749 /* Invalid VDEV Error count */ 750 uint32_t invalid_vdev; 751 /* Invalid PDEV error count */ 752 uint32_t invalid_pdev; 753 754 /* Packets delivered to stack that no related peer */ 755 uint32_t pkt_delivered_no_peer; 756 /* Defrag peer uninit error count */ 757 uint32_t defrag_peer_uninit; 758 /* Invalid sa_idx or da_idx*/ 759 uint32_t invalid_sa_da_idx; 760 /* MSDU DONE failures */ 761 uint32_t msdu_done_fail; 762 /* Invalid PEER Error count */ 763 struct cdp_pkt_info rx_invalid_peer; 764 /* Invalid PEER ID count */ 765 struct cdp_pkt_info rx_invalid_peer_id; 766 /* Invalid packet length */ 767 struct cdp_pkt_info rx_invalid_pkt_len; 768 /* HAL ring access Fail error count */ 769 uint32_t hal_ring_access_fail; 770 /* RX DMA error count */ 771 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 772 /* RX REO DEST Desc Invalid Magic count */ 773 uint32_t rx_desc_invalid_magic; 774 /* REO Error count */ 775 uint32_t reo_error[HAL_REO_ERR_MAX]; 776 /* HAL REO ERR Count */ 777 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 778 /* HAL REO DEST Duplicate count */ 779 uint32_t hal_reo_dest_dup; 780 /* HAL WBM RELEASE Duplicate count */ 781 uint32_t hal_wbm_rel_dup; 782 /* HAL RXDMA error Duplicate count */ 783 uint32_t hal_rxdma_err_dup; 784 /* REO cmd send fail/requeue count */ 785 uint32_t reo_cmd_send_fail; 786 /* RX msdu drop count due to scatter */ 787 uint32_t scatter_msdu; 788 } err; 789 790 /* packet count per core - per ring */ 791 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 792 } rx; 793 794 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 795 struct reo_cmd_event_history cmd_event_history; 796 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 797 }; 798 799 union dp_align_mac_addr { 800 uint8_t raw[QDF_MAC_ADDR_SIZE]; 801 struct { 802 uint16_t bytes_ab; 803 uint16_t bytes_cd; 804 uint16_t bytes_ef; 805 } align2; 806 struct { 807 uint32_t bytes_abcd; 808 uint16_t bytes_ef; 809 } align4; 810 struct __attribute__((__packed__)) { 811 uint16_t bytes_ab; 812 uint32_t bytes_cdef; 813 } align4_2; 814 }; 815 816 /** 817 * struct dp_ast_free_cb_params - HMWDS free callback cookie 818 * @mac_addr: ast mac address 819 * @peer_mac_addr: mac address of peer 820 * @type: ast entry type 821 * @vdev_id: vdev_id 822 * @flags: ast flags 823 */ 824 struct dp_ast_free_cb_params { 825 union dp_align_mac_addr mac_addr; 826 union dp_align_mac_addr peer_mac_addr; 827 enum cdp_txrx_ast_entry_type type; 828 uint8_t vdev_id; 829 uint32_t flags; 830 }; 831 832 /* 833 * dp_ast_entry 834 * 835 * @ast_idx: Hardware AST Index 836 * @mac_addr: MAC Address for this AST entry 837 * @peer: Next Hop peer (for non-WDS nodes, this will be point to 838 * associated peer with this MAC address) 839 * @next_hop: Set to 1 if this is for a WDS node 840 * @is_active: flag to indicate active data traffic on this node 841 * (used for aging out/expiry) 842 * @ase_list_elem: node in peer AST list 843 * @is_bss: flag to indicate if entry corresponds to bss peer 844 * @is_mapped: flag to indicate that we have mapped the AST entry 845 * in ast_table 846 * @pdev_id: pdev ID 847 * @vdev_id: vdev ID 848 * @ast_hash_value: hast value in HW 849 * @ref_cnt: reference count 850 * @type: flag to indicate type of the entry(static/WDS/MEC) 851 * @delete_in_progress: Flag to indicate that delete commands send to FW 852 * and host is waiting for response from FW 853 * @callback: ast free/unmap callback 854 * @cookie: argument to callback 855 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 856 */ 857 struct dp_ast_entry { 858 uint16_t ast_idx; 859 union dp_align_mac_addr mac_addr; 860 struct dp_peer *peer; 861 bool next_hop; 862 bool is_active; 863 bool is_mapped; 864 uint8_t pdev_id; 865 uint16_t ast_hash_value; 866 qdf_atomic_t ref_cnt; 867 enum cdp_txrx_ast_entry_type type; 868 bool delete_in_progress; 869 txrx_ast_free_cb callback; 870 void *cookie; 871 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 872 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 873 }; 874 875 /* SOC level htt stats */ 876 struct htt_t2h_stats { 877 /* lock to protect htt_stats_msg update */ 878 qdf_spinlock_t lock; 879 880 /* work queue to process htt stats */ 881 qdf_work_t work; 882 883 /* T2H Ext stats message queue */ 884 qdf_nbuf_queue_t msg; 885 886 /* number of completed stats in htt_stats_msg */ 887 uint32_t num_stats; 888 }; 889 890 /* SOC level structure for data path */ 891 struct dp_soc { 892 /** 893 * re-use memory section starts 894 */ 895 896 /* Common base structure - Should be the first member */ 897 struct cdp_soc_t cdp_soc; 898 899 /* SoC Obj */ 900 struct cdp_ctrl_objmgr_psoc *ctrl_psoc; 901 902 /* OS device abstraction */ 903 qdf_device_t osdev; 904 905 /* WLAN config context */ 906 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 907 908 /* HTT handle for host-fw interaction */ 909 struct htt_soc *htt_handle; 910 911 /* Commint init done */ 912 qdf_atomic_t cmn_init_done; 913 914 /* Opaque hif handle */ 915 struct hif_opaque_softc *hif_handle; 916 917 /* PDEVs on this SOC */ 918 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 919 920 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 921 struct dp_srng rx_refill_buf_ring[MAX_PDEV_CNT]; 922 923 struct dp_srng rxdma_mon_desc_ring[MAX_NUM_LMAC_HW]; 924 925 /* RXDMA error destination ring */ 926 struct dp_srng rxdma_err_dst_ring[MAX_NUM_LMAC_HW]; 927 928 /* Link descriptor memory banks */ 929 struct { 930 void *base_vaddr_unaligned; 931 void *base_vaddr; 932 qdf_dma_addr_t base_paddr_unaligned; 933 qdf_dma_addr_t base_paddr; 934 uint32_t size; 935 } mon_link_desc_banks[MAX_NUM_LMAC_HW][MAX_MON_LINK_DESC_BANKS]; 936 937 /* RXDMA monitor buffer replenish ring */ 938 struct dp_srng rxdma_mon_buf_ring[MAX_NUM_LMAC_HW]; 939 940 /* RXDMA monitor destination ring */ 941 struct dp_srng rxdma_mon_dst_ring[MAX_NUM_LMAC_HW]; 942 943 /* RXDMA monitor status ring. TBD: Check format of this ring */ 944 struct dp_srng rxdma_mon_status_ring[MAX_NUM_LMAC_HW]; 945 946 /* Number of PDEVs */ 947 uint8_t pdev_count; 948 949 /*cce disable*/ 950 bool cce_disable; 951 952 /*ast override support in HW*/ 953 bool ast_override_support; 954 955 /*number of hw dscp tid map*/ 956 uint8_t num_hw_dscp_tid_map; 957 958 /* HAL SOC handle */ 959 hal_soc_handle_t hal_soc; 960 961 /* Device ID coming from Bus sub-system */ 962 uint32_t device_id; 963 964 /* Link descriptor memory banks */ 965 struct { 966 void *base_vaddr_unaligned; 967 void *base_vaddr; 968 qdf_dma_addr_t base_paddr_unaligned; 969 qdf_dma_addr_t base_paddr; 970 uint32_t size; 971 } link_desc_banks[MAX_LINK_DESC_BANKS]; 972 973 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 974 struct dp_srng wbm_idle_link_ring; 975 976 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 977 */ 978 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 979 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 980 981 /* Tx SW descriptor pool */ 982 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 983 984 /* Tx MSDU Extension descriptor pool */ 985 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 986 987 /* Tx TSO descriptor pool */ 988 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 989 990 /* Tx TSO Num of segments pool */ 991 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 992 993 /* REO destination rings */ 994 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 995 996 /* REO exception ring - See if should combine this with reo_dest_ring */ 997 struct dp_srng reo_exception_ring; 998 999 /* REO reinjection ring */ 1000 struct dp_srng reo_reinject_ring; 1001 1002 /* REO command ring */ 1003 struct dp_srng reo_cmd_ring; 1004 1005 /* REO command status ring */ 1006 struct dp_srng reo_status_ring; 1007 1008 /* WBM Rx release ring */ 1009 struct dp_srng rx_rel_ring; 1010 1011 /* TCL data ring */ 1012 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 1013 1014 /* Number of TCL data rings */ 1015 uint8_t num_tcl_data_rings; 1016 1017 /* TCL command ring */ 1018 struct dp_srng tcl_cmd_ring; 1019 1020 /* TCL command status ring */ 1021 struct dp_srng tcl_status_ring; 1022 1023 /* WBM Tx completion rings */ 1024 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 1025 1026 /* Common WBM link descriptor release ring (SW to WBM) */ 1027 struct dp_srng wbm_desc_rel_ring; 1028 1029 /* DP Interrupts */ 1030 struct dp_intr intr_ctx[WLAN_CFG_INT_NUM_CONTEXTS]; 1031 1032 /* Rx SW descriptor pool for RXDMA monitor buffer */ 1033 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 1034 1035 /* Rx SW descriptor pool for RXDMA status buffer */ 1036 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 1037 1038 /* Rx SW descriptor pool for RXDMA buffer */ 1039 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 1040 1041 /* Number of REO destination rings */ 1042 uint8_t num_reo_dest_rings; 1043 1044 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1045 /* lock to control access to soc TX descriptors */ 1046 qdf_spinlock_t flow_pool_array_lock; 1047 1048 /* pause callback to pause TX queues as per flow control */ 1049 tx_pause_callback pause_cb; 1050 1051 /* flow pool related statistics */ 1052 struct dp_txrx_pool_stats pool_stats; 1053 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 1054 1055 /* 1056 * Re-use memory section ends. reuse memory indicator. 1057 * Everything above this variable "dp_soc_reinit" is retained across 1058 * WiFi up/down for AP use-cases. 1059 * Everything below this variable "dp_soc_reinit" is reset during 1060 * dp_soc_deinit. 1061 */ 1062 bool dp_soc_reinit; 1063 1064 uint32_t wbm_idle_scatter_buf_size; 1065 1066 /* VDEVs on this SOC */ 1067 struct dp_vdev *vdev_id_map[MAX_VDEV_CNT]; 1068 1069 /* Tx H/W queues lock */ 1070 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 1071 1072 /* Tx ring map for interrupt processing */ 1073 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 1074 1075 /* Rx ring map for interrupt processing */ 1076 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 1077 1078 /* peer ID to peer object map (array of pointers to peer objects) */ 1079 struct dp_peer **peer_id_to_obj_map; 1080 1081 struct { 1082 unsigned mask; 1083 unsigned idx_bits; 1084 TAILQ_HEAD(, dp_peer) * bins; 1085 } peer_hash; 1086 1087 /* rx defrag state – TBD: do we need this per radio? */ 1088 struct { 1089 struct { 1090 TAILQ_HEAD(, dp_rx_tid) waitlist; 1091 uint32_t timeout_ms; 1092 uint32_t next_flush_ms; 1093 qdf_spinlock_t defrag_lock; 1094 } defrag; 1095 struct { 1096 int defrag_timeout_check; 1097 int dup_check; 1098 } flags; 1099 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 1100 qdf_spinlock_t reo_cmd_lock; 1101 } rx; 1102 1103 /* optional rx processing function */ 1104 void (*rx_opt_proc)( 1105 struct dp_vdev *vdev, 1106 struct dp_peer *peer, 1107 unsigned tid, 1108 qdf_nbuf_t msdu_list); 1109 1110 /* pool addr for mcast enhance buff */ 1111 struct { 1112 int size; 1113 uint32_t paddr; 1114 uint32_t *vaddr; 1115 struct dp_tx_me_buf_t *freelist; 1116 int buf_in_use; 1117 qdf_dma_mem_context(memctx); 1118 } me_buf; 1119 1120 /** 1121 * peer ref mutex: 1122 * 1. Protect peer object lookups until the returned peer object's 1123 * reference count is incremented. 1124 * 2. Provide mutex when accessing peer object lookup structures. 1125 */ 1126 DP_MUTEX_TYPE peer_ref_mutex; 1127 1128 /* maximum value for peer_id */ 1129 uint32_t max_peers; 1130 1131 /* SoC level data path statistics */ 1132 struct dp_soc_stats stats; 1133 1134 /* Enable processing of Tx completion status words */ 1135 bool process_tx_status; 1136 bool process_rx_status; 1137 struct dp_ast_entry **ast_table; 1138 struct { 1139 unsigned mask; 1140 unsigned idx_bits; 1141 TAILQ_HEAD(, dp_ast_entry) * bins; 1142 } ast_hash; 1143 1144 qdf_spinlock_t ast_lock; 1145 /*Timer for AST entry ageout maintainance */ 1146 qdf_timer_t ast_aging_timer; 1147 1148 /*Timer counter for WDS AST entry ageout*/ 1149 uint8_t wds_ast_aging_timer_cnt; 1150 1151 /*interrupt timer*/ 1152 qdf_timer_t mon_reap_timer; 1153 uint8_t reap_timer_init; 1154 qdf_timer_t lmac_reap_timer; 1155 uint8_t lmac_timer_init; 1156 qdf_timer_t int_timer; 1157 uint8_t intr_mode; 1158 uint8_t lmac_polled_mode; 1159 1160 qdf_list_t reo_desc_freelist; 1161 qdf_spinlock_t reo_desc_freelist_lock; 1162 1163 /* htt stats */ 1164 struct htt_t2h_stats htt_stats; 1165 1166 void *external_txrx_handle; /* External data path handle */ 1167 #ifdef IPA_OFFLOAD 1168 /* IPA uC datapath offload Wlan Tx resources */ 1169 struct { 1170 /* Resource info to be passed to IPA */ 1171 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 1172 void *ipa_tcl_ring_base_vaddr; 1173 uint32_t ipa_tcl_ring_size; 1174 qdf_dma_addr_t ipa_tcl_hp_paddr; 1175 uint32_t alloc_tx_buf_cnt; 1176 1177 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 1178 void *ipa_wbm_ring_base_vaddr; 1179 uint32_t ipa_wbm_ring_size; 1180 qdf_dma_addr_t ipa_wbm_tp_paddr; 1181 1182 /* TX buffers populated into the WBM ring */ 1183 void **tx_buf_pool_vaddr_unaligned; 1184 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 1185 } ipa_uc_tx_rsc; 1186 1187 /* IPA uC datapath offload Wlan Rx resources */ 1188 struct { 1189 /* Resource info to be passed to IPA */ 1190 qdf_dma_addr_t ipa_reo_ring_base_paddr; 1191 void *ipa_reo_ring_base_vaddr; 1192 uint32_t ipa_reo_ring_size; 1193 qdf_dma_addr_t ipa_reo_tp_paddr; 1194 1195 /* Resource info to be passed to firmware and IPA */ 1196 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 1197 void *ipa_rx_refill_buf_ring_base_vaddr; 1198 uint32_t ipa_rx_refill_buf_ring_size; 1199 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 1200 } ipa_uc_rx_rsc; 1201 1202 qdf_atomic_t ipa_pipes_enabled; 1203 bool ipa_first_tx_db_access; 1204 #endif 1205 1206 #ifdef WLAN_FEATURE_STATS_EXT 1207 struct { 1208 uint32_t rx_mpdu_received; 1209 uint32_t rx_mpdu_missed; 1210 } ext_stats; 1211 qdf_event_t rx_hw_stats_event; 1212 1213 /* Ignore reo command queue status during peer delete */ 1214 bool ignore_reo_status_cb; 1215 #endif 1216 1217 /* Smart monitor capability for HKv2 */ 1218 uint8_t hw_nac_monitor_support; 1219 /* Flag to indicate if HTT v2 is enabled*/ 1220 bool is_peer_map_unmap_v2; 1221 /* Per peer per Tid ba window size support */ 1222 uint8_t per_tid_basize_max_tid; 1223 /* Soc level flag to enable da_war */ 1224 uint8_t da_war_enabled; 1225 /* number of active ast entries */ 1226 uint32_t num_ast_entries; 1227 /* rdk rate statistics context at soc level*/ 1228 struct cdp_soc_rate_stats_ctx *rate_stats_ctx; 1229 /* rdk rate statistics control flag */ 1230 bool wlanstats_enabled; 1231 1232 /* 8021p PCP-TID map values */ 1233 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 1234 /* TID map priority value */ 1235 uint8_t tidmap_prty; 1236 /* Pointer to global per ring type specific configuration table */ 1237 struct wlan_srng_cfg *wlan_srng_cfg; 1238 /* Num Tx outstanding on device */ 1239 qdf_atomic_t num_tx_outstanding; 1240 /* Num Tx allowed */ 1241 uint32_t num_tx_allowed; 1242 1243 /** 1244 * Flag to indicate whether WAR to address single cache entry 1245 * invalidation bug is enabled or not 1246 */ 1247 bool is_rx_fse_full_cache_invalidate_war_enabled; 1248 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 1249 /** 1250 * Pointer to DP RX Flow FST at SOC level if 1251 * is_rx_flow_search_table_per_pdev is false 1252 */ 1253 struct dp_rx_fst *rx_fst; 1254 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 1255 }; 1256 1257 #ifdef IPA_OFFLOAD 1258 /** 1259 * dp_ipa_resources - Resources needed for IPA 1260 */ 1261 struct dp_ipa_resources { 1262 qdf_shared_mem_t tx_ring; 1263 uint32_t tx_num_alloc_buffer; 1264 1265 qdf_shared_mem_t tx_comp_ring; 1266 qdf_shared_mem_t rx_rdy_ring; 1267 qdf_shared_mem_t rx_refill_ring; 1268 1269 /* IPA UC doorbell registers paddr */ 1270 qdf_dma_addr_t tx_comp_doorbell_paddr; 1271 uint32_t *tx_comp_doorbell_vaddr; 1272 qdf_dma_addr_t rx_ready_doorbell_paddr; 1273 }; 1274 #endif 1275 1276 #define MAX_RX_MAC_RINGS 2 1277 /* Same as NAC_MAX_CLENT */ 1278 #define DP_NAC_MAX_CLIENT 24 1279 1280 /* 1281 * Macros to setup link descriptor cookies - for link descriptors, we just 1282 * need first 3 bits to store bank ID. The remaining bytes will be used set a 1283 * unique ID, which will be useful in debugging 1284 */ 1285 #define LINK_DESC_BANK_ID_MASK 0x7 1286 #define LINK_DESC_ID_SHIFT 3 1287 #define LINK_DESC_ID_START 0x8000 1288 1289 #define LINK_DESC_COOKIE(_desc_id, _bank_id) \ 1290 ((((_desc_id) + LINK_DESC_ID_START) << LINK_DESC_ID_SHIFT) | (_bank_id)) 1291 1292 #define LINK_DESC_COOKIE_BANK_ID(_cookie) \ 1293 ((_cookie) & LINK_DESC_BANK_ID_MASK) 1294 1295 /* same as ieee80211_nac_param */ 1296 enum dp_nac_param_cmd { 1297 /* IEEE80211_NAC_PARAM_ADD */ 1298 DP_NAC_PARAM_ADD = 1, 1299 /* IEEE80211_NAC_PARAM_DEL */ 1300 DP_NAC_PARAM_DEL, 1301 /* IEEE80211_NAC_PARAM_LIST */ 1302 DP_NAC_PARAM_LIST, 1303 }; 1304 1305 /** 1306 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 1307 * @neighbour_peers_macaddr: neighbour peer's mac address 1308 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 1309 * @ast_entry: ast_entry for neighbour peer 1310 * @rssi: rssi value 1311 */ 1312 struct dp_neighbour_peer { 1313 /* MAC address of neighbour's peer */ 1314 union dp_align_mac_addr neighbour_peers_macaddr; 1315 struct dp_vdev *vdev; 1316 struct dp_ast_entry *ast_entry; 1317 uint8_t rssi; 1318 /* node in the list of neighbour's peer */ 1319 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 1320 }; 1321 1322 #ifdef WLAN_TX_PKT_CAPTURE_ENH 1323 #define WLAN_TX_PKT_CAPTURE_ENH 1 1324 #define DP_TX_PPDU_PROC_THRESHOLD 8 1325 #define DP_TX_PPDU_PROC_TIMEOUT 10 1326 #endif 1327 1328 /** 1329 * struct ppdu_info - PPDU Status info descriptor 1330 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 1331 * @sched_cmdid - schedule command id, which will be same in a burst 1332 * @max_ppdu_id - wrap around for ppdu id 1333 * @last_tlv_cnt - Keep track for missing ppdu tlvs 1334 * @last_user - last ppdu processed for user 1335 * @is_ampdu - set if Ampdu aggregate 1336 * @nbuf - ppdu descriptor payload 1337 * @ppdu_desc - ppdu descriptor 1338 * @ppdu_info_list_elem - linked list of ppdu tlvs 1339 * @ppdu_info_queue_elem - Singly linked list (queue) of ppdu tlvs 1340 * @mpdu_compltn_common_tlv - Successful MPDU counter from COMPLTN COMMON tlv 1341 * @mpdu_ack_ba_tlv - Successful MPDU from ACK BA tlv 1342 */ 1343 struct ppdu_info { 1344 uint32_t ppdu_id; 1345 uint32_t sched_cmdid; 1346 uint32_t max_ppdu_id; 1347 uint16_t tlv_bitmap; 1348 uint16_t last_tlv_cnt; 1349 uint16_t last_user:8, 1350 is_ampdu:1; 1351 qdf_nbuf_t nbuf; 1352 struct cdp_tx_completion_ppdu *ppdu_desc; 1353 #ifdef WLAN_TX_PKT_CAPTURE_ENH 1354 union { 1355 TAILQ_ENTRY(ppdu_info) ppdu_info_dlist_elem; 1356 STAILQ_ENTRY(ppdu_info) ppdu_info_slist_elem; 1357 } ulist; 1358 #define ppdu_info_list_elem ulist.ppdu_info_dlist_elem 1359 #define ppdu_info_queue_elem ulist.ppdu_info_slist_elem 1360 #else 1361 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 1362 #endif 1363 uint16_t mpdu_compltn_common_tlv; 1364 uint16_t mpdu_ack_ba_tlv; 1365 }; 1366 1367 /** 1368 * struct msdu_completion_info - wbm msdu completion info 1369 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 1370 * @peer_id - peer_id 1371 * @tid - tid which used during transmit 1372 * @first_msdu - first msdu indication 1373 * @last_msdu - last msdu indication 1374 * @msdu_part_of_amsdu - msdu part of amsdu 1375 * @transmit_cnt - retried count 1376 * @status - transmit status 1377 * @tsf - timestamp which it transmitted 1378 */ 1379 struct msdu_completion_info { 1380 uint32_t ppdu_id; 1381 uint16_t peer_id; 1382 uint8_t tid; 1383 uint8_t first_msdu:1, 1384 last_msdu:1, 1385 msdu_part_of_amsdu:1; 1386 uint8_t transmit_cnt; 1387 uint8_t status; 1388 uint32_t tsf; 1389 }; 1390 1391 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 1392 struct rx_protocol_tag_map { 1393 /* This is the user configured tag for the said protocol type */ 1394 uint16_t tag; 1395 }; 1396 1397 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 1398 struct rx_protocol_tag_stats { 1399 uint32_t tag_ctr; 1400 }; 1401 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 1402 1403 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 1404 1405 #ifndef WLAN_TX_PKT_CAPTURE_ENH 1406 struct dp_pdev_tx_capture { 1407 }; 1408 1409 struct dp_peer_tx_capture { 1410 }; 1411 #endif 1412 #ifdef WLAN_RX_PKT_CAPTURE_ENH 1413 /* Template data to be set for Enhanced RX Monitor packets */ 1414 #define RX_MON_CAP_ENH_TRAILER 0xdeadc0dedeadda7a 1415 1416 /** 1417 * struct dp_rx_mon_enh_trailer_data - Data structure to set a known pattern 1418 * at end of each MSDU in monitor-lite mode 1419 * @reserved1: reserved for future use 1420 * @reserved2: reserved for future use 1421 * @flow_tag: flow tag value read from skb->cb 1422 * @protocol_tag: protocol tag value read from skb->cb 1423 */ 1424 struct dp_rx_mon_enh_trailer_data { 1425 uint16_t reserved1; 1426 uint16_t reserved2; 1427 uint16_t flow_tag; 1428 uint16_t protocol_tag; 1429 }; 1430 #endif /* WLAN_RX_PKT_CAPTURE_ENH */ 1431 1432 /* PDEV level structure for data path */ 1433 struct dp_pdev { 1434 /** 1435 * Re-use Memory Section Starts 1436 */ 1437 1438 /* PDEV Id */ 1439 int pdev_id; 1440 1441 /* LMAC Id */ 1442 int lmac_id; 1443 1444 /* TXRX SOC handle */ 1445 struct dp_soc *soc; 1446 1447 /* Stuck count on monitor destination ring MPDU process */ 1448 uint32_t mon_dest_ring_stuck_cnt; 1449 1450 /* 1451 * re-use memory section ends 1452 * reuse memory/deinit indicator 1453 * 1454 * DO NOT CHANGE NAME OR MOVE THIS VARIABLE 1455 */ 1456 bool pdev_deinit; 1457 1458 /* pdev status down or up required to handle dynamic hw 1459 * mode switch between DBS and DBS_SBS. 1460 * 1 = down 1461 * 0 = up 1462 */ 1463 bool is_pdev_down; 1464 1465 /* Second ring used to replenish rx buffers */ 1466 struct dp_srng rx_refill_buf_ring2; 1467 1468 /* Empty ring used by firmware to post rx buffers to the MAC */ 1469 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 1470 1471 /* wlan_cfg pdev ctxt*/ 1472 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 1473 1474 /** 1475 * TODO: See if we need a ring map here for LMAC rings. 1476 * 1. Monitor rings are currently planning to be processed on receiving 1477 * PPDU end interrupts and hence wont need ring based interrupts. 1478 * 2. Rx buffer rings will be replenished during REO destination 1479 * processing and doesn't require regular interrupt handling - we will 1480 * only handle low water mark interrupts which is not expected 1481 * frequently 1482 */ 1483 1484 /* VDEV list */ 1485 TAILQ_HEAD(, dp_vdev) vdev_list; 1486 1487 /* vdev list lock */ 1488 qdf_spinlock_t vdev_list_lock; 1489 1490 /* Number of vdevs this device have */ 1491 uint16_t vdev_count; 1492 1493 /* PDEV transmit lock */ 1494 qdf_spinlock_t tx_lock; 1495 1496 #ifndef REMOVE_PKT_LOG 1497 bool pkt_log_init; 1498 /* Pktlog pdev */ 1499 struct pktlog_dev_t *pl_dev; 1500 #endif /* #ifndef REMOVE_PKT_LOG */ 1501 1502 /* Monitor mode interface and status storage */ 1503 struct dp_vdev *monitor_vdev; 1504 1505 /* Monitor mode operation channel */ 1506 int mon_chan_num; 1507 1508 /* Monitor mode operation frequency */ 1509 qdf_freq_t mon_chan_freq; 1510 1511 /* monitor mode lock */ 1512 qdf_spinlock_t mon_lock; 1513 1514 /*tx_mutex for me*/ 1515 DP_MUTEX_TYPE tx_mutex; 1516 1517 /* monitor */ 1518 bool monitor_configured; 1519 1520 /* Smart Mesh */ 1521 bool filter_neighbour_peers; 1522 1523 /*flag to indicate neighbour_peers_list not empty */ 1524 bool neighbour_peers_added; 1525 /* smart mesh mutex */ 1526 qdf_spinlock_t neighbour_peer_mutex; 1527 /* Neighnour peer list */ 1528 TAILQ_HEAD(, dp_neighbour_peer) neighbour_peers_list; 1529 /* msdu chain head & tail */ 1530 qdf_nbuf_t invalid_peer_head_msdu; 1531 qdf_nbuf_t invalid_peer_tail_msdu; 1532 1533 /* Band steering */ 1534 /* TBD */ 1535 1536 /* PDEV level data path statistics */ 1537 struct cdp_pdev_stats stats; 1538 1539 /* Global RX decap mode for the device */ 1540 enum htt_pkt_type rx_decap_mode; 1541 1542 /* Enhanced Stats is enabled */ 1543 bool enhanced_stats_en; 1544 1545 /* advance filter mode and type*/ 1546 uint8_t mon_filter_mode; 1547 uint16_t fp_mgmt_filter; 1548 uint16_t fp_ctrl_filter; 1549 uint16_t fp_data_filter; 1550 uint16_t mo_mgmt_filter; 1551 uint16_t mo_ctrl_filter; 1552 uint16_t mo_data_filter; 1553 uint16_t md_data_filter; 1554 1555 qdf_atomic_t num_tx_outstanding; 1556 1557 qdf_atomic_t num_tx_exception; 1558 1559 /* MCL specific local peer handle */ 1560 struct { 1561 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 1562 uint8_t freelist; 1563 qdf_spinlock_t lock; 1564 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 1565 } local_peer_ids; 1566 1567 /* dscp_tid_map_*/ 1568 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 1569 1570 struct hal_rx_ppdu_info ppdu_info; 1571 1572 /* operating channel */ 1573 uint8_t operating_channel; 1574 1575 qdf_nbuf_queue_t rx_status_q; 1576 uint32_t mon_ppdu_status; 1577 struct cdp_mon_status rx_mon_recv_status; 1578 /* monitor mode status/destination ring PPDU and MPDU count */ 1579 struct cdp_pdev_mon_stats rx_mon_stats; 1580 /* to track duplicate link descriptor indications by HW for a WAR */ 1581 uint64_t mon_last_linkdesc_paddr; 1582 /* to track duplicate buffer indications by HW for a WAR */ 1583 uint32_t mon_last_buf_cookie; 1584 /* 128 bytes mpdu header queue per user for ppdu */ 1585 qdf_nbuf_queue_t mpdu_q[MAX_MU_USERS]; 1586 /* is this a mpdu header TLV and not msdu header TLV */ 1587 bool is_mpdu_hdr[MAX_MU_USERS]; 1588 /* per user 128 bytes msdu header list for MPDU */ 1589 struct msdu_list msdu_list[MAX_MU_USERS]; 1590 /* RX enhanced capture mode */ 1591 uint8_t rx_enh_capture_mode; 1592 /* Rx per peer enhanced capture mode */ 1593 bool rx_enh_capture_peer; 1594 struct dp_vdev *rx_enh_monitor_vdev; 1595 /* RX enhanced capture trailer enable/disable flag */ 1596 bool is_rx_enh_capture_trailer_enabled; 1597 #ifdef WLAN_RX_PKT_CAPTURE_ENH 1598 /* RX per MPDU/PPDU information */ 1599 struct cdp_rx_indication_mpdu mpdu_ind; 1600 #endif 1601 /* pool addr for mcast enhance buff */ 1602 struct { 1603 int size; 1604 uint32_t paddr; 1605 char *vaddr; 1606 struct dp_tx_me_buf_t *freelist; 1607 int buf_in_use; 1608 qdf_dma_mem_context(memctx); 1609 } me_buf; 1610 1611 bool hmmc_tid_override_en; 1612 uint8_t hmmc_tid; 1613 1614 /* Number of VAPs with mcast enhancement enabled */ 1615 qdf_atomic_t mc_num_vap_attached; 1616 1617 qdf_atomic_t stats_cmd_complete; 1618 1619 #ifdef IPA_OFFLOAD 1620 ipa_uc_op_cb_type ipa_uc_op_cb; 1621 void *usr_ctxt; 1622 struct dp_ipa_resources ipa_resource; 1623 #endif 1624 1625 /* TBD */ 1626 1627 /* map this pdev to a particular Reo Destination ring */ 1628 enum cdp_host_reo_dest_ring reo_dest; 1629 1630 #ifndef REMOVE_PKT_LOG 1631 /* Packet log mode */ 1632 uint8_t rx_pktlog_mode; 1633 #endif 1634 1635 /* WDI event handlers */ 1636 struct wdi_event_subscribe_t **wdi_event_list; 1637 1638 /* ppdu_id of last received HTT TX stats */ 1639 uint32_t last_ppdu_id; 1640 struct { 1641 uint8_t last_user; 1642 qdf_nbuf_t buf; 1643 } tx_ppdu_info; 1644 1645 bool tx_sniffer_enable; 1646 /* mirror copy mode */ 1647 bool mcopy_mode; 1648 bool cfr_rcc_mode; 1649 bool bpr_enable; 1650 1651 /* enable time latency check for tx completion */ 1652 bool latency_capture_enable; 1653 1654 /* enable calculation of delay stats*/ 1655 bool delay_stats_flag; 1656 struct { 1657 uint16_t tx_ppdu_id; 1658 uint16_t tx_peer_id; 1659 uint16_t rx_ppdu_id; 1660 } m_copy_id; 1661 1662 /* To check if PPDU Tx stats are enabled for Pktlog */ 1663 bool pktlog_ppdu_stats; 1664 1665 void *dp_txrx_handle; /* Advanced data path handle */ 1666 1667 #ifdef ATH_SUPPORT_NAC_RSSI 1668 bool nac_rssi_filtering; 1669 #endif 1670 /* list of ppdu tlvs */ 1671 TAILQ_HEAD(, ppdu_info) ppdu_info_list; 1672 uint32_t tlv_count; 1673 uint32_t list_depth; 1674 uint32_t ppdu_id; 1675 bool first_nbuf; 1676 struct { 1677 qdf_nbuf_t last_nbuf; /*Ptr to mgmt last buf */ 1678 uint8_t *mgmt_buf; /* Ptr to mgmt. payload in HTT ppdu stats */ 1679 uint32_t mgmt_buf_len; /* Len of mgmt. payload in ppdu stats */ 1680 uint32_t ppdu_id; 1681 } mgmtctrl_frm_info; 1682 1683 /* Current noise-floor reading for the pdev channel */ 1684 int16_t chan_noise_floor; 1685 1686 /* 1687 * For multiradio device, this flag indicates if 1688 * this radio is primary or secondary. 1689 * 1690 * For HK 1.0, this is used for WAR for the AST issue. 1691 * HK 1.x mandates creation of only 1 AST entry with same MAC address 1692 * across 2 radios. is_primary indicates the radio on which DP should 1693 * install HW AST entry if there is a request to add 2 AST entries 1694 * with same MAC address across 2 radios 1695 */ 1696 uint8_t is_primary; 1697 /* Context of cal client timer */ 1698 struct cdp_cal_client *cal_client_ctx; 1699 struct cdp_tx_sojourn_stats sojourn_stats; 1700 qdf_nbuf_t sojourn_buf; 1701 1702 /* peer pointer for collecting invalid peer stats */ 1703 struct dp_peer *invalid_peer; 1704 1705 union dp_rx_desc_list_elem_t *free_list_head; 1706 union dp_rx_desc_list_elem_t *free_list_tail; 1707 /* Pdev level flag to check peer based pktlog enabled or 1708 * disabled 1709 */ 1710 uint8_t dp_peer_based_pktlog; 1711 1712 /* Cached peer_id from htt_peer_details_tlv */ 1713 uint16_t fw_stats_peer_id; 1714 1715 /* qdf_event for fw_peer_stats */ 1716 qdf_event_t fw_peer_stats_event; 1717 1718 /* User configured max number of tx buffers */ 1719 uint32_t num_tx_allowed; 1720 1721 /* unique cookie required for peer session */ 1722 uint32_t next_peer_cookie; 1723 1724 /* 1725 * Run time enabled when the first protocol tag is added, 1726 * run time disabled when the last protocol tag is deleted 1727 */ 1728 bool is_rx_protocol_tagging_enabled; 1729 1730 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 1731 /* 1732 * The protocol type is used as array index to save 1733 * user provided tag info 1734 */ 1735 struct rx_protocol_tag_map rx_proto_tag_map[RX_PROTOCOL_TAG_MAX]; 1736 1737 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 1738 /* 1739 * Track msdus received from each reo ring separately to avoid 1740 * simultaneous writes from different core 1741 */ 1742 struct rx_protocol_tag_stats 1743 reo_proto_tag_stats[MAX_REO_DEST_RINGS][RX_PROTOCOL_TAG_MAX]; 1744 /* Track msdus received from expection ring separately */ 1745 struct rx_protocol_tag_stats 1746 rx_err_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 1747 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 1748 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 1749 1750 /* tx packet capture enhancement */ 1751 enum cdp_tx_enh_capture_mode tx_capture_enabled; 1752 struct dp_pdev_tx_capture tx_capture; 1753 /* stats counter for tx ppdu processed */ 1754 uint64_t tx_ppdu_proc; 1755 1756 uint32_t *ppdu_tlv_buf; /* Buffer to hold HTT ppdu stats TLVs*/ 1757 1758 /* nbuf queue to maintain rx ppdu status buffer 1759 * belonging to one ppdu 1760 */ 1761 qdf_nbuf_queue_t rx_ppdu_buf_q; 1762 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 1763 /** 1764 * Pointer to DP Flow FST at SOC level if 1765 * is_rx_flow_search_table_per_pdev is true 1766 */ 1767 struct dp_rx_fst *rx_fst; 1768 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 1769 1770 #ifdef FEATURE_TSO_STATS 1771 /* TSO Id to index into TSO packet information */ 1772 qdf_atomic_t tso_idx; 1773 #endif /* FEATURE_TSO_STATS */ 1774 1775 #ifdef WLAN_SUPPORT_DATA_STALL 1776 data_stall_detect_cb data_stall_detect_callback; 1777 #endif /* WLAN_SUPPORT_DATA_STALL */ 1778 1779 struct dp_mon_filter **filter; /* Monitor Filter pointer */ 1780 }; 1781 1782 struct dp_peer; 1783 1784 /* VDEV structure for data path state */ 1785 struct dp_vdev { 1786 /* OS device abstraction */ 1787 qdf_device_t osdev; 1788 /* physical device that is the parent of this virtual device */ 1789 struct dp_pdev *pdev; 1790 1791 /* Handle to the OS shim SW's virtual device */ 1792 ol_osif_vdev_handle osif_vdev; 1793 1794 /* vdev_id - ID used to specify a particular vdev to the target */ 1795 uint8_t vdev_id; 1796 1797 /* MAC address */ 1798 union dp_align_mac_addr mac_addr; 1799 1800 /* node in the pdev's list of vdevs */ 1801 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 1802 1803 /* dp_peer list */ 1804 TAILQ_HEAD(, dp_peer) peer_list; 1805 1806 /* RX call back function to flush GRO packets*/ 1807 ol_txrx_rx_gro_flush_ind_fp osif_gro_flush; 1808 /* default RX call back function called by dp */ 1809 ol_txrx_rx_fp osif_rx; 1810 /* callback to deliver rx frames to the OS */ 1811 ol_txrx_rx_fp osif_rx_stack; 1812 /* call back function to flush out queued rx packets*/ 1813 ol_txrx_rx_flush_fp osif_rx_flush; 1814 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 1815 ol_txrx_get_key_fp osif_get_key; 1816 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 1817 1818 #ifdef notyet 1819 /* callback to check if the msdu is an WAI (WAPI) frame */ 1820 ol_rx_check_wai_fp osif_check_wai; 1821 #endif 1822 1823 /* proxy arp function */ 1824 ol_txrx_proxy_arp_fp osif_proxy_arp; 1825 1826 /* callback to hand rx monitor 802.11 MPDU to the OS shim */ 1827 ol_txrx_rx_mon_fp osif_rx_mon; 1828 1829 ol_txrx_mcast_me_fp me_convert; 1830 1831 /* completion function used by this vdev*/ 1832 ol_txrx_completion_fp tx_comp; 1833 1834 /* deferred vdev deletion state */ 1835 struct { 1836 /* VDEV delete pending */ 1837 int pending; 1838 /* 1839 * callback and a context argument to provide a 1840 * notification for when the vdev is deleted. 1841 */ 1842 ol_txrx_vdev_delete_cb callback; 1843 void *context; 1844 } delete; 1845 1846 /* tx data delivery notification callback function */ 1847 struct { 1848 ol_txrx_data_tx_cb func; 1849 void *ctxt; 1850 } tx_non_std_data_callback; 1851 1852 1853 /* safe mode control to bypass the encrypt and decipher process*/ 1854 uint32_t safemode; 1855 1856 /* rx filter related */ 1857 uint32_t drop_unenc; 1858 #ifdef notyet 1859 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 1860 uint32_t filters_num; 1861 #endif 1862 /* TDLS Link status */ 1863 bool tdls_link_connected; 1864 bool is_tdls_frame; 1865 1866 1867 /* VDEV operating mode */ 1868 enum wlan_op_mode opmode; 1869 1870 /* VDEV subtype */ 1871 enum wlan_op_subtype subtype; 1872 1873 /* Tx encapsulation type for this VAP */ 1874 enum htt_cmn_pkt_type tx_encap_type; 1875 /* Rx Decapsulation type for this VAP */ 1876 enum htt_cmn_pkt_type rx_decap_type; 1877 1878 /* BSS peer */ 1879 struct dp_peer *vap_bss_peer; 1880 1881 /* WDS enabled */ 1882 bool wds_enabled; 1883 1884 /* MEC enabled */ 1885 bool mec_enabled; 1886 1887 /* WDS Aging timer period */ 1888 uint32_t wds_aging_timer_val; 1889 1890 /* NAWDS enabled */ 1891 bool nawds_enabled; 1892 1893 /* Default HTT meta data for this VDEV */ 1894 /* TBD: check alignment constraints */ 1895 uint16_t htt_tcl_metadata; 1896 1897 /* Mesh mode vdev */ 1898 uint32_t mesh_vdev; 1899 1900 /* Mesh mode rx filter setting */ 1901 uint32_t mesh_rx_filter; 1902 1903 /* DSCP-TID mapping table ID */ 1904 uint8_t dscp_tid_map_id; 1905 1906 /* Multicast enhancement enabled */ 1907 uint8_t mcast_enhancement_en; 1908 1909 /* per vdev rx nbuf queue */ 1910 qdf_nbuf_queue_t rxq; 1911 1912 uint8_t tx_ring_id; 1913 struct dp_tx_desc_pool_s *tx_desc; 1914 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 1915 1916 /* VDEV Stats */ 1917 struct cdp_vdev_stats stats; 1918 1919 /* Is this a proxySTA VAP */ 1920 bool proxysta_vdev; 1921 /* Is isolation mode enabled */ 1922 bool isolation_vdev; 1923 1924 /* Address search flags to be configured in HAL descriptor */ 1925 uint8_t hal_desc_addr_search_flags; 1926 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1927 struct dp_tx_desc_pool_s *pool; 1928 #endif 1929 /* AP BRIDGE enabled */ 1930 bool ap_bridge_enabled; 1931 1932 enum cdp_sec_type sec_type; 1933 1934 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 1935 bool raw_mode_war; 1936 1937 /* Address search type to be set in TX descriptor */ 1938 uint8_t search_type; 1939 1940 /* AST hash value for BSS peer in HW valid for STA VAP*/ 1941 uint16_t bss_ast_hash; 1942 1943 /* AST hash index for BSS peer in HW valid for STA VAP*/ 1944 uint16_t bss_ast_idx; 1945 1946 /* Capture timestamp of previous tx packet enqueued */ 1947 uint64_t prev_tx_enq_tstamp; 1948 1949 /* Capture timestamp of previous rx packet delivered */ 1950 uint64_t prev_rx_deliver_tstamp; 1951 1952 /* 8021p PCP-TID mapping table ID */ 1953 uint8_t tidmap_tbl_id; 1954 1955 /* 8021p PCP-TID map values */ 1956 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 1957 1958 /* TIDmap priority */ 1959 uint8_t tidmap_prty; 1960 /* Self Peer in STA mode */ 1961 struct dp_peer *vap_self_peer; 1962 1963 bool multipass_en; 1964 #ifdef QCA_MULTIPASS_SUPPORT 1965 uint16_t *iv_vlan_map; 1966 1967 /* dp_peer special list */ 1968 TAILQ_HEAD(, dp_peer) mpass_peer_list; 1969 DP_MUTEX_TYPE mpass_peer_mutex; 1970 #endif 1971 /* Extended data path handle */ 1972 struct cdp_ext_vdev *vdev_dp_ext_handle; 1973 #ifdef VDEV_PEER_PROTOCOL_COUNT 1974 /* 1975 * Rx-Ingress and Tx-Egress are in the lower level DP layer 1976 * Rx-Egress and Tx-ingress are handled in osif layer for DP 1977 * So 1978 * Rx-Egress and Tx-ingress mask definitions are in OSIF layer 1979 * Rx-Ingress and Tx-Egress definitions are here below 1980 */ 1981 #define VDEV_PEER_PROTOCOL_RX_INGRESS_MASK 1 1982 #define VDEV_PEER_PROTOCOL_TX_INGRESS_MASK 2 1983 #define VDEV_PEER_PROTOCOL_RX_EGRESS_MASK 4 1984 #define VDEV_PEER_PROTOCOL_TX_EGRESS_MASK 8 1985 bool peer_protocol_count_track; 1986 int peer_protocol_count_dropmask; 1987 #endif 1988 }; 1989 1990 1991 enum { 1992 dp_sec_mcast = 0, 1993 dp_sec_ucast 1994 }; 1995 1996 #ifdef WDS_VENDOR_EXTENSION 1997 typedef struct { 1998 uint8_t wds_tx_mcast_4addr:1, 1999 wds_tx_ucast_4addr:1, 2000 wds_rx_filter:1, /* enforce rx filter */ 2001 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 2002 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 2003 2004 } dp_ecm_policy; 2005 #endif 2006 2007 /* 2008 * struct dp_peer_cached_bufq - cached_bufq to enqueue rx packets 2009 * @cached_bufq: nbuff list to enqueue rx packets 2010 * @bufq_lock: spinlock for nbuff list access 2011 * @thres: maximum threshold for number of rx buff to enqueue 2012 * @entries: number of entries 2013 * @dropped: number of packets dropped 2014 */ 2015 struct dp_peer_cached_bufq { 2016 qdf_list_t cached_bufq; 2017 qdf_spinlock_t bufq_lock; 2018 uint32_t thresh; 2019 uint32_t entries; 2020 uint32_t dropped; 2021 }; 2022 2023 /** 2024 * enum dp_peer_ast_flowq 2025 * @DP_PEER_AST_FLOWQ_HI_PRIO: Hi Priority flow queue 2026 * @DP_PEER_AST_FLOWQ_LOW_PRIO: Low priority flow queue 2027 * @DP_PEER_AST_FLOWQ_UDP: flow queue type is UDP 2028 * @DP_PEER_AST_FLOWQ_NON_UDP: flow queue type is Non UDP 2029 */ 2030 enum dp_peer_ast_flowq { 2031 DP_PEER_AST_FLOWQ_HI_PRIO, 2032 DP_PEER_AST_FLOWQ_LOW_PRIO, 2033 DP_PEER_AST_FLOWQ_UDP, 2034 DP_PEER_AST_FLOWQ_NON_UDP, 2035 DP_PEER_AST_FLOWQ_MAX, 2036 }; 2037 2038 /* 2039 * struct dp_ast_flow_override_info - ast override info 2040 * @ast_index - ast indexes in peer map message 2041 * @ast_valid_mask - ast valid mask for each ast index 2042 * @ast_flow_mask - ast flow mask for each ast index 2043 * @tid_valid_low_pri_mask - per tid mask for low priority flow 2044 * @tid_valid_hi_pri_mask - per tid mask for hi priority flow 2045 */ 2046 struct dp_ast_flow_override_info { 2047 uint16_t ast_idx[DP_PEER_AST_FLOWQ_MAX]; 2048 uint8_t ast_valid_mask; 2049 uint8_t ast_flow_mask[DP_PEER_AST_FLOWQ_MAX]; 2050 uint8_t tid_valid_low_pri_mask; 2051 uint8_t tid_valid_hi_pri_mask; 2052 }; 2053 2054 /* 2055 * struct dp_peer_ast_params - ast parameters for a msdu flow-queue 2056 * @ast_index - ast index populated by FW 2057 * @is_valid - ast flow valid mask 2058 * @valid_tid_mask - per tid mask for this ast index 2059 * @flowQ - flow queue id associated with this ast index 2060 */ 2061 struct dp_peer_ast_params { 2062 uint16_t ast_idx; 2063 uint8_t is_valid; 2064 uint8_t valid_tid_mask; 2065 uint8_t flowQ; 2066 }; 2067 2068 /* Peer structure for data path state */ 2069 struct dp_peer { 2070 /* VDEV to which this peer is associated */ 2071 struct dp_vdev *vdev; 2072 2073 struct dp_ast_entry *self_ast_entry; 2074 2075 qdf_atomic_t ref_cnt; 2076 2077 /* TODO: See if multiple peer IDs are required in wifi3.0 */ 2078 /* peer ID(s) for this peer */ 2079 uint16_t peer_ids[MAX_NUM_PEER_ID_PER_PEER]; 2080 2081 union dp_align_mac_addr mac_addr; 2082 2083 /* node in the vdev's list of peers */ 2084 TAILQ_ENTRY(dp_peer) peer_list_elem; 2085 /* node in the hash table bin's list of peers */ 2086 TAILQ_ENTRY(dp_peer) hash_list_elem; 2087 2088 /* TID structures */ 2089 struct dp_rx_tid rx_tid[DP_MAX_TIDS]; 2090 struct dp_peer_tx_capture tx_capture; 2091 2092 2093 /* TBD: No transmit TID state required? */ 2094 2095 struct { 2096 enum cdp_sec_type sec_type; 2097 u_int32_t michael_key[2]; /* relevant for TKIP */ 2098 } security[2]; /* 0 -> multicast, 1 -> unicast */ 2099 2100 /* NAWDS Flag and Bss Peer bit */ 2101 uint8_t nawds_enabled:1, /* NAWDS flag */ 2102 bss_peer:1, /* set for bss peer */ 2103 wds_enabled:1, /* WDS peer */ 2104 authorize:1, /* Set when authorized */ 2105 nac:1, /* NAC Peer*/ 2106 tx_cap_enabled:1, /* Peer's tx-capture is enabled */ 2107 rx_cap_enabled:1, /* Peer's rx-capture is enabled */ 2108 valid:1; /* valid bit */ 2109 2110 /* MCL specific peer local id */ 2111 uint16_t local_id; 2112 enum ol_txrx_peer_state state; 2113 qdf_spinlock_t peer_info_lock; 2114 2115 /* Peer Stats */ 2116 struct cdp_peer_stats stats; 2117 2118 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 2119 /* TBD */ 2120 2121 #ifdef WDS_VENDOR_EXTENSION 2122 dp_ecm_policy wds_ecm; 2123 #endif 2124 bool delete_in_progress; 2125 2126 /* Active Block ack sessions */ 2127 uint16_t active_ba_session_cnt; 2128 2129 /* Current HW buffersize setting */ 2130 uint16_t hw_buffer_size; 2131 2132 /* 2133 * Flag to check if sessions with 256 buffersize 2134 * should be terminated. 2135 */ 2136 uint8_t kill_256_sessions; 2137 qdf_atomic_t is_default_route_set; 2138 /* Peer level flag to check peer based pktlog enabled or 2139 * disabled 2140 */ 2141 uint8_t peer_based_pktlog_filter; 2142 2143 /* rdk statistics context */ 2144 struct cdp_peer_rate_stats_ctx *wlanstats_ctx; 2145 /* average sojourn time */ 2146 qdf_ewma_tx_lag avg_sojourn_msdu[CDP_DATA_TID_MAX]; 2147 2148 #ifdef QCA_MULTIPASS_SUPPORT 2149 /* node in the special peer list element */ 2150 TAILQ_ENTRY(dp_peer) mpass_peer_list_elem; 2151 /* vlan id for key */ 2152 uint16_t vlan_id; 2153 #endif 2154 2155 #ifdef PEER_CACHE_RX_PKTS 2156 qdf_atomic_t flush_in_progress; 2157 struct dp_peer_cached_bufq bufq_info; 2158 #endif 2159 #ifdef FEATURE_PERPKT_INFO 2160 /* delayed ba ppdu stats handling */ 2161 struct cdp_delayed_tx_completion_ppdu_user delayed_ba_ppdu_stats; 2162 /* delayed ba flag */ 2163 bool last_delayed_ba; 2164 /* delayed ba ppdu id */ 2165 uint32_t last_delayed_ba_ppduid; 2166 #endif 2167 #ifdef QCA_PEER_MULTIQ_SUPPORT 2168 struct dp_peer_ast_params peer_ast_flowq_idx[DP_PEER_AST_FLOWQ_MAX]; 2169 #endif 2170 }; 2171 2172 /* 2173 * dp_invalid_peer_msg 2174 * @nbuf: data buffer 2175 * @wh: 802.11 header 2176 * @vdev_id: id of vdev 2177 */ 2178 struct dp_invalid_peer_msg { 2179 qdf_nbuf_t nbuf; 2180 struct ieee80211_frame *wh; 2181 uint8_t vdev_id; 2182 }; 2183 2184 /* 2185 * dp_tx_me_buf_t: ME buffer 2186 * next: pointer to next buffer 2187 * data: Destination Mac address 2188 */ 2189 struct dp_tx_me_buf_t { 2190 /* Note: ME buf pool initialization logic expects next pointer to 2191 * be the first element. Dont add anything before next */ 2192 struct dp_tx_me_buf_t *next; 2193 uint8_t data[QDF_MAC_ADDR_SIZE]; 2194 }; 2195 2196 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 2197 struct hal_rx_fst; 2198 2199 struct dp_rx_fse { 2200 /* HAL Rx Flow Search Entry which matches HW definition */ 2201 void *hal_rx_fse; 2202 /* Toeplitz hash value */ 2203 uint32_t flow_hash; 2204 /* Flow index, equivalent to hash value truncated to FST size */ 2205 uint32_t flow_id; 2206 /* Stats tracking for this flow */ 2207 struct cdp_flow_stats stats; 2208 /* Flag indicating whether flow is IPv4 address tuple */ 2209 bool is_ipv4_addr_entry; 2210 /* Flag indicating whether flow is valid */ 2211 bool is_valid; 2212 }; 2213 2214 struct dp_rx_fst { 2215 /* Software (DP) FST */ 2216 uint8_t *base; 2217 /* Pointer to HAL FST */ 2218 struct hal_rx_fst *hal_rx_fst; 2219 /* Base physical address of HAL RX HW FST */ 2220 uint64_t hal_rx_fst_base_paddr; 2221 /* Maximum number of flows FSE supports */ 2222 uint16_t max_entries; 2223 /* Num entries in flow table */ 2224 uint16_t num_entries; 2225 /* SKID Length */ 2226 uint16_t max_skid_length; 2227 /* Hash mask to obtain legitimate hash entry */ 2228 uint32_t hash_mask; 2229 /* Timer for bundling of flows */ 2230 qdf_timer_t cache_invalidate_timer; 2231 /** 2232 * Flag which tracks whether cache update 2233 * is needed on timer expiry 2234 */ 2235 qdf_atomic_t is_cache_update_pending; 2236 /* Flag to indicate completion of FSE setup in HW/FW */ 2237 bool fse_setup_done; 2238 }; 2239 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 2240 2241 #endif /* _DP_TYPES_H_ */ 2242