1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DP_TYPES_H_ 20 #define _DP_TYPES_H_ 21 22 #include <qdf_types.h> 23 #include <qdf_nbuf.h> 24 #include <qdf_lock.h> 25 #include <qdf_atomic.h> 26 #include <qdf_util.h> 27 #include <qdf_list.h> 28 #include <qdf_lro.h> 29 #include <queue.h> 30 #include <htt_common.h> 31 32 #include <cdp_txrx_cmn.h> 33 #ifdef CONFIG_MCL 34 #include <cds_ieee80211_common.h> 35 #include <wdi_event_api.h> /* WDI subscriber event list */ 36 #endif 37 38 #include "hal_hw_headers.h" 39 #include <hal_tx.h> 40 #include <hal_reo.h> 41 #include "wlan_cfg.h" 42 #include "hal_rx.h" 43 #include <hal_api.h> 44 #include <hal_api_mon.h> 45 #include "hal_rx.h" 46 47 #define MAX_BW 7 48 #define MAX_RETRIES 4 49 #define MAX_RECEPTION_TYPES 4 50 51 #ifndef REMOVE_PKT_LOG 52 #include <pktlog.h> 53 #endif 54 55 #ifdef WLAN_TX_PKT_CAPTURE_ENH 56 #include "dp_tx_capture.h" 57 #endif 58 59 #define REPT_MU_MIMO 1 60 #define REPT_MU_OFDMA_MIMO 3 61 #define DP_VO_TID 6 62 /** MAX TID MAPS AVAILABLE PER PDEV */ 63 #define DP_MAX_TID_MAPS 16 64 /** pad DSCP_TID_MAP_MAX with 6 to fix oob issue */ 65 #define DSCP_TID_MAP_MAX (64 + 6) 66 #define DP_IP_DSCP_SHIFT 2 67 #define DP_IP_DSCP_MASK 0x3f 68 #define DP_FC0_SUBTYPE_QOS 0x80 69 #define DP_QOS_TID 0x0f 70 #define DP_IPV6_PRIORITY_SHIFT 20 71 #define MAX_MON_LINK_DESC_BANKS 2 72 #define DP_VDEV_ALL 0xff 73 74 #if defined(CONFIG_MCL) 75 #define MAX_PDEV_CNT 1 76 #else 77 #define MAX_PDEV_CNT 3 78 #endif 79 80 #define MAX_LINK_DESC_BANKS 8 81 #define MAX_TXDESC_POOLS 4 82 #define MAX_RXDESC_POOLS 4 83 #define MAX_REO_DEST_RINGS 4 84 #define EXCEPTION_DEST_RING_ID 0 85 #define MAX_TCL_DATA_RINGS 4 86 #define MAX_IDLE_SCATTER_BUFS 16 87 #define DP_MAX_IRQ_PER_CONTEXT 12 88 #define DEFAULT_HW_PEER_ID 0xffff 89 90 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 91 /* Maximum retries for Delba per tid per peer */ 92 #define DP_MAX_DELBA_RETRY 3 93 94 #define PCP_TID_MAP_MAX 8 95 #define MAX_MU_USERS 37 96 97 #ifndef REMOVE_PKT_LOG 98 enum rx_pktlog_mode { 99 DP_RX_PKTLOG_DISABLED = 0, 100 DP_RX_PKTLOG_FULL, 101 DP_RX_PKTLOG_LITE, 102 }; 103 #endif 104 105 struct msdu_list { 106 qdf_nbuf_t head; 107 qdf_nbuf_t tail; 108 uint32 sum_len; 109 }; 110 111 struct dp_soc_cmn; 112 struct dp_pdev; 113 struct dp_vdev; 114 struct dp_tx_desc_s; 115 struct dp_soc; 116 union dp_rx_desc_list_elem_t; 117 struct cdp_peer_rate_stats_ctx; 118 struct cdp_soc_rate_stats_ctx; 119 120 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 121 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 122 123 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 124 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 125 126 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 127 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 128 129 #define DP_MUTEX_TYPE qdf_spinlock_t 130 131 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 132 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 133 134 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 135 ((_a)[0] == 0x33 && \ 136 (_a)[1] == 0x33) 137 138 #define DP_FRAME_IS_BROADCAST(_a) \ 139 ((_a)[0] == 0xff && \ 140 (_a)[1] == 0xff && \ 141 (_a)[2] == 0xff && \ 142 (_a)[3] == 0xff && \ 143 (_a)[4] == 0xff && \ 144 (_a)[5] == 0xff) 145 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 146 (_llc)->llc_ssap == 0xaa && \ 147 (_llc)->llc_un.type_snap.control == 0x3) 148 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 149 #define DP_FRAME_FC0_TYPE_MASK 0x0c 150 #define DP_FRAME_FC0_TYPE_DATA 0x08 151 #define DP_FRAME_IS_DATA(_frame) \ 152 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 153 154 /** 155 * macros to convert hw mac id to sw mac id: 156 * mac ids used by hardware start from a value of 1 while 157 * those in host software start from a value of 0. Use the 158 * macros below to convert between mac ids used by software and 159 * hardware 160 */ 161 #define DP_SW2HW_MACID(id) ((id) + 1) 162 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 163 164 /** 165 * Number of Tx Queues 166 * enum and macro to define how many threshold levels is used 167 * for the AC based flow control 168 */ 169 #ifdef QCA_AC_BASED_FLOW_CONTROL 170 enum dp_fl_ctrl_threshold { 171 DP_TH_BE_BK = 0, 172 DP_TH_VI, 173 DP_TH_VO, 174 DP_TH_HI, 175 }; 176 177 #define FL_TH_MAX (4) 178 #define FL_TH_VI_PERCENTAGE (80) 179 #define FL_TH_VO_PERCENTAGE (60) 180 #define FL_TH_HI_PERCENTAGE (40) 181 #endif 182 183 /** 184 * enum dp_intr_mode 185 * @DP_INTR_LEGACY: Legacy/Line interrupts, for WIN 186 * @DP_INTR_MSI: MSI interrupts, for MCL 187 * @DP_INTR_POLL: Polling 188 */ 189 enum dp_intr_mode { 190 DP_INTR_LEGACY = 0, 191 DP_INTR_MSI, 192 DP_INTR_POLL, 193 }; 194 195 /** 196 * enum dp_tx_frm_type 197 * @dp_tx_frm_std: Regular frame, no added header fragments 198 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 199 * @dp_tx_frm_sg: SG segment 200 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 201 * @dp_tx_frm_me: Multicast to Unicast Converted frame 202 * @dp_tx_frm_raw: Raw Frame 203 */ 204 enum dp_tx_frm_type { 205 dp_tx_frm_std = 0, 206 dp_tx_frm_tso, 207 dp_tx_frm_sg, 208 dp_tx_frm_audio, 209 dp_tx_frm_me, 210 dp_tx_frm_raw, 211 }; 212 213 /** 214 * enum dp_ast_type 215 * @dp_ast_type_wds: WDS peer AST type 216 * @dp_ast_type_static: static ast entry type 217 * @dp_ast_type_mec: Multicast echo ast entry type 218 */ 219 enum dp_ast_type { 220 dp_ast_type_wds = 0, 221 dp_ast_type_static, 222 dp_ast_type_mec, 223 }; 224 225 /** 226 * enum dp_nss_cfg 227 * @dp_nss_cfg_default: No radios are offloaded 228 * @dp_nss_cfg_first_radio: First radio offloaded 229 * @dp_nss_cfg_second_radio: Second radio offloaded 230 * @dp_nss_cfg_dbdc: Dual radios offloaded 231 * @dp_nss_cfg_dbtc: Three radios offloaded 232 */ 233 enum dp_nss_cfg { 234 dp_nss_cfg_default = 0x0, 235 dp_nss_cfg_first_radio = 0x1, 236 dp_nss_cfg_second_radio = 0x2, 237 dp_nss_cfg_dbdc = 0x3, 238 dp_nss_cfg_dbtc = 0x7, 239 dp_nss_cfg_max 240 }; 241 242 #ifdef WLAN_TX_PKT_CAPTURE_ENH 243 #define DP_CPU_RING_MAP_1 1 244 #endif 245 246 /** 247 * dp_cpu_ring_map_type - dp tx cpu ring map 248 * @DP_NSS_DEFAULT_MAP: Default mode with no NSS offloaded 249 * @DP_NSS_FIRST_RADIO_OFFLOADED_MAP: Only First Radio is offloaded 250 * @DP_NSS_SECOND_RADIO_OFFLOADED_MAP: Only second radio is offloaded 251 * @DP_NSS_DBDC_OFFLOADED_MAP: Both radios are offloaded 252 * @DP_NSS_DBTC_OFFLOADED_MAP: All three radios are offloaded 253 * @DP_SINGLE_TX_RING_MAP: to avoid out of order all cpu mapped to single ring 254 * @DP_NSS_CPU_RING_MAP_MAX: Max cpu ring map val 255 */ 256 enum dp_cpu_ring_map_types { 257 DP_NSS_DEFAULT_MAP, 258 DP_NSS_FIRST_RADIO_OFFLOADED_MAP, 259 DP_NSS_SECOND_RADIO_OFFLOADED_MAP, 260 DP_NSS_DBDC_OFFLOADED_MAP, 261 DP_NSS_DBTC_OFFLOADED_MAP, 262 #ifdef WLAN_TX_PKT_CAPTURE_ENH 263 DP_SINGLE_TX_RING_MAP, 264 #endif 265 DP_NSS_CPU_RING_MAP_MAX 266 }; 267 268 /** 269 * struct rx_desc_pool 270 * @pool_size: number of RX descriptor in the pool 271 * @elem_size: Element size 272 * @desc_pages: Multi page descriptors 273 * @array: pointer to array of RX descriptor 274 * @freelist: pointer to free RX descriptor link list 275 * @lock: Protection for the RX descriptor pool 276 * @owner: owner for nbuf 277 */ 278 struct rx_desc_pool { 279 uint32_t pool_size; 280 #ifdef RX_DESC_MULTI_PAGE_ALLOC 281 uint16_t elem_size; 282 struct qdf_mem_multi_page_t desc_pages; 283 #else 284 union dp_rx_desc_list_elem_t *array; 285 #endif 286 union dp_rx_desc_list_elem_t *freelist; 287 qdf_spinlock_t lock; 288 uint8_t owner; 289 }; 290 291 /** 292 * struct dp_tx_ext_desc_elem_s 293 * @next: next extension descriptor pointer 294 * @vaddr: hlos virtual address pointer 295 * @paddr: physical address pointer for descriptor 296 */ 297 struct dp_tx_ext_desc_elem_s { 298 struct dp_tx_ext_desc_elem_s *next; 299 void *vaddr; 300 qdf_dma_addr_t paddr; 301 }; 302 303 /** 304 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 305 * @elem_count: Number of descriptors in the pool 306 * @elem_size: Size of each descriptor 307 * @num_free: Number of free descriptors 308 * @msdu_ext_desc: MSDU extension descriptor 309 * @desc_pages: multiple page allocation information for actual descriptors 310 * @link_elem_size: size of the link descriptor in cacheable memory used for 311 * chaining the extension descriptors 312 * @desc_link_pages: multiple page allocation information for link descriptors 313 */ 314 struct dp_tx_ext_desc_pool_s { 315 uint16_t elem_count; 316 int elem_size; 317 uint16_t num_free; 318 struct qdf_mem_multi_page_t desc_pages; 319 int link_elem_size; 320 struct qdf_mem_multi_page_t desc_link_pages; 321 struct dp_tx_ext_desc_elem_s *freelist; 322 qdf_spinlock_t lock; 323 qdf_dma_mem_context(memctx); 324 }; 325 326 /** 327 * struct dp_tx_desc_s - Tx Descriptor 328 * @next: Next in the chain of descriptors in freelist or in the completion list 329 * @nbuf: Buffer Address 330 * @msdu_ext_desc: MSDU extension descriptor 331 * @id: Descriptor ID 332 * @vdev: vdev over which the packet was transmitted 333 * @pdev: Handle to pdev 334 * @pool_id: Pool ID - used when releasing the descriptor 335 * @flags: Flags to track the state of descriptor and special frame handling 336 * @comp: Pool ID - used when releasing the descriptor 337 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 338 * This is maintained in descriptor to allow more efficient 339 * processing in completion event processing code. 340 * This field is filled in with the htt_pkt_type enum. 341 * @frm_type: Frame Type - ToDo check if this is redundant 342 * @pkt_offset: Offset from which the actual packet data starts 343 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 344 * Tx completion of ME packet 345 * @pool: handle to flow_pool this descriptor belongs to. 346 */ 347 struct dp_tx_desc_s { 348 struct dp_tx_desc_s *next; 349 qdf_nbuf_t nbuf; 350 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 351 uint32_t id; 352 struct dp_vdev *vdev; 353 struct dp_pdev *pdev; 354 uint8_t pool_id; 355 uint16_t flags; 356 struct hal_tx_desc_comp_s comp; 357 uint16_t tx_encap_type; 358 uint8_t frm_type; 359 uint8_t pkt_offset; 360 void *me_buffer; 361 void *tso_desc; 362 void *tso_num_desc; 363 uint64_t timestamp; 364 }; 365 366 /** 367 * enum flow_pool_status - flow pool status 368 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 369 * and network queues are unpaused 370 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 371 * and network queues are paused 372 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 373 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 374 */ 375 enum flow_pool_status { 376 FLOW_POOL_ACTIVE_UNPAUSED = 0, 377 FLOW_POOL_ACTIVE_PAUSED = 1, 378 FLOW_POOL_BE_BK_PAUSED = 2, 379 FLOW_POOL_VI_PAUSED = 3, 380 FLOW_POOL_VO_PAUSED = 4, 381 FLOW_POOL_INVALID = 5, 382 FLOW_POOL_INACTIVE = 6, 383 }; 384 385 /** 386 * struct dp_tx_tso_seg_pool_s 387 * @pool_size: total number of pool elements 388 * @num_free: free element count 389 * @freelist: first free element pointer 390 * @desc_pages: multiple page allocation information for actual descriptors 391 * @lock: lock for accessing the pool 392 */ 393 struct dp_tx_tso_seg_pool_s { 394 uint16_t pool_size; 395 uint16_t num_free; 396 struct qdf_tso_seg_elem_t *freelist; 397 struct qdf_mem_multi_page_t desc_pages; 398 qdf_spinlock_t lock; 399 }; 400 401 /** 402 * struct dp_tx_tso_num_seg_pool_s { 403 * @num_seg_pool_size: total number of pool elements 404 * @num_free: free element count 405 * @freelist: first free element pointer 406 * @desc_pages: multiple page allocation information for actual descriptors 407 * @lock: lock for accessing the pool 408 */ 409 410 struct dp_tx_tso_num_seg_pool_s { 411 uint16_t num_seg_pool_size; 412 uint16_t num_free; 413 struct qdf_tso_num_seg_elem_t *freelist; 414 struct qdf_mem_multi_page_t desc_pages; 415 /*tso mutex */ 416 qdf_spinlock_t lock; 417 }; 418 419 /** 420 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 421 * @elem_size: Size of each descriptor in the pool 422 * @pool_size: Total number of descriptors in the pool 423 * @num_free: Number of free descriptors 424 * @num_allocated: Number of used descriptors 425 * @freelist: Chain of free descriptors 426 * @desc_pages: multiple page allocation information for actual descriptors 427 * @num_invalid_bin: Deleted pool with pending Tx completions. 428 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 429 * @flow_pool_array: List of allocated flow pools 430 * @lock- Lock for descriptor allocation/free from/to the pool 431 */ 432 struct dp_tx_desc_pool_s { 433 uint16_t elem_size; 434 uint32_t num_allocated; 435 struct dp_tx_desc_s *freelist; 436 struct qdf_mem_multi_page_t desc_pages; 437 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 438 uint16_t pool_size; 439 uint8_t flow_pool_id; 440 uint8_t num_invalid_bin; 441 uint16_t avail_desc; 442 enum flow_pool_status status; 443 enum htt_flow_type flow_type; 444 #ifdef QCA_AC_BASED_FLOW_CONTROL 445 uint16_t stop_th[FL_TH_MAX]; 446 uint16_t start_th[FL_TH_MAX]; 447 qdf_time_t max_pause_time[FL_TH_MAX]; 448 qdf_time_t latest_pause_time[FL_TH_MAX]; 449 #else 450 uint16_t stop_th; 451 uint16_t start_th; 452 #endif 453 uint16_t pkt_drop_no_desc; 454 qdf_spinlock_t flow_pool_lock; 455 uint8_t pool_create_cnt; 456 void *pool_owner_ctx; 457 #else 458 uint16_t elem_count; 459 uint32_t num_free; 460 qdf_spinlock_t lock; 461 #endif 462 }; 463 464 /** 465 * struct dp_txrx_pool_stats - flow pool related statistics 466 * @pool_map_count: flow pool map received 467 * @pool_unmap_count: flow pool unmap received 468 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 469 */ 470 struct dp_txrx_pool_stats { 471 uint16_t pool_map_count; 472 uint16_t pool_unmap_count; 473 uint16_t pkt_drop_no_pool; 474 }; 475 476 struct dp_srng { 477 void *hal_srng; 478 void *base_vaddr_unaligned; 479 qdf_dma_addr_t base_paddr_unaligned; 480 uint32_t alloc_size; 481 int irq; 482 uint32_t num_entries; 483 }; 484 485 struct dp_rx_reorder_array_elem { 486 qdf_nbuf_t head; 487 qdf_nbuf_t tail; 488 }; 489 490 #define DP_RX_BA_INACTIVE 0 491 #define DP_RX_BA_ACTIVE 1 492 #define DP_RX_BA_IN_PROGRESS 2 493 struct dp_reo_cmd_info { 494 uint16_t cmd; 495 enum hal_reo_cmd_type cmd_type; 496 void *data; 497 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 498 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 499 }; 500 501 /* Rx TID */ 502 struct dp_rx_tid { 503 /* TID */ 504 int tid; 505 506 /* Num of addba requests */ 507 uint32_t num_of_addba_req; 508 509 /* Num of addba responses */ 510 uint32_t num_of_addba_resp; 511 512 /* Num of delba requests */ 513 uint32_t num_of_delba_req; 514 515 /* Num of addba responses successful */ 516 uint32_t num_addba_rsp_success; 517 518 /* Num of addba responses failed */ 519 uint32_t num_addba_rsp_failed; 520 521 /* pn size */ 522 uint8_t pn_size; 523 /* REO TID queue descriptors */ 524 void *hw_qdesc_vaddr_unaligned; 525 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 526 qdf_dma_addr_t hw_qdesc_paddr; 527 uint32_t hw_qdesc_alloc_size; 528 529 /* RX ADDBA session state */ 530 int ba_status; 531 532 /* RX BA window size */ 533 uint16_t ba_win_size; 534 535 /* Starting sequence number in Addba request */ 536 uint16_t startseqnum; 537 538 /* TODO: Check the following while adding defragmentation support */ 539 struct dp_rx_reorder_array_elem *array; 540 /* base - single rx reorder element used for non-aggr cases */ 541 struct dp_rx_reorder_array_elem base; 542 543 /* only used for defrag right now */ 544 TAILQ_ENTRY(dp_rx_tid) defrag_waitlist_elem; 545 546 /* Store dst desc for reinjection */ 547 void *dst_ring_desc; 548 struct dp_rx_desc *head_frag_desc; 549 550 /* rx_tid lock */ 551 qdf_spinlock_t tid_lock; 552 553 /* Sequence and fragments that are being processed currently */ 554 uint32_t curr_seq_num; 555 uint32_t curr_frag_num; 556 557 uint32_t defrag_timeout_ms; 558 uint16_t dialogtoken; 559 uint16_t statuscode; 560 /* user defined ADDBA response status code */ 561 uint16_t userstatuscode; 562 563 /* Store ppdu_id when 2k exception is received */ 564 uint32_t ppdu_id_2k; 565 566 /* Delba Tx completion status */ 567 uint8_t delba_tx_status; 568 569 /* Delba Tx retry count */ 570 uint8_t delba_tx_retry; 571 572 /* Delba stats */ 573 uint32_t delba_tx_success_cnt; 574 uint32_t delba_tx_fail_cnt; 575 576 /* Delba reason code for retries */ 577 uint8_t delba_rcode; 578 579 }; 580 581 /** 582 * struct dp_intr_stats - DP Interrupt Stats for an interrupt context 583 * @num_tx_ring_masks: interrupts with tx_ring_mask set 584 * @num_rx_ring_masks: interrupts with rx_ring_mask set 585 * @num_rx_mon_ring_masks: interrupts with rx_mon_ring_mask set 586 * @num_rx_err_ring_masks: interrupts with rx_err_ring_mask set 587 * @num_rx_wbm_rel_ring_masks: interrupts with rx_wbm_rel_ring_mask set 588 * @num_reo_status_ring_masks: interrupts with reo_status_ring_mask set 589 * @num_rxdma2host_ring_masks: interrupts with rxdma2host_ring_mask set 590 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 591 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 592 * @num_masks: total number of times the interrupt was received 593 * 594 * Counter for individual masks are incremented only if there are any packets 595 * on that ring. 596 */ 597 struct dp_intr_stats { 598 uint32_t num_tx_ring_masks[MAX_TCL_DATA_RINGS]; 599 uint32_t num_rx_ring_masks[MAX_REO_DEST_RINGS]; 600 uint32_t num_rx_mon_ring_masks; 601 uint32_t num_rx_err_ring_masks; 602 uint32_t num_rx_wbm_rel_ring_masks; 603 uint32_t num_reo_status_ring_masks; 604 uint32_t num_rxdma2host_ring_masks; 605 uint32_t num_host2rxdma_ring_masks; 606 uint32_t num_masks; 607 }; 608 609 /* per interrupt context */ 610 struct dp_intr { 611 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 612 associated with this napi context */ 613 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 614 with this interrupt context */ 615 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 616 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 617 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 618 uint8_t reo_status_ring_mask; /* REO command response ring */ 619 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 620 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 621 /* Host to RXDMA monitor buffer ring */ 622 uint8_t host2rxdma_mon_ring_mask; 623 struct dp_soc *soc; /* Reference to SoC structure , 624 to get DMA ring handles */ 625 qdf_lro_ctx_t lro_ctx; 626 uint8_t dp_intr_id; 627 628 /* Interrupt Stats for individual masks */ 629 struct dp_intr_stats intr_stats; 630 }; 631 632 #define REO_DESC_FREELIST_SIZE 64 633 #define REO_DESC_FREE_DEFER_MS 1000 634 struct reo_desc_list_node { 635 qdf_list_node_t node; 636 unsigned long free_ts; 637 struct dp_rx_tid rx_tid; 638 }; 639 640 /* SoC level data path statistics */ 641 struct dp_soc_stats { 642 struct { 643 uint32_t added; 644 uint32_t deleted; 645 uint32_t aged_out; 646 } ast; 647 648 /* SOC level TX stats */ 649 struct { 650 /* packets dropped on tx because of no peer */ 651 struct cdp_pkt_info tx_invalid_peer; 652 /* descriptors in each tcl ring */ 653 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 654 /* Descriptors in use at soc */ 655 uint32_t desc_in_use; 656 /* tqm_release_reason == FW removed */ 657 uint32_t dropped_fw_removed; 658 /* tx completion release_src != TQM or FW */ 659 uint32_t invalid_release_source; 660 /* TX Comp loop packet limit hit */ 661 uint32_t tx_comp_loop_pkt_limit_hit; 662 /* Head pointer Out of sync at the end of dp_tx_comp_handler */ 663 uint32_t hp_oos2; 664 } tx; 665 666 /* SOC level RX stats */ 667 struct { 668 /* Rx errors */ 669 /* Total Packets in Rx Error ring */ 670 uint32_t err_ring_pkts; 671 /* No of Fragments */ 672 uint32_t rx_frags; 673 /* No of incomplete fragments in waitlist */ 674 uint32_t rx_frag_wait; 675 /* Fragments dropped due to errors */ 676 uint32_t rx_frag_err; 677 /* No of reinjected packets */ 678 uint32_t reo_reinject; 679 /* Reap loop packet limit hit */ 680 uint32_t reap_loop_pkt_limit_hit; 681 /* Head pointer Out of sync at the end of dp_rx_process */ 682 uint32_t hp_oos2; 683 struct { 684 /* Invalid RBM error count */ 685 uint32_t invalid_rbm; 686 /* Invalid VDEV Error count */ 687 uint32_t invalid_vdev; 688 /* Invalid PDEV error count */ 689 uint32_t invalid_pdev; 690 691 /* Invalid sa_idx or da_idx*/ 692 uint32_t invalid_sa_da_idx; 693 /* MSDU DONE failures */ 694 uint32_t msdu_done_fail; 695 /* Invalid PEER Error count */ 696 struct cdp_pkt_info rx_invalid_peer; 697 /* Invalid PEER ID count */ 698 struct cdp_pkt_info rx_invalid_peer_id; 699 /* Invalid packet length */ 700 struct cdp_pkt_info rx_invalid_pkt_len; 701 /* HAL ring access Fail error count */ 702 uint32_t hal_ring_access_fail; 703 /* RX DMA error count */ 704 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 705 /* RX REO DEST Desc Invalid Magic count */ 706 uint32_t rx_desc_invalid_magic; 707 /* REO Error count */ 708 uint32_t reo_error[HAL_REO_ERR_MAX]; 709 /* HAL REO ERR Count */ 710 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 711 /* HAL REO DEST Duplicate count */ 712 uint32_t hal_reo_dest_dup; 713 /* HAL WBM RELEASE Duplicate count */ 714 uint32_t hal_wbm_rel_dup; 715 /* HAL RXDMA error Duplicate count */ 716 uint32_t hal_rxdma_err_dup; 717 } err; 718 719 /* packet count per core - per ring */ 720 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 721 } rx; 722 }; 723 724 union dp_align_mac_addr { 725 uint8_t raw[QDF_MAC_ADDR_SIZE]; 726 struct { 727 uint16_t bytes_ab; 728 uint16_t bytes_cd; 729 uint16_t bytes_ef; 730 } align2; 731 struct { 732 uint32_t bytes_abcd; 733 uint16_t bytes_ef; 734 } align4; 735 struct __attribute__((__packed__)) { 736 uint16_t bytes_ab; 737 uint32_t bytes_cdef; 738 } align4_2; 739 }; 740 741 /** 742 * struct dp_ast_free_cb_params - HMWDS free callback cookie 743 * @mac_addr: ast mac address 744 * @peer_mac_addr: mac address of peer 745 * @type: ast entry type 746 * @vdev_id: vdev_id 747 * @flags: ast flags 748 */ 749 struct dp_ast_free_cb_params { 750 union dp_align_mac_addr mac_addr; 751 union dp_align_mac_addr peer_mac_addr; 752 enum cdp_txrx_ast_entry_type type; 753 uint8_t vdev_id; 754 uint32_t flags; 755 }; 756 757 /* 758 * dp_ast_entry 759 * 760 * @ast_idx: Hardware AST Index 761 * @mac_addr: MAC Address for this AST entry 762 * @peer: Next Hop peer (for non-WDS nodes, this will be point to 763 * associated peer with this MAC address) 764 * @next_hop: Set to 1 if this is for a WDS node 765 * @is_active: flag to indicate active data traffic on this node 766 * (used for aging out/expiry) 767 * @ase_list_elem: node in peer AST list 768 * @is_bss: flag to indicate if entry corresponds to bss peer 769 * @is_mapped: flag to indicate that we have mapped the AST entry 770 * in ast_table 771 * @pdev_id: pdev ID 772 * @vdev_id: vdev ID 773 * @ast_hash_value: hast value in HW 774 * @ref_cnt: reference count 775 * @type: flag to indicate type of the entry(static/WDS/MEC) 776 * @delete_in_progress: Flag to indicate that delete commands send to FW 777 * and host is waiting for response from FW 778 * @callback: ast free/unmap callback 779 * @cookie: argument to callback 780 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 781 */ 782 struct dp_ast_entry { 783 uint16_t ast_idx; 784 union dp_align_mac_addr mac_addr; 785 struct dp_peer *peer; 786 bool next_hop; 787 bool is_active; 788 bool is_bss; 789 bool is_mapped; 790 uint8_t pdev_id; 791 uint8_t vdev_id; 792 uint16_t ast_hash_value; 793 qdf_atomic_t ref_cnt; 794 enum cdp_txrx_ast_entry_type type; 795 bool delete_in_progress; 796 txrx_ast_free_cb callback; 797 void *cookie; 798 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 799 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 800 }; 801 802 /* SOC level htt stats */ 803 struct htt_t2h_stats { 804 /* lock to protect htt_stats_msg update */ 805 qdf_spinlock_t lock; 806 807 /* work queue to process htt stats */ 808 qdf_work_t work; 809 810 /* T2H Ext stats message queue */ 811 qdf_nbuf_queue_t msg; 812 813 /* number of completed stats in htt_stats_msg */ 814 uint32_t num_stats; 815 }; 816 817 /* SOC level structure for data path */ 818 struct dp_soc { 819 /** 820 * re-use memory section starts 821 */ 822 823 /* Common base structure - Should be the first member */ 824 struct cdp_soc_t cdp_soc; 825 826 /* SoC Obj */ 827 void *ctrl_psoc; 828 829 /* OS device abstraction */ 830 qdf_device_t osdev; 831 832 /* WLAN config context */ 833 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 834 835 /* HTT handle for host-fw interaction */ 836 void *htt_handle; 837 838 /* Commint init done */ 839 qdf_atomic_t cmn_init_done; 840 841 /* Opaque hif handle */ 842 struct hif_opaque_softc *hif_handle; 843 844 /* PDEVs on this SOC */ 845 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 846 847 /* Number of PDEVs */ 848 uint8_t pdev_count; 849 850 /*cce disable*/ 851 bool cce_disable; 852 853 /*ast override support in HW*/ 854 bool ast_override_support; 855 856 /*number of hw dscp tid map*/ 857 uint8_t num_hw_dscp_tid_map; 858 859 /* HAL SOC handle */ 860 void *hal_soc; 861 862 /* Device ID coming from Bus sub-system */ 863 uint32_t device_id; 864 865 /* Link descriptor memory banks */ 866 struct { 867 void *base_vaddr_unaligned; 868 void *base_vaddr; 869 qdf_dma_addr_t base_paddr_unaligned; 870 qdf_dma_addr_t base_paddr; 871 uint32_t size; 872 } link_desc_banks[MAX_LINK_DESC_BANKS]; 873 874 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 875 struct dp_srng wbm_idle_link_ring; 876 877 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 878 */ 879 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 880 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 881 882 /* Tx SW descriptor pool */ 883 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 884 885 /* Tx MSDU Extension descriptor pool */ 886 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 887 888 /* Tx TSO descriptor pool */ 889 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 890 891 /* Tx TSO Num of segments pool */ 892 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 893 894 /* REO destination rings */ 895 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 896 897 /* REO exception ring - See if should combine this with reo_dest_ring */ 898 struct dp_srng reo_exception_ring; 899 900 /* REO reinjection ring */ 901 struct dp_srng reo_reinject_ring; 902 903 /* REO command ring */ 904 struct dp_srng reo_cmd_ring; 905 906 /* REO command status ring */ 907 struct dp_srng reo_status_ring; 908 909 /* WBM Rx release ring */ 910 struct dp_srng rx_rel_ring; 911 912 /* TCL data ring */ 913 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 914 915 /* Number of TCL data rings */ 916 uint8_t num_tcl_data_rings; 917 918 /* TCL command ring */ 919 struct dp_srng tcl_cmd_ring; 920 921 /* TCL command status ring */ 922 struct dp_srng tcl_status_ring; 923 924 /* WBM Tx completion rings */ 925 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 926 927 /* Common WBM link descriptor release ring (SW to WBM) */ 928 struct dp_srng wbm_desc_rel_ring; 929 930 /* DP Interrupts */ 931 struct dp_intr intr_ctx[WLAN_CFG_INT_NUM_CONTEXTS]; 932 933 /* Rx SW descriptor pool for RXDMA monitor buffer */ 934 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 935 936 /* Rx SW descriptor pool for RXDMA status buffer */ 937 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 938 939 /* Rx SW descriptor pool for RXDMA buffer */ 940 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 941 942 /* Number of REO destination rings */ 943 uint8_t num_reo_dest_rings; 944 945 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 946 /* lock to control access to soc TX descriptors */ 947 qdf_spinlock_t flow_pool_array_lock; 948 949 /* pause callback to pause TX queues as per flow control */ 950 tx_pause_callback pause_cb; 951 952 /* flow pool related statistics */ 953 struct dp_txrx_pool_stats pool_stats; 954 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 955 956 /* 957 * Re-use memory section ends. reuse memory indicator. 958 * Everything above this variable "dp_soc_reinit" is retained across 959 * WiFi up/down for AP use-cases. 960 * Everything below this variable "dp_soc_reinit" is reset during 961 * dp_soc_deinit. 962 */ 963 bool dp_soc_reinit; 964 965 uint32_t wbm_idle_scatter_buf_size; 966 967 /* Tx H/W queues lock */ 968 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 969 970 /* Tx ring map for interrupt processing */ 971 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 972 973 /* Rx ring map for interrupt processing */ 974 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 975 976 /* peer ID to peer object map (array of pointers to peer objects) */ 977 struct dp_peer **peer_id_to_obj_map; 978 979 struct { 980 unsigned mask; 981 unsigned idx_bits; 982 TAILQ_HEAD(, dp_peer) * bins; 983 } peer_hash; 984 985 /* rx defrag state – TBD: do we need this per radio? */ 986 struct { 987 struct { 988 TAILQ_HEAD(, dp_rx_tid) waitlist; 989 uint32_t timeout_ms; 990 uint32_t next_flush_ms; 991 qdf_spinlock_t defrag_lock; 992 } defrag; 993 struct { 994 int defrag_timeout_check; 995 int dup_check; 996 } flags; 997 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 998 qdf_spinlock_t reo_cmd_lock; 999 } rx; 1000 1001 /* optional rx processing function */ 1002 void (*rx_opt_proc)( 1003 struct dp_vdev *vdev, 1004 struct dp_peer *peer, 1005 unsigned tid, 1006 qdf_nbuf_t msdu_list); 1007 1008 /* pool addr for mcast enhance buff */ 1009 struct { 1010 int size; 1011 uint32_t paddr; 1012 uint32_t *vaddr; 1013 struct dp_tx_me_buf_t *freelist; 1014 int buf_in_use; 1015 qdf_dma_mem_context(memctx); 1016 } me_buf; 1017 1018 /** 1019 * peer ref mutex: 1020 * 1. Protect peer object lookups until the returned peer object's 1021 * reference count is incremented. 1022 * 2. Provide mutex when accessing peer object lookup structures. 1023 */ 1024 DP_MUTEX_TYPE peer_ref_mutex; 1025 1026 /* maximum value for peer_id */ 1027 uint32_t max_peers; 1028 1029 /* SoC level data path statistics */ 1030 struct dp_soc_stats stats; 1031 1032 /* Enable processing of Tx completion status words */ 1033 bool process_tx_status; 1034 bool process_rx_status; 1035 struct dp_ast_entry **ast_table; 1036 struct { 1037 unsigned mask; 1038 unsigned idx_bits; 1039 TAILQ_HEAD(, dp_ast_entry) * bins; 1040 } ast_hash; 1041 1042 qdf_spinlock_t ast_lock; 1043 /*Timer for AST entry ageout maintainance */ 1044 qdf_timer_t ast_aging_timer; 1045 1046 /*Timer counter for WDS AST entry ageout*/ 1047 uint8_t wds_ast_aging_timer_cnt; 1048 1049 /*interrupt timer*/ 1050 qdf_timer_t mon_reap_timer; 1051 uint8_t reap_timer_init; 1052 qdf_timer_t int_timer; 1053 uint8_t intr_mode; 1054 1055 qdf_list_t reo_desc_freelist; 1056 qdf_spinlock_t reo_desc_freelist_lock; 1057 1058 /* htt stats */ 1059 struct htt_t2h_stats htt_stats; 1060 1061 void *external_txrx_handle; /* External data path handle */ 1062 #ifdef IPA_OFFLOAD 1063 /* IPA uC datapath offload Wlan Tx resources */ 1064 struct { 1065 /* Resource info to be passed to IPA */ 1066 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 1067 void *ipa_tcl_ring_base_vaddr; 1068 uint32_t ipa_tcl_ring_size; 1069 qdf_dma_addr_t ipa_tcl_hp_paddr; 1070 uint32_t alloc_tx_buf_cnt; 1071 1072 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 1073 void *ipa_wbm_ring_base_vaddr; 1074 uint32_t ipa_wbm_ring_size; 1075 qdf_dma_addr_t ipa_wbm_tp_paddr; 1076 1077 /* TX buffers populated into the WBM ring */ 1078 void **tx_buf_pool_vaddr_unaligned; 1079 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 1080 } ipa_uc_tx_rsc; 1081 1082 /* IPA uC datapath offload Wlan Rx resources */ 1083 struct { 1084 /* Resource info to be passed to IPA */ 1085 qdf_dma_addr_t ipa_reo_ring_base_paddr; 1086 void *ipa_reo_ring_base_vaddr; 1087 uint32_t ipa_reo_ring_size; 1088 qdf_dma_addr_t ipa_reo_tp_paddr; 1089 1090 /* Resource info to be passed to firmware and IPA */ 1091 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 1092 void *ipa_rx_refill_buf_ring_base_vaddr; 1093 uint32_t ipa_rx_refill_buf_ring_size; 1094 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 1095 } ipa_uc_rx_rsc; 1096 1097 bool reo_remapped; /* Indicate if REO2IPA rings are remapped */ 1098 qdf_spinlock_t remap_lock; 1099 #endif 1100 1101 /* Smart monitor capability for HKv2 */ 1102 uint8_t hw_nac_monitor_support; 1103 /* Flag to indicate if HTT v2 is enabled*/ 1104 bool is_peer_map_unmap_v2; 1105 /* Per peer per Tid ba window size support */ 1106 uint8_t per_tid_basize_max_tid; 1107 /* Soc level flag to enable da_war */ 1108 uint8_t da_war_enabled; 1109 /* number of active ast entries */ 1110 uint32_t num_ast_entries; 1111 /* rdk rate statistics context at soc level*/ 1112 struct cdp_soc_rate_stats_ctx *rate_stats_ctx; 1113 /* rdk rate statistics control flag */ 1114 bool wlanstats_enabled; 1115 1116 /* 8021p PCP-TID map values */ 1117 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 1118 /* TID map priority value */ 1119 uint8_t tidmap_prty; 1120 }; 1121 1122 #ifdef IPA_OFFLOAD 1123 /** 1124 * dp_ipa_resources - Resources needed for IPA 1125 */ 1126 struct dp_ipa_resources { 1127 qdf_shared_mem_t tx_ring; 1128 uint32_t tx_num_alloc_buffer; 1129 1130 qdf_shared_mem_t tx_comp_ring; 1131 qdf_shared_mem_t rx_rdy_ring; 1132 qdf_shared_mem_t rx_refill_ring; 1133 1134 /* IPA UC doorbell registers paddr */ 1135 qdf_dma_addr_t tx_comp_doorbell_paddr; 1136 uint32_t *tx_comp_doorbell_vaddr; 1137 qdf_dma_addr_t rx_ready_doorbell_paddr; 1138 }; 1139 #endif 1140 1141 #define MAX_RX_MAC_RINGS 2 1142 /* Same as NAC_MAX_CLENT */ 1143 #define DP_NAC_MAX_CLIENT 24 1144 1145 /* 1146 * Macros to setup link descriptor cookies - for link descriptors, we just 1147 * need first 3 bits to store bank ID. The remaining bytes will be used set a 1148 * unique ID, which will be useful in debugging 1149 */ 1150 #define LINK_DESC_BANK_ID_MASK 0x7 1151 #define LINK_DESC_ID_SHIFT 3 1152 #define LINK_DESC_ID_START 0x8000 1153 1154 #define LINK_DESC_COOKIE(_desc_id, _bank_id) \ 1155 ((((_desc_id) + LINK_DESC_ID_START) << LINK_DESC_ID_SHIFT) | (_bank_id)) 1156 1157 #define LINK_DESC_COOKIE_BANK_ID(_cookie) \ 1158 ((_cookie) & LINK_DESC_BANK_ID_MASK) 1159 1160 /* same as ieee80211_nac_param */ 1161 enum dp_nac_param_cmd { 1162 /* IEEE80211_NAC_PARAM_ADD */ 1163 DP_NAC_PARAM_ADD = 1, 1164 /* IEEE80211_NAC_PARAM_DEL */ 1165 DP_NAC_PARAM_DEL, 1166 /* IEEE80211_NAC_PARAM_LIST */ 1167 DP_NAC_PARAM_LIST, 1168 }; 1169 1170 /** 1171 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 1172 * @neighbour_peers_macaddr: neighbour peer's mac address 1173 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 1174 * @ast_entry: ast_entry for neighbour peer 1175 * @rssi: rssi value 1176 */ 1177 struct dp_neighbour_peer { 1178 /* MAC address of neighbour's peer */ 1179 union dp_align_mac_addr neighbour_peers_macaddr; 1180 struct dp_vdev *vdev; 1181 struct dp_ast_entry *ast_entry; 1182 uint8_t rssi; 1183 /* node in the list of neighbour's peer */ 1184 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 1185 }; 1186 1187 #ifdef WLAN_TX_PKT_CAPTURE_ENH 1188 #define WLAN_TX_PKT_CAPTURE_ENH 1 1189 #define DP_TX_PPDU_PROC_THRESHOLD 8 1190 #define DP_TX_PPDU_PROC_TIMEOUT 10 1191 #endif 1192 1193 /** 1194 * struct ppdu_info - PPDU Status info descriptor 1195 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 1196 * @sched_cmdid - schedule command id, which will be same in a burst 1197 * @max_ppdu_id - wrap around for ppdu id 1198 * @last_tlv_cnt - Keep track for missing ppdu tlvs 1199 * @last_user - last ppdu processed for user 1200 * @is_ampdu - set if Ampdu aggregate 1201 * @nbuf - ppdu descriptor payload 1202 * @ppdu_desc - ppdu descriptor 1203 * @ppdu_info_list_elem - linked list of ppdu tlvs 1204 * @ppdu_info_queue_elem - Singly linked list (queue) of ppdu tlvs 1205 */ 1206 struct ppdu_info { 1207 uint32_t ppdu_id; 1208 uint32_t sched_cmdid; 1209 uint32_t max_ppdu_id; 1210 uint16_t tlv_bitmap; 1211 uint16_t last_tlv_cnt; 1212 uint16_t last_user:8, 1213 is_ampdu:1; 1214 qdf_nbuf_t nbuf; 1215 struct cdp_tx_completion_ppdu *ppdu_desc; 1216 #ifdef WLAN_TX_PKT_CAPTURE_ENH 1217 union { 1218 TAILQ_ENTRY(ppdu_info) ppdu_info_dlist_elem; 1219 STAILQ_ENTRY(ppdu_info) ppdu_info_slist_elem; 1220 } ulist; 1221 #define ppdu_info_list_elem ulist.ppdu_info_dlist_elem 1222 #define ppdu_info_queue_elem ulist.ppdu_info_slist_elem 1223 #else 1224 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 1225 #endif 1226 }; 1227 1228 /** 1229 * struct msdu_completion_info - wbm msdu completion info 1230 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 1231 * @peer_id - peer_id 1232 * @tid - tid which used during transmit 1233 * @first_msdu - first msdu indication 1234 * @last_msdu - last msdu indication 1235 * @msdu_part_of_amsdu - msdu part of amsdu 1236 * @transmit_cnt - retried count 1237 * @tsf - timestamp which it transmitted 1238 */ 1239 struct msdu_completion_info { 1240 uint32_t ppdu_id; 1241 uint16_t peer_id; 1242 uint8_t tid; 1243 uint8_t first_msdu:1, 1244 last_msdu:1, 1245 msdu_part_of_amsdu:1; 1246 uint8_t transmit_cnt; 1247 uint32_t tsf; 1248 }; 1249 1250 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 1251 struct rx_protocol_tag_map { 1252 /* This is the user configured tag for the said protocol type */ 1253 uint16_t tag; 1254 }; 1255 1256 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 1257 struct rx_protocol_tag_stats { 1258 uint32_t tag_ctr; 1259 }; 1260 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 1261 1262 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 1263 1264 #ifndef WLAN_TX_PKT_CAPTURE_ENH 1265 struct dp_pdev_tx_capture { 1266 }; 1267 1268 struct dp_peer_tx_capture { 1269 }; 1270 #endif 1271 1272 /* PDEV level structure for data path */ 1273 struct dp_pdev { 1274 /** 1275 * Re-use Memory Section Starts 1276 */ 1277 /* PDEV handle from OSIF layer TBD: see if we really need osif_pdev */ 1278 struct cdp_ctrl_objmgr_pdev *ctrl_pdev; 1279 1280 /* PDEV Id */ 1281 int pdev_id; 1282 1283 /* LMAC Id */ 1284 int lmac_id; 1285 1286 /* TXRX SOC handle */ 1287 struct dp_soc *soc; 1288 1289 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 1290 struct dp_srng rx_refill_buf_ring; 1291 1292 /* RXDMA error destination ring */ 1293 struct dp_srng rxdma_err_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1294 1295 /* Link descriptor memory banks */ 1296 struct { 1297 void *base_vaddr_unaligned; 1298 void *base_vaddr; 1299 qdf_dma_addr_t base_paddr_unaligned; 1300 qdf_dma_addr_t base_paddr; 1301 uint32_t size; 1302 } link_desc_banks[NUM_RXDMA_RINGS_PER_PDEV][MAX_MON_LINK_DESC_BANKS]; 1303 1304 /* RXDMA monitor buffer replenish ring */ 1305 struct dp_srng rxdma_mon_buf_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1306 1307 /* RXDMA monitor destination ring */ 1308 struct dp_srng rxdma_mon_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1309 1310 /* RXDMA monitor status ring. TBD: Check format of this ring */ 1311 struct dp_srng rxdma_mon_status_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1312 1313 struct dp_srng rxdma_mon_desc_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1314 1315 /* 1316 * re-use memory section ends 1317 * reuse memory/deinit indicator 1318 * 1319 * DO NOT CHANGE NAME OR MOVE THIS VARIABLE 1320 */ 1321 bool pdev_deinit; 1322 1323 /* Second ring used to replenish rx buffers */ 1324 struct dp_srng rx_refill_buf_ring2; 1325 1326 /* Empty ring used by firmware to post rx buffers to the MAC */ 1327 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 1328 1329 /* wlan_cfg pdev ctxt*/ 1330 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 1331 1332 /** 1333 * TODO: See if we need a ring map here for LMAC rings. 1334 * 1. Monitor rings are currently planning to be processed on receiving 1335 * PPDU end interrupts and hence wont need ring based interrupts. 1336 * 2. Rx buffer rings will be replenished during REO destination 1337 * processing and doesn't require regular interrupt handling - we will 1338 * only handle low water mark interrupts which is not expected 1339 * frequently 1340 */ 1341 1342 /* VDEV list */ 1343 TAILQ_HEAD(, dp_vdev) vdev_list; 1344 1345 /* vdev list lock */ 1346 qdf_spinlock_t vdev_list_lock; 1347 1348 /* Number of vdevs this device have */ 1349 uint16_t vdev_count; 1350 1351 /* PDEV transmit lock */ 1352 qdf_spinlock_t tx_lock; 1353 1354 #ifndef REMOVE_PKT_LOG 1355 bool pkt_log_init; 1356 /* Pktlog pdev */ 1357 struct pktlog_dev_t *pl_dev; 1358 #endif /* #ifndef REMOVE_PKT_LOG */ 1359 1360 /* Monitor mode interface and status storage */ 1361 struct dp_vdev *monitor_vdev; 1362 1363 /* monitor mode lock */ 1364 qdf_spinlock_t mon_lock; 1365 1366 /*tx_mutex for me*/ 1367 DP_MUTEX_TYPE tx_mutex; 1368 1369 /* monitor */ 1370 bool monitor_configured; 1371 1372 /* Smart Mesh */ 1373 bool filter_neighbour_peers; 1374 1375 /*flag to indicate neighbour_peers_list not empty */ 1376 bool neighbour_peers_added; 1377 /* smart mesh mutex */ 1378 qdf_spinlock_t neighbour_peer_mutex; 1379 /* Neighnour peer list */ 1380 TAILQ_HEAD(, dp_neighbour_peer) neighbour_peers_list; 1381 /* msdu chain head & tail */ 1382 qdf_nbuf_t invalid_peer_head_msdu; 1383 qdf_nbuf_t invalid_peer_tail_msdu; 1384 1385 /* Band steering */ 1386 /* TBD */ 1387 1388 /* PDEV level data path statistics */ 1389 struct cdp_pdev_stats stats; 1390 1391 /* Global RX decap mode for the device */ 1392 enum htt_pkt_type rx_decap_mode; 1393 1394 /* Enhanced Stats is enabled */ 1395 bool enhanced_stats_en; 1396 1397 /* advance filter mode and type*/ 1398 uint8_t mon_filter_mode; 1399 uint16_t fp_mgmt_filter; 1400 uint16_t fp_ctrl_filter; 1401 uint16_t fp_data_filter; 1402 uint16_t mo_mgmt_filter; 1403 uint16_t mo_ctrl_filter; 1404 uint16_t mo_data_filter; 1405 uint16_t md_data_filter; 1406 1407 qdf_atomic_t num_tx_outstanding; 1408 1409 qdf_atomic_t num_tx_exception; 1410 1411 /* MCL specific local peer handle */ 1412 struct { 1413 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 1414 uint8_t freelist; 1415 qdf_spinlock_t lock; 1416 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 1417 } local_peer_ids; 1418 1419 /* dscp_tid_map_*/ 1420 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 1421 1422 struct hal_rx_ppdu_info ppdu_info; 1423 1424 /* operating channel */ 1425 uint8_t operating_channel; 1426 1427 qdf_nbuf_queue_t rx_status_q; 1428 uint32_t mon_ppdu_status; 1429 struct cdp_mon_status rx_mon_recv_status; 1430 /* monitor mode status/destination ring PPDU and MPDU count */ 1431 struct cdp_pdev_mon_stats rx_mon_stats; 1432 /* to track duplicate link descriptor indications by HW for a WAR */ 1433 uint64_t mon_last_linkdesc_paddr; 1434 /* to track duplicate buffer indications by HW for a WAR */ 1435 uint32_t mon_last_buf_cookie; 1436 /* 128 bytes mpdu header queue per user for ppdu */ 1437 qdf_nbuf_queue_t mpdu_q[MAX_MU_USERS]; 1438 /* is this a mpdu header TLV and not msdu header TLV */ 1439 bool is_mpdu_hdr[MAX_MU_USERS]; 1440 /* per user 128 bytes msdu header list for MPDU */ 1441 struct msdu_list msdu_list[MAX_MU_USERS]; 1442 /* RX enhanced capture mode */ 1443 uint32_t rx_enh_capture_mode; 1444 #ifdef WLAN_RX_PKT_CAPTURE_ENH 1445 /* RX per MPDU/PPDU information */ 1446 struct cdp_rx_indication_mpdu mpdu_ind[MAX_MU_USERS]; 1447 #endif 1448 /* pool addr for mcast enhance buff */ 1449 struct { 1450 int size; 1451 uint32_t paddr; 1452 char *vaddr; 1453 struct dp_tx_me_buf_t *freelist; 1454 int buf_in_use; 1455 qdf_dma_mem_context(memctx); 1456 } me_buf; 1457 1458 bool hmmc_tid_override_en; 1459 uint8_t hmmc_tid; 1460 1461 /* Number of VAPs with mcast enhancement enabled */ 1462 qdf_atomic_t mc_num_vap_attached; 1463 1464 qdf_atomic_t stats_cmd_complete; 1465 1466 #ifdef IPA_OFFLOAD 1467 ipa_uc_op_cb_type ipa_uc_op_cb; 1468 void *usr_ctxt; 1469 struct dp_ipa_resources ipa_resource; 1470 #endif 1471 1472 /* TBD */ 1473 1474 /* map this pdev to a particular Reo Destination ring */ 1475 enum cdp_host_reo_dest_ring reo_dest; 1476 1477 #ifndef REMOVE_PKT_LOG 1478 /* Packet log mode */ 1479 uint8_t rx_pktlog_mode; 1480 #endif 1481 1482 /* WDI event handlers */ 1483 struct wdi_event_subscribe_t **wdi_event_list; 1484 1485 /* ppdu_id of last received HTT TX stats */ 1486 uint32_t last_ppdu_id; 1487 struct { 1488 uint8_t last_user; 1489 qdf_nbuf_t buf; 1490 } tx_ppdu_info; 1491 1492 bool tx_sniffer_enable; 1493 /* mirror copy mode */ 1494 bool mcopy_mode; 1495 bool bpr_enable; 1496 1497 /* enable time latency check for tx completion */ 1498 bool latency_capture_enable; 1499 1500 /* enable calculation of delay stats*/ 1501 bool delay_stats_flag; 1502 struct { 1503 uint16_t tx_ppdu_id; 1504 uint16_t tx_peer_id; 1505 uint16_t rx_ppdu_id; 1506 } m_copy_id; 1507 1508 /* To check if PPDU Tx stats are enabled for Pktlog */ 1509 bool pktlog_ppdu_stats; 1510 1511 void *dp_txrx_handle; /* Advanced data path handle */ 1512 1513 #ifdef ATH_SUPPORT_NAC_RSSI 1514 bool nac_rssi_filtering; 1515 #endif 1516 /* list of ppdu tlvs */ 1517 TAILQ_HEAD(, ppdu_info) ppdu_info_list; 1518 uint32_t tlv_count; 1519 uint32_t list_depth; 1520 uint32_t ppdu_id; 1521 bool first_nbuf; 1522 struct { 1523 qdf_nbuf_t last_nbuf; /*Ptr to mgmt last buf */ 1524 uint8_t *mgmt_buf; /* Ptr to mgmt. payload in HTT ppdu stats */ 1525 uint32_t mgmt_buf_len; /* Len of mgmt. payload in ppdu stats */ 1526 uint32_t ppdu_id; 1527 } mgmtctrl_frm_info; 1528 1529 /* Current noise-floor reading for the pdev channel */ 1530 int16_t chan_noise_floor; 1531 1532 /* 1533 * For multiradio device, this flag indicates if 1534 * this radio is primary or secondary. 1535 * 1536 * For HK 1.0, this is used for WAR for the AST issue. 1537 * HK 1.x mandates creation of only 1 AST entry with same MAC address 1538 * across 2 radios. is_primary indicates the radio on which DP should 1539 * install HW AST entry if there is a request to add 2 AST entries 1540 * with same MAC address across 2 radios 1541 */ 1542 uint8_t is_primary; 1543 /* Context of cal client timer */ 1544 void *cal_client_ctx; 1545 struct cdp_tx_sojourn_stats sojourn_stats; 1546 qdf_nbuf_t sojourn_buf; 1547 1548 /* peer pointer for collecting invalid peer stats */ 1549 struct dp_peer *invalid_peer; 1550 1551 union dp_rx_desc_list_elem_t *free_list_head; 1552 union dp_rx_desc_list_elem_t *free_list_tail; 1553 /* Pdev level flag to check peer based pktlog enabled or 1554 * disabled 1555 */ 1556 uint8_t dp_peer_based_pktlog; 1557 1558 /* Cached peer_id from htt_peer_details_tlv */ 1559 uint8_t fw_stats_peer_id; 1560 1561 /* qdf_event for fw_peer_stats */ 1562 qdf_event_t fw_peer_stats_event; 1563 1564 /* User configured max number of tx buffers */ 1565 uint32_t num_tx_allowed; 1566 1567 /* unique cookie required for peer session */ 1568 uint32_t next_peer_cookie; 1569 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 1570 /* 1571 * Run time enabled when the first protocol tag is added, 1572 * run time disabled when the last protocol tag is deleted 1573 */ 1574 bool is_rx_protocol_tagging_enabled; 1575 1576 /* 1577 * The protocol type is used as array index to save 1578 * user provided tag info 1579 */ 1580 struct rx_protocol_tag_map rx_proto_tag_map[RX_PROTOCOL_TAG_MAX]; 1581 1582 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 1583 /* 1584 * Track msdus received from each reo ring separately to avoid 1585 * simultaneous writes from different core 1586 */ 1587 struct rx_protocol_tag_stats 1588 reo_proto_tag_stats[MAX_REO_DEST_RINGS][RX_PROTOCOL_TAG_MAX]; 1589 /* Track msdus received from expection ring separately */ 1590 struct rx_protocol_tag_stats 1591 rx_err_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 1592 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 1593 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 1594 1595 /* tx packet capture enhancement */ 1596 bool tx_capture_enabled; 1597 struct dp_pdev_tx_capture tx_capture; 1598 /* stats counter for tx ppdu processed */ 1599 uint64_t tx_ppdu_proc; 1600 }; 1601 1602 struct dp_peer; 1603 1604 /* VDEV structure for data path state */ 1605 struct dp_vdev { 1606 /* OS device abstraction */ 1607 qdf_device_t osdev; 1608 /* physical device that is the parent of this virtual device */ 1609 struct dp_pdev *pdev; 1610 1611 /* Handle to the OS shim SW's virtual device */ 1612 ol_osif_vdev_handle osif_vdev; 1613 1614 /* Handle to the UMAC handle */ 1615 struct cdp_ctrl_objmgr_vdev *ctrl_vdev; 1616 /* vdev_id - ID used to specify a particular vdev to the target */ 1617 uint8_t vdev_id; 1618 1619 /* MAC address */ 1620 union dp_align_mac_addr mac_addr; 1621 1622 /* node in the pdev's list of vdevs */ 1623 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 1624 1625 /* dp_peer list */ 1626 TAILQ_HEAD(, dp_peer) peer_list; 1627 1628 /* default RX call back function called by dp */ 1629 ol_txrx_rx_fp osif_rx; 1630 /* callback to deliver rx frames to the OS */ 1631 ol_txrx_rx_fp osif_rx_stack; 1632 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 1633 ol_txrx_get_key_fp osif_get_key; 1634 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 1635 1636 #ifdef notyet 1637 /* callback to check if the msdu is an WAI (WAPI) frame */ 1638 ol_rx_check_wai_fp osif_check_wai; 1639 #endif 1640 1641 /* proxy arp function */ 1642 ol_txrx_proxy_arp_fp osif_proxy_arp; 1643 1644 /* callback to hand rx monitor 802.11 MPDU to the OS shim */ 1645 ol_txrx_rx_mon_fp osif_rx_mon; 1646 1647 ol_txrx_mcast_me_fp me_convert; 1648 1649 /* completion function used by this vdev*/ 1650 ol_txrx_completion_fp tx_comp; 1651 1652 /* deferred vdev deletion state */ 1653 struct { 1654 /* VDEV delete pending */ 1655 int pending; 1656 /* 1657 * callback and a context argument to provide a 1658 * notification for when the vdev is deleted. 1659 */ 1660 ol_txrx_vdev_delete_cb callback; 1661 void *context; 1662 } delete; 1663 1664 /* tx data delivery notification callback function */ 1665 struct { 1666 ol_txrx_data_tx_cb func; 1667 void *ctxt; 1668 } tx_non_std_data_callback; 1669 1670 1671 /* safe mode control to bypass the encrypt and decipher process*/ 1672 uint32_t safemode; 1673 1674 /* rx filter related */ 1675 uint32_t drop_unenc; 1676 #ifdef notyet 1677 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 1678 uint32_t filters_num; 1679 #endif 1680 /* TDLS Link status */ 1681 bool tdls_link_connected; 1682 bool is_tdls_frame; 1683 1684 1685 /* VDEV operating mode */ 1686 enum wlan_op_mode opmode; 1687 1688 /* Tx encapsulation type for this VAP */ 1689 enum htt_cmn_pkt_type tx_encap_type; 1690 /* Rx Decapsulation type for this VAP */ 1691 enum htt_cmn_pkt_type rx_decap_type; 1692 1693 /* BSS peer */ 1694 struct dp_peer *vap_bss_peer; 1695 1696 /* WDS enabled */ 1697 bool wds_enabled; 1698 1699 /* MEC enabled */ 1700 bool mec_enabled; 1701 1702 /* WDS Aging timer period */ 1703 uint32_t wds_aging_timer_val; 1704 1705 /* NAWDS enabled */ 1706 bool nawds_enabled; 1707 1708 /* Default HTT meta data for this VDEV */ 1709 /* TBD: check alignment constraints */ 1710 uint16_t htt_tcl_metadata; 1711 1712 /* Mesh mode vdev */ 1713 uint32_t mesh_vdev; 1714 1715 /* Mesh mode rx filter setting */ 1716 uint32_t mesh_rx_filter; 1717 1718 /* DSCP-TID mapping table ID */ 1719 uint8_t dscp_tid_map_id; 1720 1721 /* Multicast enhancement enabled */ 1722 uint8_t mcast_enhancement_en; 1723 1724 /* per vdev rx nbuf queue */ 1725 qdf_nbuf_queue_t rxq; 1726 1727 uint8_t tx_ring_id; 1728 struct dp_tx_desc_pool_s *tx_desc; 1729 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 1730 1731 /* VDEV Stats */ 1732 struct cdp_vdev_stats stats; 1733 1734 /* Is this a proxySTA VAP */ 1735 bool proxysta_vdev; 1736 /* Is isolation mode enabled */ 1737 bool isolation_vdev; 1738 1739 /* Address search flags to be configured in HAL descriptor */ 1740 uint8_t hal_desc_addr_search_flags; 1741 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1742 struct dp_tx_desc_pool_s *pool; 1743 #endif 1744 /* AP BRIDGE enabled */ 1745 uint32_t ap_bridge_enabled; 1746 1747 enum cdp_sec_type sec_type; 1748 1749 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 1750 bool raw_mode_war; 1751 1752 /* Address search type to be set in TX descriptor */ 1753 uint8_t search_type; 1754 1755 /* AST hash value for BSS peer in HW valid for STA VAP*/ 1756 uint16_t bss_ast_hash; 1757 1758 /* Capture timestamp of previous tx packet enqueued */ 1759 uint64_t prev_tx_enq_tstamp; 1760 1761 /* Capture timestamp of previous rx packet delivered */ 1762 uint64_t prev_rx_deliver_tstamp; 1763 1764 /* 8021p PCP-TID mapping table ID */ 1765 uint8_t tidmap_tbl_id; 1766 1767 /* 8021p PCP-TID map values */ 1768 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 1769 1770 /* TIDmap priority */ 1771 uint8_t tidmap_prty; 1772 /* Self Peer in STA mode */ 1773 struct dp_peer *vap_self_peer; 1774 }; 1775 1776 1777 enum { 1778 dp_sec_mcast = 0, 1779 dp_sec_ucast 1780 }; 1781 1782 #ifdef WDS_VENDOR_EXTENSION 1783 typedef struct { 1784 uint8_t wds_tx_mcast_4addr:1, 1785 wds_tx_ucast_4addr:1, 1786 wds_rx_filter:1, /* enforce rx filter */ 1787 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 1788 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 1789 1790 } dp_ecm_policy; 1791 #endif 1792 1793 /* 1794 * struct dp_peer_cached_bufq - cached_bufq to enqueue rx packets 1795 * @cached_bufq: nbuff list to enqueue rx packets 1796 * @bufq_lock: spinlock for nbuff list access 1797 * @thres: maximum threshold for number of rx buff to enqueue 1798 * @entries: number of entries 1799 * @dropped: number of packets dropped 1800 */ 1801 struct dp_peer_cached_bufq { 1802 qdf_list_t cached_bufq; 1803 qdf_spinlock_t bufq_lock; 1804 uint32_t thresh; 1805 uint32_t entries; 1806 uint32_t dropped; 1807 }; 1808 1809 /* Peer structure for data path state */ 1810 struct dp_peer { 1811 /* VDEV to which this peer is associated */ 1812 struct dp_vdev *vdev; 1813 1814 struct cdp_ctrl_objmgr_peer *ctrl_peer; 1815 1816 struct dp_ast_entry *self_ast_entry; 1817 1818 qdf_atomic_t ref_cnt; 1819 1820 /* TODO: See if multiple peer IDs are required in wifi3.0 */ 1821 /* peer ID(s) for this peer */ 1822 uint16_t peer_ids[MAX_NUM_PEER_ID_PER_PEER]; 1823 1824 union dp_align_mac_addr mac_addr; 1825 1826 /* node in the vdev's list of peers */ 1827 TAILQ_ENTRY(dp_peer) peer_list_elem; 1828 /* node in the hash table bin's list of peers */ 1829 TAILQ_ENTRY(dp_peer) hash_list_elem; 1830 1831 /* TID structures */ 1832 struct dp_rx_tid rx_tid[DP_MAX_TIDS]; 1833 struct dp_peer_tx_capture tx_capture; 1834 1835 1836 /* TBD: No transmit TID state required? */ 1837 1838 struct { 1839 enum cdp_sec_type sec_type; 1840 u_int32_t michael_key[2]; /* relevant for TKIP */ 1841 } security[2]; /* 0 -> multicast, 1 -> unicast */ 1842 1843 /* 1844 * rx proc function: this either is a copy of pdev's rx_opt_proc for 1845 * regular rx processing, or has been redirected to a /dev/null discard 1846 * function when peer deletion is in progress. 1847 */ 1848 void (*rx_opt_proc)(struct dp_vdev *vdev, struct dp_peer *peer, 1849 unsigned tid, qdf_nbuf_t msdu_list); 1850 1851 /* set when node is authorized */ 1852 uint8_t authorize:1; 1853 1854 u_int8_t nac; 1855 1856 /* Band steering: Set when node is inactive */ 1857 uint8_t peer_bs_inact_flag:1; 1858 u_int16_t peer_bs_inact; /* inactivity mark count */ 1859 1860 /* NAWDS Flag and Bss Peer bit */ 1861 uint8_t nawds_enabled:1, 1862 bss_peer:1, 1863 wapi:1, 1864 wds_enabled:1, 1865 valid:1; 1866 1867 /* MCL specific peer local id */ 1868 uint16_t local_id; 1869 enum ol_txrx_peer_state state; 1870 qdf_spinlock_t peer_info_lock; 1871 1872 qdf_time_t last_assoc_rcvd; 1873 qdf_time_t last_disassoc_rcvd; 1874 qdf_time_t last_deauth_rcvd; 1875 /* Peer Stats */ 1876 struct cdp_peer_stats stats; 1877 1878 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 1879 /* TBD */ 1880 1881 #ifdef WDS_VENDOR_EXTENSION 1882 dp_ecm_policy wds_ecm; 1883 #endif 1884 bool delete_in_progress; 1885 1886 /* Active Block ack sessions */ 1887 uint16_t active_ba_session_cnt; 1888 1889 /* Current HW buffersize setting */ 1890 uint16_t hw_buffer_size; 1891 1892 /* 1893 * Flag to check if sessions with 256 buffersize 1894 * should be terminated. 1895 */ 1896 uint8_t kill_256_sessions; 1897 qdf_atomic_t is_default_route_set; 1898 /* Peer level flag to check peer based pktlog enabled or 1899 * disabled 1900 */ 1901 uint8_t peer_based_pktlog_filter; 1902 1903 /* rdk statistics context */ 1904 struct cdp_peer_rate_stats_ctx *wlanstats_ctx; 1905 /* average sojourn time */ 1906 qdf_ewma_tx_lag avg_sojourn_msdu[CDP_DATA_TID_MAX]; 1907 1908 #ifdef PEER_CACHE_RX_PKTS 1909 qdf_atomic_t flush_in_progress; 1910 struct dp_peer_cached_bufq bufq_info; 1911 #endif 1912 }; 1913 1914 /* 1915 * dp_invalid_peer_msg 1916 * @nbuf: data buffer 1917 * @wh: 802.11 header 1918 * @vdev_id: id of vdev 1919 */ 1920 struct dp_invalid_peer_msg { 1921 qdf_nbuf_t nbuf; 1922 struct ieee80211_frame *wh; 1923 uint8_t vdev_id; 1924 }; 1925 1926 /* 1927 * dp_tx_me_buf_t: ME buffer 1928 * next: pointer to next buffer 1929 * data: Destination Mac address 1930 */ 1931 struct dp_tx_me_buf_t { 1932 /* Note: ME buf pool initialization logic expects next pointer to 1933 * be the first element. Dont add anything before next */ 1934 struct dp_tx_me_buf_t *next; 1935 uint8_t data[QDF_MAC_ADDR_SIZE]; 1936 }; 1937 1938 #endif /* _DP_TYPES_H_ */ 1939