1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _DP_TYPES_H_ 21 #define _DP_TYPES_H_ 22 23 #include <qdf_types.h> 24 #include <qdf_nbuf.h> 25 #include <qdf_lock.h> 26 #include <qdf_atomic.h> 27 #include <qdf_util.h> 28 #include <qdf_list.h> 29 #include <qdf_lro.h> 30 #include <queue.h> 31 #include <htt_common.h> 32 #include <htt.h> 33 #include <htt_stats.h> 34 #include <cdp_txrx_cmn.h> 35 #ifdef DP_MOB_DEFS 36 #include <cds_ieee80211_common.h> 37 #endif 38 #include <wdi_event_api.h> /* WDI subscriber event list */ 39 40 #include "hal_hw_headers.h" 41 #include <hal_tx.h> 42 #include <hal_reo.h> 43 #include "wlan_cfg.h" 44 #include "hal_rx.h" 45 #include <hal_api.h> 46 #include <hal_api_mon.h> 47 #include "hal_rx.h" 48 49 #define dp_init_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_INIT, params) 50 #define dp_init_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_INIT, params) 51 #define dp_init_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_INIT, params) 52 #define dp_init_info(params...) \ 53 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_INIT, ## params) 54 #define dp_init_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_INIT, params) 55 56 #define dp_vdev_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_VDEV, params) 57 #define dp_vdev_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_VDEV, params) 58 #define dp_vdev_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_VDEV, params) 59 #define dp_vdev_info(params...) \ 60 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_VDEV, ## params) 61 #define dp_vdev_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_VDEV, params) 62 63 #define MAX_BW 8 64 #define MAX_RETRIES 4 65 #define MAX_RECEPTION_TYPES 4 66 67 #define MINIDUMP_STR_SIZE 25 68 #include <dp_umac_reset.h> 69 70 #define REPT_MU_MIMO 1 71 #define REPT_MU_OFDMA_MIMO 3 72 #define DP_VO_TID 6 73 /** MAX TID MAPS AVAILABLE PER PDEV */ 74 #define DP_MAX_TID_MAPS 16 75 /** pad DSCP_TID_MAP_MAX with 6 to fix oob issue */ 76 #define DSCP_TID_MAP_MAX (64 + 6) 77 #define DP_IP_DSCP_SHIFT 2 78 #define DP_IP_DSCP_MASK 0x3f 79 #define DP_FC0_SUBTYPE_QOS 0x80 80 #define DP_QOS_TID 0x0f 81 #define DP_IPV6_PRIORITY_SHIFT 20 82 #define MAX_MON_LINK_DESC_BANKS 2 83 #define DP_VDEV_ALL CDP_VDEV_ALL 84 85 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 86 #define WLAN_DP_RESET_MON_BUF_RING_FILTER 87 #define MAX_TXDESC_POOLS 6 88 #else 89 #define MAX_TXDESC_POOLS 4 90 #endif 91 92 /* Max no of descriptors to handle special frames like EAPOL */ 93 #define MAX_TX_SPL_DESC 1024 94 95 #define MAX_RXDESC_POOLS 4 96 #define MAX_PPE_TXDESC_POOLS 1 97 98 /* Max no. of VDEV per PSOC */ 99 #ifdef WLAN_PSOC_MAX_VDEVS 100 #define MAX_VDEV_CNT WLAN_PSOC_MAX_VDEVS 101 #else 102 #define MAX_VDEV_CNT 51 103 #endif 104 105 /* Max no. of VDEVs, a PDEV can support */ 106 #ifdef WLAN_PDEV_MAX_VDEVS 107 #define DP_PDEV_MAX_VDEVS WLAN_PDEV_MAX_VDEVS 108 #else 109 #define DP_PDEV_MAX_VDEVS 17 110 #endif 111 112 #define EXCEPTION_DEST_RING_ID 0 113 #define MAX_IDLE_SCATTER_BUFS 16 114 #define DP_MAX_IRQ_PER_CONTEXT 12 115 #define DEFAULT_HW_PEER_ID 0xffff 116 117 #define MAX_AST_AGEOUT_COUNT 128 118 119 #ifdef TX_ADDR_INDEX_SEARCH 120 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_INDEX_SEARCH 121 #else 122 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_SEARCH_DEFAULT 123 #endif 124 125 #define WBM_INT_ERROR_ALL 0 126 #define WBM_INT_ERROR_REO_NULL_BUFFER 1 127 #define WBM_INT_ERROR_REO_NULL_LINK_DESC 2 128 #define WBM_INT_ERROR_REO_NULL_MSDU_BUFF 3 129 #define WBM_INT_ERROR_REO_BUFF_REAPED 4 130 #define MAX_WBM_INT_ERROR_REASONS 5 131 132 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 133 /* Maximum retries for Delba per tid per peer */ 134 #define DP_MAX_DELBA_RETRY 3 135 136 #ifdef AST_OFFLOAD_ENABLE 137 #define AST_OFFLOAD_ENABLE_STATUS 1 138 #else 139 #define AST_OFFLOAD_ENABLE_STATUS 0 140 #endif 141 142 #ifdef FEATURE_MEC_OFFLOAD 143 #define FW_MEC_FW_OFFLOAD_ENABLED 1 144 #else 145 #define FW_MEC_FW_OFFLOAD_ENABLED 0 146 #endif 147 148 #define PCP_TID_MAP_MAX 8 149 #define MAX_MU_USERS 37 150 151 #define REO_CMD_EVENT_HIST_MAX 64 152 153 #define DP_MAX_SRNGS 64 154 155 /* 2G PHYB */ 156 #define PHYB_2G_LMAC_ID 2 157 #define PHYB_2G_TARGET_PDEV_ID 2 158 159 /* Flags for skippig s/w tid classification */ 160 #define DP_TX_HW_DSCP_TID_MAP_VALID 0x1 161 #define DP_TXRX_HLOS_TID_OVERRIDE_ENABLED 0x2 162 #define DP_TX_MESH_ENABLED 0x4 163 #define DP_TX_INVALID_QOS_TAG 0xf 164 165 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 166 #define DP_RX_REFILL_BUFF_POOL_SIZE 2048 167 #define DP_RX_REFILL_BUFF_POOL_BURST 64 168 #define DP_RX_REFILL_THRD_THRESHOLD 512 169 #endif 170 171 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 172 #define DP_RX_FSE_FLOW_MATCH_SFE 0xAAAA 173 #endif 174 175 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 176 #define DP_SKIP_BAR_UPDATE_TIMEOUT 5000 177 #endif 178 179 #define DP_TX_MAGIC_PATTERN_INUSE 0xABCD1234 180 #define DP_TX_MAGIC_PATTERN_FREE 0xDEADBEEF 181 182 #define DP_INTR_POLL_TIMER_MS 5 183 184 #ifdef IPA_OFFLOAD 185 #define DP_PEER_REO_STATS_TID_SHIFT 16 186 #define DP_PEER_REO_STATS_TID_MASK 0xFFFF0000 187 #define DP_PEER_REO_STATS_PEER_ID_MASK 0x0000FFFF 188 #define DP_PEER_GET_REO_STATS_TID(comb_peer_id_tid) \ 189 ((comb_peer_id_tid & DP_PEER_REO_STATS_TID_MASK) >> \ 190 DP_PEER_REO_STATS_TID_SHIFT) 191 #define DP_PEER_GET_REO_STATS_PEER_ID(comb_peer_id_tid) \ 192 (comb_peer_id_tid & DP_PEER_REO_STATS_PEER_ID_MASK) 193 #endif 194 195 typedef void dp_ptnr_soc_iter_func(struct dp_soc *ptnr_soc, void *arg, 196 int chip_id); 197 198 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 199 #define DP_MLD_MODE_UNIFIED_NONBOND 0 200 #define DP_MLD_MODE_UNIFIED_BOND 1 201 #define DP_MLD_MODE_HYBRID_NONBOND 2 202 #define DP_MLD_MODE_MAX DP_MLD_MODE_HYBRID_NONBOND 203 204 #define DP_LINK_VDEV_ITER 1 205 #define DP_BRIDGE_VDEV_ITER 2 206 #define DP_ALL_VDEV_ITER 3 207 #define IS_LINK_VDEV_ITER_REQUIRED(type) (type & DP_LINK_VDEV_ITER) 208 #define IS_BRIDGE_VDEV_ITER_REQUIRED(type) (type & DP_BRIDGE_VDEV_ITER) 209 #endif 210 211 enum rx_pktlog_mode { 212 DP_RX_PKTLOG_DISABLED = 0, 213 DP_RX_PKTLOG_FULL, 214 DP_RX_PKTLOG_LITE, 215 }; 216 217 /* enum m_copy_mode - Available mcopy mode 218 * 219 */ 220 enum m_copy_mode { 221 M_COPY_DISABLED = 0, 222 M_COPY = 2, 223 M_COPY_EXTENDED = 4, 224 }; 225 226 struct msdu_list { 227 qdf_nbuf_t head; 228 qdf_nbuf_t tail; 229 uint32_t sum_len; 230 }; 231 232 struct dp_soc_cmn; 233 struct dp_pdev; 234 struct dp_vdev; 235 struct dp_tx_desc_s; 236 struct dp_soc; 237 union dp_rx_desc_list_elem_t; 238 struct cdp_peer_rate_stats_ctx; 239 struct cdp_soc_rate_stats_ctx; 240 struct dp_rx_fst; 241 struct dp_mon_filter; 242 struct dp_mon_mpdu; 243 #ifdef BE_PKTLOG_SUPPORT 244 struct dp_mon_filter_be; 245 #endif 246 struct dp_peer; 247 struct dp_txrx_peer; 248 249 /** 250 * enum dp_peer_state - DP peer states 251 * @DP_PEER_STATE_NONE: 252 * @DP_PEER_STATE_INIT: 253 * @DP_PEER_STATE_ACTIVE: 254 * @DP_PEER_STATE_LOGICAL_DELETE: 255 * @DP_PEER_STATE_INACTIVE: 256 * @DP_PEER_STATE_FREED: 257 * @DP_PEER_STATE_INVALID: 258 */ 259 enum dp_peer_state { 260 DP_PEER_STATE_NONE, 261 DP_PEER_STATE_INIT, 262 DP_PEER_STATE_ACTIVE, 263 DP_PEER_STATE_LOGICAL_DELETE, 264 DP_PEER_STATE_INACTIVE, 265 DP_PEER_STATE_FREED, 266 DP_PEER_STATE_INVALID, 267 }; 268 269 /** 270 * enum dp_mod_id - DP module IDs 271 * @DP_MOD_ID_TX_RX: 272 * @DP_MOD_ID_TX_COMP: 273 * @DP_MOD_ID_RX: 274 * @DP_MOD_ID_HTT_COMP: 275 * @DP_MOD_ID_RX_ERR: 276 * @DP_MOD_ID_TX_PPDU_STATS: 277 * @DP_MOD_ID_RX_PPDU_STATS: 278 * @DP_MOD_ID_CDP: 279 * @DP_MOD_ID_GENERIC_STATS: 280 * @DP_MOD_ID_TX_MULTIPASS: 281 * @DP_MOD_ID_TX_CAPTURE: 282 * @DP_MOD_ID_NSS_OFFLOAD: 283 * @DP_MOD_ID_CONFIG: 284 * @DP_MOD_ID_HTT: 285 * @DP_MOD_ID_IPA: 286 * @DP_MOD_ID_AST: 287 * @DP_MOD_ID_MCAST2UCAST: 288 * @DP_MOD_ID_CHILD: 289 * @DP_MOD_ID_MESH: 290 * @DP_MOD_ID_TX_EXCEPTION: 291 * @DP_MOD_ID_TDLS: 292 * @DP_MOD_ID_MISC: 293 * @DP_MOD_ID_MSCS: 294 * @DP_MOD_ID_TX: 295 * @DP_MOD_ID_SAWF: 296 * @DP_MOD_ID_REINJECT: 297 * @DP_MOD_ID_SCS: 298 * @DP_MOD_ID_UMAC_RESET: 299 * @DP_MOD_ID_TX_MCAST: 300 * @DP_MOD_ID_DS: 301 * @DP_MOD_ID_MAX: 302 */ 303 enum dp_mod_id { 304 DP_MOD_ID_TX_RX, 305 DP_MOD_ID_TX_COMP, 306 DP_MOD_ID_RX, 307 DP_MOD_ID_HTT_COMP, 308 DP_MOD_ID_RX_ERR, 309 DP_MOD_ID_TX_PPDU_STATS, 310 DP_MOD_ID_RX_PPDU_STATS, 311 DP_MOD_ID_CDP, 312 DP_MOD_ID_GENERIC_STATS, 313 DP_MOD_ID_TX_MULTIPASS, 314 DP_MOD_ID_TX_CAPTURE, 315 DP_MOD_ID_NSS_OFFLOAD, 316 DP_MOD_ID_CONFIG, 317 DP_MOD_ID_HTT, 318 DP_MOD_ID_IPA, 319 DP_MOD_ID_AST, 320 DP_MOD_ID_MCAST2UCAST, 321 DP_MOD_ID_CHILD, 322 DP_MOD_ID_MESH, 323 DP_MOD_ID_TX_EXCEPTION, 324 DP_MOD_ID_TDLS, 325 DP_MOD_ID_MISC, 326 DP_MOD_ID_MSCS, 327 DP_MOD_ID_TX, 328 DP_MOD_ID_SAWF, 329 DP_MOD_ID_REINJECT, 330 DP_MOD_ID_SCS, 331 DP_MOD_ID_UMAC_RESET, 332 DP_MOD_ID_TX_MCAST, 333 DP_MOD_ID_DS, 334 DP_MOD_ID_MAX, 335 }; 336 337 /** 338 * enum dp_peer_type - DP peer type 339 * @DP_PEER_TYPE_LEGACY: 340 * @DP_PEER_TYPE_MLO_LINK: 341 * @DP_PEER_TYPE_MLO: 342 */ 343 enum dp_peer_type { 344 DP_PEER_TYPE_LEGACY, 345 DP_PEER_TYPE_MLO_LINK, 346 DP_PEER_TYPE_MLO, 347 }; 348 349 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 350 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 351 352 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 353 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 354 355 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 356 TAILQ_FOREACH_SAFE((_ase), &_peer->ast_entry_list, ase_list_elem, (_temp_ase)) 357 358 #define DP_MUTEX_TYPE qdf_spinlock_t 359 360 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 361 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 362 363 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 364 ((_a)[0] == 0x33 && \ 365 (_a)[1] == 0x33) 366 367 #define DP_FRAME_IS_BROADCAST(_a) \ 368 ((_a)[0] == 0xff && \ 369 (_a)[1] == 0xff && \ 370 (_a)[2] == 0xff && \ 371 (_a)[3] == 0xff && \ 372 (_a)[4] == 0xff && \ 373 (_a)[5] == 0xff) 374 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 375 (_llc)->llc_ssap == 0xaa && \ 376 (_llc)->llc_un.type_snap.control == 0x3) 377 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 378 #define DP_FRAME_FC0_TYPE_MASK 0x0c 379 #define DP_FRAME_FC0_TYPE_DATA 0x08 380 #define DP_FRAME_IS_DATA(_frame) \ 381 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 382 383 /* 384 * macros to convert hw mac id to sw mac id: 385 * mac ids used by hardware start from a value of 1 while 386 * those in host software start from a value of 0. Use the 387 * macros below to convert between mac ids used by software and 388 * hardware 389 */ 390 #define DP_SW2HW_MACID(id) ((id) + 1) 391 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 392 393 /* 394 * Number of Tx Queues 395 * enum and macro to define how many threshold levels is used 396 * for the AC based flow control 397 */ 398 #ifdef QCA_AC_BASED_FLOW_CONTROL 399 enum dp_fl_ctrl_threshold { 400 DP_TH_BE_BK = 0, 401 DP_TH_VI, 402 DP_TH_VO, 403 DP_TH_HI, 404 }; 405 406 #define FL_TH_MAX (4) 407 #define FL_TH_VI_PERCENTAGE (80) 408 #define FL_TH_VO_PERCENTAGE (60) 409 #define FL_TH_HI_PERCENTAGE (40) 410 #endif 411 412 /** 413 * enum dp_intr_mode 414 * @DP_INTR_INTEGRATED: Line interrupts 415 * @DP_INTR_MSI: MSI interrupts 416 * @DP_INTR_POLL: Polling 417 * @DP_INTR_LEGACY_VIRTUAL_IRQ: 418 */ 419 enum dp_intr_mode { 420 DP_INTR_INTEGRATED = 0, 421 DP_INTR_MSI, 422 DP_INTR_POLL, 423 DP_INTR_LEGACY_VIRTUAL_IRQ, 424 }; 425 426 /** 427 * enum dp_tx_frm_type 428 * @dp_tx_frm_std: Regular frame, no added header fragments 429 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 430 * @dp_tx_frm_sg: SG segment 431 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 432 * @dp_tx_frm_me: Multicast to Unicast Converted frame 433 * @dp_tx_frm_raw: Raw Frame 434 * @dp_tx_frm_rmnet: 435 */ 436 enum dp_tx_frm_type { 437 dp_tx_frm_std = 0, 438 dp_tx_frm_tso, 439 dp_tx_frm_sg, 440 dp_tx_frm_audio, 441 dp_tx_frm_me, 442 dp_tx_frm_raw, 443 dp_tx_frm_rmnet, 444 }; 445 446 /** 447 * enum dp_ast_type 448 * @dp_ast_type_wds: WDS peer AST type 449 * @dp_ast_type_static: static ast entry type 450 * @dp_ast_type_mec: Multicast echo ast entry type 451 */ 452 enum dp_ast_type { 453 dp_ast_type_wds = 0, 454 dp_ast_type_static, 455 dp_ast_type_mec, 456 }; 457 458 /** 459 * enum dp_nss_cfg 460 * @dp_nss_cfg_default: No radios are offloaded 461 * @dp_nss_cfg_first_radio: First radio offloaded 462 * @dp_nss_cfg_second_radio: Second radio offloaded 463 * @dp_nss_cfg_dbdc: Dual radios offloaded 464 * @dp_nss_cfg_dbtc: Three radios offloaded 465 * @dp_nss_cfg_max: max value 466 */ 467 enum dp_nss_cfg { 468 dp_nss_cfg_default = 0x0, 469 dp_nss_cfg_first_radio = 0x1, 470 dp_nss_cfg_second_radio = 0x2, 471 dp_nss_cfg_dbdc = 0x3, 472 dp_nss_cfg_dbtc = 0x7, 473 dp_nss_cfg_max 474 }; 475 476 #ifdef WLAN_TX_PKT_CAPTURE_ENH 477 #define DP_CPU_RING_MAP_1 1 478 #endif 479 480 /** 481 * enum dp_cpu_ring_map_types - dp tx cpu ring map 482 * @DP_NSS_DEFAULT_MAP: Default mode with no NSS offloaded 483 * @DP_NSS_FIRST_RADIO_OFFLOADED_MAP: Only First Radio is offloaded 484 * @DP_NSS_SECOND_RADIO_OFFLOADED_MAP: Only second radio is offloaded 485 * @DP_NSS_DBDC_OFFLOADED_MAP: Both radios are offloaded 486 * @DP_NSS_DBTC_OFFLOADED_MAP: All three radios are offloaded 487 * @DP_SINGLE_TX_RING_MAP: to avoid out of order all cpu mapped to single ring 488 * @DP_NSS_CPU_RING_MAP_MAX: Max cpu ring map val 489 */ 490 enum dp_cpu_ring_map_types { 491 DP_NSS_DEFAULT_MAP, 492 DP_NSS_FIRST_RADIO_OFFLOADED_MAP, 493 DP_NSS_SECOND_RADIO_OFFLOADED_MAP, 494 DP_NSS_DBDC_OFFLOADED_MAP, 495 DP_NSS_DBTC_OFFLOADED_MAP, 496 #ifdef WLAN_TX_PKT_CAPTURE_ENH 497 DP_SINGLE_TX_RING_MAP, 498 #endif 499 DP_NSS_CPU_RING_MAP_MAX 500 }; 501 502 /** 503 * struct dp_rx_nbuf_frag_info - Hold vaddr and paddr for a buffer 504 * 505 * @paddr: Physical address of buffer allocated. 506 * @virt_addr: union of virtual address representations 507 * @nbuf: Allocated nbuf in case of nbuf approach. 508 * @vaddr: Virtual address of frag allocated in case of frag approach. 509 */ 510 struct dp_rx_nbuf_frag_info { 511 qdf_dma_addr_t paddr; 512 union { 513 qdf_nbuf_t nbuf; 514 qdf_frag_t vaddr; 515 } virt_addr; 516 }; 517 518 /** 519 * enum dp_ctxt_type - context type 520 * @DP_PDEV_TYPE: PDEV context 521 * @DP_RX_RING_HIST_TYPE: Datapath rx ring history 522 * @DP_RX_ERR_RING_HIST_TYPE: Datapath rx error ring history 523 * @DP_RX_REINJECT_RING_HIST_TYPE: Datapath reinject ring history 524 * @DP_TX_TCL_HIST_TYPE: 525 * @DP_TX_COMP_HIST_TYPE: 526 * @DP_FISA_RX_FT_TYPE: 527 * @DP_RX_REFILL_RING_HIST_TYPE: Datapath rx refill ring history 528 * @DP_TX_HW_DESC_HIST_TYPE: Datapath TX HW descriptor history 529 * @DP_MON_SOC_TYPE: Datapath monitor soc context 530 * @DP_MON_PDEV_TYPE: Datapath monitor pdev context 531 * @DP_MON_STATUS_BUF_HIST_TYPE: DP monitor status buffer history 532 * @DP_CFG_EVENT_HIST_TYPE: DP config events history 533 * @DP_MON_TX_DESC_POOL_TYPE: DP TX desc pool buffer 534 * @DP_MON_RX_DESC_POOL_TYPE: DP RX desc pool buffer 535 */ 536 enum dp_ctxt_type { 537 DP_PDEV_TYPE, 538 DP_RX_RING_HIST_TYPE, 539 DP_RX_ERR_RING_HIST_TYPE, 540 DP_RX_REINJECT_RING_HIST_TYPE, 541 DP_TX_TCL_HIST_TYPE, 542 DP_TX_COMP_HIST_TYPE, 543 DP_FISA_RX_FT_TYPE, 544 DP_RX_REFILL_RING_HIST_TYPE, 545 DP_TX_HW_DESC_HIST_TYPE, 546 DP_MON_SOC_TYPE, 547 DP_MON_PDEV_TYPE, 548 DP_MON_STATUS_BUF_HIST_TYPE, 549 DP_CFG_EVENT_HIST_TYPE, 550 DP_MON_TX_DESC_POOL_TYPE, 551 DP_MON_RX_DESC_POOL_TYPE, 552 }; 553 554 /** 555 * struct rx_desc_pool 556 * @pool_size: number of RX descriptor in the pool 557 * @elem_size: Element size 558 * @desc_pages: Multi page descriptors 559 * @array: pointer to array of RX descriptor 560 * @freelist: pointer to free RX descriptor link list 561 * @lock: Protection for the RX descriptor pool 562 * @owner: owner for nbuf 563 * @buf_size: Buffer size 564 * @buf_alignment: Buffer alignment 565 * @rx_mon_dest_frag_enable: Enable frag processing for mon dest buffer 566 * @desc_type: type of desc this pool serves 567 */ 568 struct rx_desc_pool { 569 uint32_t pool_size; 570 #ifdef RX_DESC_MULTI_PAGE_ALLOC 571 uint16_t elem_size; 572 struct qdf_mem_multi_page_t desc_pages; 573 #else 574 union dp_rx_desc_list_elem_t *array; 575 #endif 576 union dp_rx_desc_list_elem_t *freelist; 577 qdf_spinlock_t lock; 578 uint8_t owner; 579 uint16_t buf_size; 580 uint8_t buf_alignment; 581 bool rx_mon_dest_frag_enable; 582 enum qdf_dp_desc_type desc_type; 583 }; 584 585 /** 586 * struct dp_tx_ext_desc_elem_s 587 * @next: next extension descriptor pointer 588 * @vaddr: hlos virtual address pointer 589 * @paddr: physical address pointer for descriptor 590 * @flags: mark features for extension descriptor 591 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 592 * Tx completion of ME packet 593 * @tso_desc: Pointer to Tso desc 594 * @tso_num_desc: Pointer to tso_num_desc 595 */ 596 struct dp_tx_ext_desc_elem_s { 597 struct dp_tx_ext_desc_elem_s *next; 598 void *vaddr; 599 qdf_dma_addr_t paddr; 600 uint16_t flags; 601 struct dp_tx_me_buf_t *me_buffer; 602 struct qdf_tso_seg_elem_t *tso_desc; 603 struct qdf_tso_num_seg_elem_t *tso_num_desc; 604 }; 605 606 /* 607 * NB: intentionally not using kernel-doc comment because the kernel-doc 608 * script does not handle the qdf_dma_mem_context macro 609 * struct dp_tx_ext_desc_pool_s - Tx Extension Descriptor Pool 610 * @elem_count: Number of descriptors in the pool 611 * @elem_size: Size of each descriptor 612 * @num_free: Number of free descriptors 613 * @desc_pages: multiple page allocation information for actual descriptors 614 * @link_elem_size: size of the link descriptor in cacheable memory used for 615 * chaining the extension descriptors 616 * @desc_link_pages: multiple page allocation information for link descriptors 617 * @freelist: 618 * @lock: 619 * @memctx: 620 */ 621 struct dp_tx_ext_desc_pool_s { 622 uint16_t elem_count; 623 int elem_size; 624 uint16_t num_free; 625 struct qdf_mem_multi_page_t desc_pages; 626 int link_elem_size; 627 struct qdf_mem_multi_page_t desc_link_pages; 628 struct dp_tx_ext_desc_elem_s *freelist; 629 qdf_spinlock_t lock; 630 qdf_dma_mem_context(memctx); 631 }; 632 633 /** 634 * struct dp_tx_desc_s - Tx Descriptor 635 * @next: Next in the chain of descriptors in freelist or in the completion list 636 * @nbuf: Buffer Address 637 * @length: 638 * @magic: 639 * @timestamp_tick: 640 * @flags: Flags to track the state of descriptor and special frame handling 641 * @id: Descriptor ID 642 * @dma_addr: 643 * @vdev_id: vdev_id of vdev over which the packet was transmitted 644 * @tx_status: 645 * @peer_id: 646 * @pdev: Handle to pdev 647 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 648 * This is maintained in descriptor to allow more efficient 649 * processing in completion event processing code. 650 * This field is filled in with the htt_pkt_type enum. 651 * @buffer_src: buffer source TQM, REO, FW etc. 652 * @reserved: 653 * @frm_type: Frame Type - ToDo check if this is redundant 654 * @pkt_offset: Offset from which the actual packet data starts 655 * @pool_id: Pool ID - used when releasing the descriptor 656 * @shinfo_addr: 657 * @msdu_ext_desc: MSDU extension descriptor 658 * @timestamp: 659 * @comp: 660 * @tcl_cmd_vaddr: VADDR of the TCL descriptor, valid for soft-umac arch 661 * @tcl_cmd_paddr: PADDR of the TCL descriptor, valid for soft-umac arch 662 */ 663 struct dp_tx_desc_s { 664 struct dp_tx_desc_s *next; 665 qdf_nbuf_t nbuf; 666 uint16_t length; 667 #ifdef DP_TX_TRACKING 668 uint32_t magic; 669 uint64_t timestamp_tick; 670 #endif 671 uint16_t flags; 672 uint32_t id; 673 qdf_dma_addr_t dma_addr; 674 uint8_t vdev_id; 675 uint8_t tx_status; 676 uint16_t peer_id; 677 struct dp_pdev *pdev; 678 uint8_t tx_encap_type:2, 679 buffer_src:3, 680 reserved:3; 681 uint8_t frm_type; 682 uint8_t pkt_offset; 683 uint8_t pool_id; 684 unsigned char *shinfo_addr; 685 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 686 qdf_ktime_t timestamp; 687 struct hal_tx_desc_comp_s comp; 688 #ifdef WLAN_SOFTUMAC_SUPPORT 689 void *tcl_cmd_vaddr; 690 qdf_dma_addr_t tcl_cmd_paddr; 691 #endif 692 }; 693 694 #ifdef QCA_AC_BASED_FLOW_CONTROL 695 /** 696 * enum flow_pool_status - flow pool status 697 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 698 * and network queues are unpaused 699 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 700 * and network queues are paused 701 * @FLOW_POOL_BE_BK_PAUSED: 702 * @FLOW_POOL_VI_PAUSED: 703 * @FLOW_POOL_VO_PAUSED: 704 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 705 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 706 * @FLOW_POOL_ACTIVE_UNPAUSED_REATTACH: pool is reattached but network 707 * queues are not paused 708 */ 709 enum flow_pool_status { 710 FLOW_POOL_ACTIVE_UNPAUSED = 0, 711 FLOW_POOL_ACTIVE_PAUSED = 1, 712 FLOW_POOL_BE_BK_PAUSED = 2, 713 FLOW_POOL_VI_PAUSED = 3, 714 FLOW_POOL_VO_PAUSED = 4, 715 FLOW_POOL_INVALID = 5, 716 FLOW_POOL_INACTIVE = 6, 717 FLOW_POOL_ACTIVE_UNPAUSED_REATTACH = 7, 718 }; 719 720 #else 721 /** 722 * enum flow_pool_status - flow pool status 723 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 724 * and network queues are unpaused 725 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 726 * and network queues are paused 727 * @FLOW_POOL_BE_BK_PAUSED: 728 * @FLOW_POOL_VI_PAUSED: 729 * @FLOW_POOL_VO_PAUSED: 730 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 731 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 732 */ 733 enum flow_pool_status { 734 FLOW_POOL_ACTIVE_UNPAUSED = 0, 735 FLOW_POOL_ACTIVE_PAUSED = 1, 736 FLOW_POOL_BE_BK_PAUSED = 2, 737 FLOW_POOL_VI_PAUSED = 3, 738 FLOW_POOL_VO_PAUSED = 4, 739 FLOW_POOL_INVALID = 5, 740 FLOW_POOL_INACTIVE = 6, 741 }; 742 743 #endif 744 745 /** 746 * struct dp_tx_tso_seg_pool_s 747 * @pool_size: total number of pool elements 748 * @num_free: free element count 749 * @freelist: first free element pointer 750 * @desc_pages: multiple page allocation information for actual descriptors 751 * @lock: lock for accessing the pool 752 */ 753 struct dp_tx_tso_seg_pool_s { 754 uint16_t pool_size; 755 uint16_t num_free; 756 struct qdf_tso_seg_elem_t *freelist; 757 struct qdf_mem_multi_page_t desc_pages; 758 qdf_spinlock_t lock; 759 }; 760 761 /** 762 * struct dp_tx_tso_num_seg_pool_s - TSO Num seg pool 763 * @num_seg_pool_size: total number of pool elements 764 * @num_free: free element count 765 * @freelist: first free element pointer 766 * @desc_pages: multiple page allocation information for actual descriptors 767 * @lock: lock for accessing the pool 768 */ 769 770 struct dp_tx_tso_num_seg_pool_s { 771 uint16_t num_seg_pool_size; 772 uint16_t num_free; 773 struct qdf_tso_num_seg_elem_t *freelist; 774 struct qdf_mem_multi_page_t desc_pages; 775 /*tso mutex */ 776 qdf_spinlock_t lock; 777 }; 778 779 /** 780 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 781 * @elem_size: Size of each descriptor in the pool 782 * @num_allocated: Number of used descriptors 783 * @freelist: Chain of free descriptors 784 * @desc_pages: multiple page allocation information for actual descriptors 785 * @pool_size: Total number of descriptors in the pool 786 * @flow_pool_id: 787 * @num_invalid_bin: Deleted pool with pending Tx completions. 788 * @avail_desc: 789 * @status: 790 * @flow_type: 791 * @stop_th: 792 * @start_th: 793 * @max_pause_time: 794 * @latest_pause_time: 795 * @pkt_drop_no_desc: 796 * @flow_pool_lock: 797 * @pool_create_cnt: 798 * @pool_owner_ctx: 799 * @elem_count: 800 * @num_free: Number of free descriptors 801 * @lock: Lock for descriptor allocation/free from/to the pool 802 */ 803 struct dp_tx_desc_pool_s { 804 uint16_t elem_size; 805 uint32_t num_allocated; 806 struct dp_tx_desc_s *freelist; 807 struct qdf_mem_multi_page_t desc_pages; 808 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 809 uint16_t pool_size; 810 uint8_t flow_pool_id; 811 uint8_t num_invalid_bin; 812 uint16_t avail_desc; 813 enum flow_pool_status status; 814 enum htt_flow_type flow_type; 815 #ifdef QCA_AC_BASED_FLOW_CONTROL 816 uint16_t stop_th[FL_TH_MAX]; 817 uint16_t start_th[FL_TH_MAX]; 818 qdf_time_t max_pause_time[FL_TH_MAX]; 819 qdf_time_t latest_pause_time[FL_TH_MAX]; 820 #else 821 uint16_t stop_th; 822 uint16_t start_th; 823 #endif 824 uint16_t pkt_drop_no_desc; 825 qdf_spinlock_t flow_pool_lock; 826 uint8_t pool_create_cnt; 827 void *pool_owner_ctx; 828 #else 829 uint16_t elem_count; 830 uint32_t num_free; 831 qdf_spinlock_t lock; 832 #endif 833 }; 834 835 /** 836 * struct dp_txrx_pool_stats - flow pool related statistics 837 * @pool_map_count: flow pool map received 838 * @pool_unmap_count: flow pool unmap received 839 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 840 */ 841 struct dp_txrx_pool_stats { 842 uint16_t pool_map_count; 843 uint16_t pool_unmap_count; 844 uint16_t pkt_drop_no_pool; 845 }; 846 847 /** 848 * struct dp_srng - DP srng structure 849 * @hal_srng: hal_srng handle 850 * @base_vaddr_unaligned: un-aligned virtual base address of the srng ring 851 * @base_vaddr_aligned: aligned virtual base address of the srng ring 852 * @base_paddr_unaligned: un-aligned physical base address of the srng ring 853 * @base_paddr_aligned: aligned physical base address of the srng ring 854 * @alloc_size: size of the srng ring 855 * @cached: is the srng ring memory cached or un-cached memory 856 * @irq: irq number of the srng ring 857 * @num_entries: number of entries in the srng ring 858 * @stats: Structure to track the ring utilization stats 859 * @is_mem_prealloc: Is this srng memory pre-allocated 860 * @crit_thresh: Critical threshold for near-full processing of this srng 861 * @safe_thresh: Safe threshold for near-full processing of this srng 862 * @near_full: Flag to indicate srng is near-full 863 */ 864 struct dp_srng { 865 hal_ring_handle_t hal_srng; 866 void *base_vaddr_unaligned; 867 void *base_vaddr_aligned; 868 qdf_dma_addr_t base_paddr_unaligned; 869 qdf_dma_addr_t base_paddr_aligned; 870 uint32_t alloc_size; 871 uint8_t cached; 872 int irq; 873 uint32_t num_entries; 874 struct ring_util_stats stats; 875 #ifdef DP_MEM_PRE_ALLOC 876 uint8_t is_mem_prealloc; 877 #endif 878 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 879 uint16_t crit_thresh; 880 uint16_t safe_thresh; 881 qdf_atomic_t near_full; 882 #endif 883 }; 884 885 struct dp_rx_reorder_array_elem { 886 qdf_nbuf_t head; 887 qdf_nbuf_t tail; 888 }; 889 890 #define DP_RX_BA_INACTIVE 0 891 #define DP_RX_BA_ACTIVE 1 892 #define DP_RX_BA_IN_PROGRESS 2 893 struct dp_reo_cmd_info { 894 uint16_t cmd; 895 enum hal_reo_cmd_type cmd_type; 896 void *data; 897 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 898 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 899 }; 900 901 struct dp_peer_delay_stats { 902 struct cdp_delay_tid_stats delay_tid_stats[CDP_MAX_DATA_TIDS] 903 [CDP_MAX_TXRX_CTX]; 904 }; 905 906 /* Rx TID defrag*/ 907 struct dp_rx_tid_defrag { 908 /* TID */ 909 int tid; 910 911 /* only used for defrag right now */ 912 TAILQ_ENTRY(dp_rx_tid_defrag) defrag_waitlist_elem; 913 914 /* Store dst desc for reinjection */ 915 hal_ring_desc_t dst_ring_desc; 916 struct dp_rx_desc *head_frag_desc; 917 918 /* Sequence and fragments that are being processed currently */ 919 uint32_t curr_seq_num; 920 uint32_t curr_frag_num; 921 922 /* TODO: Check the following while adding defragmentation support */ 923 struct dp_rx_reorder_array_elem *array; 924 /* base - single rx reorder element used for non-aggr cases */ 925 struct dp_rx_reorder_array_elem base; 926 /* rx_tid lock */ 927 qdf_spinlock_t defrag_tid_lock; 928 929 /* head PN number */ 930 uint64_t pn128[2]; 931 932 uint32_t defrag_timeout_ms; 933 934 /* defrag usage only, dp_peer pointer related with this tid */ 935 struct dp_txrx_peer *defrag_peer; 936 }; 937 938 /* Rx TID */ 939 struct dp_rx_tid { 940 /* TID */ 941 int tid; 942 943 /* Num of addba requests */ 944 uint32_t num_of_addba_req; 945 946 /* Num of addba responses */ 947 uint32_t num_of_addba_resp; 948 949 /* Num of delba requests */ 950 uint32_t num_of_delba_req; 951 952 /* Num of addba responses successful */ 953 uint32_t num_addba_rsp_success; 954 955 /* Num of addba responses failed */ 956 uint32_t num_addba_rsp_failed; 957 958 /* pn size */ 959 uint8_t pn_size; 960 /* REO TID queue descriptors */ 961 void *hw_qdesc_vaddr_unaligned; 962 void *hw_qdesc_vaddr_aligned; 963 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 964 qdf_dma_addr_t hw_qdesc_paddr; 965 uint32_t hw_qdesc_alloc_size; 966 967 /* RX ADDBA session state */ 968 int ba_status; 969 970 /* RX BA window size */ 971 uint16_t ba_win_size; 972 973 /* Starting sequence number in Addba request */ 974 uint16_t startseqnum; 975 uint16_t dialogtoken; 976 uint16_t statuscode; 977 /* user defined ADDBA response status code */ 978 uint16_t userstatuscode; 979 980 /* rx_tid lock */ 981 qdf_spinlock_t tid_lock; 982 983 /* Store ppdu_id when 2k exception is received */ 984 uint32_t ppdu_id_2k; 985 986 /* Delba Tx completion status */ 987 uint8_t delba_tx_status; 988 989 /* Delba Tx retry count */ 990 uint8_t delba_tx_retry; 991 992 /* Delba stats */ 993 uint32_t delba_tx_success_cnt; 994 uint32_t delba_tx_fail_cnt; 995 996 /* Delba reason code for retries */ 997 uint8_t delba_rcode; 998 999 /* Coex Override preserved windows size 1 based */ 1000 uint16_t rx_ba_win_size_override; 1001 #ifdef IPA_OFFLOAD 1002 /* rx msdu count per tid */ 1003 struct cdp_pkt_info rx_msdu_cnt; 1004 #endif 1005 1006 }; 1007 1008 /** 1009 * struct dp_intr_stats - DP Interrupt Stats for an interrupt context 1010 * @num_tx_ring_masks: interrupts with tx_ring_mask set 1011 * @num_rx_ring_masks: interrupts with rx_ring_mask set 1012 * @num_rx_mon_ring_masks: interrupts with rx_mon_ring_mask set 1013 * @num_rx_err_ring_masks: interrupts with rx_err_ring_mask set 1014 * @num_rx_wbm_rel_ring_masks: interrupts with rx_wbm_rel_ring_mask set 1015 * @num_reo_status_ring_masks: interrupts with reo_status_ring_mask set 1016 * @num_rxdma2host_ring_masks: interrupts with rxdma2host_ring_mask set 1017 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 1018 * @num_host2rxdma_mon_ring_masks: interrupts with host2rxdma_ring_mask set 1019 * @num_rx_ring_near_full_masks: Near-full interrupts for REO DST ring 1020 * @num_tx_comp_ring_near_full_masks: Near-full interrupts for TX completion 1021 * @num_rx_wbm_rel_ring_near_full_masks: total number of times the wbm rel ring 1022 * near full interrupt was received 1023 * @num_reo_status_ring_near_full_masks: total number of times the reo status 1024 * near full interrupt was received 1025 * @num_near_full_masks: total number of times the near full interrupt 1026 * was received 1027 * @num_masks: total number of times the interrupt was received 1028 * @num_host2txmon_ring__masks: interrupts with host2txmon_ring_mask set 1029 * @num_near_full_masks: total number of times the interrupt was received 1030 * @num_masks: total number of times the near full interrupt was received 1031 * @num_tx_mon_ring_masks: interrupts with num_tx_mon_ring_masks set 1032 * 1033 * Counter for individual masks are incremented only if there are any packets 1034 * on that ring. 1035 */ 1036 struct dp_intr_stats { 1037 uint32_t num_tx_ring_masks[MAX_TCL_DATA_RINGS]; 1038 uint32_t num_rx_ring_masks[MAX_REO_DEST_RINGS]; 1039 uint32_t num_rx_mon_ring_masks; 1040 uint32_t num_rx_err_ring_masks; 1041 uint32_t num_rx_wbm_rel_ring_masks; 1042 uint32_t num_reo_status_ring_masks; 1043 uint32_t num_rxdma2host_ring_masks; 1044 uint32_t num_host2rxdma_ring_masks; 1045 uint32_t num_host2rxdma_mon_ring_masks; 1046 uint32_t num_rx_ring_near_full_masks[MAX_REO_DEST_RINGS]; 1047 uint32_t num_tx_comp_ring_near_full_masks[MAX_TCL_DATA_RINGS]; 1048 uint32_t num_rx_wbm_rel_ring_near_full_masks; 1049 uint32_t num_reo_status_ring_near_full_masks; 1050 uint32_t num_host2txmon_ring__masks; 1051 uint32_t num_near_full_masks; 1052 uint32_t num_masks; 1053 uint32_t num_tx_mon_ring_masks; 1054 }; 1055 1056 #ifdef DP_UMAC_HW_RESET_SUPPORT 1057 /** 1058 * struct dp_intr_bkp - DP per interrupt context ring masks old state 1059 * @tx_ring_mask: WBM Tx completion rings (0-2) associated with this napi ctxt 1060 * @rx_ring_mask: Rx REO rings (0-3) associated with this interrupt context 1061 * @rx_mon_ring_mask: Rx monitor ring mask (0-2) 1062 * @rx_err_ring_mask: REO Exception Ring 1063 * @rx_wbm_rel_ring_mask: WBM2SW Rx Release Ring 1064 * @reo_status_ring_mask: REO command response ring 1065 * @rxdma2host_ring_mask: RXDMA to host destination ring 1066 * @host2rxdma_ring_mask: Host to RXDMA buffer ring 1067 * @host2rxdma_mon_ring_mask: Host to RXDMA monitor buffer ring 1068 * @host2txmon_ring_mask: Tx monitor buffer ring 1069 * @tx_mon_ring_mask: Tx monitor ring mask (0-2) 1070 * 1071 */ 1072 struct dp_intr_bkp { 1073 uint8_t tx_ring_mask; 1074 uint8_t rx_ring_mask; 1075 uint8_t rx_mon_ring_mask; 1076 uint8_t rx_err_ring_mask; 1077 uint8_t rx_wbm_rel_ring_mask; 1078 uint8_t reo_status_ring_mask; 1079 uint8_t rxdma2host_ring_mask; 1080 uint8_t host2rxdma_ring_mask; 1081 uint8_t host2rxdma_mon_ring_mask; 1082 uint8_t host2txmon_ring_mask; 1083 uint8_t tx_mon_ring_mask; 1084 }; 1085 #endif 1086 1087 /* per interrupt context */ 1088 struct dp_intr { 1089 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 1090 associated with this napi context */ 1091 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 1092 with this interrupt context */ 1093 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 1094 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 1095 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 1096 uint8_t reo_status_ring_mask; /* REO command response ring */ 1097 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 1098 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 1099 /* Host to RXDMA monitor buffer ring */ 1100 uint8_t host2rxdma_mon_ring_mask; 1101 /* RX REO rings near full interrupt mask */ 1102 uint8_t rx_near_full_grp_1_mask; 1103 /* RX REO rings near full interrupt mask */ 1104 uint8_t rx_near_full_grp_2_mask; 1105 /* WBM TX completion rings near full interrupt mask */ 1106 uint8_t tx_ring_near_full_mask; 1107 uint8_t host2txmon_ring_mask; /* Tx monitor buffer ring */ 1108 uint8_t tx_mon_ring_mask; /* Tx monitor ring mask (0-2) */ 1109 struct dp_soc *soc; /* Reference to SoC structure , 1110 to get DMA ring handles */ 1111 qdf_lro_ctx_t lro_ctx; 1112 uint8_t dp_intr_id; 1113 1114 /* Interrupt Stats for individual masks */ 1115 struct dp_intr_stats intr_stats; 1116 uint8_t umac_reset_intr_mask; /* UMAC reset interrupt mask */ 1117 }; 1118 1119 #define REO_DESC_FREELIST_SIZE 64 1120 #define REO_DESC_FREE_DEFER_MS 1000 1121 struct reo_desc_list_node { 1122 qdf_list_node_t node; 1123 unsigned long free_ts; 1124 struct dp_rx_tid rx_tid; 1125 bool resend_update_reo_cmd; 1126 uint32_t pending_ext_desc_size; 1127 #ifdef REO_QDESC_HISTORY 1128 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1129 #endif 1130 }; 1131 1132 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 1133 #define REO_DESC_DEFERRED_FREELIST_SIZE 256 1134 #define REO_DESC_DEFERRED_FREE_MS 30000 1135 1136 struct reo_desc_deferred_freelist_node { 1137 qdf_list_node_t node; 1138 unsigned long free_ts; 1139 void *hw_qdesc_vaddr_unaligned; 1140 qdf_dma_addr_t hw_qdesc_paddr; 1141 uint32_t hw_qdesc_alloc_size; 1142 #ifdef REO_QDESC_HISTORY 1143 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1144 #endif /* REO_QDESC_HISTORY */ 1145 }; 1146 #endif /* WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY */ 1147 1148 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1149 /** 1150 * struct reo_cmd_event_record: Elements to record for each reo command 1151 * @cmd_type: reo command type 1152 * @cmd_return_status: reo command post status 1153 * @timestamp: record timestamp for the reo command 1154 */ 1155 struct reo_cmd_event_record { 1156 enum hal_reo_cmd_type cmd_type; 1157 uint8_t cmd_return_status; 1158 uint64_t timestamp; 1159 }; 1160 1161 /** 1162 * struct reo_cmd_event_history: Account for reo cmd events 1163 * @index: record number 1164 * @cmd_record: list of records 1165 */ 1166 struct reo_cmd_event_history { 1167 qdf_atomic_t index; 1168 struct reo_cmd_event_record cmd_record[REO_CMD_EVENT_HIST_MAX]; 1169 }; 1170 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1171 1172 /* SoC level data path statistics */ 1173 struct dp_soc_stats { 1174 struct { 1175 uint32_t added; 1176 uint32_t deleted; 1177 uint32_t aged_out; 1178 uint32_t map_err; 1179 uint32_t ast_mismatch; 1180 } ast; 1181 1182 struct { 1183 uint32_t added; 1184 uint32_t deleted; 1185 } mec; 1186 1187 /* SOC level TX stats */ 1188 struct { 1189 /* Total packets transmitted */ 1190 struct cdp_pkt_info egress[MAX_TCL_DATA_RINGS]; 1191 /* Enqueues per tcl ring */ 1192 uint32_t tcl_enq[MAX_TCL_DATA_RINGS]; 1193 /* packets dropped on tx because of no peer */ 1194 struct cdp_pkt_info tx_invalid_peer; 1195 /* descriptors in each tcl ring */ 1196 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 1197 /* Descriptors in use at soc */ 1198 uint32_t desc_in_use; 1199 /* tqm_release_reason == FW removed */ 1200 uint32_t dropped_fw_removed; 1201 /* tx completion release_src != TQM or FW */ 1202 uint32_t invalid_release_source; 1203 /* TX descriptor from completion ring Desc is not valid */ 1204 uint32_t invalid_tx_comp_desc; 1205 /* tx completion wbm_internal_error */ 1206 uint32_t wbm_internal_error[MAX_WBM_INT_ERROR_REASONS]; 1207 /* tx completion non_wbm_internal_error */ 1208 uint32_t non_wbm_internal_err; 1209 /* TX Comp loop packet limit hit */ 1210 uint32_t tx_comp_loop_pkt_limit_hit; 1211 /* Head pointer Out of sync at the end of dp_tx_comp_handler */ 1212 uint32_t hp_oos2; 1213 /* tx desc freed as part of vdev detach */ 1214 uint32_t tx_comp_exception; 1215 /* TQM drops after/during peer delete */ 1216 uint64_t tqm_drop_no_peer; 1217 /* Number of tx completions reaped per WBM2SW release ring */ 1218 uint32_t tx_comp[MAX_TCL_DATA_RINGS]; 1219 /* Number of tx completions force freed */ 1220 uint32_t tx_comp_force_freed; 1221 /* Tx completion ring near full */ 1222 uint32_t near_full; 1223 /* Tx drops with buffer src as HAL_TX_COMP_RELEASE_SOURCE_FW */ 1224 uint32_t fw2wbm_tx_drop; 1225 } tx; 1226 1227 /* SOC level RX stats */ 1228 struct { 1229 /* Total rx packets count */ 1230 struct cdp_pkt_info ingress; 1231 /* Rx errors */ 1232 /* Total Packets in Rx Error ring */ 1233 uint32_t err_ring_pkts; 1234 /* No of Fragments */ 1235 uint32_t rx_frags; 1236 /* No of incomplete fragments in waitlist */ 1237 uint32_t rx_frag_wait; 1238 /* Fragments dropped due to errors */ 1239 uint32_t rx_frag_err; 1240 /* Fragments received OOR causing sequence num mismatch */ 1241 uint32_t rx_frag_oor; 1242 /* Fragments dropped due to len errors in skb */ 1243 uint32_t rx_frag_err_len_error; 1244 /* Fragments dropped due to no peer found */ 1245 uint32_t rx_frag_err_no_peer; 1246 /* No of reinjected packets */ 1247 uint32_t reo_reinject; 1248 /* Reap loop packet limit hit */ 1249 uint32_t reap_loop_pkt_limit_hit; 1250 /* Head pointer Out of sync at the end of dp_rx_process */ 1251 uint32_t hp_oos2; 1252 /* Rx ring near full */ 1253 uint32_t near_full; 1254 /* Break ring reaping as not all scattered msdu received */ 1255 uint32_t msdu_scatter_wait_break; 1256 /* Number of bar frames received */ 1257 uint32_t bar_frame; 1258 /* Number of frames routed from rxdma */ 1259 uint32_t rxdma2rel_route_drop; 1260 /* Number of frames routed from reo*/ 1261 uint32_t reo2rel_route_drop; 1262 uint64_t fast_recycled; 1263 /* Number of hw stats requested */ 1264 uint32_t rx_hw_stats_requested; 1265 /* Number of hw stats request timeout */ 1266 uint32_t rx_hw_stats_timeout; 1267 1268 struct { 1269 /* Invalid RBM error count */ 1270 uint32_t invalid_rbm; 1271 /* Invalid VDEV Error count */ 1272 uint32_t invalid_vdev; 1273 /* Invalid PDEV error count */ 1274 uint32_t invalid_pdev; 1275 1276 /* Packets delivered to stack that no related peer */ 1277 uint32_t pkt_delivered_no_peer; 1278 /* Defrag peer uninit error count */ 1279 uint32_t defrag_peer_uninit; 1280 /* Invalid sa_idx or da_idx*/ 1281 uint32_t invalid_sa_da_idx; 1282 /* MSDU DONE failures */ 1283 uint32_t msdu_done_fail; 1284 /* Invalid PEER Error count */ 1285 struct cdp_pkt_info rx_invalid_peer; 1286 /* Invalid PEER ID count */ 1287 struct cdp_pkt_info rx_invalid_peer_id; 1288 /* Invalid packet length */ 1289 struct cdp_pkt_info rx_invalid_pkt_len; 1290 /* HAL ring access Fail error count */ 1291 uint32_t hal_ring_access_fail; 1292 /* HAL ring access full Fail error count */ 1293 uint32_t hal_ring_access_full_fail; 1294 /* RX DMA error count */ 1295 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 1296 /* RX REO DEST Desc Invalid Magic count */ 1297 uint32_t rx_desc_invalid_magic; 1298 /* REO Error count */ 1299 uint32_t reo_error[HAL_REO_ERR_MAX]; 1300 /* HAL REO ERR Count */ 1301 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 1302 /* HAL REO DEST Duplicate count */ 1303 uint32_t hal_reo_dest_dup; 1304 /* HAL WBM RELEASE Duplicate count */ 1305 uint32_t hal_wbm_rel_dup; 1306 /* HAL RXDMA error Duplicate count */ 1307 uint32_t hal_rxdma_err_dup; 1308 /* ipa smmu map duplicate count */ 1309 uint32_t ipa_smmu_map_dup; 1310 /* ipa smmu unmap duplicate count */ 1311 uint32_t ipa_smmu_unmap_dup; 1312 /* ipa smmu unmap while ipa pipes is disabled */ 1313 uint32_t ipa_unmap_no_pipe; 1314 /* REO cmd send fail/requeue count */ 1315 uint32_t reo_cmd_send_fail; 1316 /* REO cmd send drain count */ 1317 uint32_t reo_cmd_send_drain; 1318 /* RX msdu drop count due to scatter */ 1319 uint32_t scatter_msdu; 1320 /* RX msdu drop count due to invalid cookie */ 1321 uint32_t invalid_cookie; 1322 /* Count of stale cookie read in RX path */ 1323 uint32_t stale_cookie; 1324 /* Delba sent count due to RX 2k jump */ 1325 uint32_t rx_2k_jump_delba_sent; 1326 /* RX 2k jump msdu indicated to stack count */ 1327 uint32_t rx_2k_jump_to_stack; 1328 /* RX 2k jump msdu dropped count */ 1329 uint32_t rx_2k_jump_drop; 1330 /* REO ERR msdu buffer received */ 1331 uint32_t reo_err_msdu_buf_rcved; 1332 /* REO ERR msdu buffer with invalid coookie received */ 1333 uint32_t reo_err_msdu_buf_invalid_cookie; 1334 /* REO OOR msdu drop count */ 1335 uint32_t reo_err_oor_drop; 1336 /* REO OOR msdu indicated to stack count */ 1337 uint32_t reo_err_oor_to_stack; 1338 /* REO OOR scattered msdu count */ 1339 uint32_t reo_err_oor_sg_count; 1340 /* RX msdu rejected count on delivery to vdev stack_fn*/ 1341 uint32_t rejected; 1342 /* Incorrect msdu count in MPDU desc info */ 1343 uint32_t msdu_count_mismatch; 1344 /* RX raw frame dropped count */ 1345 uint32_t raw_frm_drop; 1346 /* Stale link desc cookie count*/ 1347 uint32_t invalid_link_cookie; 1348 /* Nbuf sanity failure */ 1349 uint32_t nbuf_sanity_fail; 1350 /* Duplicate link desc refilled */ 1351 uint32_t dup_refill_link_desc; 1352 /* Incorrect msdu continuation bit in MSDU desc */ 1353 uint32_t msdu_continuation_err; 1354 /* count of start sequence (ssn) updates */ 1355 uint32_t ssn_update_count; 1356 /* count of bar handling fail */ 1357 uint32_t bar_handle_fail_count; 1358 /* EAPOL drop count in intrabss scenario */ 1359 uint32_t intrabss_eapol_drop; 1360 /* PN check failed for 2K-jump or OOR error */ 1361 uint32_t pn_in_dest_check_fail; 1362 /* MSDU len err count */ 1363 uint32_t msdu_len_err; 1364 /* Rx flush count */ 1365 uint32_t rx_flush_count; 1366 /* Rx invalid tid count */ 1367 uint32_t rx_invalid_tid_err; 1368 /* Invalid address1 in defrag path*/ 1369 uint32_t defrag_ad1_invalid; 1370 /* decrypt error drop */ 1371 uint32_t decrypt_err_drop; 1372 } err; 1373 1374 /* packet count per core - per ring */ 1375 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 1376 } rx; 1377 1378 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1379 struct reo_cmd_event_history cmd_event_history; 1380 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1381 }; 1382 1383 union dp_align_mac_addr { 1384 uint8_t raw[QDF_MAC_ADDR_SIZE]; 1385 struct { 1386 uint16_t bytes_ab; 1387 uint16_t bytes_cd; 1388 uint16_t bytes_ef; 1389 } align2; 1390 struct { 1391 uint32_t bytes_abcd; 1392 uint16_t bytes_ef; 1393 } align4; 1394 struct __attribute__((__packed__)) { 1395 uint16_t bytes_ab; 1396 uint32_t bytes_cdef; 1397 } align4_2; 1398 }; 1399 1400 /** 1401 * struct dp_ast_free_cb_params - HMWDS free callback cookie 1402 * @mac_addr: ast mac address 1403 * @peer_mac_addr: mac address of peer 1404 * @type: ast entry type 1405 * @vdev_id: vdev_id 1406 * @flags: ast flags 1407 */ 1408 struct dp_ast_free_cb_params { 1409 union dp_align_mac_addr mac_addr; 1410 union dp_align_mac_addr peer_mac_addr; 1411 enum cdp_txrx_ast_entry_type type; 1412 uint8_t vdev_id; 1413 uint32_t flags; 1414 }; 1415 1416 /** 1417 * struct dp_ast_entry - AST entry 1418 * 1419 * @ast_idx: Hardware AST Index 1420 * @peer_id: Next Hop peer_id (for non-WDS nodes, this will be point to 1421 * associated peer with this MAC address) 1422 * @mac_addr: MAC Address for this AST entry 1423 * @next_hop: Set to 1 if this is for a WDS node 1424 * @is_active: flag to indicate active data traffic on this node 1425 * (used for aging out/expiry) 1426 * @ase_list_elem: node in peer AST list 1427 * @is_bss: flag to indicate if entry corresponds to bss peer 1428 * @is_mapped: flag to indicate that we have mapped the AST entry 1429 * in ast_table 1430 * @pdev_id: pdev ID 1431 * @vdev_id: vdev ID 1432 * @ast_hash_value: hast value in HW 1433 * @ref_cnt: reference count 1434 * @type: flag to indicate type of the entry(static/WDS/MEC) 1435 * @delete_in_progress: Flag to indicate that delete commands send to FW 1436 * and host is waiting for response from FW 1437 * @callback: ast free/unmap callback 1438 * @cookie: argument to callback 1439 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 1440 */ 1441 struct dp_ast_entry { 1442 uint16_t ast_idx; 1443 uint16_t peer_id; 1444 union dp_align_mac_addr mac_addr; 1445 bool next_hop; 1446 bool is_active; 1447 bool is_mapped; 1448 uint8_t pdev_id; 1449 uint8_t vdev_id; 1450 uint16_t ast_hash_value; 1451 qdf_atomic_t ref_cnt; 1452 enum cdp_txrx_ast_entry_type type; 1453 bool delete_in_progress; 1454 txrx_ast_free_cb callback; 1455 void *cookie; 1456 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 1457 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 1458 }; 1459 1460 /** 1461 * struct dp_mec_entry - MEC entry 1462 * 1463 * @mac_addr: MAC Address for this MEC entry 1464 * @is_active: flag to indicate active data traffic on this node 1465 * (used for aging out/expiry) 1466 * @pdev_id: pdev ID 1467 * @vdev_id: vdev ID 1468 * @hash_list_elem: node in soc MEC hash list (mac address used as hash) 1469 */ 1470 struct dp_mec_entry { 1471 union dp_align_mac_addr mac_addr; 1472 bool is_active; 1473 uint8_t pdev_id; 1474 uint8_t vdev_id; 1475 1476 TAILQ_ENTRY(dp_mec_entry) hash_list_elem; 1477 }; 1478 1479 /* SOC level htt stats */ 1480 struct htt_t2h_stats { 1481 /* lock to protect htt_stats_msg update */ 1482 qdf_spinlock_t lock; 1483 1484 /* work queue to process htt stats */ 1485 qdf_work_t work; 1486 1487 /* T2H Ext stats message queue */ 1488 qdf_nbuf_queue_t msg; 1489 1490 /* number of completed stats in htt_stats_msg */ 1491 uint32_t num_stats; 1492 }; 1493 1494 struct link_desc_bank { 1495 void *base_vaddr_unaligned; 1496 void *base_vaddr; 1497 qdf_dma_addr_t base_paddr_unaligned; 1498 qdf_dma_addr_t base_paddr; 1499 uint32_t size; 1500 }; 1501 1502 struct rx_buff_pool { 1503 qdf_nbuf_queue_head_t emerg_nbuf_q; 1504 uint32_t nbuf_fail_cnt; 1505 bool is_initialized; 1506 }; 1507 1508 struct rx_refill_buff_pool { 1509 bool is_initialized; 1510 uint16_t head; 1511 uint16_t tail; 1512 struct dp_pdev *dp_pdev; 1513 uint16_t max_bufq_len; 1514 qdf_nbuf_t buf_elem[2048]; 1515 }; 1516 1517 #ifdef DP_TX_HW_DESC_HISTORY 1518 #define DP_TX_HW_DESC_HIST_MAX 6144 1519 #define DP_TX_HW_DESC_HIST_PER_SLOT_MAX 2048 1520 #define DP_TX_HW_DESC_HIST_MAX_SLOTS 3 1521 #define DP_TX_HW_DESC_HIST_SLOT_SHIFT 11 1522 1523 struct dp_tx_hw_desc_evt { 1524 uint8_t tcl_desc[HAL_TX_DESC_LEN_BYTES]; 1525 uint8_t tcl_ring_id; 1526 uint64_t posted; 1527 uint32_t hp; 1528 uint32_t tp; 1529 }; 1530 1531 /* struct dp_tx_hw_desc_history - TX HW desc hisotry 1532 * @index: Index where the last entry is written 1533 * @entry: history entries 1534 */ 1535 struct dp_tx_hw_desc_history { 1536 qdf_atomic_t index; 1537 uint16_t num_entries_per_slot; 1538 uint16_t allocated; 1539 struct dp_tx_hw_desc_evt *entry[DP_TX_HW_DESC_HIST_MAX_SLOTS]; 1540 }; 1541 #endif 1542 1543 /** 1544 * enum dp_mon_status_process_event - Events for monitor status buffer record 1545 * @DP_MON_STATUS_BUF_REAP: Monitor status buffer is reaped from ring 1546 * @DP_MON_STATUS_BUF_ENQUEUE: Status buffer is enqueued to local queue 1547 * @DP_MON_STATUS_BUF_DEQUEUE: Status buffer is dequeued from local queue 1548 */ 1549 enum dp_mon_status_process_event { 1550 DP_MON_STATUS_BUF_REAP, 1551 DP_MON_STATUS_BUF_ENQUEUE, 1552 DP_MON_STATUS_BUF_DEQUEUE, 1553 }; 1554 1555 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 1556 #define DP_MON_STATUS_HIST_MAX 2048 1557 1558 /** 1559 * struct dp_mon_stat_info_record - monitor stat ring buffer info 1560 * @hbi: HW ring buffer info 1561 * @timestamp: timestamp when this entry was recorded 1562 * @event: event 1563 * @rx_desc: RX descriptor corresponding to the received buffer 1564 * @nbuf: buffer attached to rx_desc, if event is REAP, else the buffer 1565 * which was enqueued or dequeued. 1566 * @rx_desc_nbuf_data: nbuf data pointer. 1567 */ 1568 struct dp_mon_stat_info_record { 1569 struct hal_buf_info hbi; 1570 uint64_t timestamp; 1571 enum dp_mon_status_process_event event; 1572 void *rx_desc; 1573 qdf_nbuf_t nbuf; 1574 uint8_t *rx_desc_nbuf_data; 1575 }; 1576 1577 /* struct dp_rx_history - rx ring hisotry 1578 * @index: Index where the last entry is written 1579 * @entry: history entries 1580 */ 1581 struct dp_mon_status_ring_history { 1582 qdf_atomic_t index; 1583 struct dp_mon_stat_info_record entry[DP_MON_STATUS_HIST_MAX]; 1584 }; 1585 #endif 1586 1587 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 1588 /* 1589 * The logic for get current index of these history is dependent on this 1590 * value being power of 2. 1591 */ 1592 #define DP_RX_HIST_MAX 2048 1593 #define DP_RX_ERR_HIST_MAX 2048 1594 #define DP_RX_REINJECT_HIST_MAX 1024 1595 #define DP_RX_REFILL_HIST_MAX 2048 1596 1597 QDF_COMPILE_TIME_ASSERT(rx_history_size, 1598 (DP_RX_HIST_MAX & 1599 (DP_RX_HIST_MAX - 1)) == 0); 1600 QDF_COMPILE_TIME_ASSERT(rx_err_history_size, 1601 (DP_RX_ERR_HIST_MAX & 1602 (DP_RX_ERR_HIST_MAX - 1)) == 0); 1603 QDF_COMPILE_TIME_ASSERT(rx_reinject_history_size, 1604 (DP_RX_REINJECT_HIST_MAX & 1605 (DP_RX_REINJECT_HIST_MAX - 1)) == 0); 1606 QDF_COMPILE_TIME_ASSERT(rx_refill_history_size, 1607 (DP_RX_REFILL_HIST_MAX & 1608 (DP_RX_REFILL_HIST_MAX - 1)) == 0); 1609 1610 1611 /** 1612 * struct dp_buf_info_record - ring buffer info 1613 * @hbi: HW ring buffer info 1614 * @timestamp: timestamp when this entry was recorded 1615 */ 1616 struct dp_buf_info_record { 1617 struct hal_buf_info hbi; 1618 uint64_t timestamp; 1619 }; 1620 1621 /** 1622 * struct dp_refill_info_record - ring refill buffer info 1623 * @hp: HP value after refill 1624 * @tp: cached tail value during refill 1625 * @num_req: number of buffers requested to refill 1626 * @num_refill: number of buffers refilled to ring 1627 * @timestamp: timestamp when this entry was recorded 1628 */ 1629 struct dp_refill_info_record { 1630 uint32_t hp; 1631 uint32_t tp; 1632 uint32_t num_req; 1633 uint32_t num_refill; 1634 uint64_t timestamp; 1635 }; 1636 1637 /** 1638 * struct dp_rx_history - rx ring hisotry 1639 * @index: Index where the last entry is written 1640 * @entry: history entries 1641 */ 1642 struct dp_rx_history { 1643 qdf_atomic_t index; 1644 struct dp_buf_info_record entry[DP_RX_HIST_MAX]; 1645 }; 1646 1647 /** 1648 * struct dp_rx_err_history - rx err ring hisotry 1649 * @index: Index where the last entry is written 1650 * @entry: history entries 1651 */ 1652 struct dp_rx_err_history { 1653 qdf_atomic_t index; 1654 struct dp_buf_info_record entry[DP_RX_ERR_HIST_MAX]; 1655 }; 1656 1657 /** 1658 * struct dp_rx_reinject_history - rx reinject ring hisotry 1659 * @index: Index where the last entry is written 1660 * @entry: history entries 1661 */ 1662 struct dp_rx_reinject_history { 1663 qdf_atomic_t index; 1664 struct dp_buf_info_record entry[DP_RX_REINJECT_HIST_MAX]; 1665 }; 1666 1667 /** 1668 * struct dp_rx_refill_history - rx buf refill hisotry 1669 * @index: Index where the last entry is written 1670 * @entry: history entries 1671 */ 1672 struct dp_rx_refill_history { 1673 qdf_atomic_t index; 1674 struct dp_refill_info_record entry[DP_RX_REFILL_HIST_MAX]; 1675 }; 1676 1677 #endif 1678 1679 /** 1680 * enum dp_cfg_event_type - Datapath config events type 1681 * @DP_CFG_EVENT_VDEV_ATTACH: vdev attach 1682 * @DP_CFG_EVENT_VDEV_DETACH: vdev detach 1683 * @DP_CFG_EVENT_VDEV_UNREF_DEL: vdev memory free after last ref is released 1684 * @DP_CFG_EVENT_PEER_CREATE: peer create 1685 * @DP_CFG_EVENT_PEER_DELETE: peer delete 1686 * @DP_CFG_EVENT_PEER_UNREF_DEL: peer memory free after last ref is released 1687 * @DP_CFG_EVENT_PEER_SETUP: peer setup 1688 * @DP_CFG_EVENT_MLO_ADD_LINK: add link peer to mld peer 1689 * @DP_CFG_EVENT_MLO_DEL_LINK: delete link peer from mld peer 1690 * @DP_CFG_EVENT_MLO_SETUP: MLO peer setup 1691 * @DP_CFG_EVENT_MLO_SETUP_VDEV_UPDATE: MLD peer vdev update 1692 * @DP_CFG_EVENT_PEER_MAP: peer map 1693 * @DP_CFG_EVENT_PEER_UNMAP: peer unmap 1694 * @DP_CFG_EVENT_MLO_PEER_MAP: MLD peer map 1695 * @DP_CFG_EVENT_MLO_PEER_UNMAP: MLD peer unmap 1696 */ 1697 enum dp_cfg_event_type { 1698 DP_CFG_EVENT_VDEV_ATTACH, 1699 DP_CFG_EVENT_VDEV_DETACH, 1700 DP_CFG_EVENT_VDEV_UNREF_DEL, 1701 DP_CFG_EVENT_PEER_CREATE, 1702 DP_CFG_EVENT_PEER_DELETE, 1703 DP_CFG_EVENT_PEER_UNREF_DEL, 1704 DP_CFG_EVENT_PEER_SETUP, 1705 DP_CFG_EVENT_MLO_ADD_LINK, 1706 DP_CFG_EVENT_MLO_DEL_LINK, 1707 DP_CFG_EVENT_MLO_SETUP, 1708 DP_CFG_EVENT_MLO_SETUP_VDEV_UPDATE, 1709 DP_CFG_EVENT_PEER_MAP, 1710 DP_CFG_EVENT_PEER_UNMAP, 1711 DP_CFG_EVENT_MLO_PEER_MAP, 1712 DP_CFG_EVENT_MLO_PEER_UNMAP, 1713 }; 1714 1715 #ifdef WLAN_FEATURE_DP_CFG_EVENT_HISTORY 1716 /* Size must be in 2 power, for bitwise index rotation */ 1717 #define DP_CFG_EVT_HISTORY_SIZE 0x800 1718 #define DP_CFG_EVT_HIST_PER_SLOT_MAX 256 1719 #define DP_CFG_EVT_HIST_MAX_SLOTS 8 1720 #define DP_CFG_EVT_HIST_SLOT_SHIFT 8 1721 1722 /** 1723 * struct dp_vdev_attach_detach_desc - vdev ops descriptor 1724 * @vdev: DP vdev handle 1725 * @mac_addr: vdev mac address 1726 * @vdev_id: vdev id 1727 * @ref_count: vdev ref count 1728 */ 1729 struct dp_vdev_attach_detach_desc { 1730 struct dp_vdev *vdev; 1731 union dp_align_mac_addr mac_addr; 1732 uint8_t vdev_id; 1733 int32_t ref_count; 1734 }; 1735 1736 /** 1737 * struct dp_peer_cmn_ops_desc - peer events descriptor 1738 * @vdev_id: vdev_id of the vdev on which peer exists 1739 * @is_reuse: indicates if its a peer reuse case, during peer create 1740 * @peer: DP peer handle 1741 * @vdev: DP vdev handle on which peer exists 1742 * @mac_addr: peer mac address 1743 * @vdev_mac_addr: vdev mac address 1744 * @vdev_ref_count: vdev ref count 1745 * @peer_ref_count: peer ref count 1746 */ 1747 struct dp_peer_cmn_ops_desc { 1748 uint8_t vdev_id : 5, 1749 is_reuse : 1; 1750 struct dp_peer *peer; 1751 struct dp_vdev *vdev; 1752 union dp_align_mac_addr mac_addr; 1753 union dp_align_mac_addr vdev_mac_addr; 1754 int32_t vdev_ref_count; 1755 int32_t peer_ref_count; 1756 }; 1757 1758 /** 1759 * struct dp_mlo_add_del_link_desc - MLO add/del link event descriptor 1760 * @idx: index at which link peer got added in MLD peer's list 1761 * @num_links: num links added in the MLD peer's list 1762 * @action_result: add/del was success or not 1763 * @reserved: reserved bit 1764 * @link_peer: link peer handle 1765 * @mld_peer: MLD peer handle 1766 * @link_mac_addr: link peer mac address 1767 * @mld_mac_addr: MLD peer mac address 1768 */ 1769 struct dp_mlo_add_del_link_desc { 1770 uint8_t idx : 3, 1771 num_links : 3, 1772 action_result : 1, 1773 reserved : 1; 1774 struct dp_peer *link_peer; 1775 struct dp_peer *mld_peer; 1776 union dp_align_mac_addr link_mac_addr; 1777 union dp_align_mac_addr mld_mac_addr; 1778 }; 1779 1780 /** 1781 * struct dp_mlo_setup_vdev_update_desc - MLD peer vdev update event desc 1782 * @mld_peer: MLD peer handle 1783 * @prev_vdev: previous vdev handle 1784 * @new_vdev: new vdev handle 1785 */ 1786 struct dp_mlo_setup_vdev_update_desc { 1787 struct dp_peer *mld_peer; 1788 struct dp_vdev *prev_vdev; 1789 struct dp_vdev *new_vdev; 1790 }; 1791 1792 /** 1793 * struct dp_rx_peer_map_unmap_desc - peer map/unmap event descriptor 1794 * @peer_id: peer id 1795 * @ml_peer_id: ML peer id, if its an MLD peer 1796 * @hw_peer_id: hw peer id 1797 * @vdev_id: vdev id of the peer 1798 * @is_ml_peer: is this MLD peer 1799 * @mac_addr: mac address of the peer 1800 * @peer: peer handle 1801 */ 1802 struct dp_rx_peer_map_unmap_desc { 1803 uint16_t peer_id; 1804 uint16_t ml_peer_id; 1805 uint16_t hw_peer_id; 1806 uint8_t vdev_id; 1807 uint8_t is_ml_peer; 1808 union dp_align_mac_addr mac_addr; 1809 struct dp_peer *peer; 1810 }; 1811 1812 /** 1813 * struct dp_peer_setup_desc - peer setup event descriptor 1814 * @peer: DP peer handle 1815 * @vdev: vdev handle on which peer exists 1816 * @vdev_ref_count: vdev ref count 1817 * @mac_addr: peer mac address 1818 * @mld_mac_addr: MLD mac address 1819 * @is_first_link: is the current link the first link created 1820 * @is_primary_link: is the current link primary link 1821 * @vdev_id: vdev id of the vdev on which the current link peer exists 1822 * @reserved: reserved bit 1823 */ 1824 struct dp_peer_setup_desc { 1825 struct dp_peer *peer; 1826 struct dp_vdev *vdev; 1827 int32_t vdev_ref_count; 1828 union dp_align_mac_addr mac_addr; 1829 union dp_align_mac_addr mld_mac_addr; 1830 uint8_t is_first_link : 1, 1831 is_primary_link : 1, 1832 vdev_id : 5, 1833 reserved : 1; 1834 }; 1835 1836 /** 1837 * union dp_cfg_event_desc - DP config event descriptor 1838 * @vdev_evt: vdev events desc 1839 * @peer_cmn_evt: common peer events desc 1840 * @peer_setup_evt: peer setup event desc 1841 * @mlo_link_delink_evt: MLO link/delink event desc 1842 * @mlo_setup_vdev_update: MLD peer vdev update event desc 1843 * @peer_map_unmap_evt: peer map/unmap event desc 1844 */ 1845 union dp_cfg_event_desc { 1846 struct dp_vdev_attach_detach_desc vdev_evt; 1847 struct dp_peer_cmn_ops_desc peer_cmn_evt; 1848 struct dp_peer_setup_desc peer_setup_evt; 1849 struct dp_mlo_add_del_link_desc mlo_link_delink_evt; 1850 struct dp_mlo_setup_vdev_update_desc mlo_setup_vdev_update; 1851 struct dp_rx_peer_map_unmap_desc peer_map_unmap_evt; 1852 }; 1853 1854 /** 1855 * struct dp_cfg_event - DP config event descriptor 1856 * @timestamp: timestamp at which event was recorded 1857 * @type: event type 1858 * @event_desc: event descriptor 1859 */ 1860 struct dp_cfg_event { 1861 uint64_t timestamp; 1862 enum dp_cfg_event_type type; 1863 union dp_cfg_event_desc event_desc; 1864 }; 1865 1866 /** 1867 * struct dp_cfg_event_history - DP config event history 1868 * @index: current index 1869 * @num_entries_per_slot: number of entries per slot 1870 * @allocated: Is the history allocated or not 1871 * @entry: event history descriptors 1872 */ 1873 struct dp_cfg_event_history { 1874 qdf_atomic_t index; 1875 uint16_t num_entries_per_slot; 1876 uint16_t allocated; 1877 struct dp_cfg_event *entry[DP_CFG_EVT_HIST_MAX_SLOTS]; 1878 }; 1879 #endif 1880 1881 enum dp_tx_event_type { 1882 DP_TX_DESC_INVAL_EVT = 0, 1883 DP_TX_DESC_MAP, 1884 DP_TX_DESC_COOKIE, 1885 DP_TX_DESC_FLUSH, 1886 DP_TX_DESC_UNMAP, 1887 DP_TX_COMP_UNMAP, 1888 DP_TX_COMP_UNMAP_ERR, 1889 DP_TX_COMP_MSDU_EXT, 1890 }; 1891 1892 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 1893 /* Size must be in 2 power, for bitwise index rotation */ 1894 #define DP_TX_TCL_HISTORY_SIZE 0x4000 1895 #define DP_TX_TCL_HIST_PER_SLOT_MAX 2048 1896 #define DP_TX_TCL_HIST_MAX_SLOTS 8 1897 #define DP_TX_TCL_HIST_SLOT_SHIFT 11 1898 1899 /* Size must be in 2 power, for bitwise index rotation */ 1900 #define DP_TX_COMP_HISTORY_SIZE 0x4000 1901 #define DP_TX_COMP_HIST_PER_SLOT_MAX 2048 1902 #define DP_TX_COMP_HIST_MAX_SLOTS 8 1903 #define DP_TX_COMP_HIST_SLOT_SHIFT 11 1904 1905 struct dp_tx_desc_event { 1906 qdf_nbuf_t skb; 1907 dma_addr_t paddr; 1908 uint32_t sw_cookie; 1909 enum dp_tx_event_type type; 1910 uint64_t ts; 1911 }; 1912 1913 struct dp_tx_tcl_history { 1914 qdf_atomic_t index; 1915 uint16_t num_entries_per_slot; 1916 uint16_t allocated; 1917 struct dp_tx_desc_event *entry[DP_TX_TCL_HIST_MAX_SLOTS]; 1918 }; 1919 1920 struct dp_tx_comp_history { 1921 qdf_atomic_t index; 1922 uint16_t num_entries_per_slot; 1923 uint16_t allocated; 1924 struct dp_tx_desc_event *entry[DP_TX_COMP_HIST_MAX_SLOTS]; 1925 }; 1926 #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */ 1927 1928 /* structure to record recent operation related variable */ 1929 struct dp_last_op_info { 1930 /* last link desc buf info through WBM release ring */ 1931 struct hal_buf_info wbm_rel_link_desc; 1932 /* last link desc buf info through REO reinject ring */ 1933 struct hal_buf_info reo_reinject_link_desc; 1934 }; 1935 1936 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 1937 1938 /** 1939 * struct dp_swlm_tcl_data - params for tcl register write coalescing 1940 * decision making 1941 * @nbuf: TX packet 1942 * @tid: tid for transmitting the current packet 1943 * @num_ll_connections: Number of low latency connections on this vdev 1944 * @ring_id: TCL ring id 1945 * @pkt_len: Packet length 1946 * 1947 * This structure contains the information required by the software 1948 * latency manager to decide on whether to coalesce the current TCL 1949 * register write or not. 1950 */ 1951 struct dp_swlm_tcl_data { 1952 qdf_nbuf_t nbuf; 1953 uint8_t tid; 1954 uint8_t num_ll_connections; 1955 uint8_t ring_id; 1956 uint32_t pkt_len; 1957 }; 1958 1959 /** 1960 * union swlm_data - SWLM query data 1961 * @tcl_data: data for TCL query in SWLM 1962 */ 1963 union swlm_data { 1964 struct dp_swlm_tcl_data *tcl_data; 1965 }; 1966 1967 /** 1968 * struct dp_swlm_ops - SWLM ops 1969 * @tcl_wr_coalesce_check: handler to check if the current TCL register 1970 * write can be coalesced or not 1971 */ 1972 struct dp_swlm_ops { 1973 int (*tcl_wr_coalesce_check)(struct dp_soc *soc, 1974 struct dp_swlm_tcl_data *tcl_data); 1975 }; 1976 1977 /** 1978 * struct dp_swlm_stats - Stats for Software Latency manager. 1979 * @tcl: TCL stats 1980 * @tcl.timer_flush_success: Num TCL HP writes success from timer context 1981 * @tcl.timer_flush_fail: Num TCL HP writes failure from timer context 1982 * @tcl.tid_fail: Num TCL register write coalescing skips, since the pkt 1983 * was being transmitted on a TID above coalescing threshold 1984 * @tcl.sp_frames: Num TCL register write coalescing skips, since the pkt 1985 * being transmitted was a special frame 1986 * @tcl.ll_connection: Num TCL register write coalescing skips, since the 1987 * vdev has low latency connections 1988 * @tcl.bytes_thresh_reached: Num TCL HP writes flush after the coalescing 1989 * bytes threshold was reached 1990 * @tcl.time_thresh_reached: Num TCL HP writes flush after the coalescing 1991 * session time expired 1992 * @tcl.tput_criteria_fail: Num TCL HP writes coalescing fails, since the 1993 * throughput did not meet session threshold 1994 * @tcl.coalesce_success: Num of TCL HP writes coalesced successfully. 1995 * @tcl.coalesce_fail: Num of TCL HP writes coalesces failed 1996 */ 1997 struct dp_swlm_stats { 1998 struct { 1999 uint32_t timer_flush_success; 2000 uint32_t timer_flush_fail; 2001 uint32_t tid_fail; 2002 uint32_t sp_frames; 2003 uint32_t ll_connection; 2004 uint32_t bytes_thresh_reached; 2005 uint32_t time_thresh_reached; 2006 uint32_t tput_criteria_fail; 2007 uint32_t coalesce_success; 2008 uint32_t coalesce_fail; 2009 } tcl[MAX_TCL_DATA_RINGS]; 2010 }; 2011 2012 /** 2013 * struct dp_swlm_tcl_params: Parameters based on TCL for different modules 2014 * in the Software latency manager. 2015 * @soc: DP soc reference 2016 * @ring_id: TCL ring id 2017 * @flush_timer: Timer for flushing the coalesced TCL HP writes 2018 * @sampling_session_tx_bytes: Num bytes transmitted in the sampling time 2019 * @bytes_flush_thresh: Bytes threshold to flush the TCL HP register write 2020 * @coalesce_end_time: End timestamp for current coalescing session 2021 * @bytes_coalesced: Num bytes coalesced in the current session 2022 * @prev_tx_packets: Previous TX packets accounted 2023 * @prev_tx_bytes: Previous TX bytes accounted 2024 * @prev_rx_bytes: Previous RX bytes accounted 2025 * @expire_time: expiry time for sample 2026 * @tput_pass_cnt: threshold throughput pass counter 2027 */ 2028 struct dp_swlm_tcl_params { 2029 struct dp_soc *soc; 2030 uint32_t ring_id; 2031 qdf_timer_t flush_timer; 2032 uint32_t sampling_session_tx_bytes; 2033 uint32_t bytes_flush_thresh; 2034 uint64_t coalesce_end_time; 2035 uint32_t bytes_coalesced; 2036 uint32_t prev_tx_packets; 2037 uint32_t prev_tx_bytes; 2038 uint32_t prev_rx_bytes; 2039 uint64_t expire_time; 2040 uint32_t tput_pass_cnt; 2041 }; 2042 2043 /** 2044 * struct dp_swlm_params: Parameters for different modules in the 2045 * Software latency manager. 2046 * @rx_traffic_thresh: Threshold for RX traffic, to begin TCL register 2047 * write coalescing 2048 * @tx_traffic_thresh: Threshold for TX traffic, to begin TCL register 2049 * write coalescing 2050 * @sampling_time: Sampling time to test the throughput threshold 2051 * @time_flush_thresh: Time threshold to flush the TCL HP register write 2052 * @tx_thresh_multiplier: Multiplier to deduce the bytes threshold after 2053 * which the TCL HP register is written, thereby 2054 * ending the coalescing. 2055 * @tx_pkt_thresh: Threshold for TX packet count, to begin TCL register 2056 * write coalescing 2057 * @tcl: TCL ring specific params 2058 */ 2059 2060 struct dp_swlm_params { 2061 uint32_t rx_traffic_thresh; 2062 uint32_t tx_traffic_thresh; 2063 uint32_t sampling_time; 2064 uint32_t time_flush_thresh; 2065 uint32_t tx_thresh_multiplier; 2066 uint32_t tx_pkt_thresh; 2067 struct dp_swlm_tcl_params tcl[MAX_TCL_DATA_RINGS]; 2068 }; 2069 2070 /** 2071 * struct dp_swlm - Software latency manager context 2072 * @ops: SWLM ops pointers 2073 * @is_enabled: SWLM enabled/disabled 2074 * @is_init: SWLM module initialized 2075 * @stats: SWLM stats 2076 * @params: SWLM SRNG params 2077 * @tcl_flush_timer: flush timer for TCL register writes 2078 */ 2079 struct dp_swlm { 2080 struct dp_swlm_ops *ops; 2081 uint8_t is_enabled:1, 2082 is_init:1; 2083 struct dp_swlm_stats stats; 2084 struct dp_swlm_params params; 2085 }; 2086 #endif 2087 2088 #ifdef IPA_OFFLOAD 2089 /* IPA uC datapath offload Wlan Tx resources */ 2090 struct ipa_dp_tx_rsc { 2091 /* Resource info to be passed to IPA */ 2092 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 2093 void *ipa_tcl_ring_base_vaddr; 2094 uint32_t ipa_tcl_ring_size; 2095 qdf_dma_addr_t ipa_tcl_hp_paddr; 2096 uint32_t alloc_tx_buf_cnt; 2097 2098 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 2099 void *ipa_wbm_ring_base_vaddr; 2100 uint32_t ipa_wbm_ring_size; 2101 qdf_dma_addr_t ipa_wbm_tp_paddr; 2102 /* WBM2SW HP shadow paddr */ 2103 qdf_dma_addr_t ipa_wbm_hp_shadow_paddr; 2104 2105 /* TX buffers populated into the WBM ring */ 2106 void **tx_buf_pool_vaddr_unaligned; 2107 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 2108 }; 2109 2110 /* IPA uC datapath offload Wlan Rx resources */ 2111 struct ipa_dp_rx_rsc { 2112 /* Resource info to be passed to IPA */ 2113 qdf_dma_addr_t ipa_reo_ring_base_paddr; 2114 void *ipa_reo_ring_base_vaddr; 2115 uint32_t ipa_reo_ring_size; 2116 qdf_dma_addr_t ipa_reo_tp_paddr; 2117 2118 /* Resource info to be passed to firmware and IPA */ 2119 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 2120 void *ipa_rx_refill_buf_ring_base_vaddr; 2121 uint32_t ipa_rx_refill_buf_ring_size; 2122 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 2123 }; 2124 #endif 2125 2126 struct dp_tx_msdu_info_s; 2127 /** 2128 * enum dp_context_type- DP Context Type 2129 * @DP_CONTEXT_TYPE_SOC: Context type DP SOC 2130 * @DP_CONTEXT_TYPE_PDEV: Context type DP PDEV 2131 * @DP_CONTEXT_TYPE_VDEV: Context type DP VDEV 2132 * @DP_CONTEXT_TYPE_PEER: Context type DP PEER 2133 * @DP_CONTEXT_TYPE_MON_SOC: Context type DP MON SOC 2134 * @DP_CONTEXT_TYPE_MON_PDEV: Context type DP MON PDEV 2135 * 2136 * Helper enums to be used to retrieve the size of the corresponding 2137 * data structure by passing the type. 2138 */ 2139 enum dp_context_type { 2140 DP_CONTEXT_TYPE_SOC, 2141 DP_CONTEXT_TYPE_PDEV, 2142 DP_CONTEXT_TYPE_VDEV, 2143 DP_CONTEXT_TYPE_PEER, 2144 DP_CONTEXT_TYPE_MON_SOC, 2145 DP_CONTEXT_TYPE_MON_PDEV 2146 }; 2147 2148 /** 2149 * struct dp_arch_ops - DP target specific arch ops 2150 * @txrx_soc_attach: 2151 * @txrx_soc_detach: 2152 * @txrx_soc_init: 2153 * @txrx_soc_deinit: 2154 * @txrx_soc_srng_alloc: 2155 * @txrx_soc_srng_init: 2156 * @txrx_soc_srng_deinit: 2157 * @txrx_soc_srng_free: 2158 * @txrx_pdev_attach: 2159 * @txrx_pdev_detach: 2160 * @txrx_vdev_attach: 2161 * @txrx_vdev_detach: 2162 * @txrx_peer_map_attach: 2163 * @txrx_peer_map_detach: 2164 * @dp_rxdma_ring_sel_cfg: 2165 * @soc_cfg_attach: 2166 * @txrx_peer_setup: 2167 * @peer_get_reo_hash: 2168 * @reo_remap_config: 2169 * @tx_hw_enqueue: enqueue TX data to HW 2170 * @tx_comp_get_params_from_hal_desc: get software tx descriptor and release 2171 * source from HAL desc for wbm release ring 2172 * @dp_tx_mlo_mcast_send: Tx send handler for MLO multicast enhance 2173 * @dp_tx_process_htt_completion: 2174 * @dp_rx_process: 2175 * @dp_tx_send_fast: 2176 * @dp_tx_desc_pool_init: 2177 * @dp_tx_desc_pool_deinit: 2178 * @dp_rx_desc_pool_init: 2179 * @dp_rx_desc_pool_deinit: 2180 * @dp_wbm_get_rx_desc_from_hal_desc: 2181 * @dp_rx_intrabss_mcast_handler: 2182 * @dp_rx_word_mask_subscribe: 2183 * @dp_rx_desc_cookie_2_va: 2184 * @dp_service_near_full_srngs: Handler for servicing the near full IRQ 2185 * @tx_implicit_rbm_set: 2186 * @dp_rx_peer_metadata_peer_id_get: 2187 * @dp_rx_chain_msdus: 2188 * @txrx_set_vdev_param: target specific ops while setting vdev params 2189 * @txrx_get_vdev_mcast_param: target specific ops for getting vdev 2190 * params related to multicast 2191 * @txrx_get_context_size: 2192 * @txrx_get_mon_context_size: 2193 * @dp_srng_test_and_update_nf_params: Check if the srng is in near full state 2194 * and set the near-full params. 2195 * @dp_tx_mcast_handler: 2196 * @dp_rx_mcast_handler: 2197 * @dp_tx_is_mcast_primary: 2198 * @dp_soc_get_by_idle_bm_id: 2199 * @mlo_peer_find_hash_detach: 2200 * @mlo_peer_find_hash_attach: 2201 * @mlo_peer_find_hash_add: 2202 * @mlo_peer_find_hash_remove: 2203 * @mlo_peer_find_hash_find: 2204 * @get_hw_link_id: 2205 * @dp_rx_peer_set_link_id: set link id in nbuf cb 2206 * @get_reo_qdesc_addr: 2207 * @get_rx_hash_key: 2208 * @dp_set_rx_fst: 2209 * @dp_get_rx_fst: 2210 * @dp_rx_fst_deref: 2211 * @dp_rx_fst_ref: 2212 * @txrx_print_peer_stats: 2213 * @dp_peer_rx_reorder_queue_setup: Dp peer reorder queue setup 2214 * @dp_bank_reconfig: 2215 * @dp_get_soc_by_chip_id: Get soc by chip id 2216 * @dp_soc_get_num_soc: 2217 * @dp_reconfig_tx_vdev_mcast_ctrl: 2218 * @dp_cc_reg_cfg_init: 2219 * @dp_tx_compute_hw_delay: 2220 * @print_mlo_ast_stats: 2221 * @dp_partner_chips_map: 2222 * @dp_partner_chips_unmap: 2223 * @ipa_get_bank_id: Get TCL bank id used by IPA 2224 * @ipa_get_wdi_ver: Get WDI version 2225 * @dp_txrx_ppeds_rings_status: 2226 * @dp_tx_ppeds_inuse_desc: 2227 * @dp_ppeds_clear_stats: Clear ppeds related stats 2228 * @dp_tx_ppeds_cfg_astidx_cache_mapping: 2229 * @dp_txrx_ppeds_rings_stats: Printing the util stats of ring 2230 * @dp_txrx_ppeds_clear_rings_stats: Clearing the ring util stats 2231 * @txrx_soc_ppeds_start: 2232 * @txrx_soc_ppeds_stop: 2233 * @dp_register_ppeds_interrupts: 2234 * @dp_free_ppeds_interrupts: 2235 * @dp_rx_wbm_err_reap_desc: Reap WBM Error Ring Descriptor 2236 * @dp_rx_null_q_desc_handle: Handle Null Queue Exception Error 2237 * @dp_tx_desc_pool_alloc: Allocate arch specific TX descriptor pool 2238 * @dp_tx_desc_pool_free: Free arch specific TX descriptor pool 2239 * @txrx_srng_init: Init txrx srng 2240 * @dp_get_vdev_stats_for_unmap_peer: Get vdev stats pointer for unmap peer 2241 * @dp_get_interface_stats: Get interface stats 2242 * @ppeds_handle_attached: 2243 * @txrx_soc_ppeds_interrupt_stop: 2244 * @txrx_soc_ppeds_interrupt_start: 2245 * @txrx_soc_ppeds_service_status_update: 2246 * @txrx_soc_ppeds_enabled_check: 2247 * @txrx_soc_ppeds_txdesc_pool_reset: 2248 * @dp_update_ring_hptp: Update rings hptp during suspend/resume 2249 * @dp_get_fst_cmem_base: Get CMEM base address for FISA 2250 * @dp_flush_tx_ring: Flush TCL ring HP 2251 */ 2252 struct dp_arch_ops { 2253 /* INIT/DEINIT Arch Ops */ 2254 QDF_STATUS (*txrx_soc_attach)(struct dp_soc *soc, 2255 struct cdp_soc_attach_params *params); 2256 QDF_STATUS (*txrx_soc_detach)(struct dp_soc *soc); 2257 void* (*txrx_soc_init)(struct dp_soc *soc, HTC_HANDLE htc_handle, 2258 struct hif_opaque_softc *hif_handle); 2259 QDF_STATUS (*txrx_soc_deinit)(struct dp_soc *soc); 2260 QDF_STATUS (*txrx_soc_srng_alloc)(struct dp_soc *soc); 2261 QDF_STATUS (*txrx_soc_srng_init)(struct dp_soc *soc); 2262 void (*txrx_soc_srng_deinit)(struct dp_soc *soc); 2263 void (*txrx_soc_srng_free)(struct dp_soc *soc); 2264 QDF_STATUS (*txrx_pdev_attach)(struct dp_pdev *pdev, 2265 struct cdp_pdev_attach_params *params); 2266 QDF_STATUS (*txrx_pdev_detach)(struct dp_pdev *pdev); 2267 QDF_STATUS (*txrx_vdev_attach)(struct dp_soc *soc, 2268 struct dp_vdev *vdev); 2269 QDF_STATUS (*txrx_vdev_detach)(struct dp_soc *soc, 2270 struct dp_vdev *vdev); 2271 QDF_STATUS (*txrx_peer_map_attach)(struct dp_soc *soc); 2272 void (*txrx_peer_map_detach)(struct dp_soc *soc); 2273 QDF_STATUS (*dp_rxdma_ring_sel_cfg)(struct dp_soc *soc); 2274 void (*soc_cfg_attach)(struct dp_soc *soc); 2275 QDF_STATUS (*txrx_peer_setup)(struct cdp_soc_t *soc_hdl, 2276 uint8_t vdev_id, uint8_t *peer_mac, 2277 struct cdp_peer_setup_info *setup_info); 2278 void (*peer_get_reo_hash)(struct dp_vdev *vdev, 2279 struct cdp_peer_setup_info *setup_info, 2280 enum cdp_host_reo_dest_ring *reo_dest, 2281 bool *hash_based, 2282 uint8_t *lmac_peer_id_msb); 2283 bool (*reo_remap_config)(struct dp_soc *soc, uint32_t *remap0, 2284 uint32_t *remap1, uint32_t *remap2); 2285 2286 /* TX RX Arch Ops */ 2287 QDF_STATUS (*tx_hw_enqueue)(struct dp_soc *soc, struct dp_vdev *vdev, 2288 struct dp_tx_desc_s *tx_desc, 2289 uint16_t fw_metadata, 2290 struct cdp_tx_exception_metadata *metadata, 2291 struct dp_tx_msdu_info_s *msdu_info); 2292 2293 void (*tx_comp_get_params_from_hal_desc)(struct dp_soc *soc, 2294 void *tx_comp_hal_desc, 2295 struct dp_tx_desc_s **desc); 2296 2297 qdf_nbuf_t (*dp_tx_mlo_mcast_send)(struct dp_soc *soc, 2298 struct dp_vdev *vdev, 2299 qdf_nbuf_t nbuf, 2300 struct cdp_tx_exception_metadata 2301 *tx_exc_metadata); 2302 2303 void (*dp_tx_process_htt_completion)(struct dp_soc *soc, 2304 struct dp_tx_desc_s *tx_desc, 2305 uint8_t *status, 2306 uint8_t ring_id); 2307 2308 uint32_t (*dp_rx_process)(struct dp_intr *int_ctx, 2309 hal_ring_handle_t hal_ring_hdl, 2310 uint8_t reo_ring_num, uint32_t quota); 2311 2312 qdf_nbuf_t (*dp_tx_send_fast)(struct cdp_soc_t *soc_hdl, 2313 uint8_t vdev_id, 2314 qdf_nbuf_t nbuf); 2315 2316 QDF_STATUS (*dp_tx_desc_pool_init)(struct dp_soc *soc, 2317 uint32_t num_elem, 2318 uint8_t pool_id); 2319 void (*dp_tx_desc_pool_deinit)( 2320 struct dp_soc *soc, 2321 struct dp_tx_desc_pool_s *tx_desc_pool, 2322 uint8_t pool_id); 2323 2324 QDF_STATUS (*dp_rx_desc_pool_init)(struct dp_soc *soc, 2325 struct rx_desc_pool *rx_desc_pool, 2326 uint32_t pool_id); 2327 void (*dp_rx_desc_pool_deinit)(struct dp_soc *soc, 2328 struct rx_desc_pool *rx_desc_pool, 2329 uint32_t pool_id); 2330 2331 QDF_STATUS (*dp_wbm_get_rx_desc_from_hal_desc)( 2332 struct dp_soc *soc, 2333 void *ring_desc, 2334 struct dp_rx_desc **r_rx_desc); 2335 2336 bool 2337 (*dp_rx_intrabss_mcast_handler)(struct dp_soc *soc, 2338 struct dp_txrx_peer *ta_txrx_peer, 2339 qdf_nbuf_t nbuf_copy, 2340 struct cdp_tid_rx_stats *tid_stats, 2341 uint8_t link_id); 2342 2343 void (*dp_rx_word_mask_subscribe)( 2344 struct dp_soc *soc, 2345 uint32_t *msg_word, 2346 void *rx_filter); 2347 2348 struct dp_rx_desc *(*dp_rx_desc_cookie_2_va)(struct dp_soc *soc, 2349 uint32_t cookie); 2350 uint32_t (*dp_service_near_full_srngs)(struct dp_soc *soc, 2351 struct dp_intr *int_ctx, 2352 uint32_t dp_budget); 2353 void (*tx_implicit_rbm_set)(struct dp_soc *soc, uint8_t tx_ring_id, 2354 uint8_t bm_id); 2355 uint16_t (*dp_rx_peer_metadata_peer_id_get)(struct dp_soc *soc, 2356 uint32_t peer_metadata); 2357 bool (*dp_rx_chain_msdus)(struct dp_soc *soc, qdf_nbuf_t nbuf, 2358 uint8_t *rx_tlv_hdr, uint8_t mac_id); 2359 /* Control Arch Ops */ 2360 QDF_STATUS (*txrx_set_vdev_param)(struct dp_soc *soc, 2361 struct dp_vdev *vdev, 2362 enum cdp_vdev_param_type param, 2363 cdp_config_param_type val); 2364 2365 QDF_STATUS (*txrx_get_vdev_mcast_param)(struct dp_soc *soc, 2366 struct dp_vdev *vdev, 2367 cdp_config_param_type *val); 2368 2369 /* Misc Arch Ops */ 2370 qdf_size_t (*txrx_get_context_size)(enum dp_context_type); 2371 #ifdef WIFI_MONITOR_SUPPORT 2372 qdf_size_t (*txrx_get_mon_context_size)(enum dp_context_type); 2373 #endif 2374 int (*dp_srng_test_and_update_nf_params)(struct dp_soc *soc, 2375 struct dp_srng *dp_srng, 2376 int *max_reap_limit); 2377 2378 /* MLO ops */ 2379 #ifdef WLAN_FEATURE_11BE_MLO 2380 #ifdef WLAN_MCAST_MLO 2381 void (*dp_tx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 2382 qdf_nbuf_t nbuf); 2383 bool (*dp_rx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 2384 struct dp_txrx_peer *peer, qdf_nbuf_t nbuf, 2385 uint8_t link_id); 2386 bool (*dp_tx_is_mcast_primary)(struct dp_soc *soc, 2387 struct dp_vdev *vdev); 2388 #endif 2389 struct dp_soc * (*dp_soc_get_by_idle_bm_id)(struct dp_soc *soc, 2390 uint8_t bm_id); 2391 2392 void (*mlo_peer_find_hash_detach)(struct dp_soc *soc); 2393 QDF_STATUS (*mlo_peer_find_hash_attach)(struct dp_soc *soc); 2394 void (*mlo_peer_find_hash_add)(struct dp_soc *soc, 2395 struct dp_peer *peer); 2396 void (*mlo_peer_find_hash_remove)(struct dp_soc *soc, 2397 struct dp_peer *peer); 2398 2399 struct dp_peer *(*mlo_peer_find_hash_find)(struct dp_soc *soc, 2400 uint8_t *peer_mac_addr, 2401 int mac_addr_is_aligned, 2402 enum dp_mod_id mod_id, 2403 uint8_t vdev_id); 2404 #endif 2405 uint8_t (*get_hw_link_id)(struct dp_pdev *pdev); 2406 void (*dp_rx_peer_set_link_id)(qdf_nbuf_t nbuf, uint32_t peer_mdata); 2407 uint64_t (*get_reo_qdesc_addr)(hal_soc_handle_t hal_soc_hdl, 2408 uint8_t *dst_ring_desc, 2409 uint8_t *buf, 2410 struct dp_txrx_peer *peer, 2411 unsigned int tid); 2412 void (*get_rx_hash_key)(struct dp_soc *soc, 2413 struct cdp_lro_hash_config *lro_hash); 2414 void (*dp_set_rx_fst)(struct dp_rx_fst *fst); 2415 struct dp_rx_fst *(*dp_get_rx_fst)(void); 2416 uint32_t (*dp_rx_fst_deref)(void); 2417 void (*dp_rx_fst_ref)(void); 2418 void (*txrx_print_peer_stats)(struct cdp_peer_stats *peer_stats, 2419 enum peer_stats_type stats_type); 2420 QDF_STATUS (*dp_peer_rx_reorder_queue_setup)(struct dp_soc *soc, 2421 struct dp_peer *peer, 2422 int tid, 2423 uint32_t ba_window_size); 2424 void (*dp_bank_reconfig)(struct dp_soc *soc, struct dp_vdev *vdev); 2425 2426 struct dp_soc * (*dp_get_soc_by_chip_id)(struct dp_soc *soc, 2427 uint8_t chip_id); 2428 2429 uint8_t (*dp_soc_get_num_soc)(struct dp_soc *soc); 2430 void (*dp_reconfig_tx_vdev_mcast_ctrl)(struct dp_soc *soc, 2431 struct dp_vdev *vdev); 2432 2433 void (*dp_cc_reg_cfg_init)(struct dp_soc *soc, bool is_4k_align); 2434 2435 QDF_STATUS 2436 (*dp_tx_compute_hw_delay)(struct dp_soc *soc, 2437 struct dp_vdev *vdev, 2438 struct hal_tx_completion_status *ts, 2439 uint32_t *delay_us); 2440 void (*print_mlo_ast_stats)(struct dp_soc *soc); 2441 void (*dp_partner_chips_map)(struct dp_soc *soc, 2442 struct dp_peer *peer, 2443 uint16_t peer_id); 2444 void (*dp_partner_chips_unmap)(struct dp_soc *soc, 2445 uint16_t peer_id); 2446 2447 #ifdef IPA_OFFLOAD 2448 int8_t (*ipa_get_bank_id)(struct dp_soc *soc); 2449 void (*ipa_get_wdi_ver)(uint8_t *wdi_ver); 2450 #endif 2451 #ifdef WLAN_SUPPORT_PPEDS 2452 void (*dp_txrx_ppeds_rings_status)(struct dp_soc *soc); 2453 void (*dp_tx_ppeds_inuse_desc)(struct dp_soc *soc); 2454 void (*dp_ppeds_clear_stats)(struct dp_soc *soc); 2455 void (*dp_tx_ppeds_cfg_astidx_cache_mapping)(struct dp_soc *soc, 2456 struct dp_vdev *vdev, 2457 bool peer_map); 2458 void (*dp_txrx_ppeds_rings_stats)(struct dp_soc *soc); 2459 void (*dp_txrx_ppeds_clear_rings_stats)(struct dp_soc *soc); 2460 #endif 2461 bool (*ppeds_handle_attached)(struct dp_soc *soc); 2462 QDF_STATUS (*txrx_soc_ppeds_start)(struct dp_soc *soc); 2463 void (*txrx_soc_ppeds_stop)(struct dp_soc *soc); 2464 int (*dp_register_ppeds_interrupts)(struct dp_soc *soc, 2465 struct dp_srng *srng, int vector, 2466 int ring_type, int ring_num); 2467 void (*dp_free_ppeds_interrupts)(struct dp_soc *soc, 2468 struct dp_srng *srng, int ring_type, 2469 int ring_num); 2470 qdf_nbuf_t (*dp_rx_wbm_err_reap_desc)(struct dp_intr *int_ctx, 2471 struct dp_soc *soc, 2472 hal_ring_handle_t hal_ring_hdl, 2473 uint32_t quota, 2474 uint32_t *rx_bufs_used); 2475 QDF_STATUS (*dp_rx_null_q_desc_handle)(struct dp_soc *soc, 2476 qdf_nbuf_t nbuf, 2477 uint8_t *rx_tlv_hdr, 2478 uint8_t pool_id, 2479 struct dp_txrx_peer *txrx_peer, 2480 bool is_reo_exception, 2481 uint8_t link_id); 2482 2483 QDF_STATUS (*dp_tx_desc_pool_alloc)(struct dp_soc *soc, 2484 uint32_t num_elem, 2485 uint8_t pool_id); 2486 void (*dp_tx_desc_pool_free)(struct dp_soc *soc, uint8_t pool_id); 2487 2488 QDF_STATUS (*txrx_srng_init)(struct dp_soc *soc, struct dp_srng *srng, 2489 int ring_type, int ring_num, int mac_id); 2490 2491 void (*dp_get_vdev_stats_for_unmap_peer)( 2492 struct dp_vdev *vdev, 2493 struct dp_peer *peer, 2494 struct cdp_vdev_stats **vdev_stats); 2495 QDF_STATUS (*dp_get_interface_stats)(struct cdp_soc_t *soc_hdl, 2496 uint8_t vdev_id, 2497 void *buf, 2498 bool is_aggregate); 2499 #ifdef WLAN_SUPPORT_PPEDS 2500 void (*txrx_soc_ppeds_interrupt_stop)(struct dp_soc *soc); 2501 void (*txrx_soc_ppeds_interrupt_start)(struct dp_soc *soc); 2502 void (*txrx_soc_ppeds_service_status_update)(struct dp_soc *soc, 2503 bool enable); 2504 bool (*txrx_soc_ppeds_enabled_check)(struct dp_soc *soc); 2505 void (*txrx_soc_ppeds_txdesc_pool_reset)(struct dp_soc *soc, 2506 qdf_nbuf_t *nbuf_list); 2507 #endif 2508 void (*dp_update_ring_hptp)(struct dp_soc *soc, bool force_flush_tx); 2509 uint64_t (*dp_get_fst_cmem_base)(struct dp_soc *soc, uint64_t size); 2510 int (*dp_flush_tx_ring)(struct dp_pdev *pdev, int ring_id); 2511 }; 2512 2513 /** 2514 * struct dp_soc_features: Data structure holding the SOC level feature flags. 2515 * @pn_in_reo_dest: PN provided by hardware in the REO destination ring. 2516 * @dmac_cmn_src_rxbuf_ring_enabled: Flag to indicate DMAC mode common Rx 2517 * buffer source rings 2518 * @rssi_dbm_conv_support: Rssi dbm conversion support param. 2519 * @umac_hw_reset_support: UMAC HW reset support 2520 * @wds_ext_ast_override_enable: 2521 */ 2522 struct dp_soc_features { 2523 uint8_t pn_in_reo_dest:1, 2524 dmac_cmn_src_rxbuf_ring_enabled:1; 2525 bool rssi_dbm_conv_support; 2526 bool umac_hw_reset_support; 2527 bool wds_ext_ast_override_enable; 2528 }; 2529 2530 enum sysfs_printing_mode { 2531 PRINTING_MODE_DISABLED = 0, 2532 PRINTING_MODE_ENABLED 2533 }; 2534 2535 /** 2536 * typedef notify_pre_reset_fw_callback() - pre-reset callback 2537 * @soc: DP SoC 2538 */ 2539 typedef void (*notify_pre_reset_fw_callback)(struct dp_soc *soc); 2540 2541 #ifdef WLAN_SYSFS_DP_STATS 2542 /** 2543 * struct sysfs_stats_config: Data structure holding stats sysfs config. 2544 * @rw_stats_lock: Lock to read and write to stat_type and pdev_id. 2545 * @sysfs_read_lock: Lock held while another stat req is being executed. 2546 * @sysfs_write_user_buffer: Lock to change buff len, max buf len 2547 * and *buf. 2548 * @sysfs_txrx_fw_request_done: Event to wait for firmware response. 2549 * @stat_type_requested: stat type requested. 2550 * @mac_id: mac id for which stat type are requested. 2551 * @printing_mode: Should a print go through. 2552 * @process_id: Process allowed to write to buffer. 2553 * @curr_buffer_length: Curr length of buffer written 2554 * @max_buffer_length: Max buffer length. 2555 * @buf: Sysfs buffer. 2556 */ 2557 struct sysfs_stats_config { 2558 /* lock held to read stats */ 2559 qdf_spinlock_t rw_stats_lock; 2560 qdf_mutex_t sysfs_read_lock; 2561 qdf_spinlock_t sysfs_write_user_buffer; 2562 qdf_event_t sysfs_txrx_fw_request_done; 2563 uint32_t stat_type_requested; 2564 uint32_t mac_id; 2565 enum sysfs_printing_mode printing_mode; 2566 int process_id; 2567 uint16_t curr_buffer_length; 2568 uint16_t max_buffer_length; 2569 char *buf; 2570 }; 2571 #endif 2572 2573 struct test_mem_free { 2574 unsigned long ts_qdesc_mem_hdl; 2575 qdf_dma_addr_t hw_qdesc_paddr; 2576 void *hw_qdesc_vaddr_align; 2577 void *hw_qdesc_vaddr_unalign; 2578 uint32_t peer_id; 2579 uint32_t tid; 2580 uint8_t chip_id; 2581 unsigned long ts_hw_flush_back; 2582 }; 2583 2584 struct test_qaddr_del { 2585 unsigned long ts_qaddr_del; 2586 uint32_t peer_id; 2587 uint32_t paddr; 2588 uint32_t tid; 2589 uint8_t chip_id; 2590 }; 2591 2592 /* SOC level structure for data path */ 2593 struct dp_soc { 2594 /** 2595 * re-use memory section starts 2596 */ 2597 2598 /* Common base structure - Should be the first member */ 2599 struct cdp_soc_t cdp_soc; 2600 2601 /* SoC Obj */ 2602 struct cdp_ctrl_objmgr_psoc *ctrl_psoc; 2603 2604 /* OS device abstraction */ 2605 qdf_device_t osdev; 2606 2607 /*cce disable*/ 2608 bool cce_disable; 2609 2610 /* WLAN config context */ 2611 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 2612 2613 /* HTT handle for host-fw interaction */ 2614 struct htt_soc *htt_handle; 2615 2616 /* Commint init done */ 2617 qdf_atomic_t cmn_init_done; 2618 2619 /* Opaque hif handle */ 2620 struct hif_opaque_softc *hif_handle; 2621 2622 /* PDEVs on this SOC */ 2623 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 2624 2625 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 2626 struct dp_srng rx_refill_buf_ring[MAX_PDEV_CNT]; 2627 2628 struct dp_srng rxdma_mon_desc_ring[MAX_NUM_LMAC_HW]; 2629 2630 /* RXDMA error destination ring */ 2631 struct dp_srng rxdma_err_dst_ring[MAX_NUM_LMAC_HW]; 2632 2633 /* RXDMA monitor buffer replenish ring */ 2634 struct dp_srng rxdma_mon_buf_ring[MAX_NUM_LMAC_HW]; 2635 2636 /* RXDMA monitor destination ring */ 2637 struct dp_srng rxdma_mon_dst_ring[MAX_NUM_LMAC_HW]; 2638 2639 /* RXDMA monitor status ring. TBD: Check format of this ring */ 2640 struct dp_srng rxdma_mon_status_ring[MAX_NUM_LMAC_HW]; 2641 2642 /* Ring to handover links to hw in monitor mode for SOFTUMAC arch */ 2643 struct dp_srng sw2rxdma_link_ring[MAX_NUM_LMAC_HW]; 2644 2645 /* Number of PDEVs */ 2646 uint8_t pdev_count; 2647 2648 /*ast override support in HW*/ 2649 bool ast_override_support; 2650 2651 /*number of hw dscp tid map*/ 2652 uint8_t num_hw_dscp_tid_map; 2653 2654 /* HAL SOC handle */ 2655 hal_soc_handle_t hal_soc; 2656 2657 /* rx monitor pkt tlv size */ 2658 uint16_t rx_mon_pkt_tlv_size; 2659 /* rx pkt tlv size */ 2660 uint16_t rx_pkt_tlv_size; 2661 /* rx pkt tlv size in current operation mode */ 2662 uint16_t curr_rx_pkt_tlv_size; 2663 2664 struct dp_arch_ops arch_ops; 2665 2666 /* Device ID coming from Bus sub-system */ 2667 uint32_t device_id; 2668 2669 /* Link descriptor pages */ 2670 struct qdf_mem_multi_page_t link_desc_pages; 2671 2672 /* total link descriptors for regular RX and TX */ 2673 uint32_t total_link_descs; 2674 2675 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 2676 struct dp_srng wbm_idle_link_ring; 2677 2678 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 2679 */ 2680 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 2681 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 2682 uint32_t num_scatter_bufs; 2683 2684 /* Tx SW descriptor pool */ 2685 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 2686 2687 /* Tx MSDU Extension descriptor pool */ 2688 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 2689 2690 /* Tx TSO descriptor pool */ 2691 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 2692 2693 /* Tx TSO Num of segments pool */ 2694 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 2695 2696 /* REO destination rings */ 2697 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 2698 2699 /* REO exception ring - See if should combine this with reo_dest_ring */ 2700 struct dp_srng reo_exception_ring; 2701 2702 /* REO reinjection ring */ 2703 struct dp_srng reo_reinject_ring; 2704 2705 /* REO command ring */ 2706 struct dp_srng reo_cmd_ring; 2707 2708 /* REO command status ring */ 2709 struct dp_srng reo_status_ring; 2710 2711 /* WBM Rx release ring */ 2712 struct dp_srng rx_rel_ring; 2713 2714 /* TCL data ring */ 2715 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 2716 2717 /* Number of Tx comp rings */ 2718 uint8_t num_tx_comp_rings; 2719 2720 /* Number of TCL data rings */ 2721 uint8_t num_tcl_data_rings; 2722 2723 /* TCL CMD_CREDIT ring */ 2724 bool init_tcl_cmd_cred_ring; 2725 2726 /* It is used as credit based ring on QCN9000 else command ring */ 2727 struct dp_srng tcl_cmd_credit_ring; 2728 2729 /* TCL command status ring */ 2730 struct dp_srng tcl_status_ring; 2731 2732 /* WBM Tx completion rings */ 2733 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 2734 2735 /* Common WBM link descriptor release ring (SW to WBM) */ 2736 struct dp_srng wbm_desc_rel_ring; 2737 2738 /* DP Interrupts */ 2739 struct dp_intr intr_ctx[WLAN_CFG_INT_NUM_CONTEXTS]; 2740 2741 /* Monitor mode mac id to dp_intr_id map */ 2742 int mon_intr_id_lmac_map[MAX_NUM_LMAC_HW]; 2743 /* Rx SW descriptor pool for RXDMA monitor buffer */ 2744 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 2745 2746 /* Rx SW descriptor pool for RXDMA status buffer */ 2747 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 2748 2749 /* Rx SW descriptor pool for RXDMA buffer */ 2750 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 2751 2752 /* Number of REO destination rings */ 2753 uint8_t num_reo_dest_rings; 2754 2755 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 2756 /* lock to control access to soc TX descriptors */ 2757 qdf_spinlock_t flow_pool_array_lock; 2758 2759 /* pause callback to pause TX queues as per flow control */ 2760 tx_pause_callback pause_cb; 2761 2762 /* flow pool related statistics */ 2763 struct dp_txrx_pool_stats pool_stats; 2764 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 2765 2766 notify_pre_reset_fw_callback notify_fw_callback; 2767 2768 unsigned long service_rings_running; 2769 2770 uint32_t wbm_idle_scatter_buf_size; 2771 2772 /* VDEVs on this SOC */ 2773 struct dp_vdev *vdev_id_map[MAX_VDEV_CNT]; 2774 2775 /* Tx H/W queues lock */ 2776 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 2777 2778 /* Tx ring map for interrupt processing */ 2779 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2780 2781 /* Rx ring map for interrupt processing */ 2782 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2783 2784 /* peer ID to peer object map (array of pointers to peer objects) */ 2785 struct dp_peer **peer_id_to_obj_map; 2786 2787 struct { 2788 unsigned mask; 2789 unsigned idx_bits; 2790 TAILQ_HEAD(, dp_peer) * bins; 2791 } peer_hash; 2792 2793 /* rx defrag state – TBD: do we need this per radio? */ 2794 struct { 2795 struct { 2796 TAILQ_HEAD(, dp_rx_tid_defrag) waitlist; 2797 uint32_t timeout_ms; 2798 uint32_t next_flush_ms; 2799 qdf_spinlock_t defrag_lock; 2800 } defrag; 2801 struct { 2802 int defrag_timeout_check; 2803 int dup_check; 2804 } flags; 2805 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 2806 qdf_spinlock_t reo_cmd_lock; 2807 } rx; 2808 2809 /* optional rx processing function */ 2810 void (*rx_opt_proc)( 2811 struct dp_vdev *vdev, 2812 struct dp_peer *peer, 2813 unsigned tid, 2814 qdf_nbuf_t msdu_list); 2815 2816 /* pool addr for mcast enhance buff */ 2817 struct { 2818 int size; 2819 uint32_t paddr; 2820 uint32_t *vaddr; 2821 struct dp_tx_me_buf_t *freelist; 2822 int buf_in_use; 2823 qdf_dma_mem_context(memctx); 2824 } me_buf; 2825 2826 /* Protect peer hash table */ 2827 DP_MUTEX_TYPE peer_hash_lock; 2828 /* Protect peer_id_to_objmap */ 2829 DP_MUTEX_TYPE peer_map_lock; 2830 2831 /* maximum number of suppoerted peers */ 2832 uint32_t max_peers; 2833 /* maximum value for peer_id */ 2834 uint32_t max_peer_id; 2835 2836 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH 2837 uint32_t peer_id_shift; 2838 uint32_t peer_id_mask; 2839 #endif 2840 2841 /* rx peer metadata field shift and mask configuration */ 2842 uint8_t htt_peer_id_s; 2843 uint32_t htt_peer_id_m; 2844 uint8_t htt_vdev_id_s; 2845 uint32_t htt_vdev_id_m; 2846 uint8_t htt_mld_peer_valid_s; 2847 uint32_t htt_mld_peer_valid_m; 2848 /* rx peer metadata version */ 2849 uint8_t rx_peer_metadata_ver; 2850 2851 /* SoC level data path statistics */ 2852 struct dp_soc_stats stats; 2853 #ifdef WLAN_SYSFS_DP_STATS 2854 /* sysfs config for DP stats */ 2855 struct sysfs_stats_config *sysfs_config; 2856 #endif 2857 /* timestamp to keep track of msdu buffers received on reo err ring */ 2858 uint64_t rx_route_err_start_pkt_ts; 2859 2860 /* Num RX Route err in a given window to keep track of rate of errors */ 2861 uint32_t rx_route_err_in_window; 2862 2863 /* Enable processing of Tx completion status words */ 2864 bool process_tx_status; 2865 bool process_rx_status; 2866 struct dp_ast_entry **ast_table; 2867 struct { 2868 unsigned mask; 2869 unsigned idx_bits; 2870 TAILQ_HEAD(, dp_ast_entry) * bins; 2871 } ast_hash; 2872 2873 #ifdef DP_TX_HW_DESC_HISTORY 2874 struct dp_tx_hw_desc_history tx_hw_desc_history; 2875 #endif 2876 2877 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 2878 struct dp_rx_history *rx_ring_history[MAX_REO_DEST_RINGS]; 2879 struct dp_rx_refill_history *rx_refill_ring_history[MAX_PDEV_CNT]; 2880 struct dp_rx_err_history *rx_err_ring_history; 2881 struct dp_rx_reinject_history *rx_reinject_ring_history; 2882 #endif 2883 2884 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 2885 struct dp_mon_status_ring_history *mon_status_ring_history; 2886 #endif 2887 2888 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 2889 struct dp_tx_tcl_history tx_tcl_history; 2890 struct dp_tx_comp_history tx_comp_history; 2891 #endif 2892 2893 #ifdef WLAN_FEATURE_DP_CFG_EVENT_HISTORY 2894 struct dp_cfg_event_history cfg_event_history; 2895 #endif 2896 2897 qdf_spinlock_t ast_lock; 2898 /*Timer for AST entry ageout maintenance */ 2899 qdf_timer_t ast_aging_timer; 2900 2901 /*Timer counter for WDS AST entry ageout*/ 2902 uint8_t wds_ast_aging_timer_cnt; 2903 bool pending_ageout; 2904 bool ast_offload_support; 2905 bool host_ast_db_enable; 2906 uint32_t max_ast_ageout_count; 2907 uint8_t eapol_over_control_port; 2908 2909 uint8_t sta_mode_search_policy; 2910 qdf_timer_t lmac_reap_timer; 2911 uint8_t lmac_timer_init; 2912 qdf_timer_t int_timer; 2913 uint8_t intr_mode; 2914 uint8_t lmac_polled_mode; 2915 2916 qdf_list_t reo_desc_freelist; 2917 qdf_spinlock_t reo_desc_freelist_lock; 2918 2919 /* htt stats */ 2920 struct htt_t2h_stats htt_stats; 2921 2922 void *external_txrx_handle; /* External data path handle */ 2923 qdf_atomic_t ipa_mapped; 2924 #ifdef IPA_OFFLOAD 2925 struct ipa_dp_tx_rsc ipa_uc_tx_rsc; 2926 #ifdef IPA_WDI3_TX_TWO_PIPES 2927 /* Resources for the alternative IPA TX pipe */ 2928 struct ipa_dp_tx_rsc ipa_uc_tx_rsc_alt; 2929 #endif 2930 2931 struct ipa_dp_rx_rsc ipa_uc_rx_rsc; 2932 #ifdef IPA_WDI3_VLAN_SUPPORT 2933 struct ipa_dp_rx_rsc ipa_uc_rx_rsc_alt; 2934 #endif 2935 qdf_atomic_t ipa_pipes_enabled; 2936 bool ipa_first_tx_db_access; 2937 qdf_spinlock_t ipa_rx_buf_map_lock; 2938 bool ipa_rx_buf_map_lock_initialized; 2939 uint8_t ipa_reo_ctx_lock_required[MAX_REO_DEST_RINGS]; 2940 #endif 2941 2942 #ifdef WLAN_FEATURE_STATS_EXT 2943 struct { 2944 uint32_t rx_mpdu_received; 2945 uint32_t rx_mpdu_missed; 2946 } ext_stats; 2947 qdf_event_t rx_hw_stats_event; 2948 qdf_spinlock_t rx_hw_stats_lock; 2949 bool is_last_stats_ctx_init; 2950 #endif /* WLAN_FEATURE_STATS_EXT */ 2951 2952 /* Indicates HTT map/unmap versions*/ 2953 uint8_t peer_map_unmap_versions; 2954 /* Per peer per Tid ba window size support */ 2955 uint8_t per_tid_basize_max_tid; 2956 /* Soc level flag to enable da_war */ 2957 uint8_t da_war_enabled; 2958 /* number of active ast entries */ 2959 uint32_t num_ast_entries; 2960 /* peer extended rate statistics context at soc level*/ 2961 struct cdp_soc_rate_stats_ctx *rate_stats_ctx; 2962 /* peer extended rate statistics control flag */ 2963 bool peerstats_enabled; 2964 2965 /* 8021p PCP-TID map values */ 2966 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 2967 /* TID map priority value */ 2968 uint8_t tidmap_prty; 2969 /* Pointer to global per ring type specific configuration table */ 2970 struct wlan_srng_cfg *wlan_srng_cfg; 2971 /* Num Tx outstanding on device */ 2972 qdf_atomic_t num_tx_outstanding; 2973 /* Num Tx exception on device */ 2974 qdf_atomic_t num_tx_exception; 2975 /* Num Tx allowed */ 2976 uint32_t num_tx_allowed; 2977 /* Num Regular Tx allowed */ 2978 uint32_t num_reg_tx_allowed; 2979 /* Num Tx allowed for special frames*/ 2980 uint32_t num_tx_spl_allowed; 2981 /* Preferred HW mode */ 2982 uint8_t preferred_hw_mode; 2983 2984 /** 2985 * Flag to indicate whether WAR to address single cache entry 2986 * invalidation bug is enabled or not 2987 */ 2988 bool is_rx_fse_full_cache_invalidate_war_enabled; 2989 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) 2990 /** 2991 * Pointer to DP RX Flow FST at SOC level if 2992 * is_rx_flow_search_table_per_pdev is false 2993 * TBD: rx_fst[num_macs] if we decide to have per mac FST 2994 */ 2995 struct dp_rx_fst *rx_fst; 2996 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 2997 /* SG supported for msdu continued packets from wbm release ring */ 2998 bool wbm_release_desc_rx_sg_support; 2999 bool peer_map_attach_success; 3000 /* Flag to disable mac1 ring interrupts */ 3001 bool disable_mac1_intr; 3002 /* Flag to disable mac2 ring interrupts */ 3003 bool disable_mac2_intr; 3004 3005 struct { 3006 /* 1st msdu in sg for msdu continued packets in wbm rel ring */ 3007 bool wbm_is_first_msdu_in_sg; 3008 /* Wbm sg list head */ 3009 qdf_nbuf_t wbm_sg_nbuf_head; 3010 /* Wbm sg list tail */ 3011 qdf_nbuf_t wbm_sg_nbuf_tail; 3012 uint32_t wbm_sg_desc_msdu_len; 3013 } wbm_sg_param; 3014 /* Number of msdu exception descriptors */ 3015 uint32_t num_msdu_exception_desc; 3016 3017 /* RX buffer params */ 3018 struct rx_buff_pool rx_buff_pool[MAX_PDEV_CNT]; 3019 struct rx_refill_buff_pool rx_refill_buff_pool; 3020 /* Save recent operation related variable */ 3021 struct dp_last_op_info last_op_info; 3022 TAILQ_HEAD(, dp_peer) inactive_peer_list; 3023 qdf_spinlock_t inactive_peer_list_lock; 3024 TAILQ_HEAD(, dp_vdev) inactive_vdev_list; 3025 qdf_spinlock_t inactive_vdev_list_lock; 3026 /* lock to protect vdev_id_map table*/ 3027 qdf_spinlock_t vdev_map_lock; 3028 3029 /* Flow Search Table is in CMEM */ 3030 bool fst_in_cmem; 3031 3032 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 3033 struct dp_swlm swlm; 3034 #endif 3035 3036 #ifdef FEATURE_RUNTIME_PM 3037 /* DP Rx timestamp */ 3038 qdf_time_t rx_last_busy; 3039 /* Dp runtime refcount */ 3040 qdf_atomic_t dp_runtime_refcount; 3041 /* Dp tx pending count in RTPM */ 3042 qdf_atomic_t tx_pending_rtpm; 3043 #endif 3044 /* Invalid buffer that allocated for RX buffer */ 3045 qdf_nbuf_queue_t invalid_buf_queue; 3046 3047 #ifdef FEATURE_MEC 3048 /** @mec_lock: spinlock for MEC table */ 3049 qdf_spinlock_t mec_lock; 3050 /** @mec_cnt: number of active mec entries */ 3051 qdf_atomic_t mec_cnt; 3052 struct { 3053 /** @mask: mask bits */ 3054 uint32_t mask; 3055 /** @idx_bits: index to shift bits */ 3056 uint32_t idx_bits; 3057 /** @bins: MEC table */ 3058 TAILQ_HEAD(, dp_mec_entry) * bins; 3059 } mec_hash; 3060 #endif 3061 3062 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 3063 qdf_list_t reo_desc_deferred_freelist; 3064 qdf_spinlock_t reo_desc_deferred_freelist_lock; 3065 bool reo_desc_deferred_freelist_init; 3066 #endif 3067 /* BM id for first WBM2SW ring */ 3068 uint32_t wbm_sw0_bm_id; 3069 3070 /* Store arch_id from device_id */ 3071 uint16_t arch_id; 3072 3073 /* link desc ID start per device type */ 3074 uint32_t link_desc_id_start; 3075 3076 /* CMEM buffer target reserved for host usage */ 3077 uint64_t cmem_base; 3078 /* CMEM size in bytes */ 3079 uint64_t cmem_total_size; 3080 /* CMEM free size in bytes */ 3081 uint64_t cmem_avail_size; 3082 3083 /* SOC level feature flags */ 3084 struct dp_soc_features features; 3085 3086 #ifdef WIFI_MONITOR_SUPPORT 3087 struct dp_mon_soc *monitor_soc; 3088 #endif 3089 uint8_t rxdma2sw_rings_not_supported:1, 3090 wbm_sg_last_msdu_war:1, 3091 mec_fw_offload:1, 3092 multi_peer_grp_cmd_supported:1, 3093 umac_reset_supported:1; 3094 3095 /* Number of Rx refill rings */ 3096 uint8_t num_rx_refill_buf_rings; 3097 #ifdef FEATURE_RUNTIME_PM 3098 /* flag to indicate vote for runtime_pm for high tput castt*/ 3099 qdf_atomic_t rtpm_high_tput_flag; 3100 #endif 3101 /* Buffer manager ID for idle link descs */ 3102 uint8_t idle_link_bm_id; 3103 qdf_atomic_t ref_count; 3104 3105 unsigned long vdev_stats_id_map; 3106 bool txmon_hw_support; 3107 3108 #ifdef DP_UMAC_HW_RESET_SUPPORT 3109 struct dp_soc_umac_reset_ctx umac_reset_ctx; 3110 #endif 3111 /* PPDU to link_id mapping parameters */ 3112 uint8_t link_id_offset; 3113 uint8_t link_id_bits; 3114 #ifdef FEATURE_RX_LINKSPEED_ROAM_TRIGGER 3115 /* A flag using to decide the switch of rx link speed */ 3116 bool high_throughput; 3117 #endif 3118 bool is_tx_pause; 3119 3120 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 3121 /* number of IPv4 flows inserted */ 3122 qdf_atomic_t ipv4_fse_cnt; 3123 /* number of IPv6 flows inserted */ 3124 qdf_atomic_t ipv6_fse_cnt; 3125 #endif 3126 /* Reo queue ref table items */ 3127 struct reo_queue_ref_table reo_qref; 3128 #ifdef DP_TX_PACKET_INSPECT_FOR_ILP 3129 /* Flag to show if TX ILP is enabled */ 3130 bool tx_ilp_enable; 3131 #endif 3132 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 3133 uint8_t mld_mode_ap; 3134 #endif 3135 struct test_qaddr_del *list_shared_qaddr_del; 3136 struct test_qaddr_del *reo_write_list; 3137 struct test_mem_free *list_qdesc_addr_free; 3138 struct test_mem_free *list_qdesc_addr_alloc; 3139 uint64_t free_addr_list_idx; 3140 uint64_t alloc_addr_list_idx; 3141 uint64_t shared_qaddr_del_idx; 3142 uint64_t write_paddr_list_idx; 3143 }; 3144 3145 #ifdef IPA_OFFLOAD 3146 /** 3147 * struct dp_ipa_resources - Resources needed for IPA 3148 * @tx_ring: 3149 * @tx_num_alloc_buffer: 3150 * @tx_comp_ring: 3151 * @rx_rdy_ring: 3152 * @rx_refill_ring: 3153 * @tx_comp_doorbell_paddr: IPA UC doorbell registers paddr 3154 * @tx_comp_doorbell_vaddr: 3155 * @rx_ready_doorbell_paddr: 3156 * @is_db_ddr_mapped: 3157 * @tx_alt_ring: 3158 * @tx_alt_ring_num_alloc_buffer: 3159 * @tx_alt_comp_ring: 3160 * @tx_alt_comp_doorbell_paddr: IPA UC doorbell registers paddr 3161 * @tx_alt_comp_doorbell_vaddr: 3162 * @rx_alt_rdy_ring: 3163 * @rx_alt_refill_ring: 3164 * @rx_alt_ready_doorbell_paddr: 3165 */ 3166 struct dp_ipa_resources { 3167 qdf_shared_mem_t tx_ring; 3168 uint32_t tx_num_alloc_buffer; 3169 3170 qdf_shared_mem_t tx_comp_ring; 3171 qdf_shared_mem_t rx_rdy_ring; 3172 qdf_shared_mem_t rx_refill_ring; 3173 3174 /* IPA UC doorbell registers paddr */ 3175 qdf_dma_addr_t tx_comp_doorbell_paddr; 3176 uint32_t *tx_comp_doorbell_vaddr; 3177 qdf_dma_addr_t rx_ready_doorbell_paddr; 3178 3179 bool is_db_ddr_mapped; 3180 3181 #ifdef IPA_WDI3_TX_TWO_PIPES 3182 qdf_shared_mem_t tx_alt_ring; 3183 uint32_t tx_alt_ring_num_alloc_buffer; 3184 qdf_shared_mem_t tx_alt_comp_ring; 3185 3186 /* IPA UC doorbell registers paddr */ 3187 qdf_dma_addr_t tx_alt_comp_doorbell_paddr; 3188 uint32_t *tx_alt_comp_doorbell_vaddr; 3189 #endif 3190 #ifdef IPA_WDI3_VLAN_SUPPORT 3191 qdf_shared_mem_t rx_alt_rdy_ring; 3192 qdf_shared_mem_t rx_alt_refill_ring; 3193 qdf_dma_addr_t rx_alt_ready_doorbell_paddr; 3194 #endif 3195 }; 3196 #endif 3197 3198 #define MAX_RX_MAC_RINGS 2 3199 /* Same as NAC_MAX_CLENT */ 3200 #define DP_NAC_MAX_CLIENT 24 3201 3202 /* 3203 * 24 bits cookie size 3204 * 10 bits page id 0 ~ 1023 for MCL 3205 * 3 bits page id 0 ~ 7 for WIN 3206 * WBM Idle List Desc size = 128, 3207 * Num descs per page = 4096/128 = 32 for MCL 3208 * Num descs per page = 2MB/128 = 16384 for WIN 3209 */ 3210 /* 3211 * Macros to setup link descriptor cookies - for link descriptors, we just 3212 * need first 3 bits to store bank/page ID for WIN. The 3213 * remaining bytes will be used to set a unique ID, which will 3214 * be useful in debugging 3215 */ 3216 #ifdef MAX_ALLOC_PAGE_SIZE 3217 #if PAGE_SIZE == 4096 3218 #define LINK_DESC_PAGE_ID_MASK 0x007FE0 3219 #define LINK_DESC_ID_SHIFT 5 3220 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 3221 #elif PAGE_SIZE == 65536 3222 #define LINK_DESC_PAGE_ID_MASK 0x007E00 3223 #define LINK_DESC_ID_SHIFT 9 3224 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x800 3225 #else 3226 #error "Unsupported kernel PAGE_SIZE" 3227 #endif 3228 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 3229 ((((_page_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_desc_id)) 3230 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 3231 (((_cookie) & LINK_DESC_PAGE_ID_MASK) >> LINK_DESC_ID_SHIFT) 3232 #else 3233 #define LINK_DESC_PAGE_ID_MASK 0x7 3234 #define LINK_DESC_ID_SHIFT 3 3235 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 3236 ((((_desc_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_page_id)) 3237 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 3238 ((_cookie) & LINK_DESC_PAGE_ID_MASK) 3239 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 3240 #endif 3241 #define LINK_DESC_ID_START_20_BITS_COOKIE 0x4000 3242 3243 /* same as ieee80211_nac_param */ 3244 enum dp_nac_param_cmd { 3245 /* IEEE80211_NAC_PARAM_ADD */ 3246 DP_NAC_PARAM_ADD = 1, 3247 /* IEEE80211_NAC_PARAM_DEL */ 3248 DP_NAC_PARAM_DEL, 3249 /* IEEE80211_NAC_PARAM_LIST */ 3250 DP_NAC_PARAM_LIST, 3251 }; 3252 3253 /** 3254 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 3255 * @neighbour_peers_macaddr: neighbour peer's mac address 3256 * @vdev: associated vdev 3257 * @ast_entry: ast_entry for neighbour peer 3258 * @rssi: rssi value 3259 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 3260 */ 3261 struct dp_neighbour_peer { 3262 union dp_align_mac_addr neighbour_peers_macaddr; 3263 struct dp_vdev *vdev; 3264 struct dp_ast_entry *ast_entry; 3265 uint8_t rssi; 3266 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 3267 }; 3268 3269 #ifdef WLAN_TX_PKT_CAPTURE_ENH 3270 #define WLAN_TX_PKT_CAPTURE_ENH 1 3271 #define DP_TX_PPDU_PROC_THRESHOLD 8 3272 #define DP_TX_PPDU_PROC_TIMEOUT 10 3273 #endif 3274 3275 /** 3276 * struct ppdu_info - PPDU Status info descriptor 3277 * @ppdu_id: Unique ppduid assigned by firmware for every tx packet 3278 * @sched_cmdid: schedule command id, which will be same in a burst 3279 * @max_ppdu_id: wrap around for ppdu id 3280 * @tsf_l32: 3281 * @tlv_bitmap: 3282 * @last_tlv_cnt: Keep track for missing ppdu tlvs 3283 * @last_user: last ppdu processed for user 3284 * @is_ampdu: set if Ampdu aggregate 3285 * @nbuf: ppdu descriptor payload 3286 * @ppdu_desc: ppdu descriptor 3287 * @ulist: Union of lists 3288 * @ppdu_info_dlist_elem: linked list of ppdu tlvs 3289 * @ppdu_info_slist_elem: Singly linked list (queue) of ppdu tlvs 3290 * @ppdu_info_list_elem: linked list of ppdu tlvs 3291 * @ppdu_info_queue_elem: Singly linked list (queue) of ppdu tlvs 3292 * @compltn_common_tlv: Successful tlv counter from COMPLTN COMMON tlv 3293 * @ack_ba_tlv: Successful tlv counter from ACK BA tlv 3294 * @done: 3295 */ 3296 struct ppdu_info { 3297 uint32_t ppdu_id; 3298 uint32_t sched_cmdid; 3299 uint32_t max_ppdu_id; 3300 uint32_t tsf_l32; 3301 uint16_t tlv_bitmap; 3302 uint16_t last_tlv_cnt; 3303 uint16_t last_user:8, 3304 is_ampdu:1; 3305 qdf_nbuf_t nbuf; 3306 struct cdp_tx_completion_ppdu *ppdu_desc; 3307 #ifdef WLAN_TX_PKT_CAPTURE_ENH 3308 union { 3309 TAILQ_ENTRY(ppdu_info) ppdu_info_dlist_elem; 3310 STAILQ_ENTRY(ppdu_info) ppdu_info_slist_elem; 3311 } ulist; 3312 #define ppdu_info_list_elem ulist.ppdu_info_dlist_elem 3313 #define ppdu_info_queue_elem ulist.ppdu_info_slist_elem 3314 #else 3315 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 3316 #endif 3317 uint8_t compltn_common_tlv; 3318 uint8_t ack_ba_tlv; 3319 bool done; 3320 }; 3321 3322 /** 3323 * struct msdu_completion_info - wbm msdu completion info 3324 * @ppdu_id: Unique ppduid assigned by firmware for every tx packet 3325 * @peer_id: peer_id 3326 * @tid: tid which used during transmit 3327 * @first_msdu: first msdu indication 3328 * @last_msdu: last msdu indication 3329 * @msdu_part_of_amsdu: msdu part of amsdu 3330 * @transmit_cnt: retried count 3331 * @status: transmit status 3332 * @tsf: timestamp which it transmitted 3333 */ 3334 struct msdu_completion_info { 3335 uint32_t ppdu_id; 3336 uint16_t peer_id; 3337 uint8_t tid; 3338 uint8_t first_msdu:1, 3339 last_msdu:1, 3340 msdu_part_of_amsdu:1; 3341 uint8_t transmit_cnt; 3342 uint8_t status; 3343 uint32_t tsf; 3344 }; 3345 3346 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 3347 struct rx_protocol_tag_map { 3348 /* This is the user configured tag for the said protocol type */ 3349 uint16_t tag; 3350 }; 3351 3352 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 3353 /** 3354 * struct rx_protocol_tag_stats - protocol statistics 3355 * @tag_ctr: number of rx msdus matching this tag 3356 */ 3357 struct rx_protocol_tag_stats { 3358 uint32_t tag_ctr; 3359 }; 3360 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 3361 3362 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 3363 3364 #ifdef WLAN_RX_PKT_CAPTURE_ENH 3365 /* Template data to be set for Enhanced RX Monitor packets */ 3366 #define RX_MON_CAP_ENH_TRAILER 0xdeadc0dedeadda7a 3367 3368 /** 3369 * struct dp_rx_mon_enh_trailer_data - Data structure to set a known pattern 3370 * at end of each MSDU in monitor-lite mode 3371 * @reserved1: reserved for future use 3372 * @reserved2: reserved for future use 3373 * @flow_tag: flow tag value read from skb->cb 3374 * @protocol_tag: protocol tag value read from skb->cb 3375 */ 3376 struct dp_rx_mon_enh_trailer_data { 3377 uint16_t reserved1; 3378 uint16_t reserved2; 3379 uint16_t flow_tag; 3380 uint16_t protocol_tag; 3381 }; 3382 #endif /* WLAN_RX_PKT_CAPTURE_ENH */ 3383 3384 #ifdef HTT_STATS_DEBUGFS_SUPPORT 3385 /* Number of debugfs entries created for HTT stats */ 3386 #define PDEV_HTT_STATS_DBGFS_SIZE HTT_DBG_NUM_EXT_STATS 3387 3388 /** 3389 * struct pdev_htt_stats_dbgfs_priv - Structure to maintain debugfs information 3390 * of HTT stats 3391 * @pdev: dp pdev of debugfs entry 3392 * @stats_id: stats id of debugfs entry 3393 */ 3394 struct pdev_htt_stats_dbgfs_priv { 3395 struct dp_pdev *pdev; 3396 uint16_t stats_id; 3397 }; 3398 3399 /** 3400 * struct pdev_htt_stats_dbgfs_cfg - PDEV level data structure for debugfs 3401 * support for HTT stats 3402 * @debugfs_entry: qdf_debugfs directory entry 3403 * @m: qdf debugfs file handler 3404 * @pdev_htt_stats_dbgfs_ops: File operations of entry created 3405 * @priv: HTT stats debugfs private object 3406 * @htt_stats_dbgfs_event: HTT stats event for debugfs support 3407 * @lock: HTT stats debugfs lock 3408 * @htt_stats_dbgfs_msg_process: Function callback to print HTT stats 3409 */ 3410 struct pdev_htt_stats_dbgfs_cfg { 3411 qdf_dentry_t debugfs_entry[PDEV_HTT_STATS_DBGFS_SIZE]; 3412 qdf_debugfs_file_t m; 3413 struct qdf_debugfs_fops 3414 pdev_htt_stats_dbgfs_ops[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 3415 struct pdev_htt_stats_dbgfs_priv priv[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 3416 qdf_event_t htt_stats_dbgfs_event; 3417 qdf_mutex_t lock; 3418 void (*htt_stats_dbgfs_msg_process)(void *data, A_INT32 len); 3419 }; 3420 #endif /* HTT_STATS_DEBUGFS_SUPPORT */ 3421 3422 struct dp_srng_ring_state { 3423 enum hal_ring_type ring_type; 3424 uint32_t sw_head; 3425 uint32_t sw_tail; 3426 uint32_t hw_head; 3427 uint32_t hw_tail; 3428 3429 }; 3430 3431 struct dp_soc_srngs_state { 3432 uint32_t seq_num; 3433 uint32_t max_ring_id; 3434 struct dp_srng_ring_state ring_state[DP_MAX_SRNGS]; 3435 TAILQ_ENTRY(dp_soc_srngs_state) list_elem; 3436 }; 3437 3438 #ifdef WLAN_FEATURE_11BE_MLO 3439 /* struct dp_mlo_sync_timestamp - PDEV level data structure for storing 3440 * MLO timestamp received via HTT msg. 3441 * msg_type: This would be set to HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 3442 * pdev_id: pdev_id 3443 * chip_id: chip_id 3444 * mac_clk_freq: mac clock frequency of the mac HW block in MHz 3445 * sync_tstmp_lo_us: lower 32 bits of the WLAN global time stamp (in us) at 3446 * which last sync interrupt was received 3447 * sync_tstmp_hi_us: upper 32 bits of the WLAN global time stamp (in us) at 3448 * which last sync interrupt was received 3449 * mlo_offset_lo_us: lower 32 bits of the MLO time stamp offset in us 3450 * mlo_offset_hi_us: upper 32 bits of the MLO time stamp offset in us 3451 * mlo_offset_clks: MLO time stamp offset in clock ticks for sub us 3452 * mlo_comp_us: MLO time stamp compensation applied in us 3453 * mlo_comp_clks: MLO time stamp compensation applied in clock ticks 3454 * for sub us resolution 3455 * mlo_comp_timer: period of MLO compensation timer at which compensation 3456 * is applied, in us 3457 */ 3458 struct dp_mlo_sync_timestamp { 3459 uint32_t msg_type:8, 3460 pdev_id:2, 3461 chip_id:2, 3462 rsvd1:4, 3463 mac_clk_freq:16; 3464 uint32_t sync_tstmp_lo_us; 3465 uint32_t sync_tstmp_hi_us; 3466 uint32_t mlo_offset_lo_us; 3467 uint32_t mlo_offset_hi_us; 3468 uint32_t mlo_offset_clks; 3469 uint32_t mlo_comp_us:16, 3470 mlo_comp_clks:10, 3471 rsvd2:6; 3472 uint32_t mlo_comp_timer:22, 3473 rsvd3:10; 3474 }; 3475 #endif 3476 3477 /* PDEV level structure for data path */ 3478 struct dp_pdev { 3479 /** 3480 * Re-use Memory Section Starts 3481 */ 3482 3483 /* PDEV Id */ 3484 uint8_t pdev_id; 3485 3486 /* LMAC Id */ 3487 uint8_t lmac_id; 3488 3489 /* Target pdev Id */ 3490 uint8_t target_pdev_id; 3491 3492 bool pdev_deinit; 3493 3494 /* TXRX SOC handle */ 3495 struct dp_soc *soc; 3496 3497 /* pdev status down or up required to handle dynamic hw 3498 * mode switch between DBS and DBS_SBS. 3499 * 1 = down 3500 * 0 = up 3501 */ 3502 bool is_pdev_down; 3503 3504 /* Enhanced Stats is enabled */ 3505 uint8_t enhanced_stats_en:1, 3506 link_peer_stats:1; 3507 3508 /* Flag to indicate fast RX */ 3509 bool rx_fast_flag; 3510 3511 /* Second ring used to replenish rx buffers */ 3512 struct dp_srng rx_refill_buf_ring2; 3513 #ifdef IPA_WDI3_VLAN_SUPPORT 3514 /* Third ring used to replenish rx buffers */ 3515 struct dp_srng rx_refill_buf_ring3; 3516 #endif 3517 3518 #ifdef FEATURE_DIRECT_LINK 3519 /* Fourth ring used to replenish rx buffers */ 3520 struct dp_srng rx_refill_buf_ring4; 3521 #endif 3522 3523 /* Empty ring used by firmware to post rx buffers to the MAC */ 3524 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 3525 3526 int ch_band_lmac_id_mapping[REG_BAND_UNKNOWN]; 3527 3528 /* wlan_cfg pdev ctxt*/ 3529 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 3530 3531 /** 3532 * TODO: See if we need a ring map here for LMAC rings. 3533 * 1. Monitor rings are currently planning to be processed on receiving 3534 * PPDU end interrupts and hence won't need ring based interrupts. 3535 * 2. Rx buffer rings will be replenished during REO destination 3536 * processing and doesn't require regular interrupt handling - we will 3537 * only handle low water mark interrupts which is not expected 3538 * frequently 3539 */ 3540 3541 /* VDEV list */ 3542 TAILQ_HEAD(, dp_vdev) vdev_list; 3543 3544 /* vdev list lock */ 3545 qdf_spinlock_t vdev_list_lock; 3546 3547 /* Number of vdevs this device have */ 3548 uint16_t vdev_count; 3549 3550 /* PDEV transmit lock */ 3551 qdf_spinlock_t tx_lock; 3552 3553 /*tx_mutex for me*/ 3554 DP_MUTEX_TYPE tx_mutex; 3555 3556 /* msdu chain head & tail */ 3557 qdf_nbuf_t invalid_peer_head_msdu; 3558 qdf_nbuf_t invalid_peer_tail_msdu; 3559 3560 /* Band steering */ 3561 /* TBD */ 3562 3563 /* PDEV level data path statistics */ 3564 struct cdp_pdev_stats stats; 3565 3566 /* Global RX decap mode for the device */ 3567 enum htt_pkt_type rx_decap_mode; 3568 3569 qdf_atomic_t num_tx_outstanding; 3570 int32_t tx_descs_max; 3571 3572 qdf_atomic_t num_tx_exception; 3573 3574 /* MCL specific local peer handle */ 3575 struct { 3576 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 3577 uint8_t freelist; 3578 qdf_spinlock_t lock; 3579 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 3580 } local_peer_ids; 3581 3582 /* dscp_tid_map_*/ 3583 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 3584 3585 /* operating channel */ 3586 struct { 3587 uint8_t num; 3588 uint8_t band; 3589 uint16_t freq; 3590 } operating_channel; 3591 3592 /* pool addr for mcast enhance buff */ 3593 struct { 3594 int size; 3595 uint32_t paddr; 3596 char *vaddr; 3597 struct dp_tx_me_buf_t *freelist; 3598 int buf_in_use; 3599 qdf_dma_mem_context(memctx); 3600 } me_buf; 3601 3602 bool hmmc_tid_override_en; 3603 uint8_t hmmc_tid; 3604 3605 /* Number of VAPs with mcast enhancement enabled */ 3606 qdf_atomic_t mc_num_vap_attached; 3607 3608 qdf_atomic_t stats_cmd_complete; 3609 3610 #ifdef IPA_OFFLOAD 3611 ipa_uc_op_cb_type ipa_uc_op_cb; 3612 void *usr_ctxt; 3613 struct dp_ipa_resources ipa_resource; 3614 #endif 3615 3616 /* TBD */ 3617 3618 /* map this pdev to a particular Reo Destination ring */ 3619 enum cdp_host_reo_dest_ring reo_dest; 3620 3621 /* WDI event handlers */ 3622 struct wdi_event_subscribe_t **wdi_event_list; 3623 3624 bool cfr_rcc_mode; 3625 3626 /* enable time latency check for tx completion */ 3627 bool latency_capture_enable; 3628 3629 /* enable calculation of delay stats*/ 3630 bool delay_stats_flag; 3631 void *dp_txrx_handle; /* Advanced data path handle */ 3632 uint32_t ppdu_id; 3633 bool first_nbuf; 3634 /* Current noise-floor reading for the pdev channel */ 3635 int16_t chan_noise_floor; 3636 3637 /* 3638 * For multiradio device, this flag indicates if 3639 * this radio is primary or secondary. 3640 * 3641 * For HK 1.0, this is used for WAR for the AST issue. 3642 * HK 1.x mandates creation of only 1 AST entry with same MAC address 3643 * across 2 radios. is_primary indicates the radio on which DP should 3644 * install HW AST entry if there is a request to add 2 AST entries 3645 * with same MAC address across 2 radios 3646 */ 3647 uint8_t is_primary; 3648 struct cdp_tx_sojourn_stats sojourn_stats; 3649 qdf_nbuf_t sojourn_buf; 3650 3651 union dp_rx_desc_list_elem_t *free_list_head; 3652 union dp_rx_desc_list_elem_t *free_list_tail; 3653 /* Cached peer_id from htt_peer_details_tlv */ 3654 uint16_t fw_stats_peer_id; 3655 3656 /* qdf_event for fw_peer_stats */ 3657 qdf_event_t fw_peer_stats_event; 3658 3659 /* qdf_event for fw_stats */ 3660 qdf_event_t fw_stats_event; 3661 3662 /* qdf_event for fw__obss_stats */ 3663 qdf_event_t fw_obss_stats_event; 3664 3665 /* To check if request is already sent for obss stats */ 3666 bool pending_fw_obss_stats_response; 3667 3668 /* User configured max number of tx buffers */ 3669 uint32_t num_tx_allowed; 3670 3671 /* 3672 * User configured max num of tx buffers excluding the 3673 * number of buffers reserved for handling special frames 3674 */ 3675 uint32_t num_reg_tx_allowed; 3676 3677 /* User configured max number of tx buffers for the special frames*/ 3678 uint32_t num_tx_spl_allowed; 3679 3680 /* unique cookie required for peer session */ 3681 uint32_t next_peer_cookie; 3682 3683 /* 3684 * Run time enabled when the first protocol tag is added, 3685 * run time disabled when the last protocol tag is deleted 3686 */ 3687 bool is_rx_protocol_tagging_enabled; 3688 3689 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 3690 /* 3691 * The protocol type is used as array index to save 3692 * user provided tag info 3693 */ 3694 struct rx_protocol_tag_map rx_proto_tag_map[RX_PROTOCOL_TAG_MAX]; 3695 3696 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 3697 /* 3698 * Track msdus received from each reo ring separately to avoid 3699 * simultaneous writes from different core 3700 */ 3701 struct rx_protocol_tag_stats 3702 reo_proto_tag_stats[MAX_REO_DEST_RINGS][RX_PROTOCOL_TAG_MAX]; 3703 /* Track msdus received from exception ring separately */ 3704 struct rx_protocol_tag_stats 3705 rx_err_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 3706 struct rx_protocol_tag_stats 3707 mon_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 3708 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 3709 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 3710 3711 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 3712 /** 3713 * Pointer to DP Flow FST at SOC level if 3714 * is_rx_flow_search_table_per_pdev is true 3715 */ 3716 struct dp_rx_fst *rx_fst; 3717 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 3718 3719 #ifdef FEATURE_TSO_STATS 3720 /* TSO Id to index into TSO packet information */ 3721 qdf_atomic_t tso_idx; 3722 #endif /* FEATURE_TSO_STATS */ 3723 3724 #ifdef WLAN_SUPPORT_DATA_STALL 3725 data_stall_detect_cb data_stall_detect_callback; 3726 #endif /* WLAN_SUPPORT_DATA_STALL */ 3727 3728 /* flag to indicate whether LRO hash command has been sent to FW */ 3729 uint8_t is_lro_hash_configured; 3730 3731 #ifdef HTT_STATS_DEBUGFS_SUPPORT 3732 /* HTT stats debugfs params */ 3733 struct pdev_htt_stats_dbgfs_cfg *dbgfs_cfg; 3734 #endif 3735 struct { 3736 qdf_work_t work; 3737 qdf_workqueue_t *work_queue; 3738 uint32_t seq_num; 3739 uint8_t queue_depth; 3740 qdf_spinlock_t list_lock; 3741 3742 TAILQ_HEAD(, dp_soc_srngs_state) list; 3743 } bkp_stats; 3744 #ifdef WIFI_MONITOR_SUPPORT 3745 struct dp_mon_pdev *monitor_pdev; 3746 #endif 3747 #ifdef WLAN_FEATURE_11BE_MLO 3748 struct dp_mlo_sync_timestamp timestamp; 3749 #endif 3750 /* Is isolation mode enabled */ 3751 bool isolation; 3752 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 3753 uint8_t is_first_wakeup_packet; 3754 #endif 3755 #ifdef CONNECTIVITY_PKTLOG 3756 /* packetdump callback functions */ 3757 ol_txrx_pktdump_cb dp_tx_packetdump_cb; 3758 ol_txrx_pktdump_cb dp_rx_packetdump_cb; 3759 #endif 3760 3761 /* Firmware Stats for TLV received from Firmware */ 3762 uint64_t fw_stats_tlv_bitmap_rcvd; 3763 3764 /* For Checking Pending Firmware Response */ 3765 bool pending_fw_stats_response; 3766 }; 3767 3768 struct dp_peer; 3769 3770 #ifdef DP_RX_UDP_OVER_PEER_ROAM 3771 #define WLAN_ROAM_PEER_AUTH_STATUS_NONE 0x0 3772 /* 3773 * This macro is equivalent to macro ROAM_AUTH_STATUS_AUTHENTICATED used 3774 * in connection mgr 3775 */ 3776 #define WLAN_ROAM_PEER_AUTH_STATUS_AUTHENTICATED 0x2 3777 #endif 3778 3779 /* VDEV structure for data path state */ 3780 struct dp_vdev { 3781 /* OS device abstraction */ 3782 qdf_device_t osdev; 3783 3784 /* physical device that is the parent of this virtual device */ 3785 struct dp_pdev *pdev; 3786 3787 /* VDEV operating mode */ 3788 enum wlan_op_mode opmode; 3789 3790 /* VDEV subtype */ 3791 enum wlan_op_subtype subtype; 3792 3793 /* Tx encapsulation type for this VAP */ 3794 enum htt_cmn_pkt_type tx_encap_type; 3795 3796 /* Rx Decapsulation type for this VAP */ 3797 enum htt_cmn_pkt_type rx_decap_type; 3798 3799 /* WDS enabled */ 3800 bool wds_enabled; 3801 3802 /* MEC enabled */ 3803 bool mec_enabled; 3804 3805 #ifdef QCA_SUPPORT_WDS_EXTENDED 3806 bool wds_ext_enabled; 3807 bool drop_tx_mcast; 3808 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 3809 bool drop_3addr_mcast; 3810 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 3811 bool skip_bar_update; 3812 unsigned long skip_bar_update_last_ts; 3813 #endif 3814 /* WDS Aging timer period */ 3815 uint32_t wds_aging_timer_val; 3816 3817 /* NAWDS enabled */ 3818 bool nawds_enabled; 3819 3820 /* Multicast enhancement enabled */ 3821 uint8_t mcast_enhancement_en; 3822 3823 /* IGMP multicast enhancement enabled */ 3824 uint8_t igmp_mcast_enhanc_en; 3825 3826 /* vdev_id - ID used to specify a particular vdev to the target */ 3827 uint8_t vdev_id; 3828 3829 /* Default HTT meta data for this VDEV */ 3830 /* TBD: check alignment constraints */ 3831 uint16_t htt_tcl_metadata; 3832 3833 /* vdev lmac_id */ 3834 uint8_t lmac_id; 3835 3836 /* vdev bank_id */ 3837 uint8_t bank_id; 3838 3839 /* Mesh mode vdev */ 3840 uint32_t mesh_vdev; 3841 3842 /* Mesh mode rx filter setting */ 3843 uint32_t mesh_rx_filter; 3844 3845 /* DSCP-TID mapping table ID */ 3846 uint8_t dscp_tid_map_id; 3847 3848 /* Address search type to be set in TX descriptor */ 3849 uint8_t search_type; 3850 3851 /* 3852 * Flag to indicate if s/w tid classification should be 3853 * skipped 3854 */ 3855 uint8_t skip_sw_tid_classification; 3856 3857 /* Flag to enable peer authorization */ 3858 uint8_t peer_authorize; 3859 3860 /* AST hash value for BSS peer in HW valid for STA VAP*/ 3861 uint16_t bss_ast_hash; 3862 3863 /* AST hash index for BSS peer in HW valid for STA VAP*/ 3864 uint16_t bss_ast_idx; 3865 3866 bool multipass_en; 3867 3868 /* Address search flags to be configured in HAL descriptor */ 3869 uint8_t hal_desc_addr_search_flags; 3870 3871 /* Handle to the OS shim SW's virtual device */ 3872 ol_osif_vdev_handle osif_vdev; 3873 3874 /* MAC address */ 3875 union dp_align_mac_addr mac_addr; 3876 3877 #ifdef WLAN_FEATURE_11BE_MLO 3878 /* MLO MAC address corresponding to vdev */ 3879 union dp_align_mac_addr mld_mac_addr; 3880 #if defined(WLAN_MLO_MULTI_CHIP) && defined(WLAN_MCAST_MLO) 3881 uint8_t mlo_vdev:1, 3882 is_bridge_vdev:1, 3883 reserved_1:6; 3884 #endif 3885 #endif 3886 3887 /* node in the pdev's list of vdevs */ 3888 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 3889 3890 /* dp_peer list */ 3891 TAILQ_HEAD(, dp_peer) peer_list; 3892 /* to protect peer_list */ 3893 DP_MUTEX_TYPE peer_list_lock; 3894 3895 /* RX call back function to flush GRO packets*/ 3896 ol_txrx_rx_gro_flush_ind_fp osif_gro_flush; 3897 /* default RX call back function called by dp */ 3898 ol_txrx_rx_fp osif_rx; 3899 #ifdef QCA_SUPPORT_EAPOL_OVER_CONTROL_PORT 3900 /* callback to receive eapol frames */ 3901 ol_txrx_rx_fp osif_rx_eapol; 3902 #endif 3903 /* callback to deliver rx frames to the OS */ 3904 ol_txrx_rx_fp osif_rx_stack; 3905 /* Callback to handle rx fisa frames */ 3906 ol_txrx_fisa_rx_fp osif_fisa_rx; 3907 ol_txrx_fisa_flush_fp osif_fisa_flush; 3908 3909 /* call back function to flush out queued rx packets*/ 3910 ol_txrx_rx_flush_fp osif_rx_flush; 3911 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 3912 ol_txrx_get_key_fp osif_get_key; 3913 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 3914 3915 #ifdef notyet 3916 /* callback to check if the msdu is an WAI (WAPI) frame */ 3917 ol_rx_check_wai_fp osif_check_wai; 3918 #endif 3919 3920 /* proxy arp function */ 3921 ol_txrx_proxy_arp_fp osif_proxy_arp; 3922 3923 ol_txrx_mcast_me_fp me_convert; 3924 3925 /* completion function used by this vdev*/ 3926 ol_txrx_completion_fp tx_comp; 3927 3928 ol_txrx_get_tsf_time get_tsf_time; 3929 3930 /* callback to classify critical packets */ 3931 ol_txrx_classify_critical_pkt_fp tx_classify_critical_pkt_cb; 3932 3933 /* deferred vdev deletion state */ 3934 struct { 3935 /* VDEV delete pending */ 3936 int pending; 3937 /* 3938 * callback and a context argument to provide a 3939 * notification for when the vdev is deleted. 3940 */ 3941 ol_txrx_vdev_delete_cb callback; 3942 void *context; 3943 } delete; 3944 3945 /* tx data delivery notification callback function */ 3946 struct { 3947 ol_txrx_data_tx_cb func; 3948 void *ctxt; 3949 } tx_non_std_data_callback; 3950 3951 3952 /* safe mode control to bypass the encrypt and decipher process*/ 3953 uint32_t safemode; 3954 3955 /* rx filter related */ 3956 uint32_t drop_unenc; 3957 #ifdef notyet 3958 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 3959 uint32_t filters_num; 3960 #endif 3961 /* TDLS Link status */ 3962 bool tdls_link_connected; 3963 bool is_tdls_frame; 3964 3965 /* per vdev rx nbuf queue */ 3966 qdf_nbuf_queue_t rxq; 3967 3968 uint8_t tx_ring_id; 3969 struct dp_tx_desc_pool_s *tx_desc; 3970 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 3971 3972 /* Capture timestamp of previous tx packet enqueued */ 3973 uint64_t prev_tx_enq_tstamp; 3974 3975 /* Capture timestamp of previous rx packet delivered */ 3976 uint64_t prev_rx_deliver_tstamp; 3977 3978 /* VDEV Stats */ 3979 struct cdp_vdev_stats stats; 3980 3981 /* Is this a proxySTA VAP */ 3982 uint8_t proxysta_vdev : 1, /* Is this a proxySTA VAP */ 3983 wrap_vdev : 1, /* Is this a QWRAP AP VAP */ 3984 isolation_vdev : 1, /* Is this a QWRAP AP VAP */ 3985 reserved : 5; /* Reserved */ 3986 3987 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 3988 struct dp_tx_desc_pool_s *pool; 3989 #endif 3990 /* AP BRIDGE enabled */ 3991 bool ap_bridge_enabled; 3992 3993 enum cdp_sec_type sec_type; 3994 3995 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 3996 bool raw_mode_war; 3997 3998 3999 /* 8021p PCP-TID mapping table ID */ 4000 uint8_t tidmap_tbl_id; 4001 4002 /* 8021p PCP-TID map values */ 4003 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 4004 4005 /* TIDmap priority */ 4006 uint8_t tidmap_prty; 4007 4008 #ifdef QCA_MULTIPASS_SUPPORT 4009 uint16_t *iv_vlan_map; 4010 4011 /* dp_peer special list */ 4012 TAILQ_HEAD(, dp_txrx_peer) mpass_peer_list; 4013 DP_MUTEX_TYPE mpass_peer_mutex; 4014 #endif 4015 /* Extended data path handle */ 4016 struct cdp_ext_vdev *vdev_dp_ext_handle; 4017 #ifdef VDEV_PEER_PROTOCOL_COUNT 4018 /* 4019 * Rx-Ingress and Tx-Egress are in the lower level DP layer 4020 * Rx-Egress and Tx-ingress are handled in osif layer for DP 4021 * So 4022 * Rx-Egress and Tx-ingress mask definitions are in OSIF layer 4023 * Rx-Ingress and Tx-Egress definitions are here below 4024 */ 4025 #define VDEV_PEER_PROTOCOL_RX_INGRESS_MASK 1 4026 #define VDEV_PEER_PROTOCOL_TX_INGRESS_MASK 2 4027 #define VDEV_PEER_PROTOCOL_RX_EGRESS_MASK 4 4028 #define VDEV_PEER_PROTOCOL_TX_EGRESS_MASK 8 4029 bool peer_protocol_count_track; 4030 int peer_protocol_count_dropmask; 4031 #endif 4032 /* callback to collect connectivity stats */ 4033 ol_txrx_stats_rx_fp stats_cb; 4034 uint32_t num_peers; 4035 /* entry to inactive_list*/ 4036 TAILQ_ENTRY(dp_vdev) inactive_list_elem; 4037 4038 #ifdef WLAN_SUPPORT_RX_FISA 4039 /** 4040 * Params used for controlling the fisa aggregation dynamically 4041 */ 4042 uint8_t fisa_disallowed[MAX_REO_DEST_RINGS]; 4043 uint8_t fisa_force_flushed[MAX_REO_DEST_RINGS]; 4044 #endif 4045 /* 4046 * Refcount for VDEV currently incremented when 4047 * peer is created for VDEV 4048 */ 4049 qdf_atomic_t ref_cnt; 4050 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 4051 uint8_t num_latency_critical_conn; 4052 #ifdef WLAN_SUPPORT_MESH_LATENCY 4053 uint8_t peer_tid_latency_enabled; 4054 /* tid latency configuration parameters */ 4055 struct { 4056 uint32_t service_interval; 4057 uint32_t burst_size; 4058 uint8_t latency_tid; 4059 } mesh_tid_latency_config; 4060 #endif 4061 #ifdef WIFI_MONITOR_SUPPORT 4062 struct dp_mon_vdev *monitor_vdev; 4063 #endif 4064 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY) 4065 /* Delta between TQM clock and TSF clock */ 4066 uint32_t delta_tsf; 4067 #endif 4068 #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY 4069 /* Indicate if uplink delay report is enabled or not */ 4070 qdf_atomic_t ul_delay_report; 4071 /* accumulative delay for every TX completion */ 4072 qdf_atomic_t ul_delay_accum; 4073 /* accumulative number of packets delay has accumulated */ 4074 qdf_atomic_t ul_pkts_accum; 4075 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */ 4076 4077 /* vdev_stats_id - ID used for stats collection by FW from HW*/ 4078 uint8_t vdev_stats_id; 4079 #ifdef HW_TX_DELAY_STATS_ENABLE 4080 /* hw tx delay stats enable */ 4081 uint8_t hw_tx_delay_stats_enabled; 4082 #endif 4083 #ifdef DP_RX_UDP_OVER_PEER_ROAM 4084 uint32_t roaming_peer_status; 4085 union dp_align_mac_addr roaming_peer_mac; 4086 #endif 4087 #ifdef DP_TRAFFIC_END_INDICATION 4088 /* per vdev feature enable/disable status */ 4089 bool traffic_end_ind_en; 4090 /* per vdev nbuf queue for traffic end indication packets */ 4091 qdf_nbuf_queue_t end_ind_pkt_q; 4092 #endif 4093 #ifdef FEATURE_DIRECT_LINK 4094 /* Flag to indicate if to_fw should be set for tx pkts on this vdev */ 4095 bool to_fw; 4096 #endif 4097 /* QDF VDEV operating mode */ 4098 enum QDF_OPMODE qdf_opmode; 4099 4100 #ifdef WLAN_TX_PKT_CAPTURE_ENH 4101 /* TX capture feature to over ride return buffer manager */ 4102 bool is_override_rbm_id; 4103 /* Return buffer manager ID */ 4104 uint8_t rbm_id; 4105 #endif 4106 }; 4107 4108 enum { 4109 dp_sec_mcast = 0, 4110 dp_sec_ucast 4111 }; 4112 4113 #ifdef WDS_VENDOR_EXTENSION 4114 typedef struct { 4115 uint8_t wds_tx_mcast_4addr:1, 4116 wds_tx_ucast_4addr:1, 4117 wds_rx_filter:1, /* enforce rx filter */ 4118 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 4119 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 4120 4121 } dp_ecm_policy; 4122 #endif 4123 4124 /** 4125 * struct dp_peer_cached_bufq - cached_bufq to enqueue rx packets 4126 * @cached_bufq: nbuff list to enqueue rx packets 4127 * @bufq_lock: spinlock for nbuff list access 4128 * @thresh: maximum threshold for number of rx buff to enqueue 4129 * @entries: number of entries 4130 * @dropped: number of packets dropped 4131 */ 4132 struct dp_peer_cached_bufq { 4133 qdf_list_t cached_bufq; 4134 qdf_spinlock_t bufq_lock; 4135 uint32_t thresh; 4136 uint32_t entries; 4137 uint32_t dropped; 4138 }; 4139 4140 /** 4141 * enum dp_peer_ast_flowq 4142 * @DP_PEER_AST_FLOWQ_HI_PRIO: Hi Priority flow queue 4143 * @DP_PEER_AST_FLOWQ_LOW_PRIO: Low priority flow queue 4144 * @DP_PEER_AST_FLOWQ_UDP: flow queue type is UDP 4145 * @DP_PEER_AST_FLOWQ_NON_UDP: flow queue type is Non UDP 4146 * @DP_PEER_AST_FLOWQ_MAX: max value 4147 */ 4148 enum dp_peer_ast_flowq { 4149 DP_PEER_AST_FLOWQ_HI_PRIO, 4150 DP_PEER_AST_FLOWQ_LOW_PRIO, 4151 DP_PEER_AST_FLOWQ_UDP, 4152 DP_PEER_AST_FLOWQ_NON_UDP, 4153 DP_PEER_AST_FLOWQ_MAX, 4154 }; 4155 4156 /** 4157 * struct dp_ast_flow_override_info - ast override info 4158 * @ast_idx: ast indexes in peer map message 4159 * @ast_valid_mask: ast valid mask for each ast index 4160 * @ast_flow_mask: ast flow mask for each ast index 4161 * @tid_valid_low_pri_mask: per tid mask for low priority flow 4162 * @tid_valid_hi_pri_mask: per tid mask for hi priority flow 4163 */ 4164 struct dp_ast_flow_override_info { 4165 uint16_t ast_idx[DP_PEER_AST_FLOWQ_MAX]; 4166 uint8_t ast_valid_mask; 4167 uint8_t ast_flow_mask[DP_PEER_AST_FLOWQ_MAX]; 4168 uint8_t tid_valid_low_pri_mask; 4169 uint8_t tid_valid_hi_pri_mask; 4170 }; 4171 4172 #if defined(WLAN_FEATURE_11BE_MLO) && defined(DP_MLO_LINK_STATS_SUPPORT) 4173 /** 4174 * struct dp_peer_ext_evt_info - peer extended event info 4175 * @peer_id: peer_id from firmware 4176 * @vdev_id: vdev ID 4177 * @link_id: Link ID 4178 * @link_id_valid: link_id_valid 4179 * @peer_mac_addr: mac address of the peer 4180 */ 4181 struct dp_peer_ext_evt_info { 4182 uint16_t peer_id; 4183 uint8_t vdev_id; 4184 uint8_t link_id; 4185 bool link_id_valid; 4186 uint8_t *peer_mac_addr; 4187 }; 4188 #endif 4189 4190 /** 4191 * struct dp_peer_ast_params - ast parameters for a msdu flow-queue 4192 * @ast_idx: ast index populated by FW 4193 * @is_valid: ast flow valid mask 4194 * @valid_tid_mask: per tid mask for this ast index 4195 * @flowQ: flow queue id associated with this ast index 4196 */ 4197 struct dp_peer_ast_params { 4198 uint16_t ast_idx; 4199 uint8_t is_valid; 4200 uint8_t valid_tid_mask; 4201 uint8_t flowQ; 4202 }; 4203 4204 #define DP_MLO_FLOW_INFO_MAX 3 4205 4206 /** 4207 * struct dp_mlo_flow_override_info - Flow override info 4208 * @ast_idx: Primary TCL AST Index 4209 * @ast_idx_valid: Is AST index valid 4210 * @chip_id: CHIP ID 4211 * @tidmask: tidmask 4212 * @cache_set_num: Cache set number 4213 */ 4214 struct dp_mlo_flow_override_info { 4215 uint16_t ast_idx; 4216 uint8_t ast_idx_valid; 4217 uint8_t chip_id; 4218 uint8_t tidmask; 4219 uint8_t cache_set_num; 4220 }; 4221 4222 /** 4223 * struct dp_mlo_link_info - Link info 4224 * @peer_chip_id: Peer Chip ID 4225 * @vdev_id: Vdev ID 4226 */ 4227 struct dp_mlo_link_info { 4228 uint8_t peer_chip_id; 4229 uint8_t vdev_id; 4230 }; 4231 4232 #ifdef WLAN_SUPPORT_MSCS 4233 /*MSCS Procedure based macros */ 4234 #define IEEE80211_MSCS_MAX_ELEM_SIZE 5 4235 #define IEEE80211_TCLAS_MASK_CLA_TYPE_4 4 4236 /** 4237 * struct dp_peer_mscs_parameter - MSCS database obtained from 4238 * MSCS Request and Response in the control path. This data is used 4239 * by the AP to find out what priority to set based on the tuple 4240 * classification during packet processing. 4241 * @user_priority_bitmap: User priority bitmap obtained during 4242 * handshake 4243 * @user_priority_limit: User priority limit obtained during 4244 * handshake 4245 * @classifier_mask: params to be compared during processing 4246 */ 4247 struct dp_peer_mscs_parameter { 4248 uint8_t user_priority_bitmap; 4249 uint8_t user_priority_limit; 4250 uint8_t classifier_mask; 4251 }; 4252 #endif 4253 4254 #ifdef QCA_SUPPORT_WDS_EXTENDED 4255 #define WDS_EXT_PEER_INIT_BIT 0 4256 4257 /** 4258 * struct dp_wds_ext_peer - wds ext peer structure 4259 * This is used when wds extended feature is enabled 4260 * both compile time and run time. It is created 4261 * when 1st 4 address frame is received from 4262 * wds backhaul. 4263 * @osif_peer: Handle to the OS shim SW's virtual device 4264 * @init: wds ext netdev state 4265 */ 4266 struct dp_wds_ext_peer { 4267 ol_osif_peer_handle osif_peer; 4268 unsigned long init; 4269 }; 4270 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 4271 4272 #ifdef WLAN_SUPPORT_MESH_LATENCY 4273 /*Advanced Mesh latency feature based macros */ 4274 4275 /** 4276 * struct dp_peer_mesh_latency_parameter - Mesh latency related 4277 * parameters. This data is updated per peer per TID based on 4278 * the flow tuple classification in external rule database 4279 * during packet processing. 4280 * @service_interval_dl: Service interval associated with TID in DL 4281 * @burst_size_dl: Burst size additive over multiple flows in DL 4282 * @service_interval_ul: Service interval associated with TID in UL 4283 * @burst_size_ul: Burst size additive over multiple flows in UL 4284 * @ac: custom ac derived from service interval 4285 * @msduq: MSDU queue number within TID 4286 */ 4287 struct dp_peer_mesh_latency_parameter { 4288 uint32_t service_interval_dl; 4289 uint32_t burst_size_dl; 4290 uint32_t service_interval_ul; 4291 uint32_t burst_size_ul; 4292 uint8_t ac; 4293 uint8_t msduq; 4294 }; 4295 #endif 4296 4297 #ifdef WLAN_FEATURE_11BE_MLO 4298 /* Max number of links for MLO connection */ 4299 #define DP_MAX_MLO_LINKS 4 4300 4301 /** 4302 * struct dp_peer_link_info - link peer information for MLO 4303 * @mac_addr: Mac address 4304 * @vdev_id: Vdev ID for current link peer 4305 * @is_valid: flag for link peer info valid or not 4306 * @chip_id: chip id 4307 */ 4308 struct dp_peer_link_info { 4309 union dp_align_mac_addr mac_addr; 4310 uint8_t vdev_id; 4311 uint8_t is_valid; 4312 uint8_t chip_id; 4313 }; 4314 4315 /** 4316 * struct dp_mld_link_peers - this structure is used to get link peers 4317 * pointer from mld peer 4318 * @link_peers: link peers pointer array 4319 * @num_links: number of link peers fetched 4320 */ 4321 struct dp_mld_link_peers { 4322 struct dp_peer *link_peers[DP_MAX_MLO_LINKS]; 4323 uint8_t num_links; 4324 }; 4325 #else 4326 #define DP_MAX_MLO_LINKS 0 4327 #endif 4328 4329 typedef void *dp_txrx_ref_handle; 4330 4331 /** 4332 * struct dp_peer_per_pkt_tx_stats- Peer Tx stats updated in per pkt 4333 * Tx completion path 4334 * @ucast: Unicast Packet Count 4335 * @mcast: Multicast Packet Count 4336 * @bcast: Broadcast Packet Count 4337 * @nawds_mcast: NAWDS Multicast Packet Count 4338 * @tx_success: Successful Tx Packets 4339 * @nawds_mcast_drop: NAWDS Multicast Drop Count 4340 * @ofdma: Total Packets as ofdma 4341 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 4342 * @amsdu_cnt: Number of MSDUs part of AMSDU 4343 * @dropped: Dropped packet statistics 4344 * @dropped.fw_rem: Discarded by firmware 4345 * @dropped.fw_rem_notx: firmware_discard_untransmitted 4346 * @dropped.fw_rem_tx: firmware_discard_transmitted 4347 * @dropped.age_out: aged out in mpdu/msdu queues 4348 * @dropped.fw_reason1: discarded by firmware reason 1 4349 * @dropped.fw_reason2: discarded by firmware reason 2 4350 * @dropped.fw_reason3: discarded by firmware reason 3 4351 * @dropped.fw_rem_no_match: dropped due to fw no match command 4352 * @dropped.drop_threshold: dropped due to HW threshold 4353 * @dropped.drop_link_desc_na: dropped due resource not available in HW 4354 * @dropped.invalid_drop: Invalid msdu drop 4355 * @dropped.mcast_vdev_drop: MCAST drop configured for VDEV in HW 4356 * @dropped.invalid_rr: Invalid TQM release reason 4357 * @failed_retry_count: packets failed due to retry above 802.11 retry limit 4358 * @retry_count: packets successfully send after one or more retry 4359 * @multiple_retry_count: packets successfully sent after more than one retry 4360 * @no_ack_count: no ack pkt count for different protocols 4361 * @tx_success_twt: Successful Tx Packets in TWT session 4362 * @last_tx_ts: last timestamp in jiffies when tx comp occurred 4363 * @avg_sojourn_msdu: Avg sojourn msdu stat 4364 * @protocol_trace_cnt: per-peer protocol counter 4365 * @release_src_not_tqm: Counter to keep track of release source is not TQM 4366 * in TX completion status processing 4367 * @inval_link_id_pkt_cnt: Counter to capture Invalid Link Id 4368 */ 4369 struct dp_peer_per_pkt_tx_stats { 4370 struct cdp_pkt_info ucast; 4371 struct cdp_pkt_info mcast; 4372 struct cdp_pkt_info bcast; 4373 struct cdp_pkt_info nawds_mcast; 4374 struct cdp_pkt_info tx_success; 4375 uint32_t nawds_mcast_drop; 4376 uint32_t ofdma; 4377 uint32_t non_amsdu_cnt; 4378 uint32_t amsdu_cnt; 4379 struct { 4380 struct cdp_pkt_info fw_rem; 4381 uint32_t fw_rem_notx; 4382 uint32_t fw_rem_tx; 4383 uint32_t age_out; 4384 uint32_t fw_reason1; 4385 uint32_t fw_reason2; 4386 uint32_t fw_reason3; 4387 uint32_t fw_rem_queue_disable; 4388 uint32_t fw_rem_no_match; 4389 uint32_t drop_threshold; 4390 uint32_t drop_link_desc_na; 4391 uint32_t invalid_drop; 4392 uint32_t mcast_vdev_drop; 4393 uint32_t invalid_rr; 4394 } dropped; 4395 uint32_t failed_retry_count; 4396 uint32_t retry_count; 4397 uint32_t multiple_retry_count; 4398 uint32_t no_ack_count[QDF_PROTO_SUBTYPE_MAX]; 4399 struct cdp_pkt_info tx_success_twt; 4400 unsigned long last_tx_ts; 4401 qdf_ewma_tx_lag avg_sojourn_msdu[CDP_DATA_TID_MAX]; 4402 #ifdef VDEV_PEER_PROTOCOL_COUNT 4403 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 4404 #endif 4405 uint32_t release_src_not_tqm; 4406 uint32_t inval_link_id_pkt_cnt; 4407 }; 4408 4409 /** 4410 * struct dp_peer_extd_tx_stats - Peer Tx stats updated in either 4411 * per pkt Tx completion path when macro QCA_ENHANCED_STATS_SUPPORT is 4412 * disabled or in HTT Tx PPDU completion path when macro is enabled 4413 * @stbc: Packets in STBC 4414 * @ldpc: Packets in LDPC 4415 * @retries: Packet retries 4416 * @pkt_type: pkt count for different .11 modes 4417 * @wme_ac_type: Wireless Multimedia type Count 4418 * @excess_retries_per_ac: Wireless Multimedia type Count 4419 * @ampdu_cnt: completion of aggregation 4420 * @non_ampdu_cnt: tx completion not aggregated 4421 * @num_ppdu_cookie_valid: no. of valid ppdu cookies rcvd from FW 4422 * @tx_ppdus: ppdus in tx 4423 * @tx_mpdus_success: mpdus successful in tx 4424 * @tx_mpdus_tried: mpdus tried in tx 4425 * @tx_rate: Tx Rate in kbps 4426 * @last_tx_rate: Last tx rate for unicast packets 4427 * @last_tx_rate_mcs: Tx rate mcs for unicast packets 4428 * @mcast_last_tx_rate: Last tx rate for multicast packets 4429 * @mcast_last_tx_rate_mcs: Last tx rate mcs for multicast 4430 * @rnd_avg_tx_rate: Rounded average tx rate 4431 * @avg_tx_rate: Average TX rate 4432 * @tx_ratecode: Tx rate code of last frame 4433 * @pream_punct_cnt: Preamble Punctured count 4434 * @sgi_count: SGI count 4435 * @nss: Packet count for different num_spatial_stream values 4436 * @bw: Packet Count for different bandwidths 4437 * @ru_start: RU start index 4438 * @ru_tones: RU tones size 4439 * @ru_loc: pkt info for RU location 26/ 52/ 106/ 242/ 484 counter 4440 * @transmit_type: pkt info for tx transmit type 4441 * @mu_group_id: mumimo mu group id 4442 * @last_ack_rssi: RSSI of last acked packet 4443 * @nss_info: NSS 1,2, ...8 4444 * @mcs_info: MCS index 4445 * @bw_info: Bandwidth 4446 * <enum 0 bw_20_MHz> 4447 * <enum 1 bw_40_MHz> 4448 * <enum 2 bw_80_MHz> 4449 * <enum 3 bw_160_MHz> 4450 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 4451 * <enum 1 0_4_us_sgi > Legacy short GI 4452 * <enum 2 1_6_us_sgi > HE related GI 4453 * <enum 3 3_2_us_sgi > HE 4454 * @preamble_info: preamble 4455 * @tx_ucast_total: total ucast count 4456 * @tx_ucast_success: total ucast success count 4457 * @retries_mpdu: mpdu number of successfully transmitted after retries 4458 * @mpdu_success_with_retries: mpdu retry count in case of successful tx 4459 * @su_be_ppdu_cnt: SU Tx packet count for 11BE 4460 * @mu_be_ppdu_cnt: MU Tx packet count for 11BE 4461 * @punc_bw: MSDU count for punctured bw 4462 * @rts_success: RTS success count 4463 * @rts_failure: RTS failure count 4464 * @bar_cnt: Block ACK Request frame count 4465 * @ndpa_cnt: NDP announcement frame count 4466 * @rssi_chain: rssi chain 4467 * @wme_ac_type_bytes: Wireless Multimedia bytes Count 4468 */ 4469 struct dp_peer_extd_tx_stats { 4470 uint32_t stbc; 4471 uint32_t ldpc; 4472 uint32_t retries; 4473 struct cdp_pkt_type pkt_type[DOT11_MAX]; 4474 uint32_t wme_ac_type[WME_AC_MAX]; 4475 uint32_t excess_retries_per_ac[WME_AC_MAX]; 4476 uint32_t ampdu_cnt; 4477 uint32_t non_ampdu_cnt; 4478 uint32_t num_ppdu_cookie_valid; 4479 uint32_t tx_ppdus; 4480 uint32_t tx_mpdus_success; 4481 uint32_t tx_mpdus_tried; 4482 4483 uint32_t tx_rate; 4484 uint32_t last_tx_rate; 4485 uint32_t last_tx_rate_mcs; 4486 uint32_t mcast_last_tx_rate; 4487 uint32_t mcast_last_tx_rate_mcs; 4488 uint64_t rnd_avg_tx_rate; 4489 uint64_t avg_tx_rate; 4490 uint16_t tx_ratecode; 4491 4492 uint32_t sgi_count[MAX_GI]; 4493 uint32_t pream_punct_cnt; 4494 uint32_t nss[SS_COUNT]; 4495 uint32_t bw[MAX_BW]; 4496 uint32_t ru_start; 4497 uint32_t ru_tones; 4498 struct cdp_tx_pkt_info ru_loc[MAX_RU_LOCATIONS]; 4499 4500 struct cdp_tx_pkt_info transmit_type[MAX_TRANSMIT_TYPES]; 4501 uint32_t mu_group_id[MAX_MU_GROUP_ID]; 4502 4503 uint32_t last_ack_rssi; 4504 4505 uint32_t nss_info:4, 4506 mcs_info:4, 4507 bw_info:4, 4508 gi_info:4, 4509 preamble_info:4; 4510 4511 uint32_t retries_mpdu; 4512 uint32_t mpdu_success_with_retries; 4513 struct cdp_pkt_info tx_ucast_total; 4514 struct cdp_pkt_info tx_ucast_success; 4515 #ifdef WLAN_FEATURE_11BE 4516 struct cdp_pkt_type su_be_ppdu_cnt; 4517 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 4518 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 4519 #endif 4520 uint32_t rts_success; 4521 uint32_t rts_failure; 4522 uint32_t bar_cnt; 4523 uint32_t ndpa_cnt; 4524 int32_t rssi_chain[CDP_RSSI_CHAIN_LEN]; 4525 uint64_t wme_ac_type_bytes[WME_AC_MAX]; 4526 }; 4527 4528 /** 4529 * struct dp_peer_per_pkt_rx_stats - Peer Rx stats updated in per pkt Rx path 4530 * @rcvd_reo: Packets received on the reo ring 4531 * @rx_lmac: Packets received on each lmac 4532 * @unicast: Total unicast packets 4533 * @multicast: Total multicast packets 4534 * @bcast: Broadcast Packet Count 4535 * @raw: Raw Pakets received 4536 * @nawds_mcast_drop: Total NAWDS multicast packets dropped 4537 * @mec_drop: Total MEC packets dropped 4538 * @ppeds_drop: Total DS packets dropped 4539 * @last_rx_ts: last timestamp in jiffies when RX happened 4540 * @intra_bss: Intra BSS statistics 4541 * @intra_bss.pkts: Intra BSS packets received 4542 * @intra_bss.fail: Intra BSS packets failed 4543 * @intra_bss.mdns_no_fws: Intra BSS MDNS packets not forwarded 4544 * @err: error counters 4545 * @err.mic_err: Rx MIC errors CCMP 4546 * @err.decrypt_err: Rx Decryption Errors CRC 4547 * @err.fcserr: rx MIC check failed (CCMP) 4548 * @err.pn_err: pn check failed 4549 * @err.oor_err: Rx OOR errors 4550 * @err.jump_2k_err: 2k jump errors 4551 * @err.rxdma_wifi_parse_err: rxdma wifi parse errors 4552 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 4553 * @amsdu_cnt: Number of MSDUs part of AMSDU 4554 * @rx_retries: retries of packet in rx 4555 * @multipass_rx_pkt_drop: Dropped multipass rx pkt 4556 * @peer_unauth_rx_pkt_drop: Unauth rx packet drops 4557 * @policy_check_drop: policy check drops 4558 * @to_stack_twt: Total packets sent up the stack in TWT session 4559 * @protocol_trace_cnt: per-peer protocol counters 4560 * @mcast_3addr_drop: 4561 * @rx_total: total rx count 4562 * @inval_link_id_pkt_cnt: Counter to capture Invalid Link Id 4563 */ 4564 struct dp_peer_per_pkt_rx_stats { 4565 struct cdp_pkt_info rcvd_reo[CDP_MAX_RX_RINGS]; 4566 struct cdp_pkt_info rx_lmac[CDP_MAX_LMACS]; 4567 struct cdp_pkt_info unicast; 4568 struct cdp_pkt_info multicast; 4569 struct cdp_pkt_info bcast; 4570 struct cdp_pkt_info raw; 4571 uint32_t nawds_mcast_drop; 4572 struct cdp_pkt_info mec_drop; 4573 struct cdp_pkt_info ppeds_drop; 4574 unsigned long last_rx_ts; 4575 struct { 4576 struct cdp_pkt_info pkts; 4577 struct cdp_pkt_info fail; 4578 uint32_t mdns_no_fwd; 4579 } intra_bss; 4580 struct { 4581 uint32_t mic_err; 4582 uint32_t decrypt_err; 4583 uint32_t fcserr; 4584 uint32_t pn_err; 4585 uint32_t oor_err; 4586 uint32_t jump_2k_err; 4587 uint32_t rxdma_wifi_parse_err; 4588 } err; 4589 uint32_t non_amsdu_cnt; 4590 uint32_t amsdu_cnt; 4591 uint32_t rx_retries; 4592 uint32_t multipass_rx_pkt_drop; 4593 uint32_t peer_unauth_rx_pkt_drop; 4594 uint32_t policy_check_drop; 4595 struct cdp_pkt_info to_stack_twt; 4596 #ifdef VDEV_PEER_PROTOCOL_COUNT 4597 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 4598 #endif 4599 uint32_t mcast_3addr_drop; 4600 #ifdef IPA_OFFLOAD 4601 struct cdp_pkt_info rx_total; 4602 #endif 4603 uint32_t inval_link_id_pkt_cnt; 4604 }; 4605 4606 /** 4607 * struct dp_peer_extd_rx_stats - Peer Rx stats updated in either 4608 * per pkt Rx path when macro QCA_ENHANCED_STATS_SUPPORT is disabled or in 4609 * Rx monitor patch when macro is enabled 4610 * @pkt_type: pkt counter for different .11 modes 4611 * @wme_ac_type: Wireless Multimedia type Count 4612 * @mpdu_cnt_fcs_ok: SU Rx success mpdu count 4613 * @mpdu_cnt_fcs_err: SU Rx fail mpdu count 4614 * @non_ampdu_cnt: Number of MSDUs with no MPDU level aggregation 4615 * @ampdu_cnt: Number of MSDUs part of AMSPU 4616 * @rx_mpdus: mpdu in rx 4617 * @rx_ppdus: ppdu in rx 4618 * @su_ax_ppdu_cnt: SU Rx packet count for .11ax 4619 * @rx_mu: Rx MU stats 4620 * @reception_type: Reception type of packets 4621 * @ppdu_cnt: PPDU packet count in reception type 4622 * @sgi_count: sgi count 4623 * @nss: packet count in spatiel Streams 4624 * @ppdu_nss: PPDU packet count in spatial streams 4625 * @bw: Packet Count in different bandwidths 4626 * @rx_mpdu_cnt: rx mpdu count per MCS rate 4627 * @rx_rate: Rx rate 4628 * @last_rx_rate: Previous rx rate 4629 * @rnd_avg_rx_rate: Rounded average rx rate 4630 * @avg_rx_rate: Average Rx rate 4631 * @rx_ratecode: Rx rate code of last frame 4632 * @avg_snr: Average snr 4633 * @rx_snr_measured_time: Time at which snr is measured 4634 * @snr: SNR of received signal 4635 * @last_snr: Previous snr 4636 * @nss_info: NSS 1,2, ...8 4637 * @mcs_info: MCS index 4638 * @bw_info: Bandwidth 4639 * <enum 0 bw_20_MHz> 4640 * <enum 1 bw_40_MHz> 4641 * <enum 2 bw_80_MHz> 4642 * <enum 3 bw_160_MHz> 4643 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 4644 * <enum 1 0_4_us_sgi > Legacy short GI 4645 * <enum 2 1_6_us_sgi > HE related GI 4646 * <enum 3 3_2_us_sgi > HE 4647 * @preamble_info: preamble 4648 * @mpdu_retry_cnt: retries of mpdu in rx 4649 * @su_be_ppdu_cnt: SU Rx packet count for BE 4650 * @mu_be_ppdu_cnt: MU rx packet count for BE 4651 * @punc_bw: MSDU count for punctured bw 4652 * @bar_cnt: Block ACK Request frame count 4653 * @ndpa_cnt: NDP announcement frame count 4654 * @wme_ac_type_bytes: Wireless Multimedia type Bytes Count 4655 */ 4656 struct dp_peer_extd_rx_stats { 4657 struct cdp_pkt_type pkt_type[DOT11_MAX]; 4658 uint32_t wme_ac_type[WME_AC_MAX]; 4659 uint32_t mpdu_cnt_fcs_ok; 4660 uint32_t mpdu_cnt_fcs_err; 4661 uint32_t non_ampdu_cnt; 4662 uint32_t ampdu_cnt; 4663 uint32_t rx_mpdus; 4664 uint32_t rx_ppdus; 4665 4666 struct cdp_pkt_type su_ax_ppdu_cnt; 4667 struct cdp_rx_mu rx_mu[TXRX_TYPE_MU_MAX]; 4668 uint32_t reception_type[MAX_RECEPTION_TYPES]; 4669 uint32_t ppdu_cnt[MAX_RECEPTION_TYPES]; 4670 4671 uint32_t sgi_count[MAX_GI]; 4672 uint32_t nss[SS_COUNT]; 4673 uint32_t ppdu_nss[SS_COUNT]; 4674 uint32_t bw[MAX_BW]; 4675 uint32_t rx_mpdu_cnt[MAX_MCS]; 4676 4677 uint32_t rx_rate; 4678 uint32_t last_rx_rate; 4679 uint32_t rnd_avg_rx_rate; 4680 uint32_t avg_rx_rate; 4681 uint32_t rx_ratecode; 4682 4683 uint32_t avg_snr; 4684 unsigned long rx_snr_measured_time; 4685 uint8_t snr; 4686 uint8_t last_snr; 4687 4688 uint32_t nss_info:4, 4689 mcs_info:4, 4690 bw_info:4, 4691 gi_info:4, 4692 preamble_info:4; 4693 4694 uint32_t mpdu_retry_cnt; 4695 #ifdef WLAN_FEATURE_11BE 4696 struct cdp_pkt_type su_be_ppdu_cnt; 4697 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 4698 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 4699 #endif 4700 uint32_t bar_cnt; 4701 uint32_t ndpa_cnt; 4702 uint64_t wme_ac_type_bytes[WME_AC_MAX]; 4703 }; 4704 4705 /** 4706 * struct dp_peer_per_pkt_stats - Per pkt stats for peer 4707 * @tx: Per pkt Tx stats 4708 * @rx: Per pkt Rx stats 4709 */ 4710 struct dp_peer_per_pkt_stats { 4711 struct dp_peer_per_pkt_tx_stats tx; 4712 struct dp_peer_per_pkt_rx_stats rx; 4713 }; 4714 4715 /** 4716 * struct dp_peer_extd_stats - Stats from extended path for peer 4717 * @tx: Extended path tx stats 4718 * @rx: Extended path rx stats 4719 */ 4720 struct dp_peer_extd_stats { 4721 struct dp_peer_extd_tx_stats tx; 4722 struct dp_peer_extd_rx_stats rx; 4723 }; 4724 4725 /** 4726 * struct dp_peer_stats - Peer stats 4727 * @per_pkt_stats: Per packet path stats 4728 * @extd_stats: Extended path stats 4729 */ 4730 struct dp_peer_stats { 4731 struct dp_peer_per_pkt_stats per_pkt_stats; 4732 #ifndef QCA_ENHANCED_STATS_SUPPORT 4733 struct dp_peer_extd_stats extd_stats; 4734 #endif 4735 }; 4736 4737 /** 4738 * struct dp_txrx_peer: DP txrx_peer structure used in per pkt path 4739 * @vdev: VDEV to which this peer is associated 4740 * @peer_id: peer ID for this peer 4741 * @authorize: Set when authorized 4742 * @in_twt: in TWT session 4743 * @hw_txrx_stats_en: Indicate HW offload vdev stats 4744 * @is_mld_peer:1: MLD peer 4745 * @tx_failed: Total Tx failure 4746 * @comp_pkt: Pkt Info for which completions were received 4747 * @to_stack: Total packets sent up the stack 4748 * @delay_stats: Peer delay stats 4749 * @jitter_stats: Peer jitter stats 4750 * @security: Security credentials 4751 * @nawds_enabled: NAWDS flag 4752 * @bss_peer: set for bss peer 4753 * @isolation: enable peer isolation for this peer 4754 * @wds_enabled: WDS peer 4755 * @wds_ecm: 4756 * @flush_in_progress: 4757 * @bufq_info: 4758 * @mpass_peer_list_elem: node in the special peer list element 4759 * @vlan_id: vlan id for key 4760 * @wds_ext: 4761 * @osif_rx: 4762 * @rx_tid: 4763 * @sawf_stats: 4764 * @bw: bandwidth of peer connection 4765 * @mpdu_retry_threshold: MPDU retry threshold to increment tx bad count 4766 * @stats_arr_size: peer stats array size 4767 * @stats: Peer link and mld statistics 4768 */ 4769 struct dp_txrx_peer { 4770 struct dp_vdev *vdev; 4771 uint16_t peer_id; 4772 uint8_t authorize:1, 4773 in_twt:1, 4774 hw_txrx_stats_en:1, 4775 is_mld_peer:1; 4776 uint32_t tx_failed; 4777 struct cdp_pkt_info comp_pkt; 4778 struct cdp_pkt_info to_stack; 4779 4780 struct dp_peer_delay_stats *delay_stats; 4781 4782 struct cdp_peer_tid_stats *jitter_stats; 4783 4784 struct { 4785 enum cdp_sec_type sec_type; 4786 u_int32_t michael_key[2]; /* relevant for TKIP */ 4787 } security[2]; /* 0 -> multicast, 1 -> unicast */ 4788 4789 uint16_t nawds_enabled:1, 4790 bss_peer:1, 4791 isolation:1, 4792 wds_enabled:1; 4793 #ifdef WDS_VENDOR_EXTENSION 4794 dp_ecm_policy wds_ecm; 4795 #endif 4796 #ifdef PEER_CACHE_RX_PKTS 4797 qdf_atomic_t flush_in_progress; 4798 struct dp_peer_cached_bufq bufq_info; 4799 #endif 4800 #ifdef QCA_MULTIPASS_SUPPORT 4801 TAILQ_ENTRY(dp_txrx_peer) mpass_peer_list_elem; 4802 uint16_t vlan_id; 4803 #endif 4804 #ifdef QCA_SUPPORT_WDS_EXTENDED 4805 struct dp_wds_ext_peer wds_ext; 4806 ol_txrx_rx_fp osif_rx; 4807 #endif 4808 struct dp_rx_tid_defrag rx_tid[DP_MAX_TIDS]; 4809 #ifdef CONFIG_SAWF 4810 struct dp_peer_sawf_stats *sawf_stats; 4811 #endif 4812 #ifdef DP_PEER_EXTENDED_API 4813 enum cdp_peer_bw bw; 4814 uint8_t mpdu_retry_threshold; 4815 #endif 4816 uint8_t stats_arr_size; 4817 4818 /* dp_peer_stats should be the last member in the structure */ 4819 struct dp_peer_stats stats[]; 4820 }; 4821 4822 /* Peer structure for data path state */ 4823 struct dp_peer { 4824 struct dp_txrx_peer *txrx_peer; 4825 #ifdef WIFI_MONITOR_SUPPORT 4826 struct dp_mon_peer *monitor_peer; 4827 #endif 4828 /* peer ID for this peer */ 4829 uint16_t peer_id; 4830 4831 /* VDEV to which this peer is associated */ 4832 struct dp_vdev *vdev; 4833 4834 struct dp_ast_entry *self_ast_entry; 4835 4836 qdf_atomic_t ref_cnt; 4837 4838 union dp_align_mac_addr mac_addr; 4839 4840 /* node in the vdev's list of peers */ 4841 TAILQ_ENTRY(dp_peer) peer_list_elem; 4842 /* node in the hash table bin's list of peers */ 4843 TAILQ_ENTRY(dp_peer) hash_list_elem; 4844 4845 /* TID structures pointer */ 4846 struct dp_rx_tid *rx_tid; 4847 4848 /* TBD: No transmit TID state required? */ 4849 4850 struct { 4851 enum cdp_sec_type sec_type; 4852 u_int32_t michael_key[2]; /* relevant for TKIP */ 4853 } security[2]; /* 0 -> multicast, 1 -> unicast */ 4854 4855 /* NAWDS Flag and Bss Peer bit */ 4856 uint16_t bss_peer:1, /* set for bss peer */ 4857 authorize:1, /* Set when authorized */ 4858 valid:1, /* valid bit */ 4859 delete_in_progress:1, /* Indicate kickout sent */ 4860 sta_self_peer:1, /* Indicate STA self peer */ 4861 is_tdls_peer:1; /* Indicate TDLS peer */ 4862 4863 #ifdef WLAN_FEATURE_11BE_MLO 4864 uint8_t first_link:1, /* first link peer for MLO */ 4865 primary_link:1; /* primary link for MLO */ 4866 #endif 4867 4868 /* MCL specific peer local id */ 4869 uint16_t local_id; 4870 enum ol_txrx_peer_state state; 4871 qdf_spinlock_t peer_info_lock; 4872 4873 /* Peer calibrated stats */ 4874 struct cdp_calibr_stats stats; 4875 4876 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 4877 /* TBD */ 4878 4879 /* Active Block ack sessions */ 4880 uint16_t active_ba_session_cnt; 4881 4882 /* Current HW buffersize setting */ 4883 uint16_t hw_buffer_size; 4884 4885 /* 4886 * Flag to check if sessions with 256 buffersize 4887 * should be terminated. 4888 */ 4889 uint8_t kill_256_sessions; 4890 qdf_atomic_t is_default_route_set; 4891 4892 #ifdef QCA_PEER_MULTIQ_SUPPORT 4893 struct dp_peer_ast_params peer_ast_flowq_idx[DP_PEER_AST_FLOWQ_MAX]; 4894 #endif 4895 /* entry to inactive_list*/ 4896 TAILQ_ENTRY(dp_peer) inactive_list_elem; 4897 4898 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 4899 4900 uint8_t peer_state; 4901 qdf_spinlock_t peer_state_lock; 4902 #ifdef WLAN_SUPPORT_MSCS 4903 struct dp_peer_mscs_parameter mscs_ipv4_parameter, mscs_ipv6_parameter; 4904 bool mscs_active; 4905 #endif 4906 #ifdef WLAN_SUPPORT_MESH_LATENCY 4907 struct dp_peer_mesh_latency_parameter mesh_latency_params[DP_MAX_TIDS]; 4908 #endif 4909 #ifdef WLAN_FEATURE_11BE_MLO 4910 /* peer type */ 4911 enum cdp_peer_type peer_type; 4912 /*---------for link peer---------*/ 4913 struct dp_peer *mld_peer; 4914 4915 /*Link ID of link peer*/ 4916 uint8_t link_id; 4917 bool link_id_valid; 4918 4919 /*---------for mld peer----------*/ 4920 struct dp_peer_link_info link_peers[DP_MAX_MLO_LINKS]; 4921 uint8_t num_links; 4922 DP_MUTEX_TYPE link_peers_info_lock; 4923 #endif 4924 #ifdef CONFIG_SAWF_DEF_QUEUES 4925 struct dp_peer_sawf *sawf; 4926 #endif 4927 /* AST hash index for peer in HW */ 4928 uint16_t ast_idx; 4929 4930 /* AST hash value for peer in HW */ 4931 uint16_t ast_hash; 4932 }; 4933 4934 /** 4935 * struct dp_invalid_peer_msg - Invalid peer message 4936 * @nbuf: data buffer 4937 * @wh: 802.11 header 4938 * @vdev_id: id of vdev 4939 */ 4940 struct dp_invalid_peer_msg { 4941 qdf_nbuf_t nbuf; 4942 struct ieee80211_frame *wh; 4943 uint8_t vdev_id; 4944 }; 4945 4946 /** 4947 * struct dp_tx_me_buf_t - ME buffer 4948 * @next: pointer to next buffer 4949 * @data: Destination Mac address 4950 * @paddr_macbuf: physical address for dest_mac 4951 */ 4952 struct dp_tx_me_buf_t { 4953 /* Note: ME buf pool initialization logic expects next pointer to 4954 * be the first element. Dont add anything before next */ 4955 struct dp_tx_me_buf_t *next; 4956 uint8_t data[QDF_MAC_ADDR_SIZE]; 4957 qdf_dma_addr_t paddr_macbuf; 4958 }; 4959 4960 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) || defined(WLAN_SUPPORT_RX_FISA) 4961 struct hal_rx_fst; 4962 #endif /* WLAN_SUPPORT_RX_FLOW_TAG || WLAN_SUPPORT_RX_FISA */ 4963 4964 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 4965 struct dp_rx_fse { 4966 /* HAL Rx Flow Search Entry which matches HW definition */ 4967 void *hal_rx_fse; 4968 /* Toeplitz hash value */ 4969 uint32_t flow_hash; 4970 /* Flow index, equivalent to hash value truncated to FST size */ 4971 uint32_t flow_id; 4972 /* Stats tracking for this flow */ 4973 struct cdp_flow_stats stats; 4974 /* Flag indicating whether flow is IPv4 address tuple */ 4975 uint8_t is_ipv4_addr_entry; 4976 /* Flag indicating whether flow is valid */ 4977 uint8_t is_valid; 4978 }; 4979 4980 struct dp_rx_fst { 4981 /* Software (DP) FST */ 4982 uint8_t *base; 4983 /* Pointer to HAL FST */ 4984 struct hal_rx_fst *hal_rx_fst; 4985 /* Base physical address of HAL RX HW FST */ 4986 uint64_t hal_rx_fst_base_paddr; 4987 /* Maximum number of flows FSE supports */ 4988 uint16_t max_entries; 4989 /* Num entries in flow table */ 4990 uint16_t num_entries; 4991 /* SKID Length */ 4992 uint16_t max_skid_length; 4993 /* Hash mask to obtain legitimate hash entry */ 4994 uint32_t hash_mask; 4995 /* Timer for bundling of flows */ 4996 qdf_timer_t cache_invalidate_timer; 4997 /** 4998 * Flag which tracks whether cache update 4999 * is needed on timer expiry 5000 */ 5001 qdf_atomic_t is_cache_update_pending; 5002 /* Flag to indicate completion of FSE setup in HW/FW */ 5003 bool fse_setup_done; 5004 /* Last ring id used to add a flow */ 5005 uint8_t ring_id; 5006 }; 5007 5008 #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_rx_fse) 5009 5010 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 5011 5012 #ifdef WLAN_FEATURE_STATS_EXT 5013 /** 5014 * struct dp_req_rx_hw_stats_t - RX peer HW stats query structure 5015 * @pending_tid_stats_cnt: pending tid stats count which waits for REO status 5016 * @is_query_timeout: flag to show is stats query timeout 5017 */ 5018 struct dp_req_rx_hw_stats_t { 5019 qdf_atomic_t pending_tid_stats_cnt; 5020 bool is_query_timeout; 5021 }; 5022 #endif 5023 /* soc level structure to declare arch specific ops for DP */ 5024 5025 #ifndef WLAN_SOFTUMAC_SUPPORT 5026 /** 5027 * dp_hw_link_desc_pool_banks_free() - Free h/w link desc pool banks 5028 * @soc: DP SOC handle 5029 * @mac_id: mac id 5030 * 5031 * Return: none 5032 */ 5033 void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, uint32_t mac_id); 5034 5035 /** 5036 * dp_hw_link_desc_pool_banks_alloc() - Allocate h/w link desc pool banks 5037 * @soc: DP SOC handle 5038 * @mac_id: mac id 5039 * 5040 * Allocates memory pages for link descriptors, the page size is 4K for 5041 * MCL and 2MB for WIN. if the mac_id is invalid link descriptor pages are 5042 * allocated for regular RX/TX and if the there is a proper mac_id link 5043 * descriptors are allocated for RX monitor mode. 5044 * 5045 * Return: QDF_STATUS_SUCCESS: Success 5046 * QDF_STATUS_E_FAILURE: Failure 5047 */ 5048 QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, 5049 uint32_t mac_id); 5050 #else 5051 static inline void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, 5052 uint32_t mac_id) 5053 { 5054 } 5055 5056 static inline QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, 5057 uint32_t mac_id) 5058 { 5059 return QDF_STATUS_SUCCESS; 5060 } 5061 #endif 5062 5063 /** 5064 * dp_link_desc_ring_replenish() - Replenish hw link desc rings 5065 * @soc: DP SOC handle 5066 * @mac_id: mac id 5067 * 5068 * Return: None 5069 */ 5070 void dp_link_desc_ring_replenish(struct dp_soc *soc, uint32_t mac_id); 5071 5072 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 5073 void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc); 5074 #else 5075 static inline void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc) {} 5076 #endif 5077 5078 /** 5079 * dp_srng_alloc() - Allocate memory for SRNG 5080 * @soc : Data path soc handle 5081 * @srng : SRNG pointer 5082 * @ring_type : Ring Type 5083 * @num_entries: Number of entries 5084 * @cached: cached flag variable 5085 * 5086 * Return: QDF_STATUS 5087 */ 5088 QDF_STATUS dp_srng_alloc(struct dp_soc *soc, struct dp_srng *srng, 5089 int ring_type, uint32_t num_entries, 5090 bool cached); 5091 5092 /** 5093 * dp_srng_free() - Free SRNG memory 5094 * @soc: Data path soc handle 5095 * @srng: SRNG pointer 5096 * 5097 * Return: None 5098 */ 5099 void dp_srng_free(struct dp_soc *soc, struct dp_srng *srng); 5100 5101 /** 5102 * dp_srng_init() - Initialize SRNG 5103 * @soc : Data path soc handle 5104 * @srng : SRNG pointer 5105 * @ring_type : Ring Type 5106 * @ring_num: Ring number 5107 * @mac_id: mac_id 5108 * 5109 * Return: QDF_STATUS 5110 */ 5111 QDF_STATUS dp_srng_init(struct dp_soc *soc, struct dp_srng *srng, 5112 int ring_type, int ring_num, int mac_id); 5113 5114 /** 5115 * dp_srng_init_idx() - Initialize SRNG 5116 * @soc : Data path soc handle 5117 * @srng : SRNG pointer 5118 * @ring_type : Ring Type 5119 * @ring_num: Ring number 5120 * @mac_id: mac_id 5121 * @idx: ring index 5122 * 5123 * Return: QDF_STATUS 5124 */ 5125 QDF_STATUS dp_srng_init_idx(struct dp_soc *soc, struct dp_srng *srng, 5126 int ring_type, int ring_num, int mac_id, 5127 uint32_t idx); 5128 5129 /** 5130 * dp_srng_deinit() - Internal function to deinit SRNG rings used by data path 5131 * @soc: DP SOC handle 5132 * @srng: source ring structure 5133 * @ring_type: type of ring 5134 * @ring_num: ring number 5135 * 5136 * Return: None 5137 */ 5138 void dp_srng_deinit(struct dp_soc *soc, struct dp_srng *srng, 5139 int ring_type, int ring_num); 5140 5141 void dp_print_peer_txrx_stats_be(struct cdp_peer_stats *peer_stats, 5142 enum peer_stats_type stats_type); 5143 void dp_print_peer_txrx_stats_li(struct cdp_peer_stats *peer_stats, 5144 enum peer_stats_type stats_type); 5145 5146 void dp_print_peer_txrx_stats_rh(struct cdp_peer_stats *peer_stats, 5147 enum peer_stats_type stats_type); 5148 5149 /** 5150 * dp_should_timer_irq_yield() - Decide if the bottom half should yield 5151 * @soc: DP soc handle 5152 * @work_done: work done in softirq context 5153 * @start_time: start time for the softirq 5154 * 5155 * Return: enum with yield code 5156 */ 5157 enum timer_yield_status 5158 dp_should_timer_irq_yield(struct dp_soc *soc, uint32_t work_done, 5159 uint64_t start_time); 5160 5161 /** 5162 * dp_vdev_get_default_reo_hash() - get reo dest ring and hash values for a vdev 5163 * @vdev: Datapath VDEV handle 5164 * @reo_dest: pointer to default reo_dest ring for vdev to be populated 5165 * @hash_based: pointer to hash value (enabled/disabled) to be populated 5166 * 5167 * Return: None 5168 */ 5169 void dp_vdev_get_default_reo_hash(struct dp_vdev *vdev, 5170 enum cdp_host_reo_dest_ring *reo_dest, 5171 bool *hash_based); 5172 5173 /** 5174 * dp_reo_remap_config() - configure reo remap register value based 5175 * nss configuration. 5176 * @soc: DP soc handle 5177 * @remap0: output parameter indicates reo remap 0 register value 5178 * @remap1: output parameter indicates reo remap 1 register value 5179 * @remap2: output parameter indicates reo remap 2 register value 5180 * 5181 * based on offload_radio value below remap configuration 5182 * get applied. 5183 * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4) 5184 * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4) 5185 * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4) 5186 * 3 - both Radios handled by NSS (remap not required) 5187 * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3) 5188 * 5189 * Return: bool type, true if remap is configured else false. 5190 */ 5191 5192 bool dp_reo_remap_config(struct dp_soc *soc, uint32_t *remap0, 5193 uint32_t *remap1, uint32_t *remap2); 5194 5195 #ifdef QCA_DP_TX_HW_SW_NBUF_DESC_PREFETCH 5196 /** 5197 * dp_tx_comp_get_prefetched_params_from_hal_desc() - Get prefetched TX desc 5198 * @soc: DP soc handle 5199 * @tx_comp_hal_desc: HAL TX Comp Descriptor 5200 * @r_tx_desc: SW Tx Descriptor retrieved from HAL desc. 5201 * 5202 * Return: None 5203 */ 5204 void dp_tx_comp_get_prefetched_params_from_hal_desc( 5205 struct dp_soc *soc, 5206 void *tx_comp_hal_desc, 5207 struct dp_tx_desc_s **r_tx_desc); 5208 #endif 5209 #endif /* _DP_TYPES_H_ */ 5210