1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _DP_TYPES_H_ 21 #define _DP_TYPES_H_ 22 23 #include <qdf_types.h> 24 #include <qdf_nbuf.h> 25 #include <qdf_lock.h> 26 #include <qdf_atomic.h> 27 #include <qdf_util.h> 28 #include <qdf_list.h> 29 #include <qdf_lro.h> 30 #include <queue.h> 31 #include <htt_common.h> 32 #include <htt.h> 33 #include <htt_stats.h> 34 #include <cdp_txrx_cmn.h> 35 #ifdef DP_MOB_DEFS 36 #include <cds_ieee80211_common.h> 37 #endif 38 #include <wdi_event_api.h> /* WDI subscriber event list */ 39 40 #include "hal_hw_headers.h" 41 #include <hal_tx.h> 42 #include <hal_reo.h> 43 #include "wlan_cfg.h" 44 #include "hal_rx.h" 45 #include <hal_api.h> 46 #include <hal_api_mon.h> 47 #include "hal_rx.h" 48 //#include "hal_rx_flow.h" 49 50 #define MAX_BW 8 51 #define MAX_RETRIES 4 52 #define MAX_RECEPTION_TYPES 4 53 54 #define MINIDUMP_STR_SIZE 25 55 #ifndef REMOVE_PKT_LOG 56 #include <pktlog.h> 57 #endif 58 #include <dp_umac_reset.h> 59 60 //#include "dp_tx.h" 61 62 #define REPT_MU_MIMO 1 63 #define REPT_MU_OFDMA_MIMO 3 64 #define DP_VO_TID 6 65 /** MAX TID MAPS AVAILABLE PER PDEV */ 66 #define DP_MAX_TID_MAPS 16 67 /** pad DSCP_TID_MAP_MAX with 6 to fix oob issue */ 68 #define DSCP_TID_MAP_MAX (64 + 6) 69 #define DP_IP_DSCP_SHIFT 2 70 #define DP_IP_DSCP_MASK 0x3f 71 #define DP_FC0_SUBTYPE_QOS 0x80 72 #define DP_QOS_TID 0x0f 73 #define DP_IPV6_PRIORITY_SHIFT 20 74 #define MAX_MON_LINK_DESC_BANKS 2 75 #define DP_VDEV_ALL 0xff 76 77 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 78 #define WLAN_DP_RESET_MON_BUF_RING_FILTER 79 #define MAX_TXDESC_POOLS 6 80 #else 81 #define MAX_TXDESC_POOLS 4 82 #endif 83 84 #define MAX_RXDESC_POOLS 4 85 86 /* Max no. of VDEV per PSOC */ 87 #ifdef WLAN_PSOC_MAX_VDEVS 88 #define MAX_VDEV_CNT WLAN_PSOC_MAX_VDEVS 89 #else 90 #define MAX_VDEV_CNT 51 91 #endif 92 93 /* Max no. of VDEVs, a PDEV can support */ 94 #ifdef WLAN_PDEV_MAX_VDEVS 95 #define DP_PDEV_MAX_VDEVS WLAN_PDEV_MAX_VDEVS 96 #else 97 #define DP_PDEV_MAX_VDEVS 17 98 #endif 99 100 #define EXCEPTION_DEST_RING_ID 0 101 #define MAX_IDLE_SCATTER_BUFS 16 102 #define DP_MAX_IRQ_PER_CONTEXT 12 103 #define DEFAULT_HW_PEER_ID 0xffff 104 105 #define MAX_AST_AGEOUT_COUNT 128 106 107 #ifdef TX_ADDR_INDEX_SEARCH 108 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_INDEX_SEARCH 109 #else 110 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_SEARCH_DEFAULT 111 #endif 112 113 #define WBM_INT_ERROR_ALL 0 114 #define WBM_INT_ERROR_REO_NULL_BUFFER 1 115 #define WBM_INT_ERROR_REO_NULL_LINK_DESC 2 116 #define WBM_INT_ERROR_REO_NULL_MSDU_BUFF 3 117 #define WBM_INT_ERROR_REO_BUFF_REAPED 4 118 #define MAX_WBM_INT_ERROR_REASONS 5 119 120 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 121 /* Maximum retries for Delba per tid per peer */ 122 #define DP_MAX_DELBA_RETRY 3 123 124 #ifdef AST_OFFLOAD_ENABLE 125 #define AST_OFFLOAD_ENABLE_STATUS 1 126 #else 127 #define AST_OFFLOAD_ENABLE_STATUS 0 128 #endif 129 130 #ifdef FEATURE_MEC_OFFLOAD 131 #define FW_MEC_FW_OFFLOAD_ENABLED 1 132 #else 133 #define FW_MEC_FW_OFFLOAD_ENABLED 0 134 #endif 135 136 #define PCP_TID_MAP_MAX 8 137 #define MAX_MU_USERS 37 138 139 #define REO_CMD_EVENT_HIST_MAX 64 140 141 #define DP_MAX_SRNGS 64 142 143 /* 2G PHYB */ 144 #define PHYB_2G_LMAC_ID 2 145 #define PHYB_2G_TARGET_PDEV_ID 2 146 147 /* Flags for skippig s/w tid classification */ 148 #define DP_TX_HW_DSCP_TID_MAP_VALID 0x1 149 #define DP_TXRX_HLOS_TID_OVERRIDE_ENABLED 0x2 150 #define DP_TX_MESH_ENABLED 0x4 151 #define DP_TX_INVALID_QOS_TAG 0xf 152 153 #ifdef WLAN_SUPPORT_RX_FISA 154 #define FISA_FLOW_MAX_AGGR_COUNT 16 /* max flow aggregate count */ 155 #endif 156 157 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 158 #define DP_RX_REFILL_BUFF_POOL_SIZE 2048 159 #define DP_RX_REFILL_BUFF_POOL_BURST 64 160 #define DP_RX_REFILL_THRD_THRESHOLD 512 161 #endif 162 163 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 164 #define DP_SKIP_BAR_UPDATE_TIMEOUT 5000 165 #endif 166 167 #define DP_TX_MAGIC_PATTERN_INUSE 0xABCD1234 168 #define DP_TX_MAGIC_PATTERN_FREE 0xDEADBEEF 169 170 #ifdef IPA_OFFLOAD 171 #define DP_PEER_REO_STATS_TID_SHIFT 16 172 #define DP_PEER_REO_STATS_TID_MASK 0xFFFF0000 173 #define DP_PEER_REO_STATS_PEER_ID_MASK 0x0000FFFF 174 #define DP_PEER_GET_REO_STATS_TID(comb_peer_id_tid) \ 175 ((comb_peer_id_tid & DP_PEER_REO_STATS_TID_MASK) >> \ 176 DP_PEER_REO_STATS_TID_SHIFT) 177 #define DP_PEER_GET_REO_STATS_PEER_ID(comb_peer_id_tid) \ 178 (comb_peer_id_tid & DP_PEER_REO_STATS_PEER_ID_MASK) 179 #endif 180 181 enum rx_pktlog_mode { 182 DP_RX_PKTLOG_DISABLED = 0, 183 DP_RX_PKTLOG_FULL, 184 DP_RX_PKTLOG_LITE, 185 }; 186 187 /* enum m_copy_mode - Available mcopy mode 188 * 189 */ 190 enum m_copy_mode { 191 M_COPY_DISABLED = 0, 192 M_COPY = 2, 193 M_COPY_EXTENDED = 4, 194 }; 195 196 struct msdu_list { 197 qdf_nbuf_t head; 198 qdf_nbuf_t tail; 199 uint32_t sum_len; 200 }; 201 202 struct dp_soc_cmn; 203 struct dp_pdev; 204 struct dp_vdev; 205 struct dp_tx_desc_s; 206 struct dp_soc; 207 union dp_rx_desc_list_elem_t; 208 struct cdp_peer_rate_stats_ctx; 209 struct cdp_soc_rate_stats_ctx; 210 struct dp_rx_fst; 211 struct dp_mon_filter; 212 struct dp_mon_mpdu; 213 #ifdef BE_PKTLOG_SUPPORT 214 struct dp_mon_filter_be; 215 #endif 216 struct dp_peer; 217 struct dp_txrx_peer; 218 219 /** 220 * enum for DP peer state 221 */ 222 enum dp_peer_state { 223 DP_PEER_STATE_NONE, 224 DP_PEER_STATE_INIT, 225 DP_PEER_STATE_ACTIVE, 226 DP_PEER_STATE_LOGICAL_DELETE, 227 DP_PEER_STATE_INACTIVE, 228 DP_PEER_STATE_FREED, 229 DP_PEER_STATE_INVALID, 230 }; 231 232 /** 233 * enum for modules ids of 234 */ 235 enum dp_mod_id { 236 DP_MOD_ID_TX_RX, 237 DP_MOD_ID_TX_COMP, 238 DP_MOD_ID_RX, 239 DP_MOD_ID_HTT_COMP, 240 DP_MOD_ID_RX_ERR, 241 DP_MOD_ID_TX_PPDU_STATS, 242 DP_MOD_ID_RX_PPDU_STATS, 243 DP_MOD_ID_CDP, 244 DP_MOD_ID_GENERIC_STATS, 245 DP_MOD_ID_TX_MULTIPASS, 246 DP_MOD_ID_TX_CAPTURE, 247 DP_MOD_ID_NSS_OFFLOAD, 248 DP_MOD_ID_CONFIG, 249 DP_MOD_ID_HTT, 250 DP_MOD_ID_IPA, 251 DP_MOD_ID_AST, 252 DP_MOD_ID_MCAST2UCAST, 253 DP_MOD_ID_CHILD, 254 DP_MOD_ID_MESH, 255 DP_MOD_ID_TX_EXCEPTION, 256 DP_MOD_ID_TDLS, 257 DP_MOD_ID_MISC, 258 DP_MOD_ID_MSCS, 259 DP_MOD_ID_TX, 260 DP_MOD_ID_SAWF, 261 DP_MOD_ID_REINJECT, 262 DP_MOD_ID_SCS, 263 DP_MOD_ID_MAX, 264 }; 265 266 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 267 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 268 269 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 270 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 271 272 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 273 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 274 275 #define DP_MUTEX_TYPE qdf_spinlock_t 276 277 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 278 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 279 280 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 281 ((_a)[0] == 0x33 && \ 282 (_a)[1] == 0x33) 283 284 #define DP_FRAME_IS_BROADCAST(_a) \ 285 ((_a)[0] == 0xff && \ 286 (_a)[1] == 0xff && \ 287 (_a)[2] == 0xff && \ 288 (_a)[3] == 0xff && \ 289 (_a)[4] == 0xff && \ 290 (_a)[5] == 0xff) 291 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 292 (_llc)->llc_ssap == 0xaa && \ 293 (_llc)->llc_un.type_snap.control == 0x3) 294 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 295 #define DP_FRAME_FC0_TYPE_MASK 0x0c 296 #define DP_FRAME_FC0_TYPE_DATA 0x08 297 #define DP_FRAME_IS_DATA(_frame) \ 298 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 299 300 /** 301 * macros to convert hw mac id to sw mac id: 302 * mac ids used by hardware start from a value of 1 while 303 * those in host software start from a value of 0. Use the 304 * macros below to convert between mac ids used by software and 305 * hardware 306 */ 307 #define DP_SW2HW_MACID(id) ((id) + 1) 308 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 309 310 /** 311 * Number of Tx Queues 312 * enum and macro to define how many threshold levels is used 313 * for the AC based flow control 314 */ 315 #ifdef QCA_AC_BASED_FLOW_CONTROL 316 enum dp_fl_ctrl_threshold { 317 DP_TH_BE_BK = 0, 318 DP_TH_VI, 319 DP_TH_VO, 320 DP_TH_HI, 321 }; 322 323 #define FL_TH_MAX (4) 324 #define FL_TH_VI_PERCENTAGE (80) 325 #define FL_TH_VO_PERCENTAGE (60) 326 #define FL_TH_HI_PERCENTAGE (40) 327 #endif 328 329 /** 330 * enum dp_intr_mode 331 * @DP_INTR_INTEGRATED: Line interrupts 332 * @DP_INTR_MSI: MSI interrupts 333 * @DP_INTR_POLL: Polling 334 */ 335 enum dp_intr_mode { 336 DP_INTR_INTEGRATED = 0, 337 DP_INTR_MSI, 338 DP_INTR_POLL, 339 DP_INTR_LEGACY_VIRTUAL_IRQ, 340 }; 341 342 /** 343 * enum dp_tx_frm_type 344 * @dp_tx_frm_std: Regular frame, no added header fragments 345 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 346 * @dp_tx_frm_sg: SG segment 347 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 348 * @dp_tx_frm_me: Multicast to Unicast Converted frame 349 * @dp_tx_frm_raw: Raw Frame 350 */ 351 enum dp_tx_frm_type { 352 dp_tx_frm_std = 0, 353 dp_tx_frm_tso, 354 dp_tx_frm_sg, 355 dp_tx_frm_audio, 356 dp_tx_frm_me, 357 dp_tx_frm_raw, 358 }; 359 360 /** 361 * enum dp_ast_type 362 * @dp_ast_type_wds: WDS peer AST type 363 * @dp_ast_type_static: static ast entry type 364 * @dp_ast_type_mec: Multicast echo ast entry type 365 */ 366 enum dp_ast_type { 367 dp_ast_type_wds = 0, 368 dp_ast_type_static, 369 dp_ast_type_mec, 370 }; 371 372 /** 373 * enum dp_nss_cfg 374 * @dp_nss_cfg_default: No radios are offloaded 375 * @dp_nss_cfg_first_radio: First radio offloaded 376 * @dp_nss_cfg_second_radio: Second radio offloaded 377 * @dp_nss_cfg_dbdc: Dual radios offloaded 378 * @dp_nss_cfg_dbtc: Three radios offloaded 379 */ 380 enum dp_nss_cfg { 381 dp_nss_cfg_default = 0x0, 382 dp_nss_cfg_first_radio = 0x1, 383 dp_nss_cfg_second_radio = 0x2, 384 dp_nss_cfg_dbdc = 0x3, 385 dp_nss_cfg_dbtc = 0x7, 386 dp_nss_cfg_max 387 }; 388 389 #ifdef WLAN_TX_PKT_CAPTURE_ENH 390 #define DP_CPU_RING_MAP_1 1 391 #endif 392 393 /** 394 * dp_cpu_ring_map_type - dp tx cpu ring map 395 * @DP_NSS_DEFAULT_MAP: Default mode with no NSS offloaded 396 * @DP_NSS_FIRST_RADIO_OFFLOADED_MAP: Only First Radio is offloaded 397 * @DP_NSS_SECOND_RADIO_OFFLOADED_MAP: Only second radio is offloaded 398 * @DP_NSS_DBDC_OFFLOADED_MAP: Both radios are offloaded 399 * @DP_NSS_DBTC_OFFLOADED_MAP: All three radios are offloaded 400 * @DP_SINGLE_TX_RING_MAP: to avoid out of order all cpu mapped to single ring 401 * @DP_NSS_CPU_RING_MAP_MAX: Max cpu ring map val 402 */ 403 enum dp_cpu_ring_map_types { 404 DP_NSS_DEFAULT_MAP, 405 DP_NSS_FIRST_RADIO_OFFLOADED_MAP, 406 DP_NSS_SECOND_RADIO_OFFLOADED_MAP, 407 DP_NSS_DBDC_OFFLOADED_MAP, 408 DP_NSS_DBTC_OFFLOADED_MAP, 409 #ifdef WLAN_TX_PKT_CAPTURE_ENH 410 DP_SINGLE_TX_RING_MAP, 411 #endif 412 DP_NSS_CPU_RING_MAP_MAX 413 }; 414 415 /** 416 * dp_rx_nbuf_frag_info - Hold vaddr and paddr for a buffer 417 * 418 * paddr: Physical address of buffer allocated. 419 * nbuf: Allocated nbuf in case of nbuf approach. 420 * vaddr: Virtual address of frag allocated in case of frag approach. 421 */ 422 struct dp_rx_nbuf_frag_info { 423 qdf_dma_addr_t paddr; 424 union { 425 qdf_nbuf_t nbuf; 426 qdf_frag_t vaddr; 427 } virt_addr; 428 }; 429 430 /** 431 * enum dp_ctxt - context type 432 * @DP_PDEV_TYPE: PDEV context 433 * @DP_RX_RING_HIST_TYPE: Datapath rx ring history 434 * @DP_RX_ERR_RING_HIST_TYPE: Datapath rx error ring history 435 * @DP_RX_REINJECT_RING_HIST_TYPE: Datapath reinject ring history 436 * @DP_RX_REFILL_RING_HIST_TYPE: Datapath rx refill ring history 437 * @DP_TX_HW_DESC_HIST_TYPE: Datapath TX HW descriptor history 438 * @DP_MON_SOC_TYPE: Datapath monitor soc context 439 * @DP_MON_PDEV_TYPE: Datapath monitor pdev context 440 * @DP_MON_STATUS_BUF_HIST_TYPE: DP monitor status buffer history 441 */ 442 enum dp_ctxt_type { 443 DP_PDEV_TYPE, 444 DP_RX_RING_HIST_TYPE, 445 DP_RX_ERR_RING_HIST_TYPE, 446 DP_RX_REINJECT_RING_HIST_TYPE, 447 DP_TX_TCL_HIST_TYPE, 448 DP_TX_COMP_HIST_TYPE, 449 DP_FISA_RX_FT_TYPE, 450 DP_RX_REFILL_RING_HIST_TYPE, 451 DP_TX_HW_DESC_HIST_TYPE, 452 DP_MON_SOC_TYPE, 453 DP_MON_PDEV_TYPE, 454 DP_MON_STATUS_BUF_HIST_TYPE, 455 }; 456 457 /** 458 * enum dp_desc_type - source type for multiple pages allocation 459 * @DP_TX_DESC_TYPE: DP SW TX descriptor 460 * @DP_TX_EXT_DESC_TYPE: DP TX msdu extension descriptor 461 * @DP_TX_EXT_DESC_LINK_TYPE: DP link descriptor for msdu ext_desc 462 * @DP_TX_TSO_DESC_TYPE: DP TX TSO descriptor 463 * @DP_TX_TSO_NUM_SEG_TYPE: DP TX number of segments 464 * @DP_RX_DESC_BUF_TYPE: DP RX SW descriptor 465 * @DP_RX_DESC_STATUS_TYPE: DP RX SW descriptor for monitor status 466 * @DP_HW_LINK_DESC_TYPE: DP HW link descriptor 467 * @DP_HW_CC_SPT_PAGE_TYPE: DP pages for HW CC secondary page table 468 */ 469 enum dp_desc_type { 470 DP_TX_DESC_TYPE, 471 DP_TX_EXT_DESC_TYPE, 472 DP_TX_EXT_DESC_LINK_TYPE, 473 DP_TX_TSO_DESC_TYPE, 474 DP_TX_TSO_NUM_SEG_TYPE, 475 DP_RX_DESC_BUF_TYPE, 476 DP_RX_DESC_STATUS_TYPE, 477 DP_HW_LINK_DESC_TYPE, 478 DP_HW_CC_SPT_PAGE_TYPE, 479 }; 480 481 /** 482 * struct rx_desc_pool 483 * @pool_size: number of RX descriptor in the pool 484 * @elem_size: Element size 485 * @desc_pages: Multi page descriptors 486 * @array: pointer to array of RX descriptor 487 * @freelist: pointer to free RX descriptor link list 488 * @lock: Protection for the RX descriptor pool 489 * @owner: owner for nbuf 490 * @buf_size: Buffer size 491 * @buf_alignment: Buffer alignment 492 * @rx_mon_dest_frag_enable: Enable frag processing for mon dest buffer 493 * @desc_type: type of desc this pool serves 494 */ 495 struct rx_desc_pool { 496 uint32_t pool_size; 497 #ifdef RX_DESC_MULTI_PAGE_ALLOC 498 uint16_t elem_size; 499 struct qdf_mem_multi_page_t desc_pages; 500 #else 501 union dp_rx_desc_list_elem_t *array; 502 #endif 503 union dp_rx_desc_list_elem_t *freelist; 504 qdf_spinlock_t lock; 505 uint8_t owner; 506 uint16_t buf_size; 507 uint8_t buf_alignment; 508 bool rx_mon_dest_frag_enable; 509 enum dp_desc_type desc_type; 510 }; 511 512 /** 513 * struct dp_tx_ext_desc_elem_s 514 * @next: next extension descriptor pointer 515 * @vaddr: hlos virtual address pointer 516 * @paddr: physical address pointer for descriptor 517 * @flags: mark features for extension descriptor 518 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 519 * Tx completion of ME packet 520 * @tso_desc: Pointer to Tso desc 521 * @tso_num_desc: Pointer to tso_num_desc 522 */ 523 struct dp_tx_ext_desc_elem_s { 524 struct dp_tx_ext_desc_elem_s *next; 525 void *vaddr; 526 qdf_dma_addr_t paddr; 527 uint16_t flags; 528 struct dp_tx_me_buf_t *me_buffer; 529 struct qdf_tso_seg_elem_t *tso_desc; 530 struct qdf_tso_num_seg_elem_t *tso_num_desc; 531 }; 532 533 /** 534 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 535 * @elem_count: Number of descriptors in the pool 536 * @elem_size: Size of each descriptor 537 * @num_free: Number of free descriptors 538 * @msdu_ext_desc: MSDU extension descriptor 539 * @desc_pages: multiple page allocation information for actual descriptors 540 * @link_elem_size: size of the link descriptor in cacheable memory used for 541 * chaining the extension descriptors 542 * @desc_link_pages: multiple page allocation information for link descriptors 543 */ 544 struct dp_tx_ext_desc_pool_s { 545 uint16_t elem_count; 546 int elem_size; 547 uint16_t num_free; 548 struct qdf_mem_multi_page_t desc_pages; 549 int link_elem_size; 550 struct qdf_mem_multi_page_t desc_link_pages; 551 struct dp_tx_ext_desc_elem_s *freelist; 552 qdf_spinlock_t lock; 553 qdf_dma_mem_context(memctx); 554 }; 555 556 /** 557 * struct dp_tx_desc_s - Tx Descriptor 558 * @next: Next in the chain of descriptors in freelist or in the completion list 559 * @nbuf: Buffer Address 560 * @msdu_ext_desc: MSDU extension descriptor 561 * @id: Descriptor ID 562 * @vdev_id: vdev_id of vdev over which the packet was transmitted 563 * @pdev: Handle to pdev 564 * @pool_id: Pool ID - used when releasing the descriptor 565 * @flags: Flags to track the state of descriptor and special frame handling 566 * @comp: Pool ID - used when releasing the descriptor 567 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 568 * This is maintained in descriptor to allow more efficient 569 * processing in completion event processing code. 570 * This field is filled in with the htt_pkt_type enum. 571 * @buffer_src: buffer source TQM, REO, FW etc. 572 * @frm_type: Frame Type - ToDo check if this is redundant 573 * @pkt_offset: Offset from which the actual packet data starts 574 * @pool: handle to flow_pool this descriptor belongs to. 575 */ 576 struct dp_tx_desc_s { 577 struct dp_tx_desc_s *next; 578 qdf_nbuf_t nbuf; 579 uint16_t length; 580 #ifdef DP_TX_TRACKING 581 uint32_t magic; 582 uint64_t timestamp_tick; 583 #endif 584 uint16_t flags; 585 uint32_t id; 586 qdf_dma_addr_t dma_addr; 587 uint8_t vdev_id; 588 uint8_t tx_status; 589 uint16_t peer_id; 590 struct dp_pdev *pdev; 591 uint8_t tx_encap_type:2, 592 buffer_src:3, 593 reserved:3; 594 uint8_t frm_type; 595 uint8_t pkt_offset; 596 uint8_t pool_id; 597 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 598 qdf_ktime_t timestamp; 599 struct hal_tx_desc_comp_s comp; 600 }; 601 602 #ifdef QCA_AC_BASED_FLOW_CONTROL 603 /** 604 * enum flow_pool_status - flow pool status 605 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 606 * and network queues are unpaused 607 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 608 * and network queues are paused 609 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 610 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 611 * @FLOW_POOL_ACTIVE_UNPAUSED_REATTACH: pool is reattached but network 612 * queues are not paused 613 */ 614 enum flow_pool_status { 615 FLOW_POOL_ACTIVE_UNPAUSED = 0, 616 FLOW_POOL_ACTIVE_PAUSED = 1, 617 FLOW_POOL_BE_BK_PAUSED = 2, 618 FLOW_POOL_VI_PAUSED = 3, 619 FLOW_POOL_VO_PAUSED = 4, 620 FLOW_POOL_INVALID = 5, 621 FLOW_POOL_INACTIVE = 6, 622 FLOW_POOL_ACTIVE_UNPAUSED_REATTACH = 7, 623 }; 624 625 #else 626 /** 627 * enum flow_pool_status - flow pool status 628 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 629 * and network queues are unpaused 630 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 631 * and network queues are paused 632 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 633 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 634 */ 635 enum flow_pool_status { 636 FLOW_POOL_ACTIVE_UNPAUSED = 0, 637 FLOW_POOL_ACTIVE_PAUSED = 1, 638 FLOW_POOL_BE_BK_PAUSED = 2, 639 FLOW_POOL_VI_PAUSED = 3, 640 FLOW_POOL_VO_PAUSED = 4, 641 FLOW_POOL_INVALID = 5, 642 FLOW_POOL_INACTIVE = 6, 643 }; 644 645 #endif 646 647 /** 648 * struct dp_tx_tso_seg_pool_s 649 * @pool_size: total number of pool elements 650 * @num_free: free element count 651 * @freelist: first free element pointer 652 * @desc_pages: multiple page allocation information for actual descriptors 653 * @lock: lock for accessing the pool 654 */ 655 struct dp_tx_tso_seg_pool_s { 656 uint16_t pool_size; 657 uint16_t num_free; 658 struct qdf_tso_seg_elem_t *freelist; 659 struct qdf_mem_multi_page_t desc_pages; 660 qdf_spinlock_t lock; 661 }; 662 663 /** 664 * struct dp_tx_tso_num_seg_pool_s { 665 * @num_seg_pool_size: total number of pool elements 666 * @num_free: free element count 667 * @freelist: first free element pointer 668 * @desc_pages: multiple page allocation information for actual descriptors 669 * @lock: lock for accessing the pool 670 */ 671 672 struct dp_tx_tso_num_seg_pool_s { 673 uint16_t num_seg_pool_size; 674 uint16_t num_free; 675 struct qdf_tso_num_seg_elem_t *freelist; 676 struct qdf_mem_multi_page_t desc_pages; 677 /*tso mutex */ 678 qdf_spinlock_t lock; 679 }; 680 681 /** 682 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 683 * @elem_size: Size of each descriptor in the pool 684 * @pool_size: Total number of descriptors in the pool 685 * @num_free: Number of free descriptors 686 * @num_allocated: Number of used descriptors 687 * @freelist: Chain of free descriptors 688 * @desc_pages: multiple page allocation information for actual descriptors 689 * @num_invalid_bin: Deleted pool with pending Tx completions. 690 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 691 * @flow_pool_array: List of allocated flow pools 692 * @lock- Lock for descriptor allocation/free from/to the pool 693 */ 694 struct dp_tx_desc_pool_s { 695 uint16_t elem_size; 696 uint32_t num_allocated; 697 struct dp_tx_desc_s *freelist; 698 struct qdf_mem_multi_page_t desc_pages; 699 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 700 uint16_t pool_size; 701 uint8_t flow_pool_id; 702 uint8_t num_invalid_bin; 703 uint16_t avail_desc; 704 enum flow_pool_status status; 705 enum htt_flow_type flow_type; 706 #ifdef QCA_AC_BASED_FLOW_CONTROL 707 uint16_t stop_th[FL_TH_MAX]; 708 uint16_t start_th[FL_TH_MAX]; 709 qdf_time_t max_pause_time[FL_TH_MAX]; 710 qdf_time_t latest_pause_time[FL_TH_MAX]; 711 #else 712 uint16_t stop_th; 713 uint16_t start_th; 714 #endif 715 uint16_t pkt_drop_no_desc; 716 qdf_spinlock_t flow_pool_lock; 717 uint8_t pool_create_cnt; 718 void *pool_owner_ctx; 719 #else 720 uint16_t elem_count; 721 uint32_t num_free; 722 qdf_spinlock_t lock; 723 #endif 724 }; 725 726 /** 727 * struct dp_txrx_pool_stats - flow pool related statistics 728 * @pool_map_count: flow pool map received 729 * @pool_unmap_count: flow pool unmap received 730 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 731 */ 732 struct dp_txrx_pool_stats { 733 uint16_t pool_map_count; 734 uint16_t pool_unmap_count; 735 uint16_t pkt_drop_no_pool; 736 }; 737 738 /** 739 * struct dp_srng - DP srng structure 740 * @hal_srng: hal_srng handle 741 * @base_vaddr_unaligned: un-aligned virtual base address of the srng ring 742 * @base_vaddr_aligned: aligned virtual base address of the srng ring 743 * @base_paddr_unaligned: un-aligned physical base address of the srng ring 744 * @base_paddr_aligned: aligned physical base address of the srng ring 745 * @alloc_size: size of the srng ring 746 * @cached: is the srng ring memory cached or un-cached memory 747 * @irq: irq number of the srng ring 748 * @num_entries: number of entries in the srng ring 749 * @is_mem_prealloc: Is this srng memeory pre-allocated 750 * @crit_thresh: Critical threshold for near-full processing of this srng 751 * @safe_thresh: Safe threshold for near-full processing of this srng 752 * @near_full: Flag to indicate srng is near-full 753 */ 754 struct dp_srng { 755 hal_ring_handle_t hal_srng; 756 void *base_vaddr_unaligned; 757 void *base_vaddr_aligned; 758 qdf_dma_addr_t base_paddr_unaligned; 759 qdf_dma_addr_t base_paddr_aligned; 760 uint32_t alloc_size; 761 uint8_t cached; 762 int irq; 763 uint32_t num_entries; 764 #ifdef DP_MEM_PRE_ALLOC 765 uint8_t is_mem_prealloc; 766 #endif 767 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 768 uint16_t crit_thresh; 769 uint16_t safe_thresh; 770 qdf_atomic_t near_full; 771 #endif 772 }; 773 774 struct dp_rx_reorder_array_elem { 775 qdf_nbuf_t head; 776 qdf_nbuf_t tail; 777 }; 778 779 #define DP_RX_BA_INACTIVE 0 780 #define DP_RX_BA_ACTIVE 1 781 #define DP_RX_BA_IN_PROGRESS 2 782 struct dp_reo_cmd_info { 783 uint16_t cmd; 784 enum hal_reo_cmd_type cmd_type; 785 void *data; 786 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 787 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 788 }; 789 790 struct dp_peer_delay_stats { 791 struct cdp_delay_tid_stats delay_tid_stats[CDP_MAX_DATA_TIDS] 792 [CDP_MAX_TXRX_CTX]; 793 }; 794 795 /* Rx TID defrag*/ 796 struct dp_rx_tid_defrag { 797 /* TID */ 798 int tid; 799 800 /* only used for defrag right now */ 801 TAILQ_ENTRY(dp_rx_tid_defrag) defrag_waitlist_elem; 802 803 /* Store dst desc for reinjection */ 804 hal_ring_desc_t dst_ring_desc; 805 struct dp_rx_desc *head_frag_desc; 806 807 /* Sequence and fragments that are being processed currently */ 808 uint32_t curr_seq_num; 809 uint32_t curr_frag_num; 810 811 /* TODO: Check the following while adding defragmentation support */ 812 struct dp_rx_reorder_array_elem *array; 813 /* base - single rx reorder element used for non-aggr cases */ 814 struct dp_rx_reorder_array_elem base; 815 /* rx_tid lock */ 816 qdf_spinlock_t defrag_tid_lock; 817 818 /* head PN number */ 819 uint64_t pn128[2]; 820 821 uint32_t defrag_timeout_ms; 822 823 /* defrag usage only, dp_peer pointer related with this tid */ 824 struct dp_txrx_peer *defrag_peer; 825 }; 826 827 /* Rx TID */ 828 struct dp_rx_tid { 829 /* TID */ 830 int tid; 831 832 /* Num of addba requests */ 833 uint32_t num_of_addba_req; 834 835 /* Num of addba responses */ 836 uint32_t num_of_addba_resp; 837 838 /* Num of delba requests */ 839 uint32_t num_of_delba_req; 840 841 /* Num of addba responses successful */ 842 uint32_t num_addba_rsp_success; 843 844 /* Num of addba responses failed */ 845 uint32_t num_addba_rsp_failed; 846 847 /* pn size */ 848 uint8_t pn_size; 849 /* REO TID queue descriptors */ 850 void *hw_qdesc_vaddr_unaligned; 851 void *hw_qdesc_vaddr_aligned; 852 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 853 qdf_dma_addr_t hw_qdesc_paddr; 854 uint32_t hw_qdesc_alloc_size; 855 856 /* RX ADDBA session state */ 857 int ba_status; 858 859 /* RX BA window size */ 860 uint16_t ba_win_size; 861 862 /* Starting sequence number in Addba request */ 863 uint16_t startseqnum; 864 uint16_t dialogtoken; 865 uint16_t statuscode; 866 /* user defined ADDBA response status code */ 867 uint16_t userstatuscode; 868 869 /* rx_tid lock */ 870 qdf_spinlock_t tid_lock; 871 872 /* Store ppdu_id when 2k exception is received */ 873 uint32_t ppdu_id_2k; 874 875 /* Delba Tx completion status */ 876 uint8_t delba_tx_status; 877 878 /* Delba Tx retry count */ 879 uint8_t delba_tx_retry; 880 881 /* Delba stats */ 882 uint32_t delba_tx_success_cnt; 883 uint32_t delba_tx_fail_cnt; 884 885 /* Delba reason code for retries */ 886 uint8_t delba_rcode; 887 888 /* Coex Override preserved windows size 1 based */ 889 uint16_t rx_ba_win_size_override; 890 #ifdef IPA_OFFLOAD 891 /* rx msdu count per tid */ 892 struct cdp_pkt_info rx_msdu_cnt; 893 #endif 894 895 }; 896 897 /** 898 * struct dp_intr_stats - DP Interrupt Stats for an interrupt context 899 * @num_tx_ring_masks: interrupts with tx_ring_mask set 900 * @num_rx_ring_masks: interrupts with rx_ring_mask set 901 * @num_rx_mon_ring_masks: interrupts with rx_mon_ring_mask set 902 * @num_rx_err_ring_masks: interrupts with rx_err_ring_mask set 903 * @num_rx_wbm_rel_ring_masks: interrupts with rx_wbm_rel_ring_mask set 904 * @num_reo_status_ring_masks: interrupts with reo_status_ring_mask set 905 * @num_rxdma2host_ring_masks: interrupts with rxdma2host_ring_mask set 906 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 907 * @num_host2rxdma_mon_ring_masks: interrupts with host2rxdma_ring_mask set 908 * @num_rx_ring_near_full_masks: Near-full interrupts for REO DST ring 909 * @num_tx_comp_ring_near_full_masks: Near-full interrupts for TX completion 910 * @num_rx_wbm_rel_ring_near_full_masks: total number of times the wbm rel ring 911 * near full interrupt was received 912 * @num_reo_status_ring_near_full_masks: total number of times the reo status 913 * near full interrupt was received 914 * @num_near_full_masks: total number of times the near full interrupt 915 * was received 916 * @num_masks: total number of times the interrupt was received 917 * @num_host2txmon_ring_masks: interrupts with host2txmon_ring_mask set 918 * @num_near_full_masks: total number of times the interrupt was received 919 * @num_masks: total number of times the near full interrupt was received 920 * @num_tx_mon_ring_masks: interrupts with num_tx_mon_ring_masks set 921 * 922 * Counter for individual masks are incremented only if there are any packets 923 * on that ring. 924 */ 925 struct dp_intr_stats { 926 uint32_t num_tx_ring_masks[MAX_TCL_DATA_RINGS]; 927 uint32_t num_rx_ring_masks[MAX_REO_DEST_RINGS]; 928 uint32_t num_rx_mon_ring_masks; 929 uint32_t num_rx_err_ring_masks; 930 uint32_t num_rx_wbm_rel_ring_masks; 931 uint32_t num_reo_status_ring_masks; 932 uint32_t num_rxdma2host_ring_masks; 933 uint32_t num_host2rxdma_ring_masks; 934 uint32_t num_host2rxdma_mon_ring_masks; 935 uint32_t num_rx_ring_near_full_masks[MAX_REO_DEST_RINGS]; 936 uint32_t num_tx_comp_ring_near_full_masks[MAX_TCL_DATA_RINGS]; 937 uint32_t num_rx_wbm_rel_ring_near_full_masks; 938 uint32_t num_reo_status_ring_near_full_masks; 939 uint32_t num_host2txmon_ring__masks; 940 uint32_t num_near_full_masks; 941 uint32_t num_masks; 942 uint32_t num_tx_mon_ring_masks; 943 }; 944 945 /* per interrupt context */ 946 struct dp_intr { 947 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 948 associated with this napi context */ 949 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 950 with this interrupt context */ 951 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 952 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 953 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 954 uint8_t reo_status_ring_mask; /* REO command response ring */ 955 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 956 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 957 /* Host to RXDMA monitor buffer ring */ 958 uint8_t host2rxdma_mon_ring_mask; 959 /* RX REO rings near full interrupt mask */ 960 uint8_t rx_near_full_grp_1_mask; 961 /* RX REO rings near full interrupt mask */ 962 uint8_t rx_near_full_grp_2_mask; 963 /* WBM TX completion rings near full interrupt mask */ 964 uint8_t tx_ring_near_full_mask; 965 uint8_t host2txmon_ring_mask; /* Tx monitor buffer ring */ 966 uint8_t tx_mon_ring_mask; /* Tx monitor ring mask (0-2) */ 967 struct dp_soc *soc; /* Reference to SoC structure , 968 to get DMA ring handles */ 969 qdf_lro_ctx_t lro_ctx; 970 uint8_t dp_intr_id; 971 972 /* Interrupt Stats for individual masks */ 973 struct dp_intr_stats intr_stats; 974 uint8_t umac_reset_intr_mask; /* UMAC reset interrupt mask */ 975 }; 976 977 #define REO_DESC_FREELIST_SIZE 64 978 #define REO_DESC_FREE_DEFER_MS 1000 979 struct reo_desc_list_node { 980 qdf_list_node_t node; 981 unsigned long free_ts; 982 struct dp_rx_tid rx_tid; 983 bool resend_update_reo_cmd; 984 uint32_t pending_ext_desc_size; 985 #ifdef REO_QDESC_HISTORY 986 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 987 #endif 988 }; 989 990 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 991 #define REO_DESC_DEFERRED_FREELIST_SIZE 256 992 #define REO_DESC_DEFERRED_FREE_MS 30000 993 994 struct reo_desc_deferred_freelist_node { 995 qdf_list_node_t node; 996 unsigned long free_ts; 997 void *hw_qdesc_vaddr_unaligned; 998 qdf_dma_addr_t hw_qdesc_paddr; 999 uint32_t hw_qdesc_alloc_size; 1000 #ifdef REO_QDESC_HISTORY 1001 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1002 #endif /* REO_QDESC_HISTORY */ 1003 }; 1004 #endif /* WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY */ 1005 1006 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1007 /** 1008 * struct reo_cmd_event_record: Elements to record for each reo command 1009 * @cmd_type: reo command type 1010 * @cmd_return_status: reo command post status 1011 * @timestamp: record timestamp for the reo command 1012 */ 1013 struct reo_cmd_event_record { 1014 enum hal_reo_cmd_type cmd_type; 1015 uint8_t cmd_return_status; 1016 uint64_t timestamp; 1017 }; 1018 1019 /** 1020 * struct reo_cmd_event_history: Account for reo cmd events 1021 * @index: record number 1022 * @cmd_record: list of records 1023 */ 1024 struct reo_cmd_event_history { 1025 qdf_atomic_t index; 1026 struct reo_cmd_event_record cmd_record[REO_CMD_EVENT_HIST_MAX]; 1027 }; 1028 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1029 1030 /* SoC level data path statistics */ 1031 struct dp_soc_stats { 1032 struct { 1033 uint32_t added; 1034 uint32_t deleted; 1035 uint32_t aged_out; 1036 uint32_t map_err; 1037 uint32_t ast_mismatch; 1038 } ast; 1039 1040 struct { 1041 uint32_t added; 1042 uint32_t deleted; 1043 } mec; 1044 1045 /* SOC level TX stats */ 1046 struct { 1047 /* Total packets transmitted */ 1048 struct cdp_pkt_info egress[MAX_TCL_DATA_RINGS]; 1049 /* Enqueues per tcl ring */ 1050 uint32_t tcl_enq[MAX_TCL_DATA_RINGS]; 1051 /* packets dropped on tx because of no peer */ 1052 struct cdp_pkt_info tx_invalid_peer; 1053 /* descriptors in each tcl ring */ 1054 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 1055 /* Descriptors in use at soc */ 1056 uint32_t desc_in_use; 1057 /* tqm_release_reason == FW removed */ 1058 uint32_t dropped_fw_removed; 1059 /* tx completion release_src != TQM or FW */ 1060 uint32_t invalid_release_source; 1061 /* tx completion wbm_internal_error */ 1062 uint32_t wbm_internal_error[MAX_WBM_INT_ERROR_REASONS]; 1063 /* tx completion non_wbm_internal_error */ 1064 uint32_t non_wbm_internal_err; 1065 /* TX Comp loop packet limit hit */ 1066 uint32_t tx_comp_loop_pkt_limit_hit; 1067 /* Head pointer Out of sync at the end of dp_tx_comp_handler */ 1068 uint32_t hp_oos2; 1069 /* tx desc freed as part of vdev detach */ 1070 uint32_t tx_comp_exception; 1071 /* TQM drops after/during peer delete */ 1072 uint64_t tqm_drop_no_peer; 1073 /* Number of tx completions reaped per WBM2SW release ring */ 1074 uint32_t tx_comp[MAX_TCL_DATA_RINGS]; 1075 /* Number of tx completions force freed */ 1076 uint32_t tx_comp_force_freed; 1077 } tx; 1078 1079 /* SOC level RX stats */ 1080 struct { 1081 /* Total rx packets count */ 1082 struct cdp_pkt_info ingress; 1083 /* Rx errors */ 1084 /* Total Packets in Rx Error ring */ 1085 uint32_t err_ring_pkts; 1086 /* No of Fragments */ 1087 uint32_t rx_frags; 1088 /* No of incomplete fragments in waitlist */ 1089 uint32_t rx_frag_wait; 1090 /* Fragments dropped due to errors */ 1091 uint32_t rx_frag_err; 1092 /* Fragments received OOR causing sequence num mismatch */ 1093 uint32_t rx_frag_oor; 1094 /* Fragments dropped due to len errors in skb */ 1095 uint32_t rx_frag_err_len_error; 1096 /* Fragments dropped due to no peer found */ 1097 uint32_t rx_frag_err_no_peer; 1098 /* No of reinjected packets */ 1099 uint32_t reo_reinject; 1100 /* Reap loop packet limit hit */ 1101 uint32_t reap_loop_pkt_limit_hit; 1102 /* Head pointer Out of sync at the end of dp_rx_process */ 1103 uint32_t hp_oos2; 1104 /* Rx ring near full */ 1105 uint32_t near_full; 1106 /* Break ring reaping as not all scattered msdu received */ 1107 uint32_t msdu_scatter_wait_break; 1108 /* Number of bar frames received */ 1109 uint32_t bar_frame; 1110 /* Number of frames routed from rxdma */ 1111 uint32_t rxdma2rel_route_drop; 1112 /* Number of frames routed from reo*/ 1113 uint32_t reo2rel_route_drop; 1114 1115 struct { 1116 /* Invalid RBM error count */ 1117 uint32_t invalid_rbm; 1118 /* Invalid VDEV Error count */ 1119 uint32_t invalid_vdev; 1120 /* Invalid PDEV error count */ 1121 uint32_t invalid_pdev; 1122 1123 /* Packets delivered to stack that no related peer */ 1124 uint32_t pkt_delivered_no_peer; 1125 /* Defrag peer uninit error count */ 1126 uint32_t defrag_peer_uninit; 1127 /* Invalid sa_idx or da_idx*/ 1128 uint32_t invalid_sa_da_idx; 1129 /* MSDU DONE failures */ 1130 uint32_t msdu_done_fail; 1131 /* Invalid PEER Error count */ 1132 struct cdp_pkt_info rx_invalid_peer; 1133 /* Invalid PEER ID count */ 1134 struct cdp_pkt_info rx_invalid_peer_id; 1135 /* Invalid packet length */ 1136 struct cdp_pkt_info rx_invalid_pkt_len; 1137 /* HAL ring access Fail error count */ 1138 uint32_t hal_ring_access_fail; 1139 /* HAL ring access full Fail error count */ 1140 uint32_t hal_ring_access_full_fail; 1141 /* RX DMA error count */ 1142 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 1143 /* RX REO DEST Desc Invalid Magic count */ 1144 uint32_t rx_desc_invalid_magic; 1145 /* REO Error count */ 1146 uint32_t reo_error[HAL_REO_ERR_MAX]; 1147 /* HAL REO ERR Count */ 1148 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 1149 /* HAL REO DEST Duplicate count */ 1150 uint32_t hal_reo_dest_dup; 1151 /* HAL WBM RELEASE Duplicate count */ 1152 uint32_t hal_wbm_rel_dup; 1153 /* HAL RXDMA error Duplicate count */ 1154 uint32_t hal_rxdma_err_dup; 1155 /* ipa smmu map duplicate count */ 1156 uint32_t ipa_smmu_map_dup; 1157 /* ipa smmu unmap duplicate count */ 1158 uint32_t ipa_smmu_unmap_dup; 1159 /* ipa smmu unmap while ipa pipes is disabled */ 1160 uint32_t ipa_unmap_no_pipe; 1161 /* REO cmd send fail/requeue count */ 1162 uint32_t reo_cmd_send_fail; 1163 /* REO cmd send drain count */ 1164 uint32_t reo_cmd_send_drain; 1165 /* RX msdu drop count due to scatter */ 1166 uint32_t scatter_msdu; 1167 /* RX msdu drop count due to invalid cookie */ 1168 uint32_t invalid_cookie; 1169 /* Count of stale cookie read in RX path */ 1170 uint32_t stale_cookie; 1171 /* Delba sent count due to RX 2k jump */ 1172 uint32_t rx_2k_jump_delba_sent; 1173 /* RX 2k jump msdu indicated to stack count */ 1174 uint32_t rx_2k_jump_to_stack; 1175 /* RX 2k jump msdu dropped count */ 1176 uint32_t rx_2k_jump_drop; 1177 /* REO ERR msdu buffer received */ 1178 uint32_t reo_err_msdu_buf_rcved; 1179 /* REO ERR msdu buffer with invalid coookie received */ 1180 uint32_t reo_err_msdu_buf_invalid_cookie; 1181 /* REO OOR msdu drop count */ 1182 uint32_t reo_err_oor_drop; 1183 /* REO OOR msdu indicated to stack count */ 1184 uint32_t reo_err_oor_to_stack; 1185 /* REO OOR scattered msdu count */ 1186 uint32_t reo_err_oor_sg_count; 1187 /* RX msdu rejected count on delivery to vdev stack_fn*/ 1188 uint32_t rejected; 1189 /* Incorrect msdu count in MPDU desc info */ 1190 uint32_t msdu_count_mismatch; 1191 /* RX raw frame dropped count */ 1192 uint32_t raw_frm_drop; 1193 /* Stale link desc cookie count*/ 1194 uint32_t invalid_link_cookie; 1195 /* Nbuf sanity failure */ 1196 uint32_t nbuf_sanity_fail; 1197 /* Duplicate link desc refilled */ 1198 uint32_t dup_refill_link_desc; 1199 /* Incorrect msdu continuation bit in MSDU desc */ 1200 uint32_t msdu_continuation_err; 1201 /* count of start sequence (ssn) updates */ 1202 uint32_t ssn_update_count; 1203 /* count of bar handling fail */ 1204 uint32_t bar_handle_fail_count; 1205 /* EAPOL drop count in intrabss scenario */ 1206 uint32_t intrabss_eapol_drop; 1207 /* PN check failed for 2K-jump or OOR error */ 1208 uint32_t pn_in_dest_check_fail; 1209 /* MSDU len err count */ 1210 uint32_t msdu_len_err; 1211 /* Rx flush count */ 1212 uint32_t rx_flush_count; 1213 /* Rx invalid tid count */ 1214 uint32_t rx_invalid_tid_err; 1215 } err; 1216 1217 /* packet count per core - per ring */ 1218 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 1219 } rx; 1220 1221 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1222 struct reo_cmd_event_history cmd_event_history; 1223 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1224 }; 1225 1226 union dp_align_mac_addr { 1227 uint8_t raw[QDF_MAC_ADDR_SIZE]; 1228 struct { 1229 uint16_t bytes_ab; 1230 uint16_t bytes_cd; 1231 uint16_t bytes_ef; 1232 } align2; 1233 struct { 1234 uint32_t bytes_abcd; 1235 uint16_t bytes_ef; 1236 } align4; 1237 struct __attribute__((__packed__)) { 1238 uint16_t bytes_ab; 1239 uint32_t bytes_cdef; 1240 } align4_2; 1241 }; 1242 1243 /** 1244 * struct dp_ast_free_cb_params - HMWDS free callback cookie 1245 * @mac_addr: ast mac address 1246 * @peer_mac_addr: mac address of peer 1247 * @type: ast entry type 1248 * @vdev_id: vdev_id 1249 * @flags: ast flags 1250 */ 1251 struct dp_ast_free_cb_params { 1252 union dp_align_mac_addr mac_addr; 1253 union dp_align_mac_addr peer_mac_addr; 1254 enum cdp_txrx_ast_entry_type type; 1255 uint8_t vdev_id; 1256 uint32_t flags; 1257 }; 1258 1259 /* 1260 * dp_ast_entry 1261 * 1262 * @ast_idx: Hardware AST Index 1263 * @peer_id: Next Hop peer_id (for non-WDS nodes, this will be point to 1264 * associated peer with this MAC address) 1265 * @mac_addr: MAC Address for this AST entry 1266 * @next_hop: Set to 1 if this is for a WDS node 1267 * @is_active: flag to indicate active data traffic on this node 1268 * (used for aging out/expiry) 1269 * @ase_list_elem: node in peer AST list 1270 * @is_bss: flag to indicate if entry corresponds to bss peer 1271 * @is_mapped: flag to indicate that we have mapped the AST entry 1272 * in ast_table 1273 * @pdev_id: pdev ID 1274 * @vdev_id: vdev ID 1275 * @ast_hash_value: hast value in HW 1276 * @ref_cnt: reference count 1277 * @type: flag to indicate type of the entry(static/WDS/MEC) 1278 * @delete_in_progress: Flag to indicate that delete commands send to FW 1279 * and host is waiting for response from FW 1280 * @callback: ast free/unmap callback 1281 * @cookie: argument to callback 1282 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 1283 */ 1284 struct dp_ast_entry { 1285 uint16_t ast_idx; 1286 uint16_t peer_id; 1287 union dp_align_mac_addr mac_addr; 1288 bool next_hop; 1289 bool is_active; 1290 bool is_mapped; 1291 uint8_t pdev_id; 1292 uint8_t vdev_id; 1293 uint16_t ast_hash_value; 1294 qdf_atomic_t ref_cnt; 1295 enum cdp_txrx_ast_entry_type type; 1296 bool delete_in_progress; 1297 txrx_ast_free_cb callback; 1298 void *cookie; 1299 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 1300 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 1301 }; 1302 1303 /* 1304 * dp_mec_entry 1305 * 1306 * @mac_addr: MAC Address for this MEC entry 1307 * @is_active: flag to indicate active data traffic on this node 1308 * (used for aging out/expiry) 1309 * @pdev_id: pdev ID 1310 * @vdev_id: vdev ID 1311 * @hash_list_elem: node in soc MEC hash list (mac address used as hash) 1312 */ 1313 struct dp_mec_entry { 1314 union dp_align_mac_addr mac_addr; 1315 bool is_active; 1316 uint8_t pdev_id; 1317 uint8_t vdev_id; 1318 1319 TAILQ_ENTRY(dp_mec_entry) hash_list_elem; 1320 }; 1321 1322 /* SOC level htt stats */ 1323 struct htt_t2h_stats { 1324 /* lock to protect htt_stats_msg update */ 1325 qdf_spinlock_t lock; 1326 1327 /* work queue to process htt stats */ 1328 qdf_work_t work; 1329 1330 /* T2H Ext stats message queue */ 1331 qdf_nbuf_queue_t msg; 1332 1333 /* number of completed stats in htt_stats_msg */ 1334 uint32_t num_stats; 1335 }; 1336 1337 struct link_desc_bank { 1338 void *base_vaddr_unaligned; 1339 void *base_vaddr; 1340 qdf_dma_addr_t base_paddr_unaligned; 1341 qdf_dma_addr_t base_paddr; 1342 uint32_t size; 1343 }; 1344 1345 struct rx_buff_pool { 1346 qdf_nbuf_queue_head_t emerg_nbuf_q; 1347 uint32_t nbuf_fail_cnt; 1348 bool is_initialized; 1349 }; 1350 1351 struct rx_refill_buff_pool { 1352 bool is_initialized; 1353 uint16_t head; 1354 uint16_t tail; 1355 struct dp_pdev *dp_pdev; 1356 uint16_t max_bufq_len; 1357 qdf_nbuf_t buf_elem[2048]; 1358 }; 1359 1360 #ifdef DP_TX_HW_DESC_HISTORY 1361 #define DP_TX_HW_DESC_HIST_MAX 6144 1362 1363 struct dp_tx_hw_desc_evt { 1364 uint8_t tcl_desc[HAL_TX_DESC_LEN_BYTES]; 1365 uint64_t posted; 1366 uint32_t hp; 1367 uint32_t tp; 1368 }; 1369 1370 /* struct dp_tx_hw_desc_history - TX HW desc hisotry 1371 * @index: Index where the last entry is written 1372 * @entry: history entries 1373 */ 1374 struct dp_tx_hw_desc_history { 1375 uint64_t index; 1376 struct dp_tx_hw_desc_evt entry[DP_TX_HW_DESC_HIST_MAX]; 1377 }; 1378 #endif 1379 1380 /* 1381 * enum dp_mon_status_process_event - Events for monitor status buffer record 1382 * @DP_MON_STATUS_BUF_REAP: Monitor status buffer is reaped from ring 1383 * @DP_MON_STATUS_BUF_ENQUEUE: Status buffer is enqueued to local queue 1384 * @DP_MON_STATUS_BUF_DEQUEUE: Status buffer is dequeued from local queue 1385 */ 1386 enum dp_mon_status_process_event { 1387 DP_MON_STATUS_BUF_REAP, 1388 DP_MON_STATUS_BUF_ENQUEUE, 1389 DP_MON_STATUS_BUF_DEQUEUE, 1390 }; 1391 1392 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 1393 #define DP_MON_STATUS_HIST_MAX 2048 1394 1395 /** 1396 * struct dp_buf_info_record - ring buffer info 1397 * @hbi: HW ring buffer info 1398 * @timestamp: timestamp when this entry was recorded 1399 * @event: event 1400 * @rx_desc: RX descriptor corresponding to the received buffer 1401 * @nbuf: buffer attached to rx_desc, if event is REAP, else the buffer 1402 * which was enqueued or dequeued. 1403 * @rx_desc_nbuf_data: nbuf data pointer. 1404 */ 1405 struct dp_mon_stat_info_record { 1406 struct hal_buf_info hbi; 1407 uint64_t timestamp; 1408 enum dp_mon_status_process_event event; 1409 void *rx_desc; 1410 qdf_nbuf_t nbuf; 1411 uint8_t *rx_desc_nbuf_data; 1412 }; 1413 1414 /* struct dp_rx_history - rx ring hisotry 1415 * @index: Index where the last entry is written 1416 * @entry: history entries 1417 */ 1418 struct dp_mon_status_ring_history { 1419 qdf_atomic_t index; 1420 struct dp_mon_stat_info_record entry[DP_MON_STATUS_HIST_MAX]; 1421 }; 1422 #endif 1423 1424 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 1425 /* 1426 * The logic for get current index of these history is dependent on this 1427 * value being power of 2. 1428 */ 1429 #define DP_RX_HIST_MAX 2048 1430 #define DP_RX_ERR_HIST_MAX 2048 1431 #define DP_RX_REINJECT_HIST_MAX 1024 1432 #define DP_RX_REFILL_HIST_MAX 2048 1433 1434 QDF_COMPILE_TIME_ASSERT(rx_history_size, 1435 (DP_RX_HIST_MAX & 1436 (DP_RX_HIST_MAX - 1)) == 0); 1437 QDF_COMPILE_TIME_ASSERT(rx_err_history_size, 1438 (DP_RX_ERR_HIST_MAX & 1439 (DP_RX_ERR_HIST_MAX - 1)) == 0); 1440 QDF_COMPILE_TIME_ASSERT(rx_reinject_history_size, 1441 (DP_RX_REINJECT_HIST_MAX & 1442 (DP_RX_REINJECT_HIST_MAX - 1)) == 0); 1443 QDF_COMPILE_TIME_ASSERT(rx_refill_history_size, 1444 (DP_RX_REFILL_HIST_MAX & 1445 (DP_RX_REFILL_HIST_MAX - 1)) == 0); 1446 1447 1448 /** 1449 * struct dp_buf_info_record - ring buffer info 1450 * @hbi: HW ring buffer info 1451 * @timestamp: timestamp when this entry was recorded 1452 */ 1453 struct dp_buf_info_record { 1454 struct hal_buf_info hbi; 1455 uint64_t timestamp; 1456 }; 1457 1458 /** 1459 * struct dp_refill_info_record - ring refill buffer info 1460 * @hp: HP value after refill 1461 * @tp: cached tail value during refill 1462 * @num_req: number of buffers requested to refill 1463 * @num_refill: number of buffers refilled to ring 1464 * @timestamp: timestamp when this entry was recorded 1465 */ 1466 struct dp_refill_info_record { 1467 uint32_t hp; 1468 uint32_t tp; 1469 uint32_t num_req; 1470 uint32_t num_refill; 1471 uint64_t timestamp; 1472 }; 1473 1474 /* struct dp_rx_history - rx ring hisotry 1475 * @index: Index where the last entry is written 1476 * @entry: history entries 1477 */ 1478 struct dp_rx_history { 1479 qdf_atomic_t index; 1480 struct dp_buf_info_record entry[DP_RX_HIST_MAX]; 1481 }; 1482 1483 /* struct dp_rx_err_history - rx err ring hisotry 1484 * @index: Index where the last entry is written 1485 * @entry: history entries 1486 */ 1487 struct dp_rx_err_history { 1488 qdf_atomic_t index; 1489 struct dp_buf_info_record entry[DP_RX_ERR_HIST_MAX]; 1490 }; 1491 1492 /* struct dp_rx_reinject_history - rx reinject ring hisotry 1493 * @index: Index where the last entry is written 1494 * @entry: history entries 1495 */ 1496 struct dp_rx_reinject_history { 1497 qdf_atomic_t index; 1498 struct dp_buf_info_record entry[DP_RX_REINJECT_HIST_MAX]; 1499 }; 1500 1501 /* struct dp_rx_refill_history - rx buf refill hisotry 1502 * @index: Index where the last entry is written 1503 * @entry: history entries 1504 */ 1505 struct dp_rx_refill_history { 1506 qdf_atomic_t index; 1507 struct dp_refill_info_record entry[DP_RX_REFILL_HIST_MAX]; 1508 }; 1509 1510 #endif 1511 1512 enum dp_tx_event_type { 1513 DP_TX_DESC_INVAL_EVT = 0, 1514 DP_TX_DESC_MAP, 1515 DP_TX_DESC_COOKIE, 1516 DP_TX_DESC_FLUSH, 1517 DP_TX_DESC_UNMAP, 1518 DP_TX_COMP_UNMAP, 1519 DP_TX_COMP_UNMAP_ERR, 1520 DP_TX_COMP_MSDU_EXT, 1521 }; 1522 1523 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 1524 /* Size must be in 2 power, for bitwise index rotation */ 1525 #define DP_TX_TCL_HISTORY_SIZE 0x4000 1526 #define DP_TX_COMP_HISTORY_SIZE 0x4000 1527 1528 struct dp_tx_desc_event { 1529 qdf_nbuf_t skb; 1530 dma_addr_t paddr; 1531 uint32_t sw_cookie; 1532 enum dp_tx_event_type type; 1533 uint64_t ts; 1534 }; 1535 1536 struct dp_tx_tcl_history { 1537 qdf_atomic_t index; 1538 struct dp_tx_desc_event entry[DP_TX_TCL_HISTORY_SIZE]; 1539 }; 1540 1541 struct dp_tx_comp_history { 1542 qdf_atomic_t index; 1543 struct dp_tx_desc_event entry[DP_TX_COMP_HISTORY_SIZE]; 1544 }; 1545 #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */ 1546 1547 /* structure to record recent operation related variable */ 1548 struct dp_last_op_info { 1549 /* last link desc buf info through WBM release ring */ 1550 struct hal_buf_info wbm_rel_link_desc; 1551 /* last link desc buf info through REO reinject ring */ 1552 struct hal_buf_info reo_reinject_link_desc; 1553 }; 1554 1555 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 1556 1557 /** 1558 * struct dp_swlm_tcl_data - params for tcl register write coalescing 1559 * descision making 1560 * @nbuf: TX packet 1561 * @tid: tid for transmitting the current packet 1562 * @num_ll_connections: Number of low latency connections on this vdev 1563 * @ring_id: TCL ring id 1564 * @pkt_len: Packet length 1565 * 1566 * This structure contains the information required by the software 1567 * latency manager to decide on whether to coalesce the current TCL 1568 * register write or not. 1569 */ 1570 struct dp_swlm_tcl_data { 1571 qdf_nbuf_t nbuf; 1572 uint8_t tid; 1573 uint8_t num_ll_connections; 1574 uint8_t ring_id; 1575 uint32_t pkt_len; 1576 }; 1577 1578 /** 1579 * union swlm_data - SWLM query data 1580 * @tcl_data: data for TCL query in SWLM 1581 */ 1582 union swlm_data { 1583 struct dp_swlm_tcl_data *tcl_data; 1584 }; 1585 1586 /** 1587 * struct dp_swlm_ops - SWLM ops 1588 * @tcl_wr_coalesce_check: handler to check if the current TCL register 1589 * write can be coalesced or not 1590 */ 1591 struct dp_swlm_ops { 1592 int (*tcl_wr_coalesce_check)(struct dp_soc *soc, 1593 struct dp_swlm_tcl_data *tcl_data); 1594 }; 1595 1596 /** 1597 * struct dp_swlm_stats - Stats for Software Latency manager. 1598 * @tcl.timer_flush_success: Num TCL HP writes success from timer context 1599 * @tcl.timer_flush_fail: Num TCL HP writes failure from timer context 1600 * @tcl.tid_fail: Num TCL register write coalescing skips, since the pkt 1601 * was being transmitted on a TID above coalescing threshold 1602 * @tcl.sp_frames: Num TCL register write coalescing skips, since the pkt 1603 * being transmitted was a special frame 1604 * @tcl.ll_connection: Num TCL register write coalescing skips, since the 1605 * vdev has low latency connections 1606 * @tcl.bytes_thresh_reached: Num TCL HP writes flush after the coalescing 1607 * bytes threshold was reached 1608 * @tcl.time_thresh_reached: Num TCL HP writes flush after the coalescing 1609 * session time expired 1610 * @tcl.tput_criteria_fail: Num TCL HP writes coalescing fails, since the 1611 * throughput did not meet session threshold 1612 * @tcl.coalesce_success: Num of TCL HP writes coalesced successfully. 1613 * @tcl.coalesce_fail: Num of TCL HP writes coalesces failed 1614 */ 1615 struct dp_swlm_stats { 1616 struct { 1617 uint32_t timer_flush_success; 1618 uint32_t timer_flush_fail; 1619 uint32_t tid_fail; 1620 uint32_t sp_frames; 1621 uint32_t ll_connection; 1622 uint32_t bytes_thresh_reached; 1623 uint32_t time_thresh_reached; 1624 uint32_t tput_criteria_fail; 1625 uint32_t coalesce_success; 1626 uint32_t coalesce_fail; 1627 } tcl[MAX_TCL_DATA_RINGS]; 1628 }; 1629 1630 /** 1631 * struct dp_swlm_tcl_params: Parameters based on TCL for different modules 1632 * in the Software latency manager. 1633 * @soc: DP soc reference 1634 * @ring_id: TCL ring id 1635 * @flush_timer: Timer for flushing the coalesced TCL HP writes 1636 * @sampling_session_tx_bytes: Num bytes transmitted in the sampling time 1637 * @bytes_flush_thresh: Bytes threshold to flush the TCL HP register write 1638 * @coalesce_end_time: End timestamp for current coalescing session 1639 * @bytes_coalesced: Num bytes coalesced in the current session 1640 * @prev_tx_packets: Previous TX packets accounted 1641 * @prev_tx_bytes: Previous TX bytes accounted 1642 * @prev_rx_bytes: Previous RX bytes accounted 1643 * @expire_time: expiry time for sample 1644 * @tput_pass_cnt: threshold throughput pass counter 1645 */ 1646 struct dp_swlm_tcl_params { 1647 struct dp_soc *soc; 1648 uint32_t ring_id; 1649 qdf_timer_t flush_timer; 1650 uint32_t sampling_session_tx_bytes; 1651 uint32_t bytes_flush_thresh; 1652 uint64_t coalesce_end_time; 1653 uint32_t bytes_coalesced; 1654 uint32_t prev_tx_packets; 1655 uint32_t prev_tx_bytes; 1656 uint32_t prev_rx_bytes; 1657 uint64_t expire_time; 1658 uint32_t tput_pass_cnt; 1659 }; 1660 1661 /** 1662 * struct dp_swlm_params: Parameters for different modules in the 1663 * Software latency manager. 1664 * @rx_traffic_thresh: Threshold for RX traffic, to begin TCL register 1665 * write coalescing 1666 * @tx_traffic_thresh: Threshold for TX traffic, to begin TCL register 1667 * write coalescing 1668 * @sampling_time: Sampling time to test the throughput threshold 1669 * @time_flush_thresh: Time threshold to flush the TCL HP register write 1670 * @tx_thresh_multiplier: Multiplier to deduce the bytes threshold after 1671 * which the TCL HP register is written, thereby 1672 * ending the coalescing. 1673 * @tx_pkt_thresh: Threshold for TX packet count, to begin TCL register 1674 * write coalescing 1675 * @tcl: TCL ring specific params 1676 */ 1677 1678 struct dp_swlm_params { 1679 uint32_t rx_traffic_thresh; 1680 uint32_t tx_traffic_thresh; 1681 uint32_t sampling_time; 1682 uint32_t time_flush_thresh; 1683 uint32_t tx_thresh_multiplier; 1684 uint32_t tx_pkt_thresh; 1685 struct dp_swlm_tcl_params tcl[MAX_TCL_DATA_RINGS]; 1686 }; 1687 1688 /** 1689 * struct dp_swlm - Software latency manager context 1690 * @ops: SWLM ops pointers 1691 * @is_enabled: SWLM enabled/disabled 1692 * @is_init: SWLM module initialized 1693 * @stats: SWLM stats 1694 * @params: SWLM SRNG params 1695 * @tcl_flush_timer: flush timer for TCL register writes 1696 */ 1697 struct dp_swlm { 1698 struct dp_swlm_ops *ops; 1699 uint8_t is_enabled:1, 1700 is_init:1; 1701 struct dp_swlm_stats stats; 1702 struct dp_swlm_params params; 1703 }; 1704 #endif 1705 1706 #ifdef IPA_OFFLOAD 1707 /* IPA uC datapath offload Wlan Tx resources */ 1708 struct ipa_dp_tx_rsc { 1709 /* Resource info to be passed to IPA */ 1710 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 1711 void *ipa_tcl_ring_base_vaddr; 1712 uint32_t ipa_tcl_ring_size; 1713 qdf_dma_addr_t ipa_tcl_hp_paddr; 1714 uint32_t alloc_tx_buf_cnt; 1715 1716 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 1717 void *ipa_wbm_ring_base_vaddr; 1718 uint32_t ipa_wbm_ring_size; 1719 qdf_dma_addr_t ipa_wbm_tp_paddr; 1720 /* WBM2SW HP shadow paddr */ 1721 qdf_dma_addr_t ipa_wbm_hp_shadow_paddr; 1722 1723 /* TX buffers populated into the WBM ring */ 1724 void **tx_buf_pool_vaddr_unaligned; 1725 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 1726 }; 1727 1728 /* IPA uC datapath offload Wlan Rx resources */ 1729 struct ipa_dp_rx_rsc { 1730 /* Resource info to be passed to IPA */ 1731 qdf_dma_addr_t ipa_reo_ring_base_paddr; 1732 void *ipa_reo_ring_base_vaddr; 1733 uint32_t ipa_reo_ring_size; 1734 qdf_dma_addr_t ipa_reo_tp_paddr; 1735 1736 /* Resource info to be passed to firmware and IPA */ 1737 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 1738 void *ipa_rx_refill_buf_ring_base_vaddr; 1739 uint32_t ipa_rx_refill_buf_ring_size; 1740 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 1741 }; 1742 #endif 1743 1744 struct dp_tx_msdu_info_s; 1745 /* 1746 * enum dp_context_type- DP Context Type 1747 * @DP_CONTEXT_TYPE_SOC: Context type DP SOC 1748 * @DP_CONTEXT_TYPE_PDEV: Context type DP PDEV 1749 * @DP_CONTEXT_TYPE_VDEV: Context type DP VDEV 1750 * @DP_CONTEXT_TYPE_PEER: Context type DP PEER 1751 * @DP_CONTEXT_TYPE_MON_SOC: Context type DP MON SOC 1752 * @DP_CONTEXT_TYPE_MON_PDEV: Context type DP MON PDEV 1753 * 1754 * Helper enums to be used to retrieve the size of the corresponding 1755 * data structure by passing the type. 1756 */ 1757 enum dp_context_type { 1758 DP_CONTEXT_TYPE_SOC, 1759 DP_CONTEXT_TYPE_PDEV, 1760 DP_CONTEXT_TYPE_VDEV, 1761 DP_CONTEXT_TYPE_PEER, 1762 DP_CONTEXT_TYPE_MON_SOC, 1763 DP_CONTEXT_TYPE_MON_PDEV 1764 }; 1765 1766 /* 1767 * struct dp_arch_ops- DP target specific arch ops 1768 * @DP_CONTEXT_TYPE_SOC: Context type DP SOC 1769 * @DP_CONTEXT_TYPE_PDEV: Context type DP PDEV 1770 * @tx_hw_enqueue: enqueue TX data to HW 1771 * @tx_comp_get_params_from_hal_desc: get software tx descriptor and release 1772 * source from HAL desc for wbm release ring 1773 * @dp_service_near_full_srngs: Handler for servicing the near full IRQ 1774 * @txrx_set_vdev_param: target specific ops while setting vdev params 1775 * @dp_srng_test_and_update_nf_params: Check if the srng is in near full state 1776 * and set the near-full params. 1777 */ 1778 struct dp_arch_ops { 1779 /* INIT/DEINIT Arch Ops */ 1780 QDF_STATUS (*txrx_soc_attach)(struct dp_soc *soc, 1781 struct cdp_soc_attach_params *params); 1782 QDF_STATUS (*txrx_soc_detach)(struct dp_soc *soc); 1783 QDF_STATUS (*txrx_soc_init)(struct dp_soc *soc); 1784 QDF_STATUS (*txrx_soc_deinit)(struct dp_soc *soc); 1785 QDF_STATUS (*txrx_soc_srng_alloc)(struct dp_soc *soc); 1786 QDF_STATUS (*txrx_soc_srng_init)(struct dp_soc *soc); 1787 void (*txrx_soc_srng_deinit)(struct dp_soc *soc); 1788 void (*txrx_soc_srng_free)(struct dp_soc *soc); 1789 QDF_STATUS (*txrx_pdev_attach)(struct dp_pdev *pdev, 1790 struct cdp_pdev_attach_params *params); 1791 QDF_STATUS (*txrx_pdev_detach)(struct dp_pdev *pdev); 1792 QDF_STATUS (*txrx_vdev_attach)(struct dp_soc *soc, 1793 struct dp_vdev *vdev); 1794 QDF_STATUS (*txrx_vdev_detach)(struct dp_soc *soc, 1795 struct dp_vdev *vdev); 1796 QDF_STATUS (*txrx_peer_map_attach)(struct dp_soc *soc); 1797 void (*txrx_peer_map_detach)(struct dp_soc *soc); 1798 QDF_STATUS (*dp_rxdma_ring_sel_cfg)(struct dp_soc *soc); 1799 void (*soc_cfg_attach)(struct dp_soc *soc); 1800 1801 /* TX RX Arch Ops */ 1802 QDF_STATUS (*tx_hw_enqueue)(struct dp_soc *soc, struct dp_vdev *vdev, 1803 struct dp_tx_desc_s *tx_desc, 1804 uint16_t fw_metadata, 1805 struct cdp_tx_exception_metadata *metadata, 1806 struct dp_tx_msdu_info_s *msdu_info); 1807 1808 void (*tx_comp_get_params_from_hal_desc)(struct dp_soc *soc, 1809 void *tx_comp_hal_desc, 1810 struct dp_tx_desc_s **desc); 1811 void (*dp_tx_process_htt_completion)(struct dp_soc *soc, 1812 struct dp_tx_desc_s *tx_desc, 1813 uint8_t *status, 1814 uint8_t ring_id); 1815 1816 uint32_t (*dp_rx_process)(struct dp_intr *int_ctx, 1817 hal_ring_handle_t hal_ring_hdl, 1818 uint8_t reo_ring_num, uint32_t quota); 1819 1820 QDF_STATUS (*dp_tx_desc_pool_init)(struct dp_soc *soc, 1821 uint32_t num_elem, 1822 uint8_t pool_id); 1823 void (*dp_tx_desc_pool_deinit)( 1824 struct dp_soc *soc, 1825 struct dp_tx_desc_pool_s *tx_desc_pool, 1826 uint8_t pool_id); 1827 1828 QDF_STATUS (*dp_rx_desc_pool_init)(struct dp_soc *soc, 1829 struct rx_desc_pool *rx_desc_pool, 1830 uint32_t pool_id); 1831 void (*dp_rx_desc_pool_deinit)(struct dp_soc *soc, 1832 struct rx_desc_pool *rx_desc_pool, 1833 uint32_t pool_id); 1834 1835 QDF_STATUS (*dp_wbm_get_rx_desc_from_hal_desc)( 1836 struct dp_soc *soc, 1837 void *ring_desc, 1838 struct dp_rx_desc **r_rx_desc); 1839 1840 bool 1841 (*dp_rx_intrabss_handle_nawds)(struct dp_soc *soc, 1842 struct dp_txrx_peer *ta_txrx_peer, 1843 qdf_nbuf_t nbuf_copy, 1844 struct cdp_tid_rx_stats *tid_stats); 1845 1846 struct dp_rx_desc *(*dp_rx_desc_cookie_2_va)(struct dp_soc *soc, 1847 uint32_t cookie); 1848 uint32_t (*dp_service_near_full_srngs)(struct dp_soc *soc, 1849 struct dp_intr *int_ctx, 1850 uint32_t dp_budget); 1851 void (*tx_implicit_rbm_set)(struct dp_soc *soc, uint8_t tx_ring_id, 1852 uint8_t bm_id); 1853 uint16_t (*dp_rx_peer_metadata_peer_id_get)(struct dp_soc *soc, 1854 uint32_t peer_metadata); 1855 /* Control Arch Ops */ 1856 QDF_STATUS (*txrx_set_vdev_param)(struct dp_soc *soc, 1857 struct dp_vdev *vdev, 1858 enum cdp_vdev_param_type param, 1859 cdp_config_param_type val); 1860 1861 /* Misc Arch Ops */ 1862 qdf_size_t (*txrx_get_context_size)(enum dp_context_type); 1863 qdf_size_t (*txrx_get_mon_context_size)(enum dp_context_type); 1864 int (*dp_srng_test_and_update_nf_params)(struct dp_soc *soc, 1865 struct dp_srng *dp_srng, 1866 int *max_reap_limit); 1867 1868 /* MLO ops */ 1869 #ifdef WLAN_FEATURE_11BE_MLO 1870 #ifdef WLAN_MCAST_MLO 1871 void (*dp_tx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 1872 qdf_nbuf_t nbuf); 1873 bool (*dp_rx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 1874 struct dp_txrx_peer *peer, qdf_nbuf_t nbuf); 1875 #endif 1876 void (*mlo_peer_find_hash_detach)(struct dp_soc *soc); 1877 QDF_STATUS (*mlo_peer_find_hash_attach)(struct dp_soc *soc); 1878 void (*mlo_peer_find_hash_add)(struct dp_soc *soc, 1879 struct dp_peer *peer); 1880 void (*mlo_peer_find_hash_remove)(struct dp_soc *soc, 1881 struct dp_peer *peer); 1882 struct dp_peer *(*mlo_peer_find_hash_find)(struct dp_soc *soc, 1883 uint8_t *peer_mac_addr, 1884 int mac_addr_is_aligned, 1885 enum dp_mod_id mod_id, 1886 uint8_t vdev_id); 1887 #endif 1888 void (*get_rx_hash_key)(struct dp_soc *soc, 1889 struct cdp_lro_hash_config *lro_hash); 1890 void (*txrx_print_peer_stats)(struct cdp_peer_stats *peer_stats, 1891 enum peer_stats_type stats_type); 1892 /* Dp peer reorder queue setup */ 1893 QDF_STATUS (*dp_peer_rx_reorder_queue_setup)(struct dp_soc *soc, 1894 struct dp_peer *peer, 1895 int tid, 1896 uint32_t ba_window_size); 1897 struct dp_peer *(*dp_find_peer_by_destmac)(struct dp_soc *soc, 1898 uint8_t *dest_mac_addr, 1899 uint8_t vdev_id); 1900 QDF_STATUS 1901 (*dp_tx_compute_hw_delay)(struct dp_soc *soc, 1902 struct dp_vdev *vdev, 1903 struct hal_tx_completion_status *ts, 1904 uint32_t *delay_us); 1905 void (*print_mlo_ast_stats)(struct dp_soc *soc); 1906 }; 1907 1908 /** 1909 * struct dp_soc_features: Data structure holding the SOC level feature flags. 1910 * @pn_in_reo_dest: PN provided by hardware in the REO destination ring. 1911 * @dmac_cmn_src_rxbuf_ring_enabled: Flag to indicate DMAC mode common Rx 1912 * buffer source rings 1913 * @rssi_dbm_conv_support: Rssi dbm converstion support param. 1914 * @umac_hw_reset_support: UMAC HW reset support 1915 */ 1916 struct dp_soc_features { 1917 uint8_t pn_in_reo_dest:1, 1918 dmac_cmn_src_rxbuf_ring_enabled:1; 1919 bool rssi_dbm_conv_support; 1920 bool umac_hw_reset_support; 1921 }; 1922 1923 enum sysfs_printing_mode { 1924 PRINTING_MODE_DISABLED = 0, 1925 PRINTING_MODE_ENABLED 1926 }; 1927 1928 #ifdef WLAN_SYSFS_DP_STATS 1929 /** 1930 * struct sysfs_stats_config: Data structure holding stats sysfs config. 1931 * @rw_stats_lock: Lock to read and write to stat_type and pdev_id. 1932 * @sysfs_read_lock: Lock held while another stat req is being executed. 1933 * @sysfs_write_user_buffer: Lock to change buff len, max buf len 1934 * and *buf. 1935 * @sysfs_txrx_fw_request_done: Event to wait for firmware response. 1936 * @stat_type_requested: stat type requested. 1937 * @mac_id: mac id for which stat type are requested. 1938 * @printing_mode: Should a print go through. 1939 * @process_id: Process allowed to write to buffer. 1940 * @curr_buffer_length: Curr length of buffer written 1941 * @max_buffer_length: Max buffer length. 1942 * @buf: Sysfs buffer. 1943 */ 1944 struct sysfs_stats_config { 1945 /* lock held to read stats */ 1946 qdf_spinlock_t rw_stats_lock; 1947 qdf_mutex_t sysfs_read_lock; 1948 qdf_spinlock_t sysfs_write_user_buffer; 1949 qdf_event_t sysfs_txrx_fw_request_done; 1950 uint32_t stat_type_requested; 1951 uint32_t mac_id; 1952 enum sysfs_printing_mode printing_mode; 1953 int process_id; 1954 uint16_t curr_buffer_length; 1955 uint16_t max_buffer_length; 1956 char *buf; 1957 }; 1958 #endif 1959 1960 /* SOC level structure for data path */ 1961 struct dp_soc { 1962 /** 1963 * re-use memory section starts 1964 */ 1965 1966 /* Common base structure - Should be the first member */ 1967 struct cdp_soc_t cdp_soc; 1968 1969 /* SoC Obj */ 1970 struct cdp_ctrl_objmgr_psoc *ctrl_psoc; 1971 1972 /* OS device abstraction */ 1973 qdf_device_t osdev; 1974 1975 /*cce disable*/ 1976 bool cce_disable; 1977 1978 /* WLAN config context */ 1979 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 1980 1981 /* HTT handle for host-fw interaction */ 1982 struct htt_soc *htt_handle; 1983 1984 /* Commint init done */ 1985 qdf_atomic_t cmn_init_done; 1986 1987 /* Opaque hif handle */ 1988 struct hif_opaque_softc *hif_handle; 1989 1990 /* PDEVs on this SOC */ 1991 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 1992 1993 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 1994 struct dp_srng rx_refill_buf_ring[MAX_PDEV_CNT]; 1995 1996 struct dp_srng rxdma_mon_desc_ring[MAX_NUM_LMAC_HW]; 1997 1998 /* RXDMA error destination ring */ 1999 struct dp_srng rxdma_err_dst_ring[MAX_NUM_LMAC_HW]; 2000 2001 /* RXDMA monitor buffer replenish ring */ 2002 struct dp_srng rxdma_mon_buf_ring[MAX_NUM_LMAC_HW]; 2003 2004 /* RXDMA monitor destination ring */ 2005 struct dp_srng rxdma_mon_dst_ring[MAX_NUM_LMAC_HW]; 2006 2007 /* RXDMA monitor status ring. TBD: Check format of this ring */ 2008 struct dp_srng rxdma_mon_status_ring[MAX_NUM_LMAC_HW]; 2009 2010 /* Number of PDEVs */ 2011 uint8_t pdev_count; 2012 2013 /*ast override support in HW*/ 2014 bool ast_override_support; 2015 2016 /*number of hw dscp tid map*/ 2017 uint8_t num_hw_dscp_tid_map; 2018 2019 /* HAL SOC handle */ 2020 hal_soc_handle_t hal_soc; 2021 2022 /* rx monitor pkt tlv size */ 2023 uint16_t rx_mon_pkt_tlv_size; 2024 /* rx pkt tlv size */ 2025 uint16_t rx_pkt_tlv_size; 2026 2027 struct dp_arch_ops arch_ops; 2028 2029 /* Device ID coming from Bus sub-system */ 2030 uint32_t device_id; 2031 2032 /* Link descriptor pages */ 2033 struct qdf_mem_multi_page_t link_desc_pages; 2034 2035 /* total link descriptors for regular RX and TX */ 2036 uint32_t total_link_descs; 2037 2038 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 2039 struct dp_srng wbm_idle_link_ring; 2040 2041 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 2042 */ 2043 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 2044 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 2045 uint32_t num_scatter_bufs; 2046 2047 /* Tx SW descriptor pool */ 2048 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 2049 2050 /* Tx MSDU Extension descriptor pool */ 2051 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 2052 2053 /* Tx TSO descriptor pool */ 2054 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 2055 2056 /* Tx TSO Num of segments pool */ 2057 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 2058 2059 /* REO destination rings */ 2060 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 2061 2062 /* REO exception ring - See if should combine this with reo_dest_ring */ 2063 struct dp_srng reo_exception_ring; 2064 2065 /* REO reinjection ring */ 2066 struct dp_srng reo_reinject_ring; 2067 2068 /* REO command ring */ 2069 struct dp_srng reo_cmd_ring; 2070 2071 /* REO command status ring */ 2072 struct dp_srng reo_status_ring; 2073 2074 /* WBM Rx release ring */ 2075 struct dp_srng rx_rel_ring; 2076 2077 /* TCL data ring */ 2078 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 2079 2080 /* Number of Tx comp rings */ 2081 uint8_t num_tx_comp_rings; 2082 2083 /* Number of TCL data rings */ 2084 uint8_t num_tcl_data_rings; 2085 2086 /* TCL CMD_CREDIT ring */ 2087 bool init_tcl_cmd_cred_ring; 2088 2089 /* It is used as credit based ring on QCN9000 else command ring */ 2090 struct dp_srng tcl_cmd_credit_ring; 2091 2092 /* TCL command status ring */ 2093 struct dp_srng tcl_status_ring; 2094 2095 /* WBM Tx completion rings */ 2096 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 2097 2098 /* Common WBM link descriptor release ring (SW to WBM) */ 2099 struct dp_srng wbm_desc_rel_ring; 2100 2101 /* DP Interrupts */ 2102 struct dp_intr intr_ctx[WLAN_CFG_INT_NUM_CONTEXTS]; 2103 2104 /* Monitor mode mac id to dp_intr_id map */ 2105 int mon_intr_id_lmac_map[MAX_NUM_LMAC_HW]; 2106 /* Rx SW descriptor pool for RXDMA monitor buffer */ 2107 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 2108 2109 /* Rx SW descriptor pool for RXDMA status buffer */ 2110 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 2111 2112 /* Rx SW descriptor pool for RXDMA buffer */ 2113 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 2114 2115 /* Number of REO destination rings */ 2116 uint8_t num_reo_dest_rings; 2117 2118 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 2119 /* lock to control access to soc TX descriptors */ 2120 qdf_spinlock_t flow_pool_array_lock; 2121 2122 /* pause callback to pause TX queues as per flow control */ 2123 tx_pause_callback pause_cb; 2124 2125 /* flow pool related statistics */ 2126 struct dp_txrx_pool_stats pool_stats; 2127 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 2128 2129 uint32_t wbm_idle_scatter_buf_size; 2130 2131 /* VDEVs on this SOC */ 2132 struct dp_vdev *vdev_id_map[MAX_VDEV_CNT]; 2133 2134 /* Tx H/W queues lock */ 2135 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 2136 2137 /* Tx ring map for interrupt processing */ 2138 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2139 2140 /* Rx ring map for interrupt processing */ 2141 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2142 2143 /* peer ID to peer object map (array of pointers to peer objects) */ 2144 struct dp_peer **peer_id_to_obj_map; 2145 2146 struct { 2147 unsigned mask; 2148 unsigned idx_bits; 2149 TAILQ_HEAD(, dp_peer) * bins; 2150 } peer_hash; 2151 2152 /* rx defrag state – TBD: do we need this per radio? */ 2153 struct { 2154 struct { 2155 TAILQ_HEAD(, dp_rx_tid_defrag) waitlist; 2156 uint32_t timeout_ms; 2157 uint32_t next_flush_ms; 2158 qdf_spinlock_t defrag_lock; 2159 } defrag; 2160 struct { 2161 int defrag_timeout_check; 2162 int dup_check; 2163 } flags; 2164 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 2165 qdf_spinlock_t reo_cmd_lock; 2166 } rx; 2167 2168 /* optional rx processing function */ 2169 void (*rx_opt_proc)( 2170 struct dp_vdev *vdev, 2171 struct dp_peer *peer, 2172 unsigned tid, 2173 qdf_nbuf_t msdu_list); 2174 2175 /* pool addr for mcast enhance buff */ 2176 struct { 2177 int size; 2178 uint32_t paddr; 2179 uint32_t *vaddr; 2180 struct dp_tx_me_buf_t *freelist; 2181 int buf_in_use; 2182 qdf_dma_mem_context(memctx); 2183 } me_buf; 2184 2185 /* Protect peer hash table */ 2186 DP_MUTEX_TYPE peer_hash_lock; 2187 /* Protect peer_id_to_objmap */ 2188 DP_MUTEX_TYPE peer_map_lock; 2189 2190 /* maximum number of suppoerted peers */ 2191 uint32_t max_peers; 2192 /* maximum value for peer_id */ 2193 uint32_t max_peer_id; 2194 2195 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH 2196 uint32_t peer_id_shift; 2197 uint32_t peer_id_mask; 2198 #endif 2199 2200 /* SoC level data path statistics */ 2201 struct dp_soc_stats stats; 2202 #ifdef WLAN_SYSFS_DP_STATS 2203 /* sysfs config for DP stats */ 2204 struct sysfs_stats_config *sysfs_config; 2205 #endif 2206 /* timestamp to keep track of msdu buffers received on reo err ring */ 2207 uint64_t rx_route_err_start_pkt_ts; 2208 2209 /* Num RX Route err in a given window to keep track of rate of errors */ 2210 uint32_t rx_route_err_in_window; 2211 2212 /* Enable processing of Tx completion status words */ 2213 bool process_tx_status; 2214 bool process_rx_status; 2215 struct dp_ast_entry **ast_table; 2216 struct { 2217 unsigned mask; 2218 unsigned idx_bits; 2219 TAILQ_HEAD(, dp_ast_entry) * bins; 2220 } ast_hash; 2221 2222 #ifdef DP_TX_HW_DESC_HISTORY 2223 struct dp_tx_hw_desc_history *tx_hw_desc_history; 2224 #endif 2225 2226 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 2227 struct dp_rx_history *rx_ring_history[MAX_REO_DEST_RINGS]; 2228 struct dp_rx_refill_history *rx_refill_ring_history[MAX_PDEV_CNT]; 2229 struct dp_rx_err_history *rx_err_ring_history; 2230 struct dp_rx_reinject_history *rx_reinject_ring_history; 2231 #endif 2232 2233 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 2234 struct dp_mon_status_ring_history *mon_status_ring_history; 2235 #endif 2236 2237 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 2238 struct dp_tx_tcl_history *tx_tcl_history; 2239 struct dp_tx_comp_history *tx_comp_history; 2240 #endif 2241 2242 qdf_spinlock_t ast_lock; 2243 /*Timer for AST entry ageout maintainance */ 2244 qdf_timer_t ast_aging_timer; 2245 2246 /*Timer counter for WDS AST entry ageout*/ 2247 uint8_t wds_ast_aging_timer_cnt; 2248 bool pending_ageout; 2249 bool ast_offload_support; 2250 bool host_ast_db_enable; 2251 uint32_t max_ast_ageout_count; 2252 uint8_t eapol_over_control_port; 2253 2254 uint8_t sta_mode_search_policy; 2255 qdf_timer_t lmac_reap_timer; 2256 uint8_t lmac_timer_init; 2257 qdf_timer_t int_timer; 2258 uint8_t intr_mode; 2259 uint8_t lmac_polled_mode; 2260 2261 qdf_list_t reo_desc_freelist; 2262 qdf_spinlock_t reo_desc_freelist_lock; 2263 2264 /* htt stats */ 2265 struct htt_t2h_stats htt_stats; 2266 2267 void *external_txrx_handle; /* External data path handle */ 2268 #ifdef IPA_OFFLOAD 2269 struct ipa_dp_tx_rsc ipa_uc_tx_rsc; 2270 #ifdef IPA_WDI3_TX_TWO_PIPES 2271 /* Resources for the alternative IPA TX pipe */ 2272 struct ipa_dp_tx_rsc ipa_uc_tx_rsc_alt; 2273 #endif 2274 2275 struct ipa_dp_rx_rsc ipa_uc_rx_rsc; 2276 #ifdef IPA_WDI3_VLAN_SUPPORT 2277 struct ipa_dp_rx_rsc ipa_uc_rx_rsc_alt; 2278 #endif 2279 qdf_atomic_t ipa_pipes_enabled; 2280 bool ipa_first_tx_db_access; 2281 qdf_spinlock_t ipa_rx_buf_map_lock; 2282 bool ipa_rx_buf_map_lock_initialized; 2283 uint8_t ipa_reo_ctx_lock_required[MAX_REO_DEST_RINGS]; 2284 #endif 2285 2286 #ifdef WLAN_FEATURE_STATS_EXT 2287 struct { 2288 uint32_t rx_mpdu_received; 2289 uint32_t rx_mpdu_missed; 2290 } ext_stats; 2291 qdf_event_t rx_hw_stats_event; 2292 qdf_spinlock_t rx_hw_stats_lock; 2293 bool is_last_stats_ctx_init; 2294 #endif /* WLAN_FEATURE_STATS_EXT */ 2295 2296 /* Indicates HTT map/unmap versions*/ 2297 uint8_t peer_map_unmap_versions; 2298 /* Per peer per Tid ba window size support */ 2299 uint8_t per_tid_basize_max_tid; 2300 /* Soc level flag to enable da_war */ 2301 uint8_t da_war_enabled; 2302 /* number of active ast entries */ 2303 uint32_t num_ast_entries; 2304 /* peer extended rate statistics context at soc level*/ 2305 struct cdp_soc_rate_stats_ctx *rate_stats_ctx; 2306 /* peer extended rate statistics control flag */ 2307 bool peerstats_enabled; 2308 2309 /* 8021p PCP-TID map values */ 2310 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 2311 /* TID map priority value */ 2312 uint8_t tidmap_prty; 2313 /* Pointer to global per ring type specific configuration table */ 2314 struct wlan_srng_cfg *wlan_srng_cfg; 2315 /* Num Tx outstanding on device */ 2316 qdf_atomic_t num_tx_outstanding; 2317 /* Num Tx exception on device */ 2318 qdf_atomic_t num_tx_exception; 2319 /* Num Tx allowed */ 2320 uint32_t num_tx_allowed; 2321 /* Preferred HW mode */ 2322 uint8_t preferred_hw_mode; 2323 2324 /** 2325 * Flag to indicate whether WAR to address single cache entry 2326 * invalidation bug is enabled or not 2327 */ 2328 bool is_rx_fse_full_cache_invalidate_war_enabled; 2329 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) || defined(WLAN_SUPPORT_RX_FISA) 2330 /** 2331 * Pointer to DP RX Flow FST at SOC level if 2332 * is_rx_flow_search_table_per_pdev is false 2333 * TBD: rx_fst[num_macs] if we decide to have per mac FST 2334 */ 2335 struct dp_rx_fst *rx_fst; 2336 #ifdef WLAN_SUPPORT_RX_FISA 2337 uint8_t fisa_enable; 2338 uint8_t fisa_lru_del_enable; 2339 /** 2340 * Params used for controlling the fisa aggregation dynamically 2341 */ 2342 struct { 2343 qdf_atomic_t skip_fisa; 2344 uint8_t fisa_force_flush[MAX_REO_DEST_RINGS]; 2345 } skip_fisa_param; 2346 2347 /** 2348 * CMEM address and size for FST in CMEM, This is the address 2349 * shared during init time. 2350 */ 2351 uint64_t fst_cmem_base; 2352 uint64_t fst_cmem_size; 2353 #endif 2354 #endif /* WLAN_SUPPORT_RX_FLOW_TAG || WLAN_SUPPORT_RX_FISA */ 2355 /* SG supported for msdu continued packets from wbm release ring */ 2356 bool wbm_release_desc_rx_sg_support; 2357 bool peer_map_attach_success; 2358 /* Flag to disable mac1 ring interrupts */ 2359 bool disable_mac1_intr; 2360 /* Flag to disable mac2 ring interrupts */ 2361 bool disable_mac2_intr; 2362 2363 struct { 2364 /* 1st msdu in sg for msdu continued packets in wbm rel ring */ 2365 bool wbm_is_first_msdu_in_sg; 2366 /* Wbm sg list head */ 2367 qdf_nbuf_t wbm_sg_nbuf_head; 2368 /* Wbm sg list tail */ 2369 qdf_nbuf_t wbm_sg_nbuf_tail; 2370 uint32_t wbm_sg_desc_msdu_len; 2371 } wbm_sg_param; 2372 /* Number of msdu exception descriptors */ 2373 uint32_t num_msdu_exception_desc; 2374 2375 /* RX buffer params */ 2376 struct rx_buff_pool rx_buff_pool[MAX_PDEV_CNT]; 2377 struct rx_refill_buff_pool rx_refill_buff_pool; 2378 /* Save recent operation related variable */ 2379 struct dp_last_op_info last_op_info; 2380 TAILQ_HEAD(, dp_peer) inactive_peer_list; 2381 qdf_spinlock_t inactive_peer_list_lock; 2382 TAILQ_HEAD(, dp_vdev) inactive_vdev_list; 2383 qdf_spinlock_t inactive_vdev_list_lock; 2384 /* lock to protect vdev_id_map table*/ 2385 qdf_spinlock_t vdev_map_lock; 2386 2387 /* Flow Search Table is in CMEM */ 2388 bool fst_in_cmem; 2389 2390 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 2391 struct dp_swlm swlm; 2392 #endif 2393 2394 #ifdef FEATURE_RUNTIME_PM 2395 /* DP Rx timestamp */ 2396 qdf_time_t rx_last_busy; 2397 /* Dp runtime refcount */ 2398 qdf_atomic_t dp_runtime_refcount; 2399 /* Dp tx pending count in RTPM */ 2400 qdf_atomic_t tx_pending_rtpm; 2401 #endif 2402 /* Invalid buffer that allocated for RX buffer */ 2403 qdf_nbuf_queue_t invalid_buf_queue; 2404 2405 #ifdef FEATURE_MEC 2406 /** @mec_lock: spinlock for MEC table */ 2407 qdf_spinlock_t mec_lock; 2408 /** @mec_cnt: number of active mec entries */ 2409 qdf_atomic_t mec_cnt; 2410 struct { 2411 /** @mask: mask bits */ 2412 uint32_t mask; 2413 /** @idx_bits: index to shift bits */ 2414 uint32_t idx_bits; 2415 /** @bins: MEC table */ 2416 TAILQ_HEAD(, dp_mec_entry) * bins; 2417 } mec_hash; 2418 #endif 2419 2420 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 2421 qdf_list_t reo_desc_deferred_freelist; 2422 qdf_spinlock_t reo_desc_deferred_freelist_lock; 2423 bool reo_desc_deferred_freelist_init; 2424 #endif 2425 /* BM id for first WBM2SW ring */ 2426 uint32_t wbm_sw0_bm_id; 2427 2428 /* Store arch_id from device_id */ 2429 uint16_t arch_id; 2430 2431 /* link desc ID start per device type */ 2432 uint32_t link_desc_id_start; 2433 2434 /* CMEM buffer target reserved for host usage */ 2435 uint64_t cmem_base; 2436 /* CMEM size in bytes */ 2437 uint64_t cmem_total_size; 2438 /* CMEM free size in bytes */ 2439 uint64_t cmem_avail_size; 2440 2441 /* SOC level feature flags */ 2442 struct dp_soc_features features; 2443 2444 #ifdef WIFI_MONITOR_SUPPORT 2445 struct dp_mon_soc *monitor_soc; 2446 #endif 2447 uint8_t rxdma2sw_rings_not_supported:1, 2448 wbm_sg_last_msdu_war:1, 2449 mec_fw_offload:1, 2450 multi_peer_grp_cmd_supported:1; 2451 2452 /* Number of Rx refill rings */ 2453 uint8_t num_rx_refill_buf_rings; 2454 #ifdef FEATURE_RUNTIME_PM 2455 /* flag to indicate vote for runtime_pm for high tput castt*/ 2456 qdf_atomic_t rtpm_high_tput_flag; 2457 #endif 2458 /* Buffer manager ID for idle link descs */ 2459 uint8_t idle_link_bm_id; 2460 qdf_atomic_t ref_count; 2461 2462 unsigned long vdev_stats_id_map; 2463 bool txmon_hw_support; 2464 2465 #ifdef DP_UMAC_HW_RESET_SUPPORT 2466 struct dp_soc_umac_reset_ctx umac_reset_ctx; 2467 #endif 2468 /* PPDU to link_id mapping parameters */ 2469 uint8_t link_id_offset; 2470 uint8_t link_id_bits; 2471 #ifdef FEATURE_RX_LINKSPEED_ROAM_TRIGGER 2472 /* A flag using to decide the switch of rx link speed */ 2473 bool high_throughput; 2474 #endif 2475 }; 2476 2477 #ifdef IPA_OFFLOAD 2478 /** 2479 * dp_ipa_resources - Resources needed for IPA 2480 */ 2481 struct dp_ipa_resources { 2482 qdf_shared_mem_t tx_ring; 2483 uint32_t tx_num_alloc_buffer; 2484 2485 qdf_shared_mem_t tx_comp_ring; 2486 qdf_shared_mem_t rx_rdy_ring; 2487 qdf_shared_mem_t rx_refill_ring; 2488 2489 /* IPA UC doorbell registers paddr */ 2490 qdf_dma_addr_t tx_comp_doorbell_paddr; 2491 uint32_t *tx_comp_doorbell_vaddr; 2492 qdf_dma_addr_t rx_ready_doorbell_paddr; 2493 2494 bool is_db_ddr_mapped; 2495 2496 #ifdef IPA_WDI3_TX_TWO_PIPES 2497 qdf_shared_mem_t tx_alt_ring; 2498 uint32_t tx_alt_ring_num_alloc_buffer; 2499 qdf_shared_mem_t tx_alt_comp_ring; 2500 2501 /* IPA UC doorbell registers paddr */ 2502 qdf_dma_addr_t tx_alt_comp_doorbell_paddr; 2503 uint32_t *tx_alt_comp_doorbell_vaddr; 2504 #endif 2505 #ifdef IPA_WDI3_VLAN_SUPPORT 2506 qdf_shared_mem_t rx_alt_rdy_ring; 2507 qdf_shared_mem_t rx_alt_refill_ring; 2508 qdf_dma_addr_t rx_alt_ready_doorbell_paddr; 2509 #endif 2510 }; 2511 #endif 2512 2513 #define MAX_RX_MAC_RINGS 2 2514 /* Same as NAC_MAX_CLENT */ 2515 #define DP_NAC_MAX_CLIENT 24 2516 2517 /* 2518 * 24 bits cookie size 2519 * 10 bits page id 0 ~ 1023 for MCL 2520 * 3 bits page id 0 ~ 7 for WIN 2521 * WBM Idle List Desc size = 128, 2522 * Num descs per page = 4096/128 = 32 for MCL 2523 * Num descs per page = 2MB/128 = 16384 for WIN 2524 */ 2525 /* 2526 * Macros to setup link descriptor cookies - for link descriptors, we just 2527 * need first 3 bits to store bank/page ID for WIN. The 2528 * remaining bytes will be used to set a unique ID, which will 2529 * be useful in debugging 2530 */ 2531 #ifdef MAX_ALLOC_PAGE_SIZE 2532 #define LINK_DESC_PAGE_ID_MASK 0x007FE0 2533 #define LINK_DESC_ID_SHIFT 5 2534 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 2535 ((((_page_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_desc_id)) 2536 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 2537 (((_cookie) & LINK_DESC_PAGE_ID_MASK) >> LINK_DESC_ID_SHIFT) 2538 #else 2539 #define LINK_DESC_PAGE_ID_MASK 0x7 2540 #define LINK_DESC_ID_SHIFT 3 2541 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 2542 ((((_desc_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_page_id)) 2543 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 2544 ((_cookie) & LINK_DESC_PAGE_ID_MASK) 2545 #endif 2546 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 2547 #define LINK_DESC_ID_START_20_BITS_COOKIE 0x4000 2548 2549 /* same as ieee80211_nac_param */ 2550 enum dp_nac_param_cmd { 2551 /* IEEE80211_NAC_PARAM_ADD */ 2552 DP_NAC_PARAM_ADD = 1, 2553 /* IEEE80211_NAC_PARAM_DEL */ 2554 DP_NAC_PARAM_DEL, 2555 /* IEEE80211_NAC_PARAM_LIST */ 2556 DP_NAC_PARAM_LIST, 2557 }; 2558 2559 /** 2560 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 2561 * @neighbour_peers_macaddr: neighbour peer's mac address 2562 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 2563 * @ast_entry: ast_entry for neighbour peer 2564 * @rssi: rssi value 2565 */ 2566 struct dp_neighbour_peer { 2567 /* MAC address of neighbour's peer */ 2568 union dp_align_mac_addr neighbour_peers_macaddr; 2569 struct dp_vdev *vdev; 2570 struct dp_ast_entry *ast_entry; 2571 uint8_t rssi; 2572 /* node in the list of neighbour's peer */ 2573 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 2574 }; 2575 2576 #ifdef WLAN_TX_PKT_CAPTURE_ENH 2577 #define WLAN_TX_PKT_CAPTURE_ENH 1 2578 #define DP_TX_PPDU_PROC_THRESHOLD 8 2579 #define DP_TX_PPDU_PROC_TIMEOUT 10 2580 #endif 2581 2582 /** 2583 * struct ppdu_info - PPDU Status info descriptor 2584 * @ppdu_id: Unique ppduid assigned by firmware for every tx packet 2585 * @sched_cmdid: schedule command id, which will be same in a burst 2586 * @max_ppdu_id: wrap around for ppdu id 2587 * @last_tlv_cnt: Keep track for missing ppdu tlvs 2588 * @last_user: last ppdu processed for user 2589 * @is_ampdu: set if Ampdu aggregate 2590 * @nbuf: ppdu descriptor payload 2591 * @ppdu_desc: ppdu descriptor 2592 * @ppdu_info_list_elem: linked list of ppdu tlvs 2593 * @ppdu_info_queue_elem: Singly linked list (queue) of ppdu tlvs 2594 * @mpdu_compltn_common_tlv: Successful tlv counter from COMPLTN COMMON tlv 2595 * @mpdu_ack_ba_tlv: Successful tlv counter from ACK BA tlv 2596 */ 2597 struct ppdu_info { 2598 uint32_t ppdu_id; 2599 uint32_t sched_cmdid; 2600 uint32_t max_ppdu_id; 2601 uint32_t tsf_l32; 2602 uint16_t tlv_bitmap; 2603 uint16_t last_tlv_cnt; 2604 uint16_t last_user:8, 2605 is_ampdu:1; 2606 qdf_nbuf_t nbuf; 2607 struct cdp_tx_completion_ppdu *ppdu_desc; 2608 #ifdef WLAN_TX_PKT_CAPTURE_ENH 2609 union { 2610 TAILQ_ENTRY(ppdu_info) ppdu_info_dlist_elem; 2611 STAILQ_ENTRY(ppdu_info) ppdu_info_slist_elem; 2612 } ulist; 2613 #define ppdu_info_list_elem ulist.ppdu_info_dlist_elem 2614 #define ppdu_info_queue_elem ulist.ppdu_info_slist_elem 2615 #else 2616 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 2617 #endif 2618 uint8_t compltn_common_tlv; 2619 uint8_t ack_ba_tlv; 2620 bool done; 2621 }; 2622 2623 /** 2624 * struct msdu_completion_info - wbm msdu completion info 2625 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 2626 * @peer_id - peer_id 2627 * @tid - tid which used during transmit 2628 * @first_msdu - first msdu indication 2629 * @last_msdu - last msdu indication 2630 * @msdu_part_of_amsdu - msdu part of amsdu 2631 * @transmit_cnt - retried count 2632 * @status - transmit status 2633 * @tsf - timestamp which it transmitted 2634 */ 2635 struct msdu_completion_info { 2636 uint32_t ppdu_id; 2637 uint16_t peer_id; 2638 uint8_t tid; 2639 uint8_t first_msdu:1, 2640 last_msdu:1, 2641 msdu_part_of_amsdu:1; 2642 uint8_t transmit_cnt; 2643 uint8_t status; 2644 uint32_t tsf; 2645 }; 2646 2647 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 2648 struct rx_protocol_tag_map { 2649 /* This is the user configured tag for the said protocol type */ 2650 uint16_t tag; 2651 }; 2652 2653 /** 2654 * rx_protocol_tag_stats - protocol statistics 2655 * @tag_ctr: number of rx msdus matching this tag 2656 * @mon_tag_ctr: number of msdus matching this tag in mon path 2657 */ 2658 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 2659 struct rx_protocol_tag_stats { 2660 uint32_t tag_ctr; 2661 }; 2662 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 2663 2664 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 2665 2666 #ifdef WLAN_RX_PKT_CAPTURE_ENH 2667 /* Template data to be set for Enhanced RX Monitor packets */ 2668 #define RX_MON_CAP_ENH_TRAILER 0xdeadc0dedeadda7a 2669 2670 /** 2671 * struct dp_rx_mon_enh_trailer_data - Data structure to set a known pattern 2672 * at end of each MSDU in monitor-lite mode 2673 * @reserved1: reserved for future use 2674 * @reserved2: reserved for future use 2675 * @flow_tag: flow tag value read from skb->cb 2676 * @protocol_tag: protocol tag value read from skb->cb 2677 */ 2678 struct dp_rx_mon_enh_trailer_data { 2679 uint16_t reserved1; 2680 uint16_t reserved2; 2681 uint16_t flow_tag; 2682 uint16_t protocol_tag; 2683 }; 2684 #endif /* WLAN_RX_PKT_CAPTURE_ENH */ 2685 2686 #ifdef HTT_STATS_DEBUGFS_SUPPORT 2687 /* Number of debugfs entries created for HTT stats */ 2688 #define PDEV_HTT_STATS_DBGFS_SIZE HTT_DBG_NUM_EXT_STATS 2689 2690 /* struct pdev_htt_stats_dbgfs_priv - Structure to maintain debugfs information 2691 * of HTT stats 2692 * @pdev: dp pdev of debugfs entry 2693 * @stats_id: stats id of debugfs entry 2694 */ 2695 struct pdev_htt_stats_dbgfs_priv { 2696 struct dp_pdev *pdev; 2697 uint16_t stats_id; 2698 }; 2699 2700 /* struct pdev_htt_stats_dbgfs_cfg - PDEV level data structure for debugfs 2701 * support for HTT stats 2702 * @debugfs_entry: qdf_debugfs directory entry 2703 * @m: qdf debugfs file handler 2704 * @pdev_htt_stats_dbgfs_ops: File operations of entry created 2705 * @priv: HTT stats debugfs private object 2706 * @htt_stats_dbgfs_event: HTT stats event for debugfs support 2707 * @lock: HTT stats debugfs lock 2708 * @htt_stats_dbgfs_msg_process: Function callback to print HTT stats 2709 */ 2710 struct pdev_htt_stats_dbgfs_cfg { 2711 qdf_dentry_t debugfs_entry[PDEV_HTT_STATS_DBGFS_SIZE]; 2712 qdf_debugfs_file_t m; 2713 struct qdf_debugfs_fops 2714 pdev_htt_stats_dbgfs_ops[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 2715 struct pdev_htt_stats_dbgfs_priv priv[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 2716 qdf_event_t htt_stats_dbgfs_event; 2717 qdf_mutex_t lock; 2718 void (*htt_stats_dbgfs_msg_process)(void *data, A_INT32 len); 2719 }; 2720 #endif /* HTT_STATS_DEBUGFS_SUPPORT */ 2721 2722 struct dp_srng_ring_state { 2723 enum hal_ring_type ring_type; 2724 uint32_t sw_head; 2725 uint32_t sw_tail; 2726 uint32_t hw_head; 2727 uint32_t hw_tail; 2728 2729 }; 2730 2731 struct dp_soc_srngs_state { 2732 uint32_t seq_num; 2733 uint32_t max_ring_id; 2734 struct dp_srng_ring_state ring_state[DP_MAX_SRNGS]; 2735 TAILQ_ENTRY(dp_soc_srngs_state) list_elem; 2736 }; 2737 2738 #ifdef WLAN_FEATURE_11BE_MLO 2739 /* struct dp_mlo_sync_timestamp - PDEV level data structure for storing 2740 * MLO timestamp received via HTT msg. 2741 * msg_type: This would be set to HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 2742 * pdev_id: pdev_id 2743 * chip_id: chip_id 2744 * mac_clk_freq: mac clock frequency of the mac HW block in MHz 2745 * sync_tstmp_lo_us: lower 32 bits of the WLAN global time stamp (in us) at 2746 * which last sync interrupt was received 2747 * sync_tstmp_hi_us: upper 32 bits of the WLAN global time stamp (in us) at 2748 * which last sync interrupt was received 2749 * mlo_offset_lo_us: lower 32 bits of the MLO time stamp offset in us 2750 * mlo_offset_hi_us: upper 32 bits of the MLO time stamp offset in us 2751 * mlo_offset_clks: MLO time stamp offset in clock ticks for sub us 2752 * mlo_comp_us: MLO time stamp compensation applied in us 2753 * mlo_comp_clks: MLO time stamp compensation applied in clock ticks 2754 * for sub us resolution 2755 * mlo_comp_timer: period of MLO compensation timer at which compensation 2756 * is applied, in us 2757 */ 2758 struct dp_mlo_sync_timestamp { 2759 uint32_t msg_type:8, 2760 pdev_id:2, 2761 chip_id:2, 2762 rsvd1:4, 2763 mac_clk_freq:16; 2764 uint32_t sync_tstmp_lo_us; 2765 uint32_t sync_tstmp_hi_us; 2766 uint32_t mlo_offset_lo_us; 2767 uint32_t mlo_offset_hi_us; 2768 uint32_t mlo_offset_clks; 2769 uint32_t mlo_comp_us:16, 2770 mlo_comp_clks:10, 2771 rsvd2:6; 2772 uint32_t mlo_comp_timer:22, 2773 rsvd3:10; 2774 }; 2775 #endif 2776 2777 /* PDEV level structure for data path */ 2778 struct dp_pdev { 2779 /** 2780 * Re-use Memory Section Starts 2781 */ 2782 2783 /* PDEV Id */ 2784 int pdev_id; 2785 2786 /* LMAC Id */ 2787 int lmac_id; 2788 2789 /* Target pdev Id */ 2790 int target_pdev_id; 2791 2792 /* TXRX SOC handle */ 2793 struct dp_soc *soc; 2794 2795 bool pdev_deinit; 2796 2797 /* pdev status down or up required to handle dynamic hw 2798 * mode switch between DBS and DBS_SBS. 2799 * 1 = down 2800 * 0 = up 2801 */ 2802 bool is_pdev_down; 2803 2804 /* Enhanced Stats is enabled */ 2805 bool enhanced_stats_en; 2806 2807 /* Second ring used to replenish rx buffers */ 2808 struct dp_srng rx_refill_buf_ring2; 2809 #ifdef IPA_WDI3_VLAN_SUPPORT 2810 /* Third ring used to replenish rx buffers */ 2811 struct dp_srng rx_refill_buf_ring3; 2812 #endif 2813 2814 /* Empty ring used by firmware to post rx buffers to the MAC */ 2815 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 2816 2817 int ch_band_lmac_id_mapping[REG_BAND_UNKNOWN]; 2818 2819 /* wlan_cfg pdev ctxt*/ 2820 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 2821 2822 /** 2823 * TODO: See if we need a ring map here for LMAC rings. 2824 * 1. Monitor rings are currently planning to be processed on receiving 2825 * PPDU end interrupts and hence wont need ring based interrupts. 2826 * 2. Rx buffer rings will be replenished during REO destination 2827 * processing and doesn't require regular interrupt handling - we will 2828 * only handle low water mark interrupts which is not expected 2829 * frequently 2830 */ 2831 2832 /* VDEV list */ 2833 TAILQ_HEAD(, dp_vdev) vdev_list; 2834 2835 /* vdev list lock */ 2836 qdf_spinlock_t vdev_list_lock; 2837 2838 /* Number of vdevs this device have */ 2839 uint16_t vdev_count; 2840 2841 /* PDEV transmit lock */ 2842 qdf_spinlock_t tx_lock; 2843 2844 /*tx_mutex for me*/ 2845 DP_MUTEX_TYPE tx_mutex; 2846 2847 /* msdu chain head & tail */ 2848 qdf_nbuf_t invalid_peer_head_msdu; 2849 qdf_nbuf_t invalid_peer_tail_msdu; 2850 2851 /* Band steering */ 2852 /* TBD */ 2853 2854 /* PDEV level data path statistics */ 2855 struct cdp_pdev_stats stats; 2856 2857 /* Global RX decap mode for the device */ 2858 enum htt_pkt_type rx_decap_mode; 2859 2860 qdf_atomic_t num_tx_outstanding; 2861 int32_t tx_descs_max; 2862 2863 qdf_atomic_t num_tx_exception; 2864 2865 /* MCL specific local peer handle */ 2866 struct { 2867 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 2868 uint8_t freelist; 2869 qdf_spinlock_t lock; 2870 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 2871 } local_peer_ids; 2872 2873 /* dscp_tid_map_*/ 2874 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 2875 2876 /* operating channel */ 2877 struct { 2878 uint8_t num; 2879 uint8_t band; 2880 uint16_t freq; 2881 } operating_channel; 2882 2883 /* pool addr for mcast enhance buff */ 2884 struct { 2885 int size; 2886 uint32_t paddr; 2887 char *vaddr; 2888 struct dp_tx_me_buf_t *freelist; 2889 int buf_in_use; 2890 qdf_dma_mem_context(memctx); 2891 } me_buf; 2892 2893 bool hmmc_tid_override_en; 2894 uint8_t hmmc_tid; 2895 2896 /* Number of VAPs with mcast enhancement enabled */ 2897 qdf_atomic_t mc_num_vap_attached; 2898 2899 qdf_atomic_t stats_cmd_complete; 2900 2901 #ifdef IPA_OFFLOAD 2902 ipa_uc_op_cb_type ipa_uc_op_cb; 2903 void *usr_ctxt; 2904 struct dp_ipa_resources ipa_resource; 2905 #endif 2906 2907 /* TBD */ 2908 2909 /* map this pdev to a particular Reo Destination ring */ 2910 enum cdp_host_reo_dest_ring reo_dest; 2911 2912 /* WDI event handlers */ 2913 struct wdi_event_subscribe_t **wdi_event_list; 2914 2915 bool cfr_rcc_mode; 2916 2917 /* enable time latency check for tx completion */ 2918 bool latency_capture_enable; 2919 2920 /* enable calculation of delay stats*/ 2921 bool delay_stats_flag; 2922 void *dp_txrx_handle; /* Advanced data path handle */ 2923 uint32_t ppdu_id; 2924 bool first_nbuf; 2925 /* Current noise-floor reading for the pdev channel */ 2926 int16_t chan_noise_floor; 2927 2928 /* 2929 * For multiradio device, this flag indicates if 2930 * this radio is primary or secondary. 2931 * 2932 * For HK 1.0, this is used for WAR for the AST issue. 2933 * HK 1.x mandates creation of only 1 AST entry with same MAC address 2934 * across 2 radios. is_primary indicates the radio on which DP should 2935 * install HW AST entry if there is a request to add 2 AST entries 2936 * with same MAC address across 2 radios 2937 */ 2938 uint8_t is_primary; 2939 struct cdp_tx_sojourn_stats sojourn_stats; 2940 qdf_nbuf_t sojourn_buf; 2941 2942 union dp_rx_desc_list_elem_t *free_list_head; 2943 union dp_rx_desc_list_elem_t *free_list_tail; 2944 /* Cached peer_id from htt_peer_details_tlv */ 2945 uint16_t fw_stats_peer_id; 2946 2947 /* qdf_event for fw_peer_stats */ 2948 qdf_event_t fw_peer_stats_event; 2949 qdf_event_t fw_stats_event; 2950 2951 /* User configured max number of tx buffers */ 2952 uint32_t num_tx_allowed; 2953 2954 /* unique cookie required for peer session */ 2955 uint32_t next_peer_cookie; 2956 2957 /* 2958 * Run time enabled when the first protocol tag is added, 2959 * run time disabled when the last protocol tag is deleted 2960 */ 2961 bool is_rx_protocol_tagging_enabled; 2962 2963 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 2964 /* 2965 * The protocol type is used as array index to save 2966 * user provided tag info 2967 */ 2968 struct rx_protocol_tag_map rx_proto_tag_map[RX_PROTOCOL_TAG_MAX]; 2969 2970 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 2971 /* 2972 * Track msdus received from each reo ring separately to avoid 2973 * simultaneous writes from different core 2974 */ 2975 struct rx_protocol_tag_stats 2976 reo_proto_tag_stats[MAX_REO_DEST_RINGS][RX_PROTOCOL_TAG_MAX]; 2977 /* Track msdus received from expection ring separately */ 2978 struct rx_protocol_tag_stats 2979 rx_err_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 2980 struct rx_protocol_tag_stats 2981 mon_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 2982 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 2983 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 2984 2985 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 2986 /** 2987 * Pointer to DP Flow FST at SOC level if 2988 * is_rx_flow_search_table_per_pdev is true 2989 */ 2990 struct dp_rx_fst *rx_fst; 2991 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 2992 2993 #ifdef FEATURE_TSO_STATS 2994 /* TSO Id to index into TSO packet information */ 2995 qdf_atomic_t tso_idx; 2996 #endif /* FEATURE_TSO_STATS */ 2997 2998 #ifdef WLAN_SUPPORT_DATA_STALL 2999 data_stall_detect_cb data_stall_detect_callback; 3000 #endif /* WLAN_SUPPORT_DATA_STALL */ 3001 3002 /* flag to indicate whether LRO hash command has been sent to FW */ 3003 uint8_t is_lro_hash_configured; 3004 3005 #ifdef HTT_STATS_DEBUGFS_SUPPORT 3006 /* HTT stats debugfs params */ 3007 struct pdev_htt_stats_dbgfs_cfg *dbgfs_cfg; 3008 #endif 3009 struct { 3010 qdf_work_t work; 3011 qdf_workqueue_t *work_queue; 3012 uint32_t seq_num; 3013 uint8_t queue_depth; 3014 qdf_spinlock_t list_lock; 3015 3016 TAILQ_HEAD(, dp_soc_srngs_state) list; 3017 } bkp_stats; 3018 #ifdef WIFI_MONITOR_SUPPORT 3019 struct dp_mon_pdev *monitor_pdev; 3020 #endif 3021 #ifdef WLAN_FEATURE_11BE_MLO 3022 struct dp_mlo_sync_timestamp timestamp; 3023 #endif 3024 /* Is isolation mode enabled */ 3025 bool isolation; 3026 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 3027 uint8_t is_first_wakeup_packet; 3028 #endif 3029 #ifdef CONNECTIVITY_PKTLOG 3030 /* packetdump callback functions */ 3031 ol_txrx_pktdump_cb dp_tx_packetdump_cb; 3032 ol_txrx_pktdump_cb dp_rx_packetdump_cb; 3033 #endif 3034 uint64_t fw_stats_tlv_bitmap_rcvd; 3035 bool pending_fw_response; 3036 }; 3037 3038 struct dp_peer; 3039 3040 #ifdef DP_RX_UDP_OVER_PEER_ROAM 3041 #define WLAN_ROAM_PEER_AUTH_STATUS_NONE 0x0 3042 /** 3043 * This macro is equivalent to macro ROAM_AUTH_STATUS_AUTHENTICATED used 3044 * in connection mgr 3045 */ 3046 #define WLAN_ROAM_PEER_AUTH_STATUS_AUTHENTICATED 0x2 3047 #endif 3048 3049 /* VDEV structure for data path state */ 3050 struct dp_vdev { 3051 /* OS device abstraction */ 3052 qdf_device_t osdev; 3053 3054 /* physical device that is the parent of this virtual device */ 3055 struct dp_pdev *pdev; 3056 3057 /* VDEV operating mode */ 3058 enum wlan_op_mode opmode; 3059 3060 /* VDEV subtype */ 3061 enum wlan_op_subtype subtype; 3062 3063 /* Tx encapsulation type for this VAP */ 3064 enum htt_cmn_pkt_type tx_encap_type; 3065 3066 /* Rx Decapsulation type for this VAP */ 3067 enum htt_cmn_pkt_type rx_decap_type; 3068 3069 /* WDS enabled */ 3070 bool wds_enabled; 3071 3072 /* MEC enabled */ 3073 bool mec_enabled; 3074 3075 #ifdef QCA_SUPPORT_WDS_EXTENDED 3076 bool wds_ext_enabled; 3077 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 3078 bool drop_3addr_mcast; 3079 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 3080 bool skip_bar_update; 3081 unsigned long skip_bar_update_last_ts; 3082 #endif 3083 /* WDS Aging timer period */ 3084 uint32_t wds_aging_timer_val; 3085 3086 /* NAWDS enabled */ 3087 bool nawds_enabled; 3088 3089 /* Multicast enhancement enabled */ 3090 uint8_t mcast_enhancement_en; 3091 3092 /* IGMP multicast enhancement enabled */ 3093 uint8_t igmp_mcast_enhanc_en; 3094 3095 /* vdev_id - ID used to specify a particular vdev to the target */ 3096 uint8_t vdev_id; 3097 3098 /* Default HTT meta data for this VDEV */ 3099 /* TBD: check alignment constraints */ 3100 uint16_t htt_tcl_metadata; 3101 3102 /* Mesh mode vdev */ 3103 uint32_t mesh_vdev; 3104 3105 /* Mesh mode rx filter setting */ 3106 uint32_t mesh_rx_filter; 3107 3108 /* DSCP-TID mapping table ID */ 3109 uint8_t dscp_tid_map_id; 3110 3111 /* Address search type to be set in TX descriptor */ 3112 uint8_t search_type; 3113 3114 /* 3115 * Flag to indicate if s/w tid classification should be 3116 * skipped 3117 */ 3118 uint8_t skip_sw_tid_classification; 3119 3120 /* Flag to enable peer authorization */ 3121 uint8_t peer_authorize; 3122 3123 /* AST hash value for BSS peer in HW valid for STA VAP*/ 3124 uint16_t bss_ast_hash; 3125 3126 /* vdev lmac_id */ 3127 int lmac_id; 3128 3129 bool multipass_en; 3130 3131 /* Address search flags to be configured in HAL descriptor */ 3132 uint8_t hal_desc_addr_search_flags; 3133 3134 /* Handle to the OS shim SW's virtual device */ 3135 ol_osif_vdev_handle osif_vdev; 3136 3137 /* MAC address */ 3138 union dp_align_mac_addr mac_addr; 3139 3140 #ifdef WLAN_FEATURE_11BE_MLO 3141 /* MLO MAC address corresponding to vdev */ 3142 union dp_align_mac_addr mld_mac_addr; 3143 #if defined(WLAN_MLO_MULTI_CHIP) && defined(WLAN_MCAST_MLO) 3144 bool mlo_vdev; 3145 #endif 3146 #endif 3147 3148 /* node in the pdev's list of vdevs */ 3149 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 3150 3151 /* dp_peer list */ 3152 TAILQ_HEAD(, dp_peer) peer_list; 3153 /* to protect peer_list */ 3154 DP_MUTEX_TYPE peer_list_lock; 3155 3156 /* RX call back function to flush GRO packets*/ 3157 ol_txrx_rx_gro_flush_ind_fp osif_gro_flush; 3158 /* default RX call back function called by dp */ 3159 ol_txrx_rx_fp osif_rx; 3160 #ifdef QCA_SUPPORT_EAPOL_OVER_CONTROL_PORT 3161 /* callback to receive eapol frames */ 3162 ol_txrx_rx_fp osif_rx_eapol; 3163 #endif 3164 /* callback to deliver rx frames to the OS */ 3165 ol_txrx_rx_fp osif_rx_stack; 3166 /* Callback to handle rx fisa frames */ 3167 ol_txrx_fisa_rx_fp osif_fisa_rx; 3168 ol_txrx_fisa_flush_fp osif_fisa_flush; 3169 3170 /* call back function to flush out queued rx packets*/ 3171 ol_txrx_rx_flush_fp osif_rx_flush; 3172 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 3173 ol_txrx_get_key_fp osif_get_key; 3174 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 3175 3176 #ifdef notyet 3177 /* callback to check if the msdu is an WAI (WAPI) frame */ 3178 ol_rx_check_wai_fp osif_check_wai; 3179 #endif 3180 3181 /* proxy arp function */ 3182 ol_txrx_proxy_arp_fp osif_proxy_arp; 3183 3184 ol_txrx_mcast_me_fp me_convert; 3185 3186 /* completion function used by this vdev*/ 3187 ol_txrx_completion_fp tx_comp; 3188 3189 ol_txrx_get_tsf_time get_tsf_time; 3190 3191 /* callback to classify critical packets */ 3192 ol_txrx_classify_critical_pkt_fp tx_classify_critical_pkt_cb; 3193 3194 /* deferred vdev deletion state */ 3195 struct { 3196 /* VDEV delete pending */ 3197 int pending; 3198 /* 3199 * callback and a context argument to provide a 3200 * notification for when the vdev is deleted. 3201 */ 3202 ol_txrx_vdev_delete_cb callback; 3203 void *context; 3204 } delete; 3205 3206 /* tx data delivery notification callback function */ 3207 struct { 3208 ol_txrx_data_tx_cb func; 3209 void *ctxt; 3210 } tx_non_std_data_callback; 3211 3212 3213 /* safe mode control to bypass the encrypt and decipher process*/ 3214 uint32_t safemode; 3215 3216 /* rx filter related */ 3217 uint32_t drop_unenc; 3218 #ifdef notyet 3219 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 3220 uint32_t filters_num; 3221 #endif 3222 /* TDLS Link status */ 3223 bool tdls_link_connected; 3224 bool is_tdls_frame; 3225 3226 /* per vdev rx nbuf queue */ 3227 qdf_nbuf_queue_t rxq; 3228 3229 uint8_t tx_ring_id; 3230 struct dp_tx_desc_pool_s *tx_desc; 3231 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 3232 3233 /* VDEV Stats */ 3234 struct cdp_vdev_stats stats; 3235 3236 /* Is this a proxySTA VAP */ 3237 uint8_t proxysta_vdev : 1, /* Is this a proxySTA VAP */ 3238 wrap_vdev : 1, /* Is this a QWRAP AP VAP */ 3239 isolation_vdev : 1, /* Is this a QWRAP AP VAP */ 3240 reserved : 5; /* Reserved */ 3241 3242 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 3243 struct dp_tx_desc_pool_s *pool; 3244 #endif 3245 /* AP BRIDGE enabled */ 3246 bool ap_bridge_enabled; 3247 3248 enum cdp_sec_type sec_type; 3249 3250 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 3251 bool raw_mode_war; 3252 3253 3254 /* AST hash index for BSS peer in HW valid for STA VAP*/ 3255 uint16_t bss_ast_idx; 3256 3257 /* Capture timestamp of previous tx packet enqueued */ 3258 uint64_t prev_tx_enq_tstamp; 3259 3260 /* Capture timestamp of previous rx packet delivered */ 3261 uint64_t prev_rx_deliver_tstamp; 3262 3263 /* 8021p PCP-TID mapping table ID */ 3264 uint8_t tidmap_tbl_id; 3265 3266 /* 8021p PCP-TID map values */ 3267 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 3268 3269 /* TIDmap priority */ 3270 uint8_t tidmap_prty; 3271 3272 #ifdef QCA_MULTIPASS_SUPPORT 3273 uint16_t *iv_vlan_map; 3274 3275 /* dp_peer special list */ 3276 TAILQ_HEAD(, dp_txrx_peer) mpass_peer_list; 3277 DP_MUTEX_TYPE mpass_peer_mutex; 3278 #endif 3279 /* Extended data path handle */ 3280 struct cdp_ext_vdev *vdev_dp_ext_handle; 3281 #ifdef VDEV_PEER_PROTOCOL_COUNT 3282 /* 3283 * Rx-Ingress and Tx-Egress are in the lower level DP layer 3284 * Rx-Egress and Tx-ingress are handled in osif layer for DP 3285 * So 3286 * Rx-Egress and Tx-ingress mask definitions are in OSIF layer 3287 * Rx-Ingress and Tx-Egress definitions are here below 3288 */ 3289 #define VDEV_PEER_PROTOCOL_RX_INGRESS_MASK 1 3290 #define VDEV_PEER_PROTOCOL_TX_INGRESS_MASK 2 3291 #define VDEV_PEER_PROTOCOL_RX_EGRESS_MASK 4 3292 #define VDEV_PEER_PROTOCOL_TX_EGRESS_MASK 8 3293 bool peer_protocol_count_track; 3294 int peer_protocol_count_dropmask; 3295 #endif 3296 /* callback to collect connectivity stats */ 3297 ol_txrx_stats_rx_fp stats_cb; 3298 uint32_t num_peers; 3299 /* entry to inactive_list*/ 3300 TAILQ_ENTRY(dp_vdev) inactive_list_elem; 3301 3302 #ifdef WLAN_SUPPORT_RX_FISA 3303 /** 3304 * Params used for controlling the fisa aggregation dynamically 3305 */ 3306 uint8_t fisa_disallowed[MAX_REO_DEST_RINGS]; 3307 uint8_t fisa_force_flushed[MAX_REO_DEST_RINGS]; 3308 #endif 3309 /* 3310 * Refcount for VDEV currently incremented when 3311 * peer is created for VDEV 3312 */ 3313 qdf_atomic_t ref_cnt; 3314 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 3315 uint8_t num_latency_critical_conn; 3316 #ifdef WLAN_SUPPORT_MESH_LATENCY 3317 uint8_t peer_tid_latency_enabled; 3318 /* tid latency configuration parameters */ 3319 struct { 3320 uint32_t service_interval; 3321 uint32_t burst_size; 3322 uint8_t latency_tid; 3323 } mesh_tid_latency_config; 3324 #endif 3325 #ifdef WIFI_MONITOR_SUPPORT 3326 struct dp_mon_vdev *monitor_vdev; 3327 #endif 3328 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(CONFIG_SAWF) 3329 /* Delta between TQM clock and TSF clock */ 3330 uint32_t delta_tsf; 3331 #endif 3332 #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY 3333 /* Indicate if uplink delay report is enabled or not */ 3334 qdf_atomic_t ul_delay_report; 3335 /* accumulative delay for every TX completion */ 3336 qdf_atomic_t ul_delay_accum; 3337 /* accumulative number of packets delay has accumulated */ 3338 qdf_atomic_t ul_pkts_accum; 3339 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */ 3340 3341 /* vdev_stats_id - ID used for stats collection by FW from HW*/ 3342 uint8_t vdev_stats_id; 3343 #ifdef HW_TX_DELAY_STATS_ENABLE 3344 /* hw tx delay stats enable */ 3345 uint8_t hw_tx_delay_stats_enabled; 3346 #endif 3347 #ifdef DP_RX_UDP_OVER_PEER_ROAM 3348 uint32_t roaming_peer_status; 3349 union dp_align_mac_addr roaming_peer_mac; 3350 #endif 3351 }; 3352 3353 enum { 3354 dp_sec_mcast = 0, 3355 dp_sec_ucast 3356 }; 3357 3358 #ifdef WDS_VENDOR_EXTENSION 3359 typedef struct { 3360 uint8_t wds_tx_mcast_4addr:1, 3361 wds_tx_ucast_4addr:1, 3362 wds_rx_filter:1, /* enforce rx filter */ 3363 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 3364 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 3365 3366 } dp_ecm_policy; 3367 #endif 3368 3369 /* 3370 * struct dp_peer_cached_bufq - cached_bufq to enqueue rx packets 3371 * @cached_bufq: nbuff list to enqueue rx packets 3372 * @bufq_lock: spinlock for nbuff list access 3373 * @thres: maximum threshold for number of rx buff to enqueue 3374 * @entries: number of entries 3375 * @dropped: number of packets dropped 3376 */ 3377 struct dp_peer_cached_bufq { 3378 qdf_list_t cached_bufq; 3379 qdf_spinlock_t bufq_lock; 3380 uint32_t thresh; 3381 uint32_t entries; 3382 uint32_t dropped; 3383 }; 3384 3385 /** 3386 * enum dp_peer_ast_flowq 3387 * @DP_PEER_AST_FLOWQ_HI_PRIO: Hi Priority flow queue 3388 * @DP_PEER_AST_FLOWQ_LOW_PRIO: Low priority flow queue 3389 * @DP_PEER_AST_FLOWQ_UDP: flow queue type is UDP 3390 * @DP_PEER_AST_FLOWQ_NON_UDP: flow queue type is Non UDP 3391 */ 3392 enum dp_peer_ast_flowq { 3393 DP_PEER_AST_FLOWQ_HI_PRIO, 3394 DP_PEER_AST_FLOWQ_LOW_PRIO, 3395 DP_PEER_AST_FLOWQ_UDP, 3396 DP_PEER_AST_FLOWQ_NON_UDP, 3397 DP_PEER_AST_FLOWQ_MAX, 3398 }; 3399 3400 /* 3401 * struct dp_ast_flow_override_info - ast override info 3402 * @ast_index - ast indexes in peer map message 3403 * @ast_valid_mask - ast valid mask for each ast index 3404 * @ast_flow_mask - ast flow mask for each ast index 3405 * @tid_valid_low_pri_mask - per tid mask for low priority flow 3406 * @tid_valid_hi_pri_mask - per tid mask for hi priority flow 3407 */ 3408 struct dp_ast_flow_override_info { 3409 uint16_t ast_idx[DP_PEER_AST_FLOWQ_MAX]; 3410 uint8_t ast_valid_mask; 3411 uint8_t ast_flow_mask[DP_PEER_AST_FLOWQ_MAX]; 3412 uint8_t tid_valid_low_pri_mask; 3413 uint8_t tid_valid_hi_pri_mask; 3414 }; 3415 3416 /* 3417 * struct dp_peer_ast_params - ast parameters for a msdu flow-queue 3418 * @ast_index - ast index populated by FW 3419 * @is_valid - ast flow valid mask 3420 * @valid_tid_mask - per tid mask for this ast index 3421 * @flowQ - flow queue id associated with this ast index 3422 */ 3423 struct dp_peer_ast_params { 3424 uint16_t ast_idx; 3425 uint8_t is_valid; 3426 uint8_t valid_tid_mask; 3427 uint8_t flowQ; 3428 }; 3429 3430 #define DP_MLO_FLOW_INFO_MAX 3 3431 3432 /** 3433 * struct dp_mlo_flow_override_info - Flow override info 3434 * @ast_idx: Primary TCL AST Index 3435 * @ast_idx_valid: Is AST index valid 3436 * @chip_id: CHIP ID 3437 * @tidmask: tidmask 3438 * @cache_set_num: Cache set number 3439 */ 3440 struct dp_mlo_flow_override_info { 3441 uint16_t ast_idx; 3442 uint8_t ast_idx_valid; 3443 uint8_t chip_id; 3444 uint8_t tidmask; 3445 uint8_t cache_set_num; 3446 }; 3447 3448 /** 3449 * struct dp_mlo_link_info - Link info 3450 * @peer_chip_id: Peer Chip ID 3451 * @vdev_id: Vdev ID 3452 */ 3453 struct dp_mlo_link_info { 3454 uint8_t peer_chip_id; 3455 uint8_t vdev_id; 3456 }; 3457 3458 #ifdef WLAN_SUPPORT_MSCS 3459 /*MSCS Procedure based macros */ 3460 #define IEEE80211_MSCS_MAX_ELEM_SIZE 5 3461 #define IEEE80211_TCLAS_MASK_CLA_TYPE_4 4 3462 /* 3463 * struct dp_peer_mscs_parameter - MSCS database obtained from 3464 * MSCS Request and Response in the control path. This data is used 3465 * by the AP to find out what priority to set based on the tuple 3466 * classification during packet processing. 3467 * @user_priority_bitmap - User priority bitmap obtained during 3468 * handshake 3469 * @user_priority_limit - User priority limit obtained during 3470 * handshake 3471 * @classifier_mask - params to be compared during processing 3472 */ 3473 struct dp_peer_mscs_parameter { 3474 uint8_t user_priority_bitmap; 3475 uint8_t user_priority_limit; 3476 uint8_t classifier_mask; 3477 }; 3478 #endif 3479 3480 #ifdef QCA_SUPPORT_WDS_EXTENDED 3481 #define WDS_EXT_PEER_INIT_BIT 0 3482 3483 /** 3484 * struct dp_wds_ext_peer - wds ext peer structure 3485 * This is used when wds extended feature is enabled 3486 * both compile time and run time. It is created 3487 * when 1st 4 address frame is received from 3488 * wds backhaul. 3489 * @osif_vdev: Handle to the OS shim SW's virtual device 3490 * @init: wds ext netdev state 3491 */ 3492 struct dp_wds_ext_peer { 3493 ol_osif_peer_handle osif_peer; 3494 unsigned long init; 3495 }; 3496 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 3497 3498 #ifdef WLAN_SUPPORT_MESH_LATENCY 3499 /*Advanced Mesh latency feature based macros */ 3500 /* 3501 * struct dp_peer_mesh_latency parameter - Mesh latency related 3502 * parameters. This data is updated per peer per TID based on 3503 * the flow tuple classification in external rule database 3504 * during packet processing. 3505 * @service_interval_dl - Service interval associated with TID in DL 3506 * @burst_size_dl - Burst size additive over multiple flows in DL 3507 * @service_interval_ul - Service interval associated with TID in UL 3508 * @burst_size_ul - Burst size additive over multiple flows in UL 3509 * @ac - custom ac derived from service interval 3510 * @msduq - MSDU queue number within TID 3511 */ 3512 struct dp_peer_mesh_latency_parameter { 3513 uint32_t service_interval_dl; 3514 uint32_t burst_size_dl; 3515 uint32_t service_interval_ul; 3516 uint32_t burst_size_ul; 3517 uint8_t ac; 3518 uint8_t msduq; 3519 }; 3520 #endif 3521 3522 #ifdef WLAN_FEATURE_11BE_MLO 3523 /* Max number of links for MLO connection */ 3524 #define DP_MAX_MLO_LINKS 3 3525 3526 /** 3527 * struct dp_peer_link_info - link peer information for MLO 3528 * @mac_add: Mac address 3529 * @vdev_id: Vdev ID for current link peer 3530 * @is_valid: flag for link peer info valid or not 3531 * @chip_id: chip id 3532 */ 3533 struct dp_peer_link_info { 3534 union dp_align_mac_addr mac_addr; 3535 uint8_t vdev_id; 3536 uint8_t is_valid; 3537 uint8_t chip_id; 3538 }; 3539 3540 /** 3541 * struct dp_mld_link_peers - this structure is used to get link peers 3542 pointer from mld peer 3543 * @link_peers: link peers pointer array 3544 * @num_links: number of link peers fetched 3545 */ 3546 struct dp_mld_link_peers { 3547 struct dp_peer *link_peers[DP_MAX_MLO_LINKS]; 3548 uint8_t num_links; 3549 }; 3550 #endif 3551 3552 typedef void *dp_txrx_ref_handle; 3553 3554 /** 3555 * struct dp_peer_per_pkt_tx_stats- Peer Tx stats updated in per pkt 3556 * Tx completion path 3557 * @cdp_pkt_info ucast: Unicast Packet Count 3558 * @cdp_pkt_info mcast: Multicast Packet Count 3559 * @cdp_pkt_info bcast: Broadcast Packet Count 3560 * @cdp_pkt_info nawds_mcast: NAWDS Multicast Packet Count 3561 * @cdp_pkt_info tx_success: Successful Tx Packets 3562 * @nawds_mcast_drop: NAWDS Multicast Drop Count 3563 * @ofdma: Total Packets as ofdma 3564 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 3565 * @amsdu_cnt: Number of MSDUs part of AMSDU 3566 * @cdp_pkt_info fw_rem: Discarded by firmware 3567 * @fw_rem_notx: firmware_discard_untransmitted 3568 * @fw_rem_tx: firmware_discard_transmitted 3569 * @age_out: aged out in mpdu/msdu queues 3570 * @fw_reason1: discarded by firmware reason 1 3571 * @fw_reason2: discarded by firmware reason 2 3572 * @fw_reason3: discarded by firmware reason 3 3573 * @fw_rem_no_match: dropped due to fw no match command 3574 * @drop_threshold: dropped due to HW threshold 3575 * @drop_link_desc_na: dropped due resource not available in HW 3576 * @invalid_drop: Invalid msdu drop 3577 * @mcast_vdev_drop: MCAST drop configured for VDEV in HW 3578 * @invalid_rr: Invalid TQM release reason 3579 * @failed_retry_count: packets failed due to retry above 802.11 retry limit 3580 * @retry_count: packets successfully send after one or more retry 3581 * @multiple_retry_count: packets successfully sent after more than one retry 3582 * @no_ack_count: no ack pkt count for different protocols 3583 * @tx_success_twt: Successful Tx Packets in TWT session 3584 * @last_tx_ts: last timestamp in jiffies when tx comp occurred 3585 * @avg_sojourn_msdu[CDP_DATA_TID_MAX]: Avg sojourn msdu stat 3586 * @protocol_trace_cnt: per-peer protocol counter 3587 * @release_src_not_tqm: Counter to keep track of release source is not TQM 3588 * in TX completion status processing 3589 */ 3590 struct dp_peer_per_pkt_tx_stats { 3591 struct cdp_pkt_info ucast; 3592 struct cdp_pkt_info mcast; 3593 struct cdp_pkt_info bcast; 3594 struct cdp_pkt_info nawds_mcast; 3595 struct cdp_pkt_info tx_success; 3596 uint32_t nawds_mcast_drop; 3597 uint32_t ofdma; 3598 uint32_t non_amsdu_cnt; 3599 uint32_t amsdu_cnt; 3600 struct { 3601 struct cdp_pkt_info fw_rem; 3602 uint32_t fw_rem_notx; 3603 uint32_t fw_rem_tx; 3604 uint32_t age_out; 3605 uint32_t fw_reason1; 3606 uint32_t fw_reason2; 3607 uint32_t fw_reason3; 3608 uint32_t fw_rem_queue_disable; 3609 uint32_t fw_rem_no_match; 3610 uint32_t drop_threshold; 3611 uint32_t drop_link_desc_na; 3612 uint32_t invalid_drop; 3613 uint32_t mcast_vdev_drop; 3614 uint32_t invalid_rr; 3615 } dropped; 3616 uint32_t failed_retry_count; 3617 uint32_t retry_count; 3618 uint32_t multiple_retry_count; 3619 uint32_t no_ack_count[QDF_PROTO_SUBTYPE_MAX]; 3620 struct cdp_pkt_info tx_success_twt; 3621 unsigned long last_tx_ts; 3622 qdf_ewma_tx_lag avg_sojourn_msdu[CDP_DATA_TID_MAX]; 3623 #ifdef VDEV_PEER_PROTOCOL_COUNT 3624 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 3625 #endif 3626 uint32_t release_src_not_tqm; 3627 }; 3628 3629 /** 3630 * struct dp_peer_extd_tx_stats - Peer Tx stats updated in either 3631 * per pkt Tx completion path when macro QCA_ENHANCED_STATS_SUPPORT is 3632 * disabled or in HTT Tx PPDU completion path when macro is enabled 3633 * @stbc: Packets in STBC 3634 * @ldpc: Packets in LDPC 3635 * @retries: Packet retries 3636 * @pkt_type[DOT11_MAX]: pkt count for different .11 modes 3637 * @wme_ac_type[WME_AC_MAX]: Wireless Multimedia type Count 3638 * @excess_retries_per_ac[WME_AC_MAX]: Wireless Multimedia type Count 3639 * @ampdu_cnt: completion of aggregation 3640 * @non_ampdu_cnt: tx completion not aggregated 3641 * @num_ppdu_cookie_valid: no. of valid ppdu cookies rcvd from FW 3642 * @tx_ppdus: ppdus in tx 3643 * @tx_mpdus_success: mpdus successful in tx 3644 * @tx_mpdus_tried: mpdus tried in tx 3645 * @tx_rate: Tx Rate in kbps 3646 * @last_tx_rate: Last tx rate for unicast packets 3647 * @last_tx_rate_mcs: Tx rate mcs for unicast packets 3648 * @mcast_last_tx_rate: Last tx rate for multicast packets 3649 * @mcast_last_tx_rate_mcs: Last tx rate mcs for multicast 3650 * @rnd_avg_tx_rate: Rounded average tx rate 3651 * @avg_tx_rate: Average TX rate 3652 * @tx_ratecode: Tx rate code of last frame 3653 * @pream_punct_cnt: Preamble Punctured count 3654 * @sgi_count[MAX_GI]: SGI count 3655 * @nss[SS_COUNT]: Packet count for different num_spatial_stream values 3656 * @bw[MAX_BW]: Packet Count for different bandwidths 3657 * @ru_start: RU start index 3658 * @ru_tones: RU tones size 3659 * @ru_loc: pkt info for RU location 26/ 52/ 106/ 242/ 484 counter 3660 * @transmit_type: pkt info for tx transmit type 3661 * @mu_group_id: mumimo mu group id 3662 * @last_ack_rssi: RSSI of last acked packet 3663 * @nss_info: NSS 1,2, ...8 3664 * @mcs_info: MCS index 3665 * @bw_info: Bandwidth 3666 * <enum 0 bw_20_MHz> 3667 * <enum 1 bw_40_MHz> 3668 * <enum 2 bw_80_MHz> 3669 * <enum 3 bw_160_MHz> 3670 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 3671 * <enum 1 0_4_us_sgi > Legacy short GI 3672 * <enum 2 1_6_us_sgi > HE related GI 3673 * <enum 3 3_2_us_sgi > HE 3674 * @preamble_info: preamble 3675 * @tx_ucast_total: total ucast count 3676 * @tx_ucast_success: total ucast success count 3677 * @retries_mpdu: mpdu number of successfully transmitted after retries 3678 * @mpdu_success_with_retries: mpdu retry count in case of successful tx 3679 * @su_be_ppdu_cnt: SU Tx packet count for 11BE 3680 * @mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]: MU Tx packet count for 11BE 3681 * @punc_bw[MAX_PUNCTURED_MODE]: MSDU count for punctured bw 3682 */ 3683 struct dp_peer_extd_tx_stats { 3684 uint32_t stbc; 3685 uint32_t ldpc; 3686 uint32_t retries; 3687 struct cdp_pkt_type pkt_type[DOT11_MAX]; 3688 uint32_t wme_ac_type[WME_AC_MAX]; 3689 uint32_t excess_retries_per_ac[WME_AC_MAX]; 3690 uint32_t ampdu_cnt; 3691 uint32_t non_ampdu_cnt; 3692 uint32_t num_ppdu_cookie_valid; 3693 uint32_t tx_ppdus; 3694 uint32_t tx_mpdus_success; 3695 uint32_t tx_mpdus_tried; 3696 3697 uint32_t tx_rate; 3698 uint32_t last_tx_rate; 3699 uint32_t last_tx_rate_mcs; 3700 uint32_t mcast_last_tx_rate; 3701 uint32_t mcast_last_tx_rate_mcs; 3702 uint64_t rnd_avg_tx_rate; 3703 uint64_t avg_tx_rate; 3704 uint16_t tx_ratecode; 3705 3706 uint32_t sgi_count[MAX_GI]; 3707 uint32_t pream_punct_cnt; 3708 uint32_t nss[SS_COUNT]; 3709 uint32_t bw[MAX_BW]; 3710 uint32_t ru_start; 3711 uint32_t ru_tones; 3712 struct cdp_tx_pkt_info ru_loc[MAX_RU_LOCATIONS]; 3713 3714 struct cdp_tx_pkt_info transmit_type[MAX_TRANSMIT_TYPES]; 3715 uint32_t mu_group_id[MAX_MU_GROUP_ID]; 3716 3717 uint32_t last_ack_rssi; 3718 3719 uint32_t nss_info:4, 3720 mcs_info:4, 3721 bw_info:4, 3722 gi_info:4, 3723 preamble_info:4; 3724 3725 uint32_t retries_mpdu; 3726 uint32_t mpdu_success_with_retries; 3727 struct cdp_pkt_info tx_ucast_total; 3728 struct cdp_pkt_info tx_ucast_success; 3729 #ifdef WLAN_FEATURE_11BE 3730 struct cdp_pkt_type su_be_ppdu_cnt; 3731 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 3732 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 3733 #endif 3734 }; 3735 3736 /** 3737 * struct dp_peer_per_pkt_rx_stats - Peer Rx stats updated in per pkt Rx path 3738 * @rcvd_reo[CDP_MAX_RX_RINGS]: Packets received on the reo ring 3739 * @rx_lmac[CDP_MAX_LMACS]: Packets received on each lmac 3740 * @unicast: Total unicast packets 3741 * @multicast: Total multicast packets 3742 * @bcast: Broadcast Packet Count 3743 * @raw: Raw Pakets received 3744 * @nawds_mcast_drop: Total NAWDS multicast packets dropped 3745 * @mec_drop: Total MEC packets dropped 3746 * @last_rx_ts: last timestamp in jiffies when RX happened 3747 * @intra_bss.pkts: Intra BSS packets received 3748 * @intra_bss.fail: Intra BSS packets failed 3749 * @intra_bss.mdns_no_fws: Intra BSS MDNS packets not forwarded 3750 * @mic_err: Rx MIC errors CCMP 3751 * @decrypt_err: Rx Decryption Errors CRC 3752 * @fcserr: rx MIC check failed (CCMP) 3753 * @pn_err: pn check failed 3754 * @oor_err: Rx OOR errors 3755 * @jump_2k_err: 2k jump errors 3756 * @rxdma_wifi_parse_err: rxdma wifi parse errors 3757 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 3758 * @amsdu_cnt: Number of MSDUs part of AMSDU 3759 * @rx_retries: retries of packet in rx 3760 * @multipass_rx_pkt_drop: Dropped multipass rx pkt 3761 * @peer_unauth_rx_pkt_drop: Unauth rx packet drops 3762 * @policy_check_drop: policy check drops 3763 * @to_stack_twt: Total packets sent up the stack in TWT session 3764 * @protocol_trace_cnt: per-peer protocol counters 3765 */ 3766 struct dp_peer_per_pkt_rx_stats { 3767 struct cdp_pkt_info rcvd_reo[CDP_MAX_RX_RINGS]; 3768 struct cdp_pkt_info rx_lmac[CDP_MAX_LMACS]; 3769 struct cdp_pkt_info unicast; 3770 struct cdp_pkt_info multicast; 3771 struct cdp_pkt_info bcast; 3772 struct cdp_pkt_info raw; 3773 uint32_t nawds_mcast_drop; 3774 struct cdp_pkt_info mec_drop; 3775 unsigned long last_rx_ts; 3776 struct { 3777 struct cdp_pkt_info pkts; 3778 struct cdp_pkt_info fail; 3779 uint32_t mdns_no_fwd; 3780 } intra_bss; 3781 struct { 3782 uint32_t mic_err; 3783 uint32_t decrypt_err; 3784 uint32_t fcserr; 3785 uint32_t pn_err; 3786 uint32_t oor_err; 3787 uint32_t jump_2k_err; 3788 uint32_t rxdma_wifi_parse_err; 3789 } err; 3790 uint32_t non_amsdu_cnt; 3791 uint32_t amsdu_cnt; 3792 uint32_t rx_retries; 3793 uint32_t multipass_rx_pkt_drop; 3794 uint32_t peer_unauth_rx_pkt_drop; 3795 uint32_t policy_check_drop; 3796 struct cdp_pkt_info to_stack_twt; 3797 #ifdef VDEV_PEER_PROTOCOL_COUNT 3798 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 3799 #endif 3800 uint32_t mcast_3addr_drop; 3801 }; 3802 3803 /** 3804 * struct dp_peer_extd_rx_stats - Peer Rx stats updated in either 3805 * per pkt Rx path when macro QCA_ENHANCED_STATS_SUPPORT is disabled or in 3806 * Rx monitor patch when macro is enabled 3807 * @pkt_type[DOT11_MAX]: pkt counter for different .11 modes 3808 * @wme_ac_type[WME_AC_MAX]: Wireless Multimedia type Count 3809 * @mpdu_cnt_fcs_ok: SU Rx success mpdu count 3810 * @mpdu_cnt_fcs_err: SU Rx fail mpdu count 3811 * @non_ampdu_cnt: Number of MSDUs with no MPDU level aggregation 3812 * @ampdu_cnt: Number of MSDUs part of AMSPU 3813 * @rx_mpdus: mpdu in rx 3814 * @rx_ppdus: ppdu in rx 3815 * @su_ax_ppdu_cnt: SU Rx packet count for .11ax 3816 * @rx_mu[TXRX_TYPE_MU_MAX]: Rx MU stats 3817 * @reception_type[MAX_RECEPTION_TYPES]: Reception type of packets 3818 * @ppdu_cnt[MAX_RECEPTION_TYPES]: PPDU packet count in reception type 3819 * @sgi_count[MAX_GI]: sgi count 3820 * @nss[SS_COUNT]: packet count in spatiel Streams 3821 * @ppdu_nss[SS_COUNT]: PPDU packet count in spatial streams 3822 * @bw[MAX_BW]: Packet Count in different bandwidths 3823 * @rx_mpdu_cnt[MAX_MCS]: rx mpdu count per MCS rate 3824 * @rx_rate: Rx rate 3825 * @last_rx_rate: Previous rx rate 3826 * @rnd_avg_rx_rate: Rounded average rx rate 3827 * @avg_rx_rate: Average Rx rate 3828 * @rx_ratecode: Rx rate code of last frame 3829 * @avg_snr: Average snr 3830 * @rx_snr_measured_time: Time at which snr is measured 3831 * @snr: SNR of received signal 3832 * @last_snr: Previous snr 3833 * @nss_info: NSS 1,2, ...8 3834 * @mcs_info: MCS index 3835 * @bw_info: Bandwidth 3836 * <enum 0 bw_20_MHz> 3837 * <enum 1 bw_40_MHz> 3838 * <enum 2 bw_80_MHz> 3839 * <enum 3 bw_160_MHz> 3840 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 3841 * <enum 1 0_4_us_sgi > Legacy short GI 3842 * <enum 2 1_6_us_sgi > HE related GI 3843 * <enum 3 3_2_us_sgi > HE 3844 * @preamble_info: preamble 3845 * @mpdu_retry_cnt: retries of mpdu in rx 3846 * @su_be_ppdu_cnt: SU Rx packet count for BE 3847 * @mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]: MU rx packet count for BE 3848 * @punc_bw[MAX_PUNCTURED_MODE]: MSDU count for punctured bw 3849 */ 3850 struct dp_peer_extd_rx_stats { 3851 struct cdp_pkt_type pkt_type[DOT11_MAX]; 3852 uint32_t wme_ac_type[WME_AC_MAX]; 3853 uint32_t mpdu_cnt_fcs_ok; 3854 uint32_t mpdu_cnt_fcs_err; 3855 uint32_t non_ampdu_cnt; 3856 uint32_t ampdu_cnt; 3857 uint32_t rx_mpdus; 3858 uint32_t rx_ppdus; 3859 3860 struct cdp_pkt_type su_ax_ppdu_cnt; 3861 struct cdp_rx_mu rx_mu[TXRX_TYPE_MU_MAX]; 3862 uint32_t reception_type[MAX_RECEPTION_TYPES]; 3863 uint32_t ppdu_cnt[MAX_RECEPTION_TYPES]; 3864 3865 uint32_t sgi_count[MAX_GI]; 3866 uint32_t nss[SS_COUNT]; 3867 uint32_t ppdu_nss[SS_COUNT]; 3868 uint32_t bw[MAX_BW]; 3869 uint32_t rx_mpdu_cnt[MAX_MCS]; 3870 3871 uint32_t rx_rate; 3872 uint32_t last_rx_rate; 3873 uint32_t rnd_avg_rx_rate; 3874 uint32_t avg_rx_rate; 3875 uint32_t rx_ratecode; 3876 3877 uint32_t avg_snr; 3878 uint32_t rx_snr_measured_time; 3879 uint8_t snr; 3880 uint8_t last_snr; 3881 3882 uint32_t nss_info:4, 3883 mcs_info:4, 3884 bw_info:4, 3885 gi_info:4, 3886 preamble_info:4; 3887 3888 uint32_t mpdu_retry_cnt; 3889 #ifdef WLAN_FEATURE_11BE 3890 struct cdp_pkt_type su_be_ppdu_cnt; 3891 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 3892 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 3893 #endif 3894 }; 3895 3896 /** 3897 * struct dp_peer_per_pkt_stats - Per pkt stats for peer 3898 * @tx: Per pkt Tx stats 3899 * @rx: Per pkt Rx stats 3900 */ 3901 struct dp_peer_per_pkt_stats { 3902 struct dp_peer_per_pkt_tx_stats tx; 3903 struct dp_peer_per_pkt_rx_stats rx; 3904 }; 3905 3906 /** 3907 * struct dp_peer_extd_stats - Stats from extended path for peer 3908 * @tx: Extended path tx stats 3909 * @rx: Extended path rx stats 3910 */ 3911 struct dp_peer_extd_stats { 3912 struct dp_peer_extd_tx_stats tx; 3913 struct dp_peer_extd_rx_stats rx; 3914 }; 3915 3916 /** 3917 * struct dp_peer_stats - Peer stats 3918 * @per_pkt_stats: Per packet path stats 3919 * @extd_stats: Extended path stats 3920 */ 3921 struct dp_peer_stats { 3922 struct dp_peer_per_pkt_stats per_pkt_stats; 3923 #ifndef QCA_ENHANCED_STATS_SUPPORT 3924 struct dp_peer_extd_stats extd_stats; 3925 #endif 3926 }; 3927 3928 /** 3929 * struct dp_txrx_peer: DP txrx_peer strcuture used in per pkt path 3930 * @tx_failed: Total Tx failure 3931 * @cdp_pkt_info comp_pkt: Pkt Info for which completions were received 3932 * @to_stack: Total packets sent up the stack 3933 * @stats: Peer stats 3934 * @delay_stats: Peer delay stats 3935 * @jitter_stats: Peer jitter stats 3936 * @bw: bandwidth of peer connection 3937 * @mpdu_retry_threshold: MPDU retry threshold to increment tx bad count 3938 */ 3939 struct dp_txrx_peer { 3940 /* Core TxRx Peer */ 3941 3942 /* VDEV to which this peer is associated */ 3943 struct dp_vdev *vdev; 3944 3945 /* peer ID for this peer */ 3946 uint16_t peer_id; 3947 3948 uint8_t authorize:1, /* Set when authorized */ 3949 in_twt:1, /* in TWT session */ 3950 hw_txrx_stats_en:1, /*Indicate HW offload vdev stats */ 3951 mld_peer:1; /* MLD peer*/ 3952 3953 uint32_t tx_failed; 3954 struct cdp_pkt_info comp_pkt; 3955 struct cdp_pkt_info to_stack; 3956 3957 struct dp_peer_stats stats; 3958 3959 struct dp_peer_delay_stats *delay_stats; 3960 3961 struct cdp_peer_tid_stats *jitter_stats; 3962 3963 struct { 3964 enum cdp_sec_type sec_type; 3965 u_int32_t michael_key[2]; /* relevant for TKIP */ 3966 } security[2]; /* 0 -> multicast, 1 -> unicast */ 3967 3968 uint16_t nawds_enabled:1, /* NAWDS flag */ 3969 bss_peer:1, /* set for bss peer */ 3970 isolation:1, /* enable peer isolation for this peer */ 3971 wds_enabled:1; /* WDS peer */ 3972 #ifdef WDS_VENDOR_EXTENSION 3973 dp_ecm_policy wds_ecm; 3974 #endif 3975 #ifdef PEER_CACHE_RX_PKTS 3976 qdf_atomic_t flush_in_progress; 3977 struct dp_peer_cached_bufq bufq_info; 3978 #endif 3979 #ifdef QCA_MULTIPASS_SUPPORT 3980 /* node in the special peer list element */ 3981 TAILQ_ENTRY(dp_txrx_peer) mpass_peer_list_elem; 3982 /* vlan id for key */ 3983 uint16_t vlan_id; 3984 #endif 3985 #ifdef QCA_SUPPORT_WDS_EXTENDED 3986 struct dp_wds_ext_peer wds_ext; 3987 ol_txrx_rx_fp osif_rx; 3988 #endif 3989 struct dp_rx_tid_defrag rx_tid[DP_MAX_TIDS]; 3990 #ifdef CONFIG_SAWF 3991 struct dp_peer_sawf_stats *sawf_stats; 3992 #endif 3993 #ifdef DP_PEER_EXTENDED_API 3994 enum cdp_peer_bw bw; 3995 uint8_t mpdu_retry_threshold; 3996 #endif 3997 }; 3998 3999 /* Peer structure for data path state */ 4000 struct dp_peer { 4001 struct dp_txrx_peer *txrx_peer; 4002 #ifdef WIFI_MONITOR_SUPPORT 4003 struct dp_mon_peer *monitor_peer; 4004 #endif 4005 /* peer ID for this peer */ 4006 uint16_t peer_id; 4007 4008 /* VDEV to which this peer is associated */ 4009 struct dp_vdev *vdev; 4010 4011 struct dp_ast_entry *self_ast_entry; 4012 4013 qdf_atomic_t ref_cnt; 4014 4015 union dp_align_mac_addr mac_addr; 4016 4017 /* node in the vdev's list of peers */ 4018 TAILQ_ENTRY(dp_peer) peer_list_elem; 4019 /* node in the hash table bin's list of peers */ 4020 TAILQ_ENTRY(dp_peer) hash_list_elem; 4021 4022 /* TID structures pointer */ 4023 struct dp_rx_tid *rx_tid; 4024 4025 /* TBD: No transmit TID state required? */ 4026 4027 struct { 4028 enum cdp_sec_type sec_type; 4029 u_int32_t michael_key[2]; /* relevant for TKIP */ 4030 } security[2]; /* 0 -> multicast, 1 -> unicast */ 4031 4032 /* NAWDS Flag and Bss Peer bit */ 4033 uint16_t bss_peer:1, /* set for bss peer */ 4034 authorize:1, /* Set when authorized */ 4035 valid:1, /* valid bit */ 4036 delete_in_progress:1, /* Indicate kickout sent */ 4037 sta_self_peer:1, /* Indicate STA self peer */ 4038 is_tdls_peer:1; /* Indicate TDLS peer */ 4039 4040 #ifdef WLAN_FEATURE_11BE_MLO 4041 uint8_t first_link:1, /* first link peer for MLO */ 4042 primary_link:1; /* primary link for MLO */ 4043 #endif 4044 4045 /* MCL specific peer local id */ 4046 uint16_t local_id; 4047 enum ol_txrx_peer_state state; 4048 qdf_spinlock_t peer_info_lock; 4049 4050 /* Peer calibrated stats */ 4051 struct cdp_calibr_stats stats; 4052 4053 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 4054 /* TBD */ 4055 4056 /* Active Block ack sessions */ 4057 uint16_t active_ba_session_cnt; 4058 4059 /* Current HW buffersize setting */ 4060 uint16_t hw_buffer_size; 4061 4062 /* 4063 * Flag to check if sessions with 256 buffersize 4064 * should be terminated. 4065 */ 4066 uint8_t kill_256_sessions; 4067 qdf_atomic_t is_default_route_set; 4068 4069 #ifdef QCA_PEER_MULTIQ_SUPPORT 4070 struct dp_peer_ast_params peer_ast_flowq_idx[DP_PEER_AST_FLOWQ_MAX]; 4071 #endif 4072 /* entry to inactive_list*/ 4073 TAILQ_ENTRY(dp_peer) inactive_list_elem; 4074 4075 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 4076 4077 uint8_t peer_state; 4078 qdf_spinlock_t peer_state_lock; 4079 #ifdef WLAN_SUPPORT_MSCS 4080 struct dp_peer_mscs_parameter mscs_ipv4_parameter, mscs_ipv6_parameter; 4081 bool mscs_active; 4082 #endif 4083 #ifdef WLAN_SUPPORT_MESH_LATENCY 4084 struct dp_peer_mesh_latency_parameter mesh_latency_params[DP_MAX_TIDS]; 4085 #endif 4086 #ifdef WLAN_FEATURE_11BE_MLO 4087 /* peer type */ 4088 enum cdp_peer_type peer_type; 4089 /*---------for link peer---------*/ 4090 struct dp_peer *mld_peer; 4091 /*---------for mld peer----------*/ 4092 struct dp_peer_link_info link_peers[DP_MAX_MLO_LINKS]; 4093 uint8_t num_links; 4094 DP_MUTEX_TYPE link_peers_info_lock; 4095 #endif 4096 #ifdef CONFIG_SAWF_DEF_QUEUES 4097 struct dp_peer_sawf *sawf; 4098 #endif 4099 }; 4100 4101 /* 4102 * dp_invalid_peer_msg 4103 * @nbuf: data buffer 4104 * @wh: 802.11 header 4105 * @vdev_id: id of vdev 4106 */ 4107 struct dp_invalid_peer_msg { 4108 qdf_nbuf_t nbuf; 4109 struct ieee80211_frame *wh; 4110 uint8_t vdev_id; 4111 }; 4112 4113 /* 4114 * dp_tx_me_buf_t: ME buffer 4115 * next: pointer to next buffer 4116 * data: Destination Mac address 4117 * paddr_macbuf: physical address for dest_mac 4118 */ 4119 struct dp_tx_me_buf_t { 4120 /* Note: ME buf pool initialization logic expects next pointer to 4121 * be the first element. Dont add anything before next */ 4122 struct dp_tx_me_buf_t *next; 4123 uint8_t data[QDF_MAC_ADDR_SIZE]; 4124 qdf_dma_addr_t paddr_macbuf; 4125 }; 4126 4127 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) || defined(WLAN_SUPPORT_RX_FISA) 4128 struct hal_rx_fst; 4129 4130 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 4131 struct dp_rx_fse { 4132 /* HAL Rx Flow Search Entry which matches HW definition */ 4133 void *hal_rx_fse; 4134 /* Toeplitz hash value */ 4135 uint32_t flow_hash; 4136 /* Flow index, equivalent to hash value truncated to FST size */ 4137 uint32_t flow_id; 4138 /* Stats tracking for this flow */ 4139 struct cdp_flow_stats stats; 4140 /* Flag indicating whether flow is IPv4 address tuple */ 4141 uint8_t is_ipv4_addr_entry; 4142 /* Flag indicating whether flow is valid */ 4143 uint8_t is_valid; 4144 }; 4145 4146 struct dp_rx_fst { 4147 /* Software (DP) FST */ 4148 uint8_t *base; 4149 /* Pointer to HAL FST */ 4150 struct hal_rx_fst *hal_rx_fst; 4151 /* Base physical address of HAL RX HW FST */ 4152 uint64_t hal_rx_fst_base_paddr; 4153 /* Maximum number of flows FSE supports */ 4154 uint16_t max_entries; 4155 /* Num entries in flow table */ 4156 uint16_t num_entries; 4157 /* SKID Length */ 4158 uint16_t max_skid_length; 4159 /* Hash mask to obtain legitimate hash entry */ 4160 uint32_t hash_mask; 4161 /* Timer for bundling of flows */ 4162 qdf_timer_t cache_invalidate_timer; 4163 /** 4164 * Flag which tracks whether cache update 4165 * is needed on timer expiry 4166 */ 4167 qdf_atomic_t is_cache_update_pending; 4168 /* Flag to indicate completion of FSE setup in HW/FW */ 4169 bool fse_setup_done; 4170 }; 4171 4172 #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_rx_fse) 4173 #elif WLAN_SUPPORT_RX_FISA 4174 4175 struct dp_fisa_stats { 4176 /* flow index invalid from RX HW TLV */ 4177 uint32_t invalid_flow_index; 4178 uint32_t reo_mismatch; 4179 }; 4180 4181 enum fisa_aggr_ret { 4182 FISA_AGGR_DONE, 4183 FISA_AGGR_NOT_ELIGIBLE, 4184 FISA_FLUSH_FLOW 4185 }; 4186 4187 /** 4188 * struct fisa_pkt_hist - FISA Packet history structure 4189 * @tlv_hist: array of TLV history 4190 * @ts: array of timestamps of fisa packets 4191 * @idx: index indicating the next location to be used in the array. 4192 */ 4193 struct fisa_pkt_hist { 4194 uint8_t *tlv_hist; 4195 qdf_time_t ts_hist[FISA_FLOW_MAX_AGGR_COUNT]; 4196 uint32_t idx; 4197 }; 4198 4199 struct dp_fisa_rx_sw_ft { 4200 /* HAL Rx Flow Search Entry which matches HW definition */ 4201 void *hw_fse; 4202 /* hash value */ 4203 uint32_t flow_hash; 4204 /* toeplitz hash value*/ 4205 uint32_t flow_id_toeplitz; 4206 /* Flow index, equivalent to hash value truncated to FST size */ 4207 uint32_t flow_id; 4208 /* Stats tracking for this flow */ 4209 struct cdp_flow_stats stats; 4210 /* Flag indicating whether flow is IPv4 address tuple */ 4211 uint8_t is_ipv4_addr_entry; 4212 /* Flag indicating whether flow is valid */ 4213 uint8_t is_valid; 4214 uint8_t is_populated; 4215 uint8_t is_flow_udp; 4216 uint8_t is_flow_tcp; 4217 qdf_nbuf_t head_skb; 4218 uint16_t cumulative_l4_checksum; 4219 uint16_t adjusted_cumulative_ip_length; 4220 uint16_t cur_aggr; 4221 uint16_t napi_flush_cumulative_l4_checksum; 4222 uint16_t napi_flush_cumulative_ip_length; 4223 qdf_nbuf_t last_skb; 4224 uint32_t head_skb_ip_hdr_offset; 4225 uint32_t head_skb_l4_hdr_offset; 4226 struct cdp_rx_flow_tuple_info rx_flow_tuple_info; 4227 uint8_t napi_id; 4228 struct dp_vdev *vdev; 4229 uint64_t bytes_aggregated; 4230 uint32_t flush_count; 4231 uint32_t aggr_count; 4232 uint8_t do_not_aggregate; 4233 uint16_t hal_cumultive_ip_len; 4234 struct dp_soc *soc_hdl; 4235 /* last aggregate count fetched from RX PKT TLV */ 4236 uint32_t last_hal_aggr_count; 4237 uint32_t cur_aggr_gso_size; 4238 struct udphdr *head_skb_udp_hdr; 4239 uint16_t frags_cumulative_len; 4240 /* CMEM parameters */ 4241 uint32_t cmem_offset; 4242 uint32_t metadata; 4243 uint32_t reo_dest_indication; 4244 qdf_time_t flow_init_ts; 4245 qdf_time_t last_accessed_ts; 4246 #ifdef WLAN_SUPPORT_RX_FISA_HIST 4247 struct fisa_pkt_hist pkt_hist; 4248 #endif 4249 }; 4250 4251 #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_fisa_rx_sw_ft) 4252 #define MAX_FSE_CACHE_FL_HST 10 4253 /** 4254 * struct fse_cache_flush_history - Debug history cache flush 4255 * @timestamp: Entry update timestamp 4256 * @flows_added: Number of flows added for this flush 4257 * @flows_deleted: Number of flows deleted for this flush 4258 */ 4259 struct fse_cache_flush_history { 4260 uint64_t timestamp; 4261 uint32_t flows_added; 4262 uint32_t flows_deleted; 4263 }; 4264 4265 struct dp_rx_fst { 4266 /* Software (DP) FST */ 4267 uint8_t *base; 4268 /* Pointer to HAL FST */ 4269 struct hal_rx_fst *hal_rx_fst; 4270 /* Base physical address of HAL RX HW FST */ 4271 uint64_t hal_rx_fst_base_paddr; 4272 /* Maximum number of flows FSE supports */ 4273 uint16_t max_entries; 4274 /* Num entries in flow table */ 4275 uint16_t num_entries; 4276 /* SKID Length */ 4277 uint16_t max_skid_length; 4278 /* Hash mask to obtain legitimate hash entry */ 4279 uint32_t hash_mask; 4280 /* Lock for adding/deleting entries of FST */ 4281 qdf_spinlock_t dp_rx_fst_lock; 4282 uint32_t add_flow_count; 4283 uint32_t del_flow_count; 4284 uint32_t hash_collision_cnt; 4285 struct dp_soc *soc_hdl; 4286 qdf_atomic_t fse_cache_flush_posted; 4287 qdf_timer_t fse_cache_flush_timer; 4288 /* Allow FSE cache flush cmd to FW */ 4289 bool fse_cache_flush_allow; 4290 struct fse_cache_flush_history cache_fl_rec[MAX_FSE_CACHE_FL_HST]; 4291 /* FISA DP stats */ 4292 struct dp_fisa_stats stats; 4293 4294 /* CMEM params */ 4295 qdf_work_t fst_update_work; 4296 qdf_workqueue_t *fst_update_wq; 4297 qdf_list_t fst_update_list; 4298 uint32_t meta_counter; 4299 uint32_t cmem_ba; 4300 qdf_spinlock_t dp_rx_sw_ft_lock[MAX_REO_DEST_RINGS]; 4301 qdf_event_t cmem_resp_event; 4302 bool flow_deletion_supported; 4303 bool fst_in_cmem; 4304 bool pm_suspended; 4305 }; 4306 4307 #endif /* WLAN_SUPPORT_RX_FISA */ 4308 #endif /* WLAN_SUPPORT_RX_FLOW_TAG || WLAN_SUPPORT_RX_FISA */ 4309 4310 #ifdef WLAN_FEATURE_STATS_EXT 4311 /* 4312 * dp_req_rx_hw_stats_t: RX peer HW stats query structure 4313 * @pending_tid_query_cnt: pending tid stats count which waits for REO status 4314 * @is_query_timeout: flag to show is stats query timeout 4315 */ 4316 struct dp_req_rx_hw_stats_t { 4317 qdf_atomic_t pending_tid_stats_cnt; 4318 bool is_query_timeout; 4319 }; 4320 #endif 4321 /* soc level structure to declare arch specific ops for DP */ 4322 4323 4324 void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, uint32_t mac_id); 4325 QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, 4326 uint32_t mac_id); 4327 void dp_link_desc_ring_replenish(struct dp_soc *soc, uint32_t mac_id); 4328 4329 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 4330 void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc); 4331 #else 4332 static inline void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc) {} 4333 #endif 4334 QDF_STATUS dp_srng_alloc(struct dp_soc *soc, struct dp_srng *srng, 4335 int ring_type, uint32_t num_entries, 4336 bool cached); 4337 void dp_srng_free(struct dp_soc *soc, struct dp_srng *srng); 4338 QDF_STATUS dp_srng_init(struct dp_soc *soc, struct dp_srng *srng, 4339 int ring_type, int ring_num, int mac_id); 4340 void dp_srng_deinit(struct dp_soc *soc, struct dp_srng *srng, 4341 int ring_type, int ring_num); 4342 void dp_print_peer_txrx_stats_be(struct cdp_peer_stats *peer_stats, 4343 enum peer_stats_type stats_type); 4344 void dp_print_peer_txrx_stats_li(struct cdp_peer_stats *peer_stats, 4345 enum peer_stats_type stats_type); 4346 4347 enum timer_yield_status 4348 dp_should_timer_irq_yield(struct dp_soc *soc, uint32_t work_done, 4349 uint64_t start_time); 4350 4351 /* 4352 * dp_vdev_get_default_reo_hash() - get reo dest ring and hash values for a vdev 4353 * @vdev: Datapath VDEV handle 4354 * @reo_dest: pointer to default reo_dest ring for vdev to be populated 4355 * @hash_based: pointer to hash value (enabled/disabled) to be populated 4356 * 4357 * Return: None 4358 */ 4359 void dp_vdev_get_default_reo_hash(struct dp_vdev *vdev, 4360 enum cdp_host_reo_dest_ring *reo_dest, 4361 bool *hash_based); 4362 4363 /** 4364 * dp_reo_remap_config() - configure reo remap register value based 4365 * nss configuration. 4366 * based on offload_radio value below remap configuration 4367 * get applied. 4368 * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4) 4369 * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4) 4370 * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4) 4371 * 3 - both Radios handled by NSS (remap not required) 4372 * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3) 4373 * 4374 * @remap0: output parameter indicates reo remap 0 register value 4375 * @remap1: output parameter indicates reo remap 1 register value 4376 * @remap2: output parameter indicates reo remap 2 register value 4377 * Return: bool type, true if remap is configured else false. 4378 */ 4379 4380 bool dp_reo_remap_config(struct dp_soc *soc, uint32_t *remap0, 4381 uint32_t *remap1, uint32_t *remap2); 4382 4383 #ifdef QCA_DP_TX_HW_SW_NBUF_DESC_PREFETCH 4384 /** 4385 * dp_tx_comp_get_prefetched_params_from_hal_desc() - Get prefetched TX desc 4386 * @soc: DP soc handle 4387 * @tx_comp_hal_desc: HAL TX Comp Descriptor 4388 * @r_tx_desc: SW Tx Descriptor retrieved from HAL desc. 4389 * 4390 * Return: None 4391 */ 4392 void dp_tx_comp_get_prefetched_params_from_hal_desc( 4393 struct dp_soc *soc, 4394 void *tx_comp_hal_desc, 4395 struct dp_tx_desc_s **r_tx_desc); 4396 #endif 4397 #endif /* _DP_TYPES_H_ */ 4398