1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _DP_TYPES_H_ 21 #define _DP_TYPES_H_ 22 23 #include <qdf_types.h> 24 #include <qdf_nbuf.h> 25 #include <qdf_lock.h> 26 #include <qdf_atomic.h> 27 #include <qdf_util.h> 28 #include <qdf_list.h> 29 #include <qdf_lro.h> 30 #include <queue.h> 31 #include <htt_common.h> 32 #include <htt.h> 33 #include <htt_stats.h> 34 #include <cdp_txrx_cmn.h> 35 #ifdef DP_MOB_DEFS 36 #include <cds_ieee80211_common.h> 37 #endif 38 #include <wdi_event_api.h> /* WDI subscriber event list */ 39 40 #include "hal_hw_headers.h" 41 #include <hal_tx.h> 42 #include <hal_reo.h> 43 #include "wlan_cfg.h" 44 #include "hal_rx.h" 45 #include <hal_api.h> 46 #include <hal_api_mon.h> 47 #include "hal_rx.h" 48 //#include "hal_rx_flow.h" 49 50 #define MAX_BW 8 51 #define MAX_RETRIES 4 52 #define MAX_RECEPTION_TYPES 4 53 54 #define MINIDUMP_STR_SIZE 25 55 #ifndef REMOVE_PKT_LOG 56 #include <pktlog.h> 57 #endif 58 #include <dp_umac_reset.h> 59 60 //#include "dp_tx.h" 61 62 #define REPT_MU_MIMO 1 63 #define REPT_MU_OFDMA_MIMO 3 64 #define DP_VO_TID 6 65 /** MAX TID MAPS AVAILABLE PER PDEV */ 66 #define DP_MAX_TID_MAPS 16 67 /** pad DSCP_TID_MAP_MAX with 6 to fix oob issue */ 68 #define DSCP_TID_MAP_MAX (64 + 6) 69 #define DP_IP_DSCP_SHIFT 2 70 #define DP_IP_DSCP_MASK 0x3f 71 #define DP_FC0_SUBTYPE_QOS 0x80 72 #define DP_QOS_TID 0x0f 73 #define DP_IPV6_PRIORITY_SHIFT 20 74 #define MAX_MON_LINK_DESC_BANKS 2 75 #define DP_VDEV_ALL 0xff 76 77 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 78 #define WLAN_DP_RESET_MON_BUF_RING_FILTER 79 #define MAX_TXDESC_POOLS 6 80 #else 81 #define MAX_TXDESC_POOLS 4 82 #endif 83 84 /* Max no of descriptors to handle special frames like EAPOL */ 85 #define MAX_TX_SPL_DESC 1024 86 87 #define MAX_RXDESC_POOLS 4 88 #define MAX_PPE_TXDESC_POOLS 1 89 90 /* Max no. of VDEV per PSOC */ 91 #ifdef WLAN_PSOC_MAX_VDEVS 92 #define MAX_VDEV_CNT WLAN_PSOC_MAX_VDEVS 93 #else 94 #define MAX_VDEV_CNT 51 95 #endif 96 97 /* Max no. of VDEVs, a PDEV can support */ 98 #ifdef WLAN_PDEV_MAX_VDEVS 99 #define DP_PDEV_MAX_VDEVS WLAN_PDEV_MAX_VDEVS 100 #else 101 #define DP_PDEV_MAX_VDEVS 17 102 #endif 103 104 #define EXCEPTION_DEST_RING_ID 0 105 #define MAX_IDLE_SCATTER_BUFS 16 106 #define DP_MAX_IRQ_PER_CONTEXT 12 107 #define DEFAULT_HW_PEER_ID 0xffff 108 109 #define MAX_AST_AGEOUT_COUNT 128 110 111 #ifdef TX_ADDR_INDEX_SEARCH 112 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_INDEX_SEARCH 113 #else 114 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_SEARCH_DEFAULT 115 #endif 116 117 #define WBM_INT_ERROR_ALL 0 118 #define WBM_INT_ERROR_REO_NULL_BUFFER 1 119 #define WBM_INT_ERROR_REO_NULL_LINK_DESC 2 120 #define WBM_INT_ERROR_REO_NULL_MSDU_BUFF 3 121 #define WBM_INT_ERROR_REO_BUFF_REAPED 4 122 #define MAX_WBM_INT_ERROR_REASONS 5 123 124 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 125 /* Maximum retries for Delba per tid per peer */ 126 #define DP_MAX_DELBA_RETRY 3 127 128 #ifdef AST_OFFLOAD_ENABLE 129 #define AST_OFFLOAD_ENABLE_STATUS 1 130 #else 131 #define AST_OFFLOAD_ENABLE_STATUS 0 132 #endif 133 134 #ifdef FEATURE_MEC_OFFLOAD 135 #define FW_MEC_FW_OFFLOAD_ENABLED 1 136 #else 137 #define FW_MEC_FW_OFFLOAD_ENABLED 0 138 #endif 139 140 #define PCP_TID_MAP_MAX 8 141 #define MAX_MU_USERS 37 142 143 #define REO_CMD_EVENT_HIST_MAX 64 144 145 #define DP_MAX_SRNGS 64 146 147 /* 2G PHYB */ 148 #define PHYB_2G_LMAC_ID 2 149 #define PHYB_2G_TARGET_PDEV_ID 2 150 151 /* Flags for skippig s/w tid classification */ 152 #define DP_TX_HW_DSCP_TID_MAP_VALID 0x1 153 #define DP_TXRX_HLOS_TID_OVERRIDE_ENABLED 0x2 154 #define DP_TX_MESH_ENABLED 0x4 155 #define DP_TX_INVALID_QOS_TAG 0xf 156 157 #ifdef WLAN_SUPPORT_RX_FISA 158 #define FISA_FLOW_MAX_AGGR_COUNT 16 /* max flow aggregate count */ 159 #endif 160 161 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 162 #define DP_RX_REFILL_BUFF_POOL_SIZE 2048 163 #define DP_RX_REFILL_BUFF_POOL_BURST 64 164 #define DP_RX_REFILL_THRD_THRESHOLD 512 165 #endif 166 167 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 168 #define DP_SKIP_BAR_UPDATE_TIMEOUT 5000 169 #endif 170 171 #define DP_TX_MAGIC_PATTERN_INUSE 0xABCD1234 172 #define DP_TX_MAGIC_PATTERN_FREE 0xDEADBEEF 173 174 #ifdef IPA_OFFLOAD 175 #define DP_PEER_REO_STATS_TID_SHIFT 16 176 #define DP_PEER_REO_STATS_TID_MASK 0xFFFF0000 177 #define DP_PEER_REO_STATS_PEER_ID_MASK 0x0000FFFF 178 #define DP_PEER_GET_REO_STATS_TID(comb_peer_id_tid) \ 179 ((comb_peer_id_tid & DP_PEER_REO_STATS_TID_MASK) >> \ 180 DP_PEER_REO_STATS_TID_SHIFT) 181 #define DP_PEER_GET_REO_STATS_PEER_ID(comb_peer_id_tid) \ 182 (comb_peer_id_tid & DP_PEER_REO_STATS_PEER_ID_MASK) 183 #endif 184 185 enum rx_pktlog_mode { 186 DP_RX_PKTLOG_DISABLED = 0, 187 DP_RX_PKTLOG_FULL, 188 DP_RX_PKTLOG_LITE, 189 }; 190 191 /* enum m_copy_mode - Available mcopy mode 192 * 193 */ 194 enum m_copy_mode { 195 M_COPY_DISABLED = 0, 196 M_COPY = 2, 197 M_COPY_EXTENDED = 4, 198 }; 199 200 struct msdu_list { 201 qdf_nbuf_t head; 202 qdf_nbuf_t tail; 203 uint32_t sum_len; 204 }; 205 206 struct dp_soc_cmn; 207 struct dp_pdev; 208 struct dp_vdev; 209 struct dp_tx_desc_s; 210 struct dp_soc; 211 union dp_rx_desc_list_elem_t; 212 struct cdp_peer_rate_stats_ctx; 213 struct cdp_soc_rate_stats_ctx; 214 struct dp_rx_fst; 215 struct dp_mon_filter; 216 struct dp_mon_mpdu; 217 #ifdef BE_PKTLOG_SUPPORT 218 struct dp_mon_filter_be; 219 #endif 220 struct dp_peer; 221 struct dp_txrx_peer; 222 223 /** 224 * enum dp_peer_state - DP peer states 225 * @DP_PEER_STATE_NONE: 226 * @DP_PEER_STATE_INIT: 227 * @DP_PEER_STATE_ACTIVE: 228 * @DP_PEER_STATE_LOGICAL_DELETE: 229 * @DP_PEER_STATE_INACTIVE: 230 * @DP_PEER_STATE_FREED: 231 * @DP_PEER_STATE_INVALID: 232 */ 233 enum dp_peer_state { 234 DP_PEER_STATE_NONE, 235 DP_PEER_STATE_INIT, 236 DP_PEER_STATE_ACTIVE, 237 DP_PEER_STATE_LOGICAL_DELETE, 238 DP_PEER_STATE_INACTIVE, 239 DP_PEER_STATE_FREED, 240 DP_PEER_STATE_INVALID, 241 }; 242 243 /** 244 * enum dp_mod_id - DP module IDs 245 * @DP_MOD_ID_TX_RX: 246 * @DP_MOD_ID_TX_COMP: 247 * @DP_MOD_ID_RX: 248 * @DP_MOD_ID_HTT_COMP: 249 * @DP_MOD_ID_RX_ERR: 250 * @DP_MOD_ID_TX_PPDU_STATS: 251 * @DP_MOD_ID_RX_PPDU_STATS: 252 * @DP_MOD_ID_CDP: 253 * @DP_MOD_ID_GENERIC_STATS: 254 * @DP_MOD_ID_TX_MULTIPASS: 255 * @DP_MOD_ID_TX_CAPTURE: 256 * @DP_MOD_ID_NSS_OFFLOAD: 257 * @DP_MOD_ID_CONFIG: 258 * @DP_MOD_ID_HTT: 259 * @DP_MOD_ID_IPA: 260 * @DP_MOD_ID_AST: 261 * @DP_MOD_ID_MCAST2UCAST: 262 * @DP_MOD_ID_CHILD: 263 * @DP_MOD_ID_MESH: 264 * @DP_MOD_ID_TX_EXCEPTION: 265 * @DP_MOD_ID_TDLS: 266 * @DP_MOD_ID_MISC: 267 * @DP_MOD_ID_MSCS: 268 * @DP_MOD_ID_TX: 269 * @DP_MOD_ID_SAWF: 270 * @DP_MOD_ID_REINJECT: 271 * @DP_MOD_ID_SCS: 272 * @DP_MOD_ID_UMAC_RESET: 273 * @DP_MOD_ID_TX_MCAST: 274 * @DP_MOD_ID_DS: 275 * @DP_MOD_ID_MAX: 276 */ 277 enum dp_mod_id { 278 DP_MOD_ID_TX_RX, 279 DP_MOD_ID_TX_COMP, 280 DP_MOD_ID_RX, 281 DP_MOD_ID_HTT_COMP, 282 DP_MOD_ID_RX_ERR, 283 DP_MOD_ID_TX_PPDU_STATS, 284 DP_MOD_ID_RX_PPDU_STATS, 285 DP_MOD_ID_CDP, 286 DP_MOD_ID_GENERIC_STATS, 287 DP_MOD_ID_TX_MULTIPASS, 288 DP_MOD_ID_TX_CAPTURE, 289 DP_MOD_ID_NSS_OFFLOAD, 290 DP_MOD_ID_CONFIG, 291 DP_MOD_ID_HTT, 292 DP_MOD_ID_IPA, 293 DP_MOD_ID_AST, 294 DP_MOD_ID_MCAST2UCAST, 295 DP_MOD_ID_CHILD, 296 DP_MOD_ID_MESH, 297 DP_MOD_ID_TX_EXCEPTION, 298 DP_MOD_ID_TDLS, 299 DP_MOD_ID_MISC, 300 DP_MOD_ID_MSCS, 301 DP_MOD_ID_TX, 302 DP_MOD_ID_SAWF, 303 DP_MOD_ID_REINJECT, 304 DP_MOD_ID_SCS, 305 DP_MOD_ID_UMAC_RESET, 306 DP_MOD_ID_TX_MCAST, 307 DP_MOD_ID_DS, 308 DP_MOD_ID_MAX, 309 }; 310 311 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 312 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 313 314 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 315 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 316 317 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 318 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 319 320 #define DP_MUTEX_TYPE qdf_spinlock_t 321 322 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 323 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 324 325 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 326 ((_a)[0] == 0x33 && \ 327 (_a)[1] == 0x33) 328 329 #define DP_FRAME_IS_BROADCAST(_a) \ 330 ((_a)[0] == 0xff && \ 331 (_a)[1] == 0xff && \ 332 (_a)[2] == 0xff && \ 333 (_a)[3] == 0xff && \ 334 (_a)[4] == 0xff && \ 335 (_a)[5] == 0xff) 336 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 337 (_llc)->llc_ssap == 0xaa && \ 338 (_llc)->llc_un.type_snap.control == 0x3) 339 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 340 #define DP_FRAME_FC0_TYPE_MASK 0x0c 341 #define DP_FRAME_FC0_TYPE_DATA 0x08 342 #define DP_FRAME_IS_DATA(_frame) \ 343 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 344 345 /* 346 * macros to convert hw mac id to sw mac id: 347 * mac ids used by hardware start from a value of 1 while 348 * those in host software start from a value of 0. Use the 349 * macros below to convert between mac ids used by software and 350 * hardware 351 */ 352 #define DP_SW2HW_MACID(id) ((id) + 1) 353 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 354 355 /* 356 * Number of Tx Queues 357 * enum and macro to define how many threshold levels is used 358 * for the AC based flow control 359 */ 360 #ifdef QCA_AC_BASED_FLOW_CONTROL 361 enum dp_fl_ctrl_threshold { 362 DP_TH_BE_BK = 0, 363 DP_TH_VI, 364 DP_TH_VO, 365 DP_TH_HI, 366 }; 367 368 #define FL_TH_MAX (4) 369 #define FL_TH_VI_PERCENTAGE (80) 370 #define FL_TH_VO_PERCENTAGE (60) 371 #define FL_TH_HI_PERCENTAGE (40) 372 #endif 373 374 /** 375 * enum dp_intr_mode 376 * @DP_INTR_INTEGRATED: Line interrupts 377 * @DP_INTR_MSI: MSI interrupts 378 * @DP_INTR_POLL: Polling 379 * @DP_INTR_LEGACY_VIRTUAL_IRQ: 380 */ 381 enum dp_intr_mode { 382 DP_INTR_INTEGRATED = 0, 383 DP_INTR_MSI, 384 DP_INTR_POLL, 385 DP_INTR_LEGACY_VIRTUAL_IRQ, 386 }; 387 388 /** 389 * enum dp_tx_frm_type 390 * @dp_tx_frm_std: Regular frame, no added header fragments 391 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 392 * @dp_tx_frm_sg: SG segment 393 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 394 * @dp_tx_frm_me: Multicast to Unicast Converted frame 395 * @dp_tx_frm_raw: Raw Frame 396 * @dp_tx_frm_rmnet: 397 */ 398 enum dp_tx_frm_type { 399 dp_tx_frm_std = 0, 400 dp_tx_frm_tso, 401 dp_tx_frm_sg, 402 dp_tx_frm_audio, 403 dp_tx_frm_me, 404 dp_tx_frm_raw, 405 dp_tx_frm_rmnet, 406 }; 407 408 /** 409 * enum dp_ast_type 410 * @dp_ast_type_wds: WDS peer AST type 411 * @dp_ast_type_static: static ast entry type 412 * @dp_ast_type_mec: Multicast echo ast entry type 413 */ 414 enum dp_ast_type { 415 dp_ast_type_wds = 0, 416 dp_ast_type_static, 417 dp_ast_type_mec, 418 }; 419 420 /** 421 * enum dp_nss_cfg 422 * @dp_nss_cfg_default: No radios are offloaded 423 * @dp_nss_cfg_first_radio: First radio offloaded 424 * @dp_nss_cfg_second_radio: Second radio offloaded 425 * @dp_nss_cfg_dbdc: Dual radios offloaded 426 * @dp_nss_cfg_dbtc: Three radios offloaded 427 * @dp_nss_cfg_max: max value 428 */ 429 enum dp_nss_cfg { 430 dp_nss_cfg_default = 0x0, 431 dp_nss_cfg_first_radio = 0x1, 432 dp_nss_cfg_second_radio = 0x2, 433 dp_nss_cfg_dbdc = 0x3, 434 dp_nss_cfg_dbtc = 0x7, 435 dp_nss_cfg_max 436 }; 437 438 #ifdef WLAN_TX_PKT_CAPTURE_ENH 439 #define DP_CPU_RING_MAP_1 1 440 #endif 441 442 /** 443 * enum dp_cpu_ring_map_types - dp tx cpu ring map 444 * @DP_NSS_DEFAULT_MAP: Default mode with no NSS offloaded 445 * @DP_NSS_FIRST_RADIO_OFFLOADED_MAP: Only First Radio is offloaded 446 * @DP_NSS_SECOND_RADIO_OFFLOADED_MAP: Only second radio is offloaded 447 * @DP_NSS_DBDC_OFFLOADED_MAP: Both radios are offloaded 448 * @DP_NSS_DBTC_OFFLOADED_MAP: All three radios are offloaded 449 * @DP_SINGLE_TX_RING_MAP: to avoid out of order all cpu mapped to single ring 450 * @DP_NSS_CPU_RING_MAP_MAX: Max cpu ring map val 451 */ 452 enum dp_cpu_ring_map_types { 453 DP_NSS_DEFAULT_MAP, 454 DP_NSS_FIRST_RADIO_OFFLOADED_MAP, 455 DP_NSS_SECOND_RADIO_OFFLOADED_MAP, 456 DP_NSS_DBDC_OFFLOADED_MAP, 457 DP_NSS_DBTC_OFFLOADED_MAP, 458 #ifdef WLAN_TX_PKT_CAPTURE_ENH 459 DP_SINGLE_TX_RING_MAP, 460 #endif 461 DP_NSS_CPU_RING_MAP_MAX 462 }; 463 464 /** 465 * struct dp_rx_nbuf_frag_info - Hold vaddr and paddr for a buffer 466 * 467 * @paddr: Physical address of buffer allocated. 468 * @virt_addr: union of virtual address representations 469 * @nbuf: Allocated nbuf in case of nbuf approach. 470 * @vaddr: Virtual address of frag allocated in case of frag approach. 471 */ 472 struct dp_rx_nbuf_frag_info { 473 qdf_dma_addr_t paddr; 474 union { 475 qdf_nbuf_t nbuf; 476 qdf_frag_t vaddr; 477 } virt_addr; 478 }; 479 480 /** 481 * enum dp_ctxt_type - context type 482 * @DP_PDEV_TYPE: PDEV context 483 * @DP_RX_RING_HIST_TYPE: Datapath rx ring history 484 * @DP_RX_ERR_RING_HIST_TYPE: Datapath rx error ring history 485 * @DP_RX_REINJECT_RING_HIST_TYPE: Datapath reinject ring history 486 * @DP_TX_TCL_HIST_TYPE: 487 * @DP_TX_COMP_HIST_TYPE: 488 * @DP_FISA_RX_FT_TYPE: 489 * @DP_RX_REFILL_RING_HIST_TYPE: Datapath rx refill ring history 490 * @DP_TX_HW_DESC_HIST_TYPE: Datapath TX HW descriptor history 491 * @DP_MON_SOC_TYPE: Datapath monitor soc context 492 * @DP_MON_PDEV_TYPE: Datapath monitor pdev context 493 * @DP_MON_STATUS_BUF_HIST_TYPE: DP monitor status buffer history 494 * @DP_CFG_EVENT_HIST_TYPE: DP config events history 495 */ 496 enum dp_ctxt_type { 497 DP_PDEV_TYPE, 498 DP_RX_RING_HIST_TYPE, 499 DP_RX_ERR_RING_HIST_TYPE, 500 DP_RX_REINJECT_RING_HIST_TYPE, 501 DP_TX_TCL_HIST_TYPE, 502 DP_TX_COMP_HIST_TYPE, 503 DP_FISA_RX_FT_TYPE, 504 DP_RX_REFILL_RING_HIST_TYPE, 505 DP_TX_HW_DESC_HIST_TYPE, 506 DP_MON_SOC_TYPE, 507 DP_MON_PDEV_TYPE, 508 DP_MON_STATUS_BUF_HIST_TYPE, 509 DP_CFG_EVENT_HIST_TYPE, 510 }; 511 512 /** 513 * enum dp_desc_type - source type for multiple pages allocation 514 * @DP_TX_DESC_TYPE: DP SW TX descriptor 515 * @DP_TX_PPEDS_DESC_TYPE: DP PPE-DS Tx descriptor 516 * @DP_TX_EXT_DESC_TYPE: DP TX msdu extension descriptor 517 * @DP_TX_EXT_DESC_LINK_TYPE: DP link descriptor for msdu ext_desc 518 * @DP_TX_TSO_DESC_TYPE: DP TX TSO descriptor 519 * @DP_TX_TSO_NUM_SEG_TYPE: DP TX number of segments 520 * @DP_RX_DESC_BUF_TYPE: DP RX SW descriptor 521 * @DP_RX_DESC_STATUS_TYPE: DP RX SW descriptor for monitor status 522 * @DP_HW_LINK_DESC_TYPE: DP HW link descriptor 523 * @DP_HW_CC_SPT_PAGE_TYPE: DP pages for HW CC secondary page table 524 */ 525 enum dp_desc_type { 526 DP_TX_DESC_TYPE, 527 DP_TX_PPEDS_DESC_TYPE, 528 DP_TX_EXT_DESC_TYPE, 529 DP_TX_EXT_DESC_LINK_TYPE, 530 DP_TX_TSO_DESC_TYPE, 531 DP_TX_TSO_NUM_SEG_TYPE, 532 DP_RX_DESC_BUF_TYPE, 533 DP_RX_DESC_STATUS_TYPE, 534 DP_HW_LINK_DESC_TYPE, 535 DP_HW_CC_SPT_PAGE_TYPE, 536 }; 537 538 /** 539 * struct rx_desc_pool 540 * @pool_size: number of RX descriptor in the pool 541 * @elem_size: Element size 542 * @desc_pages: Multi page descriptors 543 * @array: pointer to array of RX descriptor 544 * @freelist: pointer to free RX descriptor link list 545 * @lock: Protection for the RX descriptor pool 546 * @owner: owner for nbuf 547 * @buf_size: Buffer size 548 * @buf_alignment: Buffer alignment 549 * @rx_mon_dest_frag_enable: Enable frag processing for mon dest buffer 550 * @desc_type: type of desc this pool serves 551 */ 552 struct rx_desc_pool { 553 uint32_t pool_size; 554 #ifdef RX_DESC_MULTI_PAGE_ALLOC 555 uint16_t elem_size; 556 struct qdf_mem_multi_page_t desc_pages; 557 #else 558 union dp_rx_desc_list_elem_t *array; 559 #endif 560 union dp_rx_desc_list_elem_t *freelist; 561 qdf_spinlock_t lock; 562 uint8_t owner; 563 uint16_t buf_size; 564 uint8_t buf_alignment; 565 bool rx_mon_dest_frag_enable; 566 enum dp_desc_type desc_type; 567 }; 568 569 /** 570 * struct dp_tx_ext_desc_elem_s 571 * @next: next extension descriptor pointer 572 * @vaddr: hlos virtual address pointer 573 * @paddr: physical address pointer for descriptor 574 * @flags: mark features for extension descriptor 575 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 576 * Tx completion of ME packet 577 * @tso_desc: Pointer to Tso desc 578 * @tso_num_desc: Pointer to tso_num_desc 579 */ 580 struct dp_tx_ext_desc_elem_s { 581 struct dp_tx_ext_desc_elem_s *next; 582 void *vaddr; 583 qdf_dma_addr_t paddr; 584 uint16_t flags; 585 struct dp_tx_me_buf_t *me_buffer; 586 struct qdf_tso_seg_elem_t *tso_desc; 587 struct qdf_tso_num_seg_elem_t *tso_num_desc; 588 }; 589 590 /* 591 * NB: intentionally not using kernel-doc comment because the kernel-doc 592 * script does not handle the qdf_dma_mem_context macro 593 * struct dp_tx_ext_desc_pool_s - Tx Extension Descriptor Pool 594 * @elem_count: Number of descriptors in the pool 595 * @elem_size: Size of each descriptor 596 * @num_free: Number of free descriptors 597 * @desc_pages: multiple page allocation information for actual descriptors 598 * @link_elem_size: size of the link descriptor in cacheable memory used for 599 * chaining the extension descriptors 600 * @desc_link_pages: multiple page allocation information for link descriptors 601 * @freelist: 602 * @lock: 603 * @memctx: 604 */ 605 struct dp_tx_ext_desc_pool_s { 606 uint16_t elem_count; 607 int elem_size; 608 uint16_t num_free; 609 struct qdf_mem_multi_page_t desc_pages; 610 int link_elem_size; 611 struct qdf_mem_multi_page_t desc_link_pages; 612 struct dp_tx_ext_desc_elem_s *freelist; 613 qdf_spinlock_t lock; 614 qdf_dma_mem_context(memctx); 615 }; 616 617 /** 618 * struct dp_tx_desc_s - Tx Descriptor 619 * @next: Next in the chain of descriptors in freelist or in the completion list 620 * @nbuf: Buffer Address 621 * @length: 622 * @magic: 623 * @timestamp_tick: 624 * @flags: Flags to track the state of descriptor and special frame handling 625 * @id: Descriptor ID 626 * @dma_addr: 627 * @vdev_id: vdev_id of vdev over which the packet was transmitted 628 * @tx_status: 629 * @peer_id: 630 * @pdev: Handle to pdev 631 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 632 * This is maintained in descriptor to allow more efficient 633 * processing in completion event processing code. 634 * This field is filled in with the htt_pkt_type enum. 635 * @buffer_src: buffer source TQM, REO, FW etc. 636 * @reserved: 637 * @frm_type: Frame Type - ToDo check if this is redundant 638 * @pkt_offset: Offset from which the actual packet data starts 639 * @pool_id: Pool ID - used when releasing the descriptor 640 * @shinfo_addr: 641 * @msdu_ext_desc: MSDU extension descriptor 642 * @timestamp: 643 * @comp: 644 */ 645 struct dp_tx_desc_s { 646 struct dp_tx_desc_s *next; 647 qdf_nbuf_t nbuf; 648 uint16_t length; 649 #ifdef DP_TX_TRACKING 650 uint32_t magic; 651 uint64_t timestamp_tick; 652 #endif 653 uint16_t flags; 654 uint32_t id; 655 qdf_dma_addr_t dma_addr; 656 uint8_t vdev_id; 657 uint8_t tx_status; 658 uint16_t peer_id; 659 struct dp_pdev *pdev; 660 uint8_t tx_encap_type:2, 661 buffer_src:3, 662 reserved:3; 663 uint8_t frm_type; 664 uint8_t pkt_offset; 665 uint8_t pool_id; 666 unsigned char *shinfo_addr; 667 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 668 qdf_ktime_t timestamp; 669 struct hal_tx_desc_comp_s comp; 670 }; 671 672 #ifdef QCA_AC_BASED_FLOW_CONTROL 673 /** 674 * enum flow_pool_status - flow pool status 675 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 676 * and network queues are unpaused 677 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 678 * and network queues are paused 679 * @FLOW_POOL_BE_BK_PAUSED: 680 * @FLOW_POOL_VI_PAUSED: 681 * @FLOW_POOL_VO_PAUSED: 682 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 683 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 684 * @FLOW_POOL_ACTIVE_UNPAUSED_REATTACH: pool is reattached but network 685 * queues are not paused 686 */ 687 enum flow_pool_status { 688 FLOW_POOL_ACTIVE_UNPAUSED = 0, 689 FLOW_POOL_ACTIVE_PAUSED = 1, 690 FLOW_POOL_BE_BK_PAUSED = 2, 691 FLOW_POOL_VI_PAUSED = 3, 692 FLOW_POOL_VO_PAUSED = 4, 693 FLOW_POOL_INVALID = 5, 694 FLOW_POOL_INACTIVE = 6, 695 FLOW_POOL_ACTIVE_UNPAUSED_REATTACH = 7, 696 }; 697 698 #else 699 /** 700 * enum flow_pool_status - flow pool status 701 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 702 * and network queues are unpaused 703 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 704 * and network queues are paused 705 * @FLOW_POOL_BE_BK_PAUSED: 706 * @FLOW_POOL_VI_PAUSED: 707 * @FLOW_POOL_VO_PAUSED: 708 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 709 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 710 */ 711 enum flow_pool_status { 712 FLOW_POOL_ACTIVE_UNPAUSED = 0, 713 FLOW_POOL_ACTIVE_PAUSED = 1, 714 FLOW_POOL_BE_BK_PAUSED = 2, 715 FLOW_POOL_VI_PAUSED = 3, 716 FLOW_POOL_VO_PAUSED = 4, 717 FLOW_POOL_INVALID = 5, 718 FLOW_POOL_INACTIVE = 6, 719 }; 720 721 #endif 722 723 /** 724 * struct dp_tx_tso_seg_pool_s 725 * @pool_size: total number of pool elements 726 * @num_free: free element count 727 * @freelist: first free element pointer 728 * @desc_pages: multiple page allocation information for actual descriptors 729 * @lock: lock for accessing the pool 730 */ 731 struct dp_tx_tso_seg_pool_s { 732 uint16_t pool_size; 733 uint16_t num_free; 734 struct qdf_tso_seg_elem_t *freelist; 735 struct qdf_mem_multi_page_t desc_pages; 736 qdf_spinlock_t lock; 737 }; 738 739 /** 740 * struct dp_tx_tso_num_seg_pool_s - TSO Num seg pool 741 * @num_seg_pool_size: total number of pool elements 742 * @num_free: free element count 743 * @freelist: first free element pointer 744 * @desc_pages: multiple page allocation information for actual descriptors 745 * @lock: lock for accessing the pool 746 */ 747 748 struct dp_tx_tso_num_seg_pool_s { 749 uint16_t num_seg_pool_size; 750 uint16_t num_free; 751 struct qdf_tso_num_seg_elem_t *freelist; 752 struct qdf_mem_multi_page_t desc_pages; 753 /*tso mutex */ 754 qdf_spinlock_t lock; 755 }; 756 757 /** 758 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 759 * @elem_size: Size of each descriptor in the pool 760 * @num_allocated: Number of used descriptors 761 * @freelist: Chain of free descriptors 762 * @desc_pages: multiple page allocation information for actual descriptors 763 * @pool_size: Total number of descriptors in the pool 764 * @flow_pool_id: 765 * @num_invalid_bin: Deleted pool with pending Tx completions. 766 * @avail_desc: 767 * @status: 768 * @flow_type: 769 * @stop_th: 770 * @start_th: 771 * @max_pause_time: 772 * @latest_pause_time: 773 * @pkt_drop_no_desc: 774 * @flow_pool_lock: 775 * @pool_create_cnt: 776 * @pool_owner_ctx: 777 * @elem_count: 778 * @num_free: Number of free descriptors 779 * @lock: Lock for descriptor allocation/free from/to the pool 780 */ 781 struct dp_tx_desc_pool_s { 782 uint16_t elem_size; 783 uint32_t num_allocated; 784 struct dp_tx_desc_s *freelist; 785 struct qdf_mem_multi_page_t desc_pages; 786 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 787 uint16_t pool_size; 788 uint8_t flow_pool_id; 789 uint8_t num_invalid_bin; 790 uint16_t avail_desc; 791 enum flow_pool_status status; 792 enum htt_flow_type flow_type; 793 #ifdef QCA_AC_BASED_FLOW_CONTROL 794 uint16_t stop_th[FL_TH_MAX]; 795 uint16_t start_th[FL_TH_MAX]; 796 qdf_time_t max_pause_time[FL_TH_MAX]; 797 qdf_time_t latest_pause_time[FL_TH_MAX]; 798 #else 799 uint16_t stop_th; 800 uint16_t start_th; 801 #endif 802 uint16_t pkt_drop_no_desc; 803 qdf_spinlock_t flow_pool_lock; 804 uint8_t pool_create_cnt; 805 void *pool_owner_ctx; 806 #else 807 uint16_t elem_count; 808 uint32_t num_free; 809 qdf_spinlock_t lock; 810 #endif 811 }; 812 813 /** 814 * struct dp_txrx_pool_stats - flow pool related statistics 815 * @pool_map_count: flow pool map received 816 * @pool_unmap_count: flow pool unmap received 817 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 818 */ 819 struct dp_txrx_pool_stats { 820 uint16_t pool_map_count; 821 uint16_t pool_unmap_count; 822 uint16_t pkt_drop_no_pool; 823 }; 824 825 /** 826 * struct dp_srng - DP srng structure 827 * @hal_srng: hal_srng handle 828 * @base_vaddr_unaligned: un-aligned virtual base address of the srng ring 829 * @base_vaddr_aligned: aligned virtual base address of the srng ring 830 * @base_paddr_unaligned: un-aligned physical base address of the srng ring 831 * @base_paddr_aligned: aligned physical base address of the srng ring 832 * @alloc_size: size of the srng ring 833 * @cached: is the srng ring memory cached or un-cached memory 834 * @irq: irq number of the srng ring 835 * @num_entries: number of entries in the srng ring 836 * @is_mem_prealloc: Is this srng memory pre-allocated 837 * @crit_thresh: Critical threshold for near-full processing of this srng 838 * @safe_thresh: Safe threshold for near-full processing of this srng 839 * @near_full: Flag to indicate srng is near-full 840 */ 841 struct dp_srng { 842 hal_ring_handle_t hal_srng; 843 void *base_vaddr_unaligned; 844 void *base_vaddr_aligned; 845 qdf_dma_addr_t base_paddr_unaligned; 846 qdf_dma_addr_t base_paddr_aligned; 847 uint32_t alloc_size; 848 uint8_t cached; 849 int irq; 850 uint32_t num_entries; 851 #ifdef DP_MEM_PRE_ALLOC 852 uint8_t is_mem_prealloc; 853 #endif 854 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 855 uint16_t crit_thresh; 856 uint16_t safe_thresh; 857 qdf_atomic_t near_full; 858 #endif 859 }; 860 861 struct dp_rx_reorder_array_elem { 862 qdf_nbuf_t head; 863 qdf_nbuf_t tail; 864 }; 865 866 #define DP_RX_BA_INACTIVE 0 867 #define DP_RX_BA_ACTIVE 1 868 #define DP_RX_BA_IN_PROGRESS 2 869 struct dp_reo_cmd_info { 870 uint16_t cmd; 871 enum hal_reo_cmd_type cmd_type; 872 void *data; 873 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 874 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 875 }; 876 877 struct dp_peer_delay_stats { 878 struct cdp_delay_tid_stats delay_tid_stats[CDP_MAX_DATA_TIDS] 879 [CDP_MAX_TXRX_CTX]; 880 }; 881 882 /* Rx TID defrag*/ 883 struct dp_rx_tid_defrag { 884 /* TID */ 885 int tid; 886 887 /* only used for defrag right now */ 888 TAILQ_ENTRY(dp_rx_tid_defrag) defrag_waitlist_elem; 889 890 /* Store dst desc for reinjection */ 891 hal_ring_desc_t dst_ring_desc; 892 struct dp_rx_desc *head_frag_desc; 893 894 /* Sequence and fragments that are being processed currently */ 895 uint32_t curr_seq_num; 896 uint32_t curr_frag_num; 897 898 /* TODO: Check the following while adding defragmentation support */ 899 struct dp_rx_reorder_array_elem *array; 900 /* base - single rx reorder element used for non-aggr cases */ 901 struct dp_rx_reorder_array_elem base; 902 /* rx_tid lock */ 903 qdf_spinlock_t defrag_tid_lock; 904 905 /* head PN number */ 906 uint64_t pn128[2]; 907 908 uint32_t defrag_timeout_ms; 909 910 /* defrag usage only, dp_peer pointer related with this tid */ 911 struct dp_txrx_peer *defrag_peer; 912 }; 913 914 /* Rx TID */ 915 struct dp_rx_tid { 916 /* TID */ 917 int tid; 918 919 /* Num of addba requests */ 920 uint32_t num_of_addba_req; 921 922 /* Num of addba responses */ 923 uint32_t num_of_addba_resp; 924 925 /* Num of delba requests */ 926 uint32_t num_of_delba_req; 927 928 /* Num of addba responses successful */ 929 uint32_t num_addba_rsp_success; 930 931 /* Num of addba responses failed */ 932 uint32_t num_addba_rsp_failed; 933 934 /* pn size */ 935 uint8_t pn_size; 936 /* REO TID queue descriptors */ 937 void *hw_qdesc_vaddr_unaligned; 938 void *hw_qdesc_vaddr_aligned; 939 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 940 qdf_dma_addr_t hw_qdesc_paddr; 941 uint32_t hw_qdesc_alloc_size; 942 943 /* RX ADDBA session state */ 944 int ba_status; 945 946 /* RX BA window size */ 947 uint16_t ba_win_size; 948 949 /* Starting sequence number in Addba request */ 950 uint16_t startseqnum; 951 uint16_t dialogtoken; 952 uint16_t statuscode; 953 /* user defined ADDBA response status code */ 954 uint16_t userstatuscode; 955 956 /* rx_tid lock */ 957 qdf_spinlock_t tid_lock; 958 959 /* Store ppdu_id when 2k exception is received */ 960 uint32_t ppdu_id_2k; 961 962 /* Delba Tx completion status */ 963 uint8_t delba_tx_status; 964 965 /* Delba Tx retry count */ 966 uint8_t delba_tx_retry; 967 968 /* Delba stats */ 969 uint32_t delba_tx_success_cnt; 970 uint32_t delba_tx_fail_cnt; 971 972 /* Delba reason code for retries */ 973 uint8_t delba_rcode; 974 975 /* Coex Override preserved windows size 1 based */ 976 uint16_t rx_ba_win_size_override; 977 #ifdef IPA_OFFLOAD 978 /* rx msdu count per tid */ 979 struct cdp_pkt_info rx_msdu_cnt; 980 #endif 981 982 }; 983 984 /** 985 * struct dp_intr_stats - DP Interrupt Stats for an interrupt context 986 * @num_tx_ring_masks: interrupts with tx_ring_mask set 987 * @num_rx_ring_masks: interrupts with rx_ring_mask set 988 * @num_rx_mon_ring_masks: interrupts with rx_mon_ring_mask set 989 * @num_rx_err_ring_masks: interrupts with rx_err_ring_mask set 990 * @num_rx_wbm_rel_ring_masks: interrupts with rx_wbm_rel_ring_mask set 991 * @num_reo_status_ring_masks: interrupts with reo_status_ring_mask set 992 * @num_rxdma2host_ring_masks: interrupts with rxdma2host_ring_mask set 993 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 994 * @num_host2rxdma_mon_ring_masks: interrupts with host2rxdma_ring_mask set 995 * @num_rx_ring_near_full_masks: Near-full interrupts for REO DST ring 996 * @num_tx_comp_ring_near_full_masks: Near-full interrupts for TX completion 997 * @num_rx_wbm_rel_ring_near_full_masks: total number of times the wbm rel ring 998 * near full interrupt was received 999 * @num_reo_status_ring_near_full_masks: total number of times the reo status 1000 * near full interrupt was received 1001 * @num_near_full_masks: total number of times the near full interrupt 1002 * was received 1003 * @num_masks: total number of times the interrupt was received 1004 * @num_host2txmon_ring__masks: interrupts with host2txmon_ring_mask set 1005 * @num_near_full_masks: total number of times the interrupt was received 1006 * @num_masks: total number of times the near full interrupt was received 1007 * @num_tx_mon_ring_masks: interrupts with num_tx_mon_ring_masks set 1008 * 1009 * Counter for individual masks are incremented only if there are any packets 1010 * on that ring. 1011 */ 1012 struct dp_intr_stats { 1013 uint32_t num_tx_ring_masks[MAX_TCL_DATA_RINGS]; 1014 uint32_t num_rx_ring_masks[MAX_REO_DEST_RINGS]; 1015 uint32_t num_rx_mon_ring_masks; 1016 uint32_t num_rx_err_ring_masks; 1017 uint32_t num_rx_wbm_rel_ring_masks; 1018 uint32_t num_reo_status_ring_masks; 1019 uint32_t num_rxdma2host_ring_masks; 1020 uint32_t num_host2rxdma_ring_masks; 1021 uint32_t num_host2rxdma_mon_ring_masks; 1022 uint32_t num_rx_ring_near_full_masks[MAX_REO_DEST_RINGS]; 1023 uint32_t num_tx_comp_ring_near_full_masks[MAX_TCL_DATA_RINGS]; 1024 uint32_t num_rx_wbm_rel_ring_near_full_masks; 1025 uint32_t num_reo_status_ring_near_full_masks; 1026 uint32_t num_host2txmon_ring__masks; 1027 uint32_t num_near_full_masks; 1028 uint32_t num_masks; 1029 uint32_t num_tx_mon_ring_masks; 1030 }; 1031 1032 #ifdef DP_UMAC_HW_RESET_SUPPORT 1033 /** 1034 * struct dp_intr_bkp - DP per interrupt context ring masks old state 1035 * @tx_ring_mask: WBM Tx completion rings (0-2) associated with this napi ctxt 1036 * @rx_ring_mask: Rx REO rings (0-3) associated with this interrupt context 1037 * @rx_mon_ring_mask: Rx monitor ring mask (0-2) 1038 * @rx_err_ring_mask: REO Exception Ring 1039 * @rx_wbm_rel_ring_mask: WBM2SW Rx Release Ring 1040 * @reo_status_ring_mask: REO command response ring 1041 * @rxdma2host_ring_mask: RXDMA to host destination ring 1042 * @host2rxdma_ring_mask: Host to RXDMA buffer ring 1043 * @host2rxdma_mon_ring_mask: Host to RXDMA monitor buffer ring 1044 * @host2txmon_ring_mask: Tx monitor buffer ring 1045 * @tx_mon_ring_mask: Tx monitor ring mask (0-2) 1046 * 1047 */ 1048 struct dp_intr_bkp { 1049 uint8_t tx_ring_mask; 1050 uint8_t rx_ring_mask; 1051 uint8_t rx_mon_ring_mask; 1052 uint8_t rx_err_ring_mask; 1053 uint8_t rx_wbm_rel_ring_mask; 1054 uint8_t reo_status_ring_mask; 1055 uint8_t rxdma2host_ring_mask; 1056 uint8_t host2rxdma_ring_mask; 1057 uint8_t host2rxdma_mon_ring_mask; 1058 uint8_t host2txmon_ring_mask; 1059 uint8_t tx_mon_ring_mask; 1060 }; 1061 #endif 1062 1063 /* per interrupt context */ 1064 struct dp_intr { 1065 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 1066 associated with this napi context */ 1067 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 1068 with this interrupt context */ 1069 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 1070 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 1071 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 1072 uint8_t reo_status_ring_mask; /* REO command response ring */ 1073 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 1074 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 1075 /* Host to RXDMA monitor buffer ring */ 1076 uint8_t host2rxdma_mon_ring_mask; 1077 /* RX REO rings near full interrupt mask */ 1078 uint8_t rx_near_full_grp_1_mask; 1079 /* RX REO rings near full interrupt mask */ 1080 uint8_t rx_near_full_grp_2_mask; 1081 /* WBM TX completion rings near full interrupt mask */ 1082 uint8_t tx_ring_near_full_mask; 1083 uint8_t host2txmon_ring_mask; /* Tx monitor buffer ring */ 1084 uint8_t tx_mon_ring_mask; /* Tx monitor ring mask (0-2) */ 1085 struct dp_soc *soc; /* Reference to SoC structure , 1086 to get DMA ring handles */ 1087 qdf_lro_ctx_t lro_ctx; 1088 uint8_t dp_intr_id; 1089 1090 /* Interrupt Stats for individual masks */ 1091 struct dp_intr_stats intr_stats; 1092 uint8_t umac_reset_intr_mask; /* UMAC reset interrupt mask */ 1093 }; 1094 1095 #define REO_DESC_FREELIST_SIZE 64 1096 #define REO_DESC_FREE_DEFER_MS 1000 1097 struct reo_desc_list_node { 1098 qdf_list_node_t node; 1099 unsigned long free_ts; 1100 struct dp_rx_tid rx_tid; 1101 bool resend_update_reo_cmd; 1102 uint32_t pending_ext_desc_size; 1103 #ifdef REO_QDESC_HISTORY 1104 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1105 #endif 1106 }; 1107 1108 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 1109 #define REO_DESC_DEFERRED_FREELIST_SIZE 256 1110 #define REO_DESC_DEFERRED_FREE_MS 30000 1111 1112 struct reo_desc_deferred_freelist_node { 1113 qdf_list_node_t node; 1114 unsigned long free_ts; 1115 void *hw_qdesc_vaddr_unaligned; 1116 qdf_dma_addr_t hw_qdesc_paddr; 1117 uint32_t hw_qdesc_alloc_size; 1118 #ifdef REO_QDESC_HISTORY 1119 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1120 #endif /* REO_QDESC_HISTORY */ 1121 }; 1122 #endif /* WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY */ 1123 1124 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1125 /** 1126 * struct reo_cmd_event_record: Elements to record for each reo command 1127 * @cmd_type: reo command type 1128 * @cmd_return_status: reo command post status 1129 * @timestamp: record timestamp for the reo command 1130 */ 1131 struct reo_cmd_event_record { 1132 enum hal_reo_cmd_type cmd_type; 1133 uint8_t cmd_return_status; 1134 uint64_t timestamp; 1135 }; 1136 1137 /** 1138 * struct reo_cmd_event_history: Account for reo cmd events 1139 * @index: record number 1140 * @cmd_record: list of records 1141 */ 1142 struct reo_cmd_event_history { 1143 qdf_atomic_t index; 1144 struct reo_cmd_event_record cmd_record[REO_CMD_EVENT_HIST_MAX]; 1145 }; 1146 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1147 1148 /* SoC level data path statistics */ 1149 struct dp_soc_stats { 1150 struct { 1151 uint32_t added; 1152 uint32_t deleted; 1153 uint32_t aged_out; 1154 uint32_t map_err; 1155 uint32_t ast_mismatch; 1156 } ast; 1157 1158 struct { 1159 uint32_t added; 1160 uint32_t deleted; 1161 } mec; 1162 1163 /* SOC level TX stats */ 1164 struct { 1165 /* Total packets transmitted */ 1166 struct cdp_pkt_info egress[MAX_TCL_DATA_RINGS]; 1167 /* Enqueues per tcl ring */ 1168 uint32_t tcl_enq[MAX_TCL_DATA_RINGS]; 1169 /* packets dropped on tx because of no peer */ 1170 struct cdp_pkt_info tx_invalid_peer; 1171 /* descriptors in each tcl ring */ 1172 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 1173 /* Descriptors in use at soc */ 1174 uint32_t desc_in_use; 1175 /* tqm_release_reason == FW removed */ 1176 uint32_t dropped_fw_removed; 1177 /* tx completion release_src != TQM or FW */ 1178 uint32_t invalid_release_source; 1179 /* TX descriptor from completion ring Desc is not valid */ 1180 uint32_t invalid_tx_comp_desc; 1181 /* tx completion wbm_internal_error */ 1182 uint32_t wbm_internal_error[MAX_WBM_INT_ERROR_REASONS]; 1183 /* tx completion non_wbm_internal_error */ 1184 uint32_t non_wbm_internal_err; 1185 /* TX Comp loop packet limit hit */ 1186 uint32_t tx_comp_loop_pkt_limit_hit; 1187 /* Head pointer Out of sync at the end of dp_tx_comp_handler */ 1188 uint32_t hp_oos2; 1189 /* tx desc freed as part of vdev detach */ 1190 uint32_t tx_comp_exception; 1191 /* TQM drops after/during peer delete */ 1192 uint64_t tqm_drop_no_peer; 1193 /* Number of tx completions reaped per WBM2SW release ring */ 1194 uint32_t tx_comp[MAX_TCL_DATA_RINGS]; 1195 /* Number of tx completions force freed */ 1196 uint32_t tx_comp_force_freed; 1197 /* Tx completion ring near full */ 1198 uint32_t near_full; 1199 } tx; 1200 1201 /* SOC level RX stats */ 1202 struct { 1203 /* Total rx packets count */ 1204 struct cdp_pkt_info ingress; 1205 /* Rx errors */ 1206 /* Total Packets in Rx Error ring */ 1207 uint32_t err_ring_pkts; 1208 /* No of Fragments */ 1209 uint32_t rx_frags; 1210 /* No of incomplete fragments in waitlist */ 1211 uint32_t rx_frag_wait; 1212 /* Fragments dropped due to errors */ 1213 uint32_t rx_frag_err; 1214 /* Fragments received OOR causing sequence num mismatch */ 1215 uint32_t rx_frag_oor; 1216 /* Fragments dropped due to len errors in skb */ 1217 uint32_t rx_frag_err_len_error; 1218 /* Fragments dropped due to no peer found */ 1219 uint32_t rx_frag_err_no_peer; 1220 /* No of reinjected packets */ 1221 uint32_t reo_reinject; 1222 /* Reap loop packet limit hit */ 1223 uint32_t reap_loop_pkt_limit_hit; 1224 /* Head pointer Out of sync at the end of dp_rx_process */ 1225 uint32_t hp_oos2; 1226 /* Rx ring near full */ 1227 uint32_t near_full; 1228 /* Break ring reaping as not all scattered msdu received */ 1229 uint32_t msdu_scatter_wait_break; 1230 /* Number of bar frames received */ 1231 uint32_t bar_frame; 1232 /* Number of frames routed from rxdma */ 1233 uint32_t rxdma2rel_route_drop; 1234 /* Number of frames routed from reo*/ 1235 uint32_t reo2rel_route_drop; 1236 uint64_t fast_recycled; 1237 /* Number of hw stats requested */ 1238 uint32_t rx_hw_stats_requested; 1239 /* Number of hw stats request timeout */ 1240 uint32_t rx_hw_stats_timeout; 1241 1242 struct { 1243 /* Invalid RBM error count */ 1244 uint32_t invalid_rbm; 1245 /* Invalid VDEV Error count */ 1246 uint32_t invalid_vdev; 1247 /* Invalid PDEV error count */ 1248 uint32_t invalid_pdev; 1249 1250 /* Packets delivered to stack that no related peer */ 1251 uint32_t pkt_delivered_no_peer; 1252 /* Defrag peer uninit error count */ 1253 uint32_t defrag_peer_uninit; 1254 /* Invalid sa_idx or da_idx*/ 1255 uint32_t invalid_sa_da_idx; 1256 /* MSDU DONE failures */ 1257 uint32_t msdu_done_fail; 1258 /* Invalid PEER Error count */ 1259 struct cdp_pkt_info rx_invalid_peer; 1260 /* Invalid PEER ID count */ 1261 struct cdp_pkt_info rx_invalid_peer_id; 1262 /* Invalid packet length */ 1263 struct cdp_pkt_info rx_invalid_pkt_len; 1264 /* HAL ring access Fail error count */ 1265 uint32_t hal_ring_access_fail; 1266 /* HAL ring access full Fail error count */ 1267 uint32_t hal_ring_access_full_fail; 1268 /* RX DMA error count */ 1269 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 1270 /* RX REO DEST Desc Invalid Magic count */ 1271 uint32_t rx_desc_invalid_magic; 1272 /* REO Error count */ 1273 uint32_t reo_error[HAL_REO_ERR_MAX]; 1274 /* HAL REO ERR Count */ 1275 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 1276 /* HAL REO DEST Duplicate count */ 1277 uint32_t hal_reo_dest_dup; 1278 /* HAL WBM RELEASE Duplicate count */ 1279 uint32_t hal_wbm_rel_dup; 1280 /* HAL RXDMA error Duplicate count */ 1281 uint32_t hal_rxdma_err_dup; 1282 /* ipa smmu map duplicate count */ 1283 uint32_t ipa_smmu_map_dup; 1284 /* ipa smmu unmap duplicate count */ 1285 uint32_t ipa_smmu_unmap_dup; 1286 /* ipa smmu unmap while ipa pipes is disabled */ 1287 uint32_t ipa_unmap_no_pipe; 1288 /* REO cmd send fail/requeue count */ 1289 uint32_t reo_cmd_send_fail; 1290 /* REO cmd send drain count */ 1291 uint32_t reo_cmd_send_drain; 1292 /* RX msdu drop count due to scatter */ 1293 uint32_t scatter_msdu; 1294 /* RX msdu drop count due to invalid cookie */ 1295 uint32_t invalid_cookie; 1296 /* Count of stale cookie read in RX path */ 1297 uint32_t stale_cookie; 1298 /* Delba sent count due to RX 2k jump */ 1299 uint32_t rx_2k_jump_delba_sent; 1300 /* RX 2k jump msdu indicated to stack count */ 1301 uint32_t rx_2k_jump_to_stack; 1302 /* RX 2k jump msdu dropped count */ 1303 uint32_t rx_2k_jump_drop; 1304 /* REO ERR msdu buffer received */ 1305 uint32_t reo_err_msdu_buf_rcved; 1306 /* REO ERR msdu buffer with invalid coookie received */ 1307 uint32_t reo_err_msdu_buf_invalid_cookie; 1308 /* REO OOR msdu drop count */ 1309 uint32_t reo_err_oor_drop; 1310 /* REO OOR msdu indicated to stack count */ 1311 uint32_t reo_err_oor_to_stack; 1312 /* REO OOR scattered msdu count */ 1313 uint32_t reo_err_oor_sg_count; 1314 /* REO ERR RAW mpdu drops */ 1315 uint32_t reo_err_raw_mpdu_drop; 1316 /* RX msdu rejected count on delivery to vdev stack_fn*/ 1317 uint32_t rejected; 1318 /* Incorrect msdu count in MPDU desc info */ 1319 uint32_t msdu_count_mismatch; 1320 /* RX raw frame dropped count */ 1321 uint32_t raw_frm_drop; 1322 /* Stale link desc cookie count*/ 1323 uint32_t invalid_link_cookie; 1324 /* Nbuf sanity failure */ 1325 uint32_t nbuf_sanity_fail; 1326 /* Duplicate link desc refilled */ 1327 uint32_t dup_refill_link_desc; 1328 /* Incorrect msdu continuation bit in MSDU desc */ 1329 uint32_t msdu_continuation_err; 1330 /* count of start sequence (ssn) updates */ 1331 uint32_t ssn_update_count; 1332 /* count of bar handling fail */ 1333 uint32_t bar_handle_fail_count; 1334 /* EAPOL drop count in intrabss scenario */ 1335 uint32_t intrabss_eapol_drop; 1336 /* PN check failed for 2K-jump or OOR error */ 1337 uint32_t pn_in_dest_check_fail; 1338 /* MSDU len err count */ 1339 uint32_t msdu_len_err; 1340 /* Rx flush count */ 1341 uint32_t rx_flush_count; 1342 /* Rx invalid tid count */ 1343 uint32_t rx_invalid_tid_err; 1344 /* Invalid address1 in defrag path*/ 1345 uint32_t defrag_ad1_invalid; 1346 } err; 1347 1348 /* packet count per core - per ring */ 1349 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 1350 } rx; 1351 1352 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1353 struct reo_cmd_event_history cmd_event_history; 1354 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1355 }; 1356 1357 union dp_align_mac_addr { 1358 uint8_t raw[QDF_MAC_ADDR_SIZE]; 1359 struct { 1360 uint16_t bytes_ab; 1361 uint16_t bytes_cd; 1362 uint16_t bytes_ef; 1363 } align2; 1364 struct { 1365 uint32_t bytes_abcd; 1366 uint16_t bytes_ef; 1367 } align4; 1368 struct __attribute__((__packed__)) { 1369 uint16_t bytes_ab; 1370 uint32_t bytes_cdef; 1371 } align4_2; 1372 }; 1373 1374 /** 1375 * struct dp_ast_free_cb_params - HMWDS free callback cookie 1376 * @mac_addr: ast mac address 1377 * @peer_mac_addr: mac address of peer 1378 * @type: ast entry type 1379 * @vdev_id: vdev_id 1380 * @flags: ast flags 1381 */ 1382 struct dp_ast_free_cb_params { 1383 union dp_align_mac_addr mac_addr; 1384 union dp_align_mac_addr peer_mac_addr; 1385 enum cdp_txrx_ast_entry_type type; 1386 uint8_t vdev_id; 1387 uint32_t flags; 1388 }; 1389 1390 /** 1391 * struct dp_ast_entry - AST entry 1392 * 1393 * @ast_idx: Hardware AST Index 1394 * @peer_id: Next Hop peer_id (for non-WDS nodes, this will be point to 1395 * associated peer with this MAC address) 1396 * @mac_addr: MAC Address for this AST entry 1397 * @next_hop: Set to 1 if this is for a WDS node 1398 * @is_active: flag to indicate active data traffic on this node 1399 * (used for aging out/expiry) 1400 * @ase_list_elem: node in peer AST list 1401 * @is_bss: flag to indicate if entry corresponds to bss peer 1402 * @is_mapped: flag to indicate that we have mapped the AST entry 1403 * in ast_table 1404 * @pdev_id: pdev ID 1405 * @vdev_id: vdev ID 1406 * @ast_hash_value: hast value in HW 1407 * @ref_cnt: reference count 1408 * @type: flag to indicate type of the entry(static/WDS/MEC) 1409 * @delete_in_progress: Flag to indicate that delete commands send to FW 1410 * and host is waiting for response from FW 1411 * @callback: ast free/unmap callback 1412 * @cookie: argument to callback 1413 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 1414 */ 1415 struct dp_ast_entry { 1416 uint16_t ast_idx; 1417 uint16_t peer_id; 1418 union dp_align_mac_addr mac_addr; 1419 bool next_hop; 1420 bool is_active; 1421 bool is_mapped; 1422 uint8_t pdev_id; 1423 uint8_t vdev_id; 1424 uint16_t ast_hash_value; 1425 qdf_atomic_t ref_cnt; 1426 enum cdp_txrx_ast_entry_type type; 1427 bool delete_in_progress; 1428 txrx_ast_free_cb callback; 1429 void *cookie; 1430 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 1431 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 1432 }; 1433 1434 /** 1435 * struct dp_mec_entry - MEC entry 1436 * 1437 * @mac_addr: MAC Address for this MEC entry 1438 * @is_active: flag to indicate active data traffic on this node 1439 * (used for aging out/expiry) 1440 * @pdev_id: pdev ID 1441 * @vdev_id: vdev ID 1442 * @hash_list_elem: node in soc MEC hash list (mac address used as hash) 1443 */ 1444 struct dp_mec_entry { 1445 union dp_align_mac_addr mac_addr; 1446 bool is_active; 1447 uint8_t pdev_id; 1448 uint8_t vdev_id; 1449 1450 TAILQ_ENTRY(dp_mec_entry) hash_list_elem; 1451 }; 1452 1453 /* SOC level htt stats */ 1454 struct htt_t2h_stats { 1455 /* lock to protect htt_stats_msg update */ 1456 qdf_spinlock_t lock; 1457 1458 /* work queue to process htt stats */ 1459 qdf_work_t work; 1460 1461 /* T2H Ext stats message queue */ 1462 qdf_nbuf_queue_t msg; 1463 1464 /* number of completed stats in htt_stats_msg */ 1465 uint32_t num_stats; 1466 }; 1467 1468 struct link_desc_bank { 1469 void *base_vaddr_unaligned; 1470 void *base_vaddr; 1471 qdf_dma_addr_t base_paddr_unaligned; 1472 qdf_dma_addr_t base_paddr; 1473 uint32_t size; 1474 }; 1475 1476 struct rx_buff_pool { 1477 qdf_nbuf_queue_head_t emerg_nbuf_q; 1478 uint32_t nbuf_fail_cnt; 1479 bool is_initialized; 1480 }; 1481 1482 struct rx_refill_buff_pool { 1483 bool is_initialized; 1484 uint16_t head; 1485 uint16_t tail; 1486 struct dp_pdev *dp_pdev; 1487 uint16_t max_bufq_len; 1488 qdf_nbuf_t buf_elem[2048]; 1489 }; 1490 1491 #ifdef DP_TX_HW_DESC_HISTORY 1492 #define DP_TX_HW_DESC_HIST_MAX 6144 1493 #define DP_TX_HW_DESC_HIST_PER_SLOT_MAX 2048 1494 #define DP_TX_HW_DESC_HIST_MAX_SLOTS 3 1495 #define DP_TX_HW_DESC_HIST_SLOT_SHIFT 11 1496 1497 struct dp_tx_hw_desc_evt { 1498 uint8_t tcl_desc[HAL_TX_DESC_LEN_BYTES]; 1499 uint8_t tcl_ring_id; 1500 uint64_t posted; 1501 uint32_t hp; 1502 uint32_t tp; 1503 }; 1504 1505 /* struct dp_tx_hw_desc_history - TX HW desc hisotry 1506 * @index: Index where the last entry is written 1507 * @entry: history entries 1508 */ 1509 struct dp_tx_hw_desc_history { 1510 qdf_atomic_t index; 1511 uint16_t num_entries_per_slot; 1512 uint16_t allocated; 1513 struct dp_tx_hw_desc_evt *entry[DP_TX_HW_DESC_HIST_MAX_SLOTS]; 1514 }; 1515 #endif 1516 1517 /** 1518 * enum dp_mon_status_process_event - Events for monitor status buffer record 1519 * @DP_MON_STATUS_BUF_REAP: Monitor status buffer is reaped from ring 1520 * @DP_MON_STATUS_BUF_ENQUEUE: Status buffer is enqueued to local queue 1521 * @DP_MON_STATUS_BUF_DEQUEUE: Status buffer is dequeued from local queue 1522 */ 1523 enum dp_mon_status_process_event { 1524 DP_MON_STATUS_BUF_REAP, 1525 DP_MON_STATUS_BUF_ENQUEUE, 1526 DP_MON_STATUS_BUF_DEQUEUE, 1527 }; 1528 1529 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 1530 #define DP_MON_STATUS_HIST_MAX 2048 1531 1532 /** 1533 * struct dp_mon_stat_info_record - monitor stat ring buffer info 1534 * @hbi: HW ring buffer info 1535 * @timestamp: timestamp when this entry was recorded 1536 * @event: event 1537 * @rx_desc: RX descriptor corresponding to the received buffer 1538 * @nbuf: buffer attached to rx_desc, if event is REAP, else the buffer 1539 * which was enqueued or dequeued. 1540 * @rx_desc_nbuf_data: nbuf data pointer. 1541 */ 1542 struct dp_mon_stat_info_record { 1543 struct hal_buf_info hbi; 1544 uint64_t timestamp; 1545 enum dp_mon_status_process_event event; 1546 void *rx_desc; 1547 qdf_nbuf_t nbuf; 1548 uint8_t *rx_desc_nbuf_data; 1549 }; 1550 1551 /* struct dp_rx_history - rx ring hisotry 1552 * @index: Index where the last entry is written 1553 * @entry: history entries 1554 */ 1555 struct dp_mon_status_ring_history { 1556 qdf_atomic_t index; 1557 struct dp_mon_stat_info_record entry[DP_MON_STATUS_HIST_MAX]; 1558 }; 1559 #endif 1560 1561 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 1562 /* 1563 * The logic for get current index of these history is dependent on this 1564 * value being power of 2. 1565 */ 1566 #define DP_RX_HIST_MAX 2048 1567 #define DP_RX_ERR_HIST_MAX 2048 1568 #define DP_RX_REINJECT_HIST_MAX 1024 1569 #define DP_RX_REFILL_HIST_MAX 2048 1570 1571 QDF_COMPILE_TIME_ASSERT(rx_history_size, 1572 (DP_RX_HIST_MAX & 1573 (DP_RX_HIST_MAX - 1)) == 0); 1574 QDF_COMPILE_TIME_ASSERT(rx_err_history_size, 1575 (DP_RX_ERR_HIST_MAX & 1576 (DP_RX_ERR_HIST_MAX - 1)) == 0); 1577 QDF_COMPILE_TIME_ASSERT(rx_reinject_history_size, 1578 (DP_RX_REINJECT_HIST_MAX & 1579 (DP_RX_REINJECT_HIST_MAX - 1)) == 0); 1580 QDF_COMPILE_TIME_ASSERT(rx_refill_history_size, 1581 (DP_RX_REFILL_HIST_MAX & 1582 (DP_RX_REFILL_HIST_MAX - 1)) == 0); 1583 1584 1585 /** 1586 * struct dp_buf_info_record - ring buffer info 1587 * @hbi: HW ring buffer info 1588 * @timestamp: timestamp when this entry was recorded 1589 */ 1590 struct dp_buf_info_record { 1591 struct hal_buf_info hbi; 1592 uint64_t timestamp; 1593 }; 1594 1595 /** 1596 * struct dp_refill_info_record - ring refill buffer info 1597 * @hp: HP value after refill 1598 * @tp: cached tail value during refill 1599 * @num_req: number of buffers requested to refill 1600 * @num_refill: number of buffers refilled to ring 1601 * @timestamp: timestamp when this entry was recorded 1602 */ 1603 struct dp_refill_info_record { 1604 uint32_t hp; 1605 uint32_t tp; 1606 uint32_t num_req; 1607 uint32_t num_refill; 1608 uint64_t timestamp; 1609 }; 1610 1611 /** 1612 * struct dp_rx_history - rx ring hisotry 1613 * @index: Index where the last entry is written 1614 * @entry: history entries 1615 */ 1616 struct dp_rx_history { 1617 qdf_atomic_t index; 1618 struct dp_buf_info_record entry[DP_RX_HIST_MAX]; 1619 }; 1620 1621 /** 1622 * struct dp_rx_err_history - rx err ring hisotry 1623 * @index: Index where the last entry is written 1624 * @entry: history entries 1625 */ 1626 struct dp_rx_err_history { 1627 qdf_atomic_t index; 1628 struct dp_buf_info_record entry[DP_RX_ERR_HIST_MAX]; 1629 }; 1630 1631 /** 1632 * struct dp_rx_reinject_history - rx reinject ring hisotry 1633 * @index: Index where the last entry is written 1634 * @entry: history entries 1635 */ 1636 struct dp_rx_reinject_history { 1637 qdf_atomic_t index; 1638 struct dp_buf_info_record entry[DP_RX_REINJECT_HIST_MAX]; 1639 }; 1640 1641 /** 1642 * struct dp_rx_refill_history - rx buf refill hisotry 1643 * @index: Index where the last entry is written 1644 * @entry: history entries 1645 */ 1646 struct dp_rx_refill_history { 1647 qdf_atomic_t index; 1648 struct dp_refill_info_record entry[DP_RX_REFILL_HIST_MAX]; 1649 }; 1650 1651 #endif 1652 1653 /** 1654 * enum dp_cfg_event_type - Datapath config events type 1655 * @DP_CFG_EVENT_VDEV_ATTACH: vdev attach 1656 * @DP_CFG_EVENT_VDEV_DETACH: vdev detach 1657 * @DP_CFG_EVENT_VDEV_UNREF_DEL: vdev memory free after last ref is released 1658 * @DP_CFG_EVENT_PEER_CREATE: peer create 1659 * @DP_CFG_EVENT_PEER_DELETE: peer delete 1660 * @DP_CFG_EVENT_PEER_UNREF_DEL: peer memory free after last ref is released 1661 * @DP_CFG_EVENT_PEER_SETUP: peer setup 1662 * @DP_CFG_EVENT_MLO_ADD_LINK: add link peer to mld peer 1663 * @DP_CFG_EVENT_MLO_DEL_LINK: delete link peer from mld peer 1664 * @DP_CFG_EVENT_MLO_SETUP: MLO peer setup 1665 * @DP_CFG_EVENT_MLO_SETUP_VDEV_UPDATE: MLD peer vdev update 1666 * @DP_CFG_EVENT_PEER_MAP: peer map 1667 * @DP_CFG_EVENT_PEER_UNMAP: peer unmap 1668 * @DP_CFG_EVENT_MLO_PEER_MAP: MLD peer map 1669 * @DP_CFG_EVENT_MLO_PEER_UNMAP: MLD peer unmap 1670 */ 1671 enum dp_cfg_event_type { 1672 DP_CFG_EVENT_VDEV_ATTACH, 1673 DP_CFG_EVENT_VDEV_DETACH, 1674 DP_CFG_EVENT_VDEV_UNREF_DEL, 1675 DP_CFG_EVENT_PEER_CREATE, 1676 DP_CFG_EVENT_PEER_DELETE, 1677 DP_CFG_EVENT_PEER_UNREF_DEL, 1678 DP_CFG_EVENT_PEER_SETUP, 1679 DP_CFG_EVENT_MLO_ADD_LINK, 1680 DP_CFG_EVENT_MLO_DEL_LINK, 1681 DP_CFG_EVENT_MLO_SETUP, 1682 DP_CFG_EVENT_MLO_SETUP_VDEV_UPDATE, 1683 DP_CFG_EVENT_PEER_MAP, 1684 DP_CFG_EVENT_PEER_UNMAP, 1685 DP_CFG_EVENT_MLO_PEER_MAP, 1686 DP_CFG_EVENT_MLO_PEER_UNMAP, 1687 }; 1688 1689 #ifdef WLAN_FEATURE_DP_CFG_EVENT_HISTORY 1690 /* Size must be in 2 power, for bitwise index rotation */ 1691 #define DP_CFG_EVT_HISTORY_SIZE 0x800 1692 #define DP_CFG_EVT_HIST_PER_SLOT_MAX 256 1693 #define DP_CFG_EVT_HIST_MAX_SLOTS 8 1694 #define DP_CFG_EVT_HIST_SLOT_SHIFT 8 1695 1696 /** 1697 * struct dp_vdev_attach_detach_desc - vdev ops descriptor 1698 * @vdev: DP vdev handle 1699 * @mac_addr: vdev mac address 1700 * @vdev_id: vdev id 1701 * @ref_count: vdev ref count 1702 */ 1703 struct dp_vdev_attach_detach_desc { 1704 struct dp_vdev *vdev; 1705 union dp_align_mac_addr mac_addr; 1706 uint8_t vdev_id; 1707 int32_t ref_count; 1708 }; 1709 1710 /** 1711 * struct dp_peer_cmn_ops_desc - peer events descriptor 1712 * @vdev_id: vdev_id of the vdev on which peer exists 1713 * @is_reuse: indicates if its a peer reuse case, during peer create 1714 * @peer: DP peer handle 1715 * @vdev: DP vdev handle on which peer exists 1716 * @mac_addr: peer mac address 1717 * @vdev_mac_addr: vdev mac address 1718 * @vdev_ref_count: vdev ref count 1719 * @peer_ref_count: peer ref count 1720 */ 1721 struct dp_peer_cmn_ops_desc { 1722 uint8_t vdev_id : 5, 1723 is_reuse : 1; 1724 struct dp_peer *peer; 1725 struct dp_vdev *vdev; 1726 union dp_align_mac_addr mac_addr; 1727 union dp_align_mac_addr vdev_mac_addr; 1728 int32_t vdev_ref_count; 1729 int32_t peer_ref_count; 1730 }; 1731 1732 /** 1733 * struct dp_mlo_add_del_link_desc - MLO add/del link event descriptor 1734 * @idx: index at which link peer got added in MLD peer's list 1735 * @num_links: num links added in the MLD peer's list 1736 * @action_result: add/del was success or not 1737 * @link_peer: link peer handle 1738 * @mld_peer: MLD peer handle 1739 * @link_mac_addr: link peer mac address 1740 * @mld_mac_addr: MLD peer mac address 1741 */ 1742 struct dp_mlo_add_del_link_desc { 1743 uint8_t idx : 3, 1744 num_links : 3, 1745 action_result : 1, 1746 reserved : 1; 1747 struct dp_peer *link_peer; 1748 struct dp_peer *mld_peer; 1749 union dp_align_mac_addr link_mac_addr; 1750 union dp_align_mac_addr mld_mac_addr; 1751 }; 1752 1753 /** 1754 * struct dp_mlo_setup_vdev_update_desc - MLD peer vdev update event desc 1755 * @mld_peer: MLD peer handle 1756 * @prev_vdev: previous vdev handle 1757 * @new_vdev: new vdev handle 1758 */ 1759 struct dp_mlo_setup_vdev_update_desc { 1760 struct dp_peer *mld_peer; 1761 struct dp_vdev *prev_vdev; 1762 struct dp_vdev *new_vdev; 1763 }; 1764 1765 /** 1766 * struct dp_rx_peer_map_unmap_desc - peer map/unmap event descriptor 1767 * @peer_id: peer id 1768 * @ml_peer_id: ML peer id, if its an MLD peer 1769 * @hw_peer_id: hw peer id 1770 * @vdev_id: vdev id of the peer 1771 * @is_ml_peer: is this MLD peer 1772 * @mac_addr: mac address of the peer 1773 * @peer: peer handle 1774 */ 1775 struct dp_rx_peer_map_unmap_desc { 1776 uint16_t peer_id; 1777 uint16_t ml_peer_id; 1778 uint16_t hw_peer_id; 1779 uint8_t vdev_id; 1780 uint8_t is_ml_peer; 1781 union dp_align_mac_addr mac_addr; 1782 struct dp_peer *peer; 1783 }; 1784 1785 /** 1786 * struct dp_peer_setup_desc - peer setup event descriptor 1787 * @peer: DP peer handle 1788 * @vdev: vdev handle on which peer exists 1789 * @vdev_ref_count: vdev ref count 1790 * @mac_addr: peer mac address 1791 * @mld_mac_addr: MLD mac address 1792 * @is_first_link: is the current link the first link created 1793 * @is_primary_link: is the current link primary link 1794 * @vdev_id: vdev id of the vdev on which the current link peer exists 1795 */ 1796 struct dp_peer_setup_desc { 1797 struct dp_peer *peer; 1798 struct dp_vdev *vdev; 1799 int32_t vdev_ref_count; 1800 union dp_align_mac_addr mac_addr; 1801 union dp_align_mac_addr mld_mac_addr; 1802 uint8_t is_first_link : 1, 1803 is_primary_link : 1, 1804 vdev_id : 5, 1805 reserved : 1; 1806 }; 1807 1808 /** 1809 * union dp_cfg_event_desc - DP config event descriptor 1810 * @vdev_evt: vdev events desc 1811 * @peer_cmn_evt: common peer events desc 1812 * @peer_setup_evt: peer setup event desc 1813 * @mlo_link_delink_evt: MLO link/delink event desc 1814 * @mlo_setup_vdev_update: MLD peer vdev update event desc 1815 * @peer_map_unmap_evt: peer map/unmap event desc 1816 */ 1817 union dp_cfg_event_desc { 1818 struct dp_vdev_attach_detach_desc vdev_evt; 1819 struct dp_peer_cmn_ops_desc peer_cmn_evt; 1820 struct dp_peer_setup_desc peer_setup_evt; 1821 struct dp_mlo_add_del_link_desc mlo_link_delink_evt; 1822 struct dp_mlo_setup_vdev_update_desc mlo_setup_vdev_update; 1823 struct dp_rx_peer_map_unmap_desc peer_map_unmap_evt; 1824 }; 1825 1826 /** 1827 * struct dp_cfg_event - DP config event descriptor 1828 * @timestamp: timestamp at which event was recorded 1829 * @type: event type 1830 * @event_desc: event descriptor 1831 */ 1832 struct dp_cfg_event { 1833 uint64_t timestamp; 1834 enum dp_cfg_event_type type; 1835 union dp_cfg_event_desc event_desc; 1836 }; 1837 1838 /** 1839 * struct dp_cfg_event_history - DP config event history 1840 * @index: current index 1841 * @num_entries_per_slot: number of entries per slot 1842 * @allocated: Is the history allocated or not 1843 * @entry: event history descriptors 1844 */ 1845 struct dp_cfg_event_history { 1846 qdf_atomic_t index; 1847 uint16_t num_entries_per_slot; 1848 uint16_t allocated; 1849 struct dp_cfg_event *entry[DP_CFG_EVT_HIST_MAX_SLOTS]; 1850 }; 1851 #endif 1852 1853 enum dp_tx_event_type { 1854 DP_TX_DESC_INVAL_EVT = 0, 1855 DP_TX_DESC_MAP, 1856 DP_TX_DESC_COOKIE, 1857 DP_TX_DESC_FLUSH, 1858 DP_TX_DESC_UNMAP, 1859 DP_TX_COMP_UNMAP, 1860 DP_TX_COMP_UNMAP_ERR, 1861 DP_TX_COMP_MSDU_EXT, 1862 }; 1863 1864 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 1865 /* Size must be in 2 power, for bitwise index rotation */ 1866 #define DP_TX_TCL_HISTORY_SIZE 0x4000 1867 #define DP_TX_TCL_HIST_PER_SLOT_MAX 2048 1868 #define DP_TX_TCL_HIST_MAX_SLOTS 8 1869 #define DP_TX_TCL_HIST_SLOT_SHIFT 11 1870 1871 /* Size must be in 2 power, for bitwise index rotation */ 1872 #define DP_TX_COMP_HISTORY_SIZE 0x4000 1873 #define DP_TX_COMP_HIST_PER_SLOT_MAX 2048 1874 #define DP_TX_COMP_HIST_MAX_SLOTS 8 1875 #define DP_TX_COMP_HIST_SLOT_SHIFT 11 1876 1877 struct dp_tx_desc_event { 1878 qdf_nbuf_t skb; 1879 dma_addr_t paddr; 1880 uint32_t sw_cookie; 1881 enum dp_tx_event_type type; 1882 uint64_t ts; 1883 }; 1884 1885 struct dp_tx_tcl_history { 1886 qdf_atomic_t index; 1887 uint16_t num_entries_per_slot; 1888 uint16_t allocated; 1889 struct dp_tx_desc_event *entry[DP_TX_TCL_HIST_MAX_SLOTS]; 1890 }; 1891 1892 struct dp_tx_comp_history { 1893 qdf_atomic_t index; 1894 uint16_t num_entries_per_slot; 1895 uint16_t allocated; 1896 struct dp_tx_desc_event *entry[DP_TX_COMP_HIST_MAX_SLOTS]; 1897 }; 1898 #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */ 1899 1900 /* structure to record recent operation related variable */ 1901 struct dp_last_op_info { 1902 /* last link desc buf info through WBM release ring */ 1903 struct hal_buf_info wbm_rel_link_desc; 1904 /* last link desc buf info through REO reinject ring */ 1905 struct hal_buf_info reo_reinject_link_desc; 1906 }; 1907 1908 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 1909 1910 /** 1911 * struct dp_swlm_tcl_data - params for tcl register write coalescing 1912 * decision making 1913 * @nbuf: TX packet 1914 * @tid: tid for transmitting the current packet 1915 * @num_ll_connections: Number of low latency connections on this vdev 1916 * @ring_id: TCL ring id 1917 * @pkt_len: Packet length 1918 * 1919 * This structure contains the information required by the software 1920 * latency manager to decide on whether to coalesce the current TCL 1921 * register write or not. 1922 */ 1923 struct dp_swlm_tcl_data { 1924 qdf_nbuf_t nbuf; 1925 uint8_t tid; 1926 uint8_t num_ll_connections; 1927 uint8_t ring_id; 1928 uint32_t pkt_len; 1929 }; 1930 1931 /** 1932 * union swlm_data - SWLM query data 1933 * @tcl_data: data for TCL query in SWLM 1934 */ 1935 union swlm_data { 1936 struct dp_swlm_tcl_data *tcl_data; 1937 }; 1938 1939 /** 1940 * struct dp_swlm_ops - SWLM ops 1941 * @tcl_wr_coalesce_check: handler to check if the current TCL register 1942 * write can be coalesced or not 1943 */ 1944 struct dp_swlm_ops { 1945 int (*tcl_wr_coalesce_check)(struct dp_soc *soc, 1946 struct dp_swlm_tcl_data *tcl_data); 1947 }; 1948 1949 /** 1950 * struct dp_swlm_stats - Stats for Software Latency manager. 1951 * @tcl: TCL stats 1952 * @tcl.timer_flush_success: Num TCL HP writes success from timer context 1953 * @tcl.timer_flush_fail: Num TCL HP writes failure from timer context 1954 * @tcl.tid_fail: Num TCL register write coalescing skips, since the pkt 1955 * was being transmitted on a TID above coalescing threshold 1956 * @tcl.sp_frames: Num TCL register write coalescing skips, since the pkt 1957 * being transmitted was a special frame 1958 * @tcl.ll_connection: Num TCL register write coalescing skips, since the 1959 * vdev has low latency connections 1960 * @tcl.bytes_thresh_reached: Num TCL HP writes flush after the coalescing 1961 * bytes threshold was reached 1962 * @tcl.time_thresh_reached: Num TCL HP writes flush after the coalescing 1963 * session time expired 1964 * @tcl.tput_criteria_fail: Num TCL HP writes coalescing fails, since the 1965 * throughput did not meet session threshold 1966 * @tcl.coalesce_success: Num of TCL HP writes coalesced successfully. 1967 * @tcl.coalesce_fail: Num of TCL HP writes coalesces failed 1968 */ 1969 struct dp_swlm_stats { 1970 struct { 1971 uint32_t timer_flush_success; 1972 uint32_t timer_flush_fail; 1973 uint32_t tid_fail; 1974 uint32_t sp_frames; 1975 uint32_t ll_connection; 1976 uint32_t bytes_thresh_reached; 1977 uint32_t time_thresh_reached; 1978 uint32_t tput_criteria_fail; 1979 uint32_t coalesce_success; 1980 uint32_t coalesce_fail; 1981 } tcl[MAX_TCL_DATA_RINGS]; 1982 }; 1983 1984 /** 1985 * struct dp_swlm_tcl_params: Parameters based on TCL for different modules 1986 * in the Software latency manager. 1987 * @soc: DP soc reference 1988 * @ring_id: TCL ring id 1989 * @flush_timer: Timer for flushing the coalesced TCL HP writes 1990 * @sampling_session_tx_bytes: Num bytes transmitted in the sampling time 1991 * @bytes_flush_thresh: Bytes threshold to flush the TCL HP register write 1992 * @coalesce_end_time: End timestamp for current coalescing session 1993 * @bytes_coalesced: Num bytes coalesced in the current session 1994 * @prev_tx_packets: Previous TX packets accounted 1995 * @prev_tx_bytes: Previous TX bytes accounted 1996 * @prev_rx_bytes: Previous RX bytes accounted 1997 * @expire_time: expiry time for sample 1998 * @tput_pass_cnt: threshold throughput pass counter 1999 */ 2000 struct dp_swlm_tcl_params { 2001 struct dp_soc *soc; 2002 uint32_t ring_id; 2003 qdf_timer_t flush_timer; 2004 uint32_t sampling_session_tx_bytes; 2005 uint32_t bytes_flush_thresh; 2006 uint64_t coalesce_end_time; 2007 uint32_t bytes_coalesced; 2008 uint32_t prev_tx_packets; 2009 uint32_t prev_tx_bytes; 2010 uint32_t prev_rx_bytes; 2011 uint64_t expire_time; 2012 uint32_t tput_pass_cnt; 2013 }; 2014 2015 /** 2016 * struct dp_swlm_params: Parameters for different modules in the 2017 * Software latency manager. 2018 * @rx_traffic_thresh: Threshold for RX traffic, to begin TCL register 2019 * write coalescing 2020 * @tx_traffic_thresh: Threshold for TX traffic, to begin TCL register 2021 * write coalescing 2022 * @sampling_time: Sampling time to test the throughput threshold 2023 * @time_flush_thresh: Time threshold to flush the TCL HP register write 2024 * @tx_thresh_multiplier: Multiplier to deduce the bytes threshold after 2025 * which the TCL HP register is written, thereby 2026 * ending the coalescing. 2027 * @tx_pkt_thresh: Threshold for TX packet count, to begin TCL register 2028 * write coalescing 2029 * @tcl: TCL ring specific params 2030 */ 2031 2032 struct dp_swlm_params { 2033 uint32_t rx_traffic_thresh; 2034 uint32_t tx_traffic_thresh; 2035 uint32_t sampling_time; 2036 uint32_t time_flush_thresh; 2037 uint32_t tx_thresh_multiplier; 2038 uint32_t tx_pkt_thresh; 2039 struct dp_swlm_tcl_params tcl[MAX_TCL_DATA_RINGS]; 2040 }; 2041 2042 /** 2043 * struct dp_swlm - Software latency manager context 2044 * @ops: SWLM ops pointers 2045 * @is_enabled: SWLM enabled/disabled 2046 * @is_init: SWLM module initialized 2047 * @stats: SWLM stats 2048 * @params: SWLM SRNG params 2049 * @tcl_flush_timer: flush timer for TCL register writes 2050 */ 2051 struct dp_swlm { 2052 struct dp_swlm_ops *ops; 2053 uint8_t is_enabled:1, 2054 is_init:1; 2055 struct dp_swlm_stats stats; 2056 struct dp_swlm_params params; 2057 }; 2058 #endif 2059 2060 #ifdef IPA_OFFLOAD 2061 /* IPA uC datapath offload Wlan Tx resources */ 2062 struct ipa_dp_tx_rsc { 2063 /* Resource info to be passed to IPA */ 2064 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 2065 void *ipa_tcl_ring_base_vaddr; 2066 uint32_t ipa_tcl_ring_size; 2067 qdf_dma_addr_t ipa_tcl_hp_paddr; 2068 uint32_t alloc_tx_buf_cnt; 2069 2070 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 2071 void *ipa_wbm_ring_base_vaddr; 2072 uint32_t ipa_wbm_ring_size; 2073 qdf_dma_addr_t ipa_wbm_tp_paddr; 2074 /* WBM2SW HP shadow paddr */ 2075 qdf_dma_addr_t ipa_wbm_hp_shadow_paddr; 2076 2077 /* TX buffers populated into the WBM ring */ 2078 void **tx_buf_pool_vaddr_unaligned; 2079 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 2080 }; 2081 2082 /* IPA uC datapath offload Wlan Rx resources */ 2083 struct ipa_dp_rx_rsc { 2084 /* Resource info to be passed to IPA */ 2085 qdf_dma_addr_t ipa_reo_ring_base_paddr; 2086 void *ipa_reo_ring_base_vaddr; 2087 uint32_t ipa_reo_ring_size; 2088 qdf_dma_addr_t ipa_reo_tp_paddr; 2089 2090 /* Resource info to be passed to firmware and IPA */ 2091 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 2092 void *ipa_rx_refill_buf_ring_base_vaddr; 2093 uint32_t ipa_rx_refill_buf_ring_size; 2094 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 2095 }; 2096 #endif 2097 2098 struct dp_tx_msdu_info_s; 2099 /** 2100 * enum dp_context_type- DP Context Type 2101 * @DP_CONTEXT_TYPE_SOC: Context type DP SOC 2102 * @DP_CONTEXT_TYPE_PDEV: Context type DP PDEV 2103 * @DP_CONTEXT_TYPE_VDEV: Context type DP VDEV 2104 * @DP_CONTEXT_TYPE_PEER: Context type DP PEER 2105 * @DP_CONTEXT_TYPE_MON_SOC: Context type DP MON SOC 2106 * @DP_CONTEXT_TYPE_MON_PDEV: Context type DP MON PDEV 2107 * 2108 * Helper enums to be used to retrieve the size of the corresponding 2109 * data structure by passing the type. 2110 */ 2111 enum dp_context_type { 2112 DP_CONTEXT_TYPE_SOC, 2113 DP_CONTEXT_TYPE_PDEV, 2114 DP_CONTEXT_TYPE_VDEV, 2115 DP_CONTEXT_TYPE_PEER, 2116 DP_CONTEXT_TYPE_MON_SOC, 2117 DP_CONTEXT_TYPE_MON_PDEV 2118 }; 2119 2120 /** 2121 * struct dp_arch_ops - DP target specific arch ops 2122 * @txrx_soc_attach: 2123 * @txrx_soc_detach: 2124 * @txrx_soc_init: 2125 * @txrx_soc_deinit: 2126 * @txrx_soc_srng_alloc: 2127 * @txrx_soc_srng_init: 2128 * @txrx_soc_srng_deinit: 2129 * @txrx_soc_srng_free: 2130 * @txrx_pdev_attach: 2131 * @txrx_pdev_detach: 2132 * @txrx_vdev_attach: 2133 * @txrx_vdev_detach: 2134 * @txrx_peer_map_attach: 2135 * @txrx_peer_map_detach: 2136 * @dp_rxdma_ring_sel_cfg: 2137 * @soc_cfg_attach: 2138 * @txrx_peer_setup: 2139 * @peer_get_reo_hash: 2140 * @reo_remap_config: 2141 * @tx_hw_enqueue: enqueue TX data to HW 2142 * @tx_comp_get_params_from_hal_desc: get software tx descriptor and release 2143 * source from HAL desc for wbm release ring 2144 * @dp_tx_process_htt_completion: 2145 * @dp_rx_process: 2146 * @dp_tx_send_fast: 2147 * @dp_tx_desc_pool_init: 2148 * @dp_tx_desc_pool_deinit: 2149 * @dp_rx_desc_pool_init: 2150 * @dp_rx_desc_pool_deinit: 2151 * @dp_wbm_get_rx_desc_from_hal_desc: 2152 * @dp_rx_intrabss_mcast_handler: 2153 * @dp_rx_word_mask_subscribe: 2154 * @dp_rx_desc_cookie_2_va: 2155 * @dp_service_near_full_srngs: Handler for servicing the near full IRQ 2156 * @tx_implicit_rbm_set: 2157 * @dp_rx_peer_metadata_peer_id_get: 2158 * @dp_rx_chain_msdus: 2159 * @txrx_set_vdev_param: target specific ops while setting vdev params 2160 * @txrx_get_vdev_mcast_param: target specific ops for getting vdev 2161 * params related to multicast 2162 * @txrx_get_context_size: 2163 * @txrx_get_mon_context_size: 2164 * @dp_srng_test_and_update_nf_params: Check if the srng is in near full state 2165 * and set the near-full params. 2166 * @dp_tx_mcast_handler: 2167 * @dp_rx_mcast_handler: 2168 * @dp_tx_is_mcast_primary: 2169 * @dp_soc_get_by_idle_bm_id: 2170 * @mlo_peer_find_hash_detach: 2171 * @mlo_peer_find_hash_attach: 2172 * @mlo_peer_find_hash_add: 2173 * @mlo_peer_find_hash_remove: 2174 * @mlo_peer_find_hash_find: 2175 * @get_reo_qdesc_addr: 2176 * @get_rx_hash_key: 2177 * @dp_set_rx_fst: 2178 * @dp_get_rx_fst: 2179 * @dp_rx_fst_deref: 2180 * @dp_rx_fst_ref: 2181 * @txrx_print_peer_stats: 2182 * @dp_peer_rx_reorder_queue_setup: Dp peer reorder queue setup 2183 * @dp_find_peer_by_destmac: 2184 * @dp_bank_reconfig: 2185 * @dp_rx_replenish_soc_get: 2186 * @dp_soc_get_num_soc: 2187 * @dp_reconfig_tx_vdev_mcast_ctrl: 2188 * @dp_cc_reg_cfg_init: 2189 * @dp_tx_compute_hw_delay: 2190 * @print_mlo_ast_stats: 2191 * @dp_partner_chips_map: 2192 * @dp_partner_chips_unmap: 2193 * @ipa_get_bank_id: Get TCL bank id used by IPA 2194 * @dp_txrx_ppeds_rings_status: 2195 * @dp_tx_ppeds_inuse_desc: 2196 * @dp_tx_ppeds_cfg_astidx_cache_mapping: 2197 * @txrx_soc_ppeds_start: 2198 * @txrx_soc_ppeds_stop: 2199 * @dp_register_ppeds_interrupts: 2200 * @dp_free_ppeds_interrupts: 2201 */ 2202 struct dp_arch_ops { 2203 /* INIT/DEINIT Arch Ops */ 2204 QDF_STATUS (*txrx_soc_attach)(struct dp_soc *soc, 2205 struct cdp_soc_attach_params *params); 2206 QDF_STATUS (*txrx_soc_detach)(struct dp_soc *soc); 2207 QDF_STATUS (*txrx_soc_init)(struct dp_soc *soc); 2208 QDF_STATUS (*txrx_soc_deinit)(struct dp_soc *soc); 2209 QDF_STATUS (*txrx_soc_srng_alloc)(struct dp_soc *soc); 2210 QDF_STATUS (*txrx_soc_srng_init)(struct dp_soc *soc); 2211 void (*txrx_soc_srng_deinit)(struct dp_soc *soc); 2212 void (*txrx_soc_srng_free)(struct dp_soc *soc); 2213 QDF_STATUS (*txrx_pdev_attach)(struct dp_pdev *pdev, 2214 struct cdp_pdev_attach_params *params); 2215 QDF_STATUS (*txrx_pdev_detach)(struct dp_pdev *pdev); 2216 QDF_STATUS (*txrx_vdev_attach)(struct dp_soc *soc, 2217 struct dp_vdev *vdev); 2218 QDF_STATUS (*txrx_vdev_detach)(struct dp_soc *soc, 2219 struct dp_vdev *vdev); 2220 QDF_STATUS (*txrx_peer_map_attach)(struct dp_soc *soc); 2221 void (*txrx_peer_map_detach)(struct dp_soc *soc); 2222 QDF_STATUS (*dp_rxdma_ring_sel_cfg)(struct dp_soc *soc); 2223 void (*soc_cfg_attach)(struct dp_soc *soc); 2224 QDF_STATUS (*txrx_peer_setup)(struct dp_soc *soc, 2225 struct dp_peer *peer); 2226 void (*peer_get_reo_hash)(struct dp_vdev *vdev, 2227 struct cdp_peer_setup_info *setup_info, 2228 enum cdp_host_reo_dest_ring *reo_dest, 2229 bool *hash_based, 2230 uint8_t *lmac_peer_id_msb); 2231 bool (*reo_remap_config)(struct dp_soc *soc, uint32_t *remap0, 2232 uint32_t *remap1, uint32_t *remap2); 2233 2234 /* TX RX Arch Ops */ 2235 QDF_STATUS (*tx_hw_enqueue)(struct dp_soc *soc, struct dp_vdev *vdev, 2236 struct dp_tx_desc_s *tx_desc, 2237 uint16_t fw_metadata, 2238 struct cdp_tx_exception_metadata *metadata, 2239 struct dp_tx_msdu_info_s *msdu_info); 2240 2241 void (*tx_comp_get_params_from_hal_desc)(struct dp_soc *soc, 2242 void *tx_comp_hal_desc, 2243 struct dp_tx_desc_s **desc); 2244 void (*dp_tx_process_htt_completion)(struct dp_soc *soc, 2245 struct dp_tx_desc_s *tx_desc, 2246 uint8_t *status, 2247 uint8_t ring_id); 2248 2249 uint32_t (*dp_rx_process)(struct dp_intr *int_ctx, 2250 hal_ring_handle_t hal_ring_hdl, 2251 uint8_t reo_ring_num, uint32_t quota); 2252 2253 qdf_nbuf_t (*dp_tx_send_fast)(struct cdp_soc_t *soc_hdl, 2254 uint8_t vdev_id, 2255 qdf_nbuf_t nbuf); 2256 2257 QDF_STATUS (*dp_tx_desc_pool_init)(struct dp_soc *soc, 2258 uint32_t num_elem, 2259 uint8_t pool_id); 2260 void (*dp_tx_desc_pool_deinit)( 2261 struct dp_soc *soc, 2262 struct dp_tx_desc_pool_s *tx_desc_pool, 2263 uint8_t pool_id); 2264 2265 QDF_STATUS (*dp_rx_desc_pool_init)(struct dp_soc *soc, 2266 struct rx_desc_pool *rx_desc_pool, 2267 uint32_t pool_id); 2268 void (*dp_rx_desc_pool_deinit)(struct dp_soc *soc, 2269 struct rx_desc_pool *rx_desc_pool, 2270 uint32_t pool_id); 2271 2272 QDF_STATUS (*dp_wbm_get_rx_desc_from_hal_desc)( 2273 struct dp_soc *soc, 2274 void *ring_desc, 2275 struct dp_rx_desc **r_rx_desc); 2276 2277 bool 2278 (*dp_rx_intrabss_mcast_handler)(struct dp_soc *soc, 2279 struct dp_txrx_peer *ta_txrx_peer, 2280 qdf_nbuf_t nbuf_copy, 2281 struct cdp_tid_rx_stats *tid_stats); 2282 2283 void (*dp_rx_word_mask_subscribe)( 2284 struct dp_soc *soc, 2285 uint32_t *msg_word, 2286 void *rx_filter); 2287 2288 struct dp_rx_desc *(*dp_rx_desc_cookie_2_va)(struct dp_soc *soc, 2289 uint32_t cookie); 2290 uint32_t (*dp_service_near_full_srngs)(struct dp_soc *soc, 2291 struct dp_intr *int_ctx, 2292 uint32_t dp_budget); 2293 void (*tx_implicit_rbm_set)(struct dp_soc *soc, uint8_t tx_ring_id, 2294 uint8_t bm_id); 2295 uint16_t (*dp_rx_peer_metadata_peer_id_get)(struct dp_soc *soc, 2296 uint32_t peer_metadata); 2297 bool (*dp_rx_chain_msdus)(struct dp_soc *soc, qdf_nbuf_t nbuf, 2298 uint8_t *rx_tlv_hdr, uint8_t mac_id); 2299 /* Control Arch Ops */ 2300 QDF_STATUS (*txrx_set_vdev_param)(struct dp_soc *soc, 2301 struct dp_vdev *vdev, 2302 enum cdp_vdev_param_type param, 2303 cdp_config_param_type val); 2304 2305 QDF_STATUS (*txrx_get_vdev_mcast_param)(struct dp_soc *soc, 2306 struct dp_vdev *vdev, 2307 cdp_config_param_type *val); 2308 2309 /* Misc Arch Ops */ 2310 qdf_size_t (*txrx_get_context_size)(enum dp_context_type); 2311 #ifdef WIFI_MONITOR_SUPPORT 2312 qdf_size_t (*txrx_get_mon_context_size)(enum dp_context_type); 2313 #endif 2314 int (*dp_srng_test_and_update_nf_params)(struct dp_soc *soc, 2315 struct dp_srng *dp_srng, 2316 int *max_reap_limit); 2317 2318 /* MLO ops */ 2319 #ifdef WLAN_FEATURE_11BE_MLO 2320 #ifdef WLAN_MCAST_MLO 2321 void (*dp_tx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 2322 qdf_nbuf_t nbuf); 2323 bool (*dp_rx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 2324 struct dp_txrx_peer *peer, qdf_nbuf_t nbuf); 2325 bool (*dp_tx_is_mcast_primary)(struct dp_soc *soc, 2326 struct dp_vdev *vdev); 2327 #endif 2328 struct dp_soc * (*dp_soc_get_by_idle_bm_id)(struct dp_soc *soc, 2329 uint8_t bm_id); 2330 2331 void (*mlo_peer_find_hash_detach)(struct dp_soc *soc); 2332 QDF_STATUS (*mlo_peer_find_hash_attach)(struct dp_soc *soc); 2333 void (*mlo_peer_find_hash_add)(struct dp_soc *soc, 2334 struct dp_peer *peer); 2335 void (*mlo_peer_find_hash_remove)(struct dp_soc *soc, 2336 struct dp_peer *peer); 2337 2338 struct dp_peer *(*mlo_peer_find_hash_find)(struct dp_soc *soc, 2339 uint8_t *peer_mac_addr, 2340 int mac_addr_is_aligned, 2341 enum dp_mod_id mod_id, 2342 uint8_t vdev_id); 2343 #endif 2344 uint64_t (*get_reo_qdesc_addr)(hal_soc_handle_t hal_soc_hdl, 2345 uint8_t *dst_ring_desc, 2346 uint8_t *buf, 2347 struct dp_txrx_peer *peer, 2348 unsigned int tid); 2349 void (*get_rx_hash_key)(struct dp_soc *soc, 2350 struct cdp_lro_hash_config *lro_hash); 2351 void (*dp_set_rx_fst)(struct dp_soc *soc, struct dp_rx_fst *fst); 2352 struct dp_rx_fst *(*dp_get_rx_fst)(struct dp_soc *soc); 2353 uint8_t (*dp_rx_fst_deref)(struct dp_soc *soc); 2354 void (*dp_rx_fst_ref)(struct dp_soc *soc); 2355 void (*txrx_print_peer_stats)(struct cdp_peer_stats *peer_stats, 2356 enum peer_stats_type stats_type); 2357 QDF_STATUS (*dp_peer_rx_reorder_queue_setup)(struct dp_soc *soc, 2358 struct dp_peer *peer, 2359 int tid, 2360 uint32_t ba_window_size); 2361 struct dp_peer *(*dp_find_peer_by_destmac)(struct dp_soc *soc, 2362 uint8_t *dest_mac_addr, 2363 uint8_t vdev_id); 2364 void (*dp_bank_reconfig)(struct dp_soc *soc, struct dp_vdev *vdev); 2365 2366 struct dp_soc * (*dp_rx_replenish_soc_get)(struct dp_soc *soc, 2367 uint8_t chip_id); 2368 2369 uint8_t (*dp_soc_get_num_soc)(struct dp_soc *soc); 2370 void (*dp_reconfig_tx_vdev_mcast_ctrl)(struct dp_soc *soc, 2371 struct dp_vdev *vdev); 2372 2373 void (*dp_cc_reg_cfg_init)(struct dp_soc *soc, bool is_4k_align); 2374 2375 QDF_STATUS 2376 (*dp_tx_compute_hw_delay)(struct dp_soc *soc, 2377 struct dp_vdev *vdev, 2378 struct hal_tx_completion_status *ts, 2379 uint32_t *delay_us); 2380 void (*print_mlo_ast_stats)(struct dp_soc *soc); 2381 void (*dp_partner_chips_map)(struct dp_soc *soc, 2382 struct dp_peer *peer, 2383 uint16_t peer_id); 2384 void (*dp_partner_chips_unmap)(struct dp_soc *soc, 2385 uint16_t peer_id); 2386 2387 #ifdef IPA_OFFLOAD 2388 int8_t (*ipa_get_bank_id)(struct dp_soc *soc); 2389 #endif 2390 #ifdef WLAN_SUPPORT_PPEDS 2391 void (*dp_txrx_ppeds_rings_status)(struct dp_soc *soc); 2392 void (*dp_tx_ppeds_inuse_desc)(struct dp_soc *soc); 2393 void (*dp_tx_ppeds_cfg_astidx_cache_mapping)(struct dp_soc *soc, 2394 struct dp_vdev *vdev, 2395 bool peer_map); 2396 #endif 2397 QDF_STATUS (*txrx_soc_ppeds_start)(struct dp_soc *soc); 2398 void (*txrx_soc_ppeds_stop)(struct dp_soc *soc); 2399 int (*dp_register_ppeds_interrupts)(struct dp_soc *soc, 2400 struct dp_srng *srng, int vector, 2401 int ring_type, int ring_num); 2402 void (*dp_free_ppeds_interrupts)(struct dp_soc *soc, 2403 struct dp_srng *srng, int ring_type, 2404 int ring_num); 2405 }; 2406 2407 /** 2408 * struct dp_soc_features: Data structure holding the SOC level feature flags. 2409 * @pn_in_reo_dest: PN provided by hardware in the REO destination ring. 2410 * @dmac_cmn_src_rxbuf_ring_enabled: Flag to indicate DMAC mode common Rx 2411 * buffer source rings 2412 * @rssi_dbm_conv_support: Rssi dbm conversion support param. 2413 * @umac_hw_reset_support: UMAC HW reset support 2414 * @wds_ext_ast_override_enable: 2415 */ 2416 struct dp_soc_features { 2417 uint8_t pn_in_reo_dest:1, 2418 dmac_cmn_src_rxbuf_ring_enabled:1; 2419 bool rssi_dbm_conv_support; 2420 bool umac_hw_reset_support; 2421 bool wds_ext_ast_override_enable; 2422 }; 2423 2424 enum sysfs_printing_mode { 2425 PRINTING_MODE_DISABLED = 0, 2426 PRINTING_MODE_ENABLED 2427 }; 2428 2429 /** 2430 * typedef notify_pre_reset_fw_callback() - pre-reset callback 2431 * @soc: DP SoC 2432 */ 2433 typedef void (*notify_pre_reset_fw_callback)(struct dp_soc *soc); 2434 2435 #ifdef WLAN_SYSFS_DP_STATS 2436 /** 2437 * struct sysfs_stats_config: Data structure holding stats sysfs config. 2438 * @rw_stats_lock: Lock to read and write to stat_type and pdev_id. 2439 * @sysfs_read_lock: Lock held while another stat req is being executed. 2440 * @sysfs_write_user_buffer: Lock to change buff len, max buf len 2441 * and *buf. 2442 * @sysfs_txrx_fw_request_done: Event to wait for firmware response. 2443 * @stat_type_requested: stat type requested. 2444 * @mac_id: mac id for which stat type are requested. 2445 * @printing_mode: Should a print go through. 2446 * @process_id: Process allowed to write to buffer. 2447 * @curr_buffer_length: Curr length of buffer written 2448 * @max_buffer_length: Max buffer length. 2449 * @buf: Sysfs buffer. 2450 */ 2451 struct sysfs_stats_config { 2452 /* lock held to read stats */ 2453 qdf_spinlock_t rw_stats_lock; 2454 qdf_mutex_t sysfs_read_lock; 2455 qdf_spinlock_t sysfs_write_user_buffer; 2456 qdf_event_t sysfs_txrx_fw_request_done; 2457 uint32_t stat_type_requested; 2458 uint32_t mac_id; 2459 enum sysfs_printing_mode printing_mode; 2460 int process_id; 2461 uint16_t curr_buffer_length; 2462 uint16_t max_buffer_length; 2463 char *buf; 2464 }; 2465 #endif 2466 2467 /* SOC level structure for data path */ 2468 struct dp_soc { 2469 /** 2470 * re-use memory section starts 2471 */ 2472 2473 /* Common base structure - Should be the first member */ 2474 struct cdp_soc_t cdp_soc; 2475 2476 /* SoC Obj */ 2477 struct cdp_ctrl_objmgr_psoc *ctrl_psoc; 2478 2479 /* OS device abstraction */ 2480 qdf_device_t osdev; 2481 2482 /*cce disable*/ 2483 bool cce_disable; 2484 2485 /* WLAN config context */ 2486 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 2487 2488 /* HTT handle for host-fw interaction */ 2489 struct htt_soc *htt_handle; 2490 2491 /* Commint init done */ 2492 qdf_atomic_t cmn_init_done; 2493 2494 /* Opaque hif handle */ 2495 struct hif_opaque_softc *hif_handle; 2496 2497 /* PDEVs on this SOC */ 2498 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 2499 2500 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 2501 struct dp_srng rx_refill_buf_ring[MAX_PDEV_CNT]; 2502 2503 struct dp_srng rxdma_mon_desc_ring[MAX_NUM_LMAC_HW]; 2504 2505 /* RXDMA error destination ring */ 2506 struct dp_srng rxdma_err_dst_ring[MAX_NUM_LMAC_HW]; 2507 2508 /* RXDMA monitor buffer replenish ring */ 2509 struct dp_srng rxdma_mon_buf_ring[MAX_NUM_LMAC_HW]; 2510 2511 /* RXDMA monitor destination ring */ 2512 struct dp_srng rxdma_mon_dst_ring[MAX_NUM_LMAC_HW]; 2513 2514 /* RXDMA monitor status ring. TBD: Check format of this ring */ 2515 struct dp_srng rxdma_mon_status_ring[MAX_NUM_LMAC_HW]; 2516 2517 /* Number of PDEVs */ 2518 uint8_t pdev_count; 2519 2520 /*ast override support in HW*/ 2521 bool ast_override_support; 2522 2523 /*number of hw dscp tid map*/ 2524 uint8_t num_hw_dscp_tid_map; 2525 2526 /* HAL SOC handle */ 2527 hal_soc_handle_t hal_soc; 2528 2529 /* rx monitor pkt tlv size */ 2530 uint16_t rx_mon_pkt_tlv_size; 2531 /* rx pkt tlv size */ 2532 uint16_t rx_pkt_tlv_size; 2533 /* rx pkt tlv size in current operation mode */ 2534 uint16_t curr_rx_pkt_tlv_size; 2535 2536 struct dp_arch_ops arch_ops; 2537 2538 /* Device ID coming from Bus sub-system */ 2539 uint32_t device_id; 2540 2541 /* Link descriptor pages */ 2542 struct qdf_mem_multi_page_t link_desc_pages; 2543 2544 /* total link descriptors for regular RX and TX */ 2545 uint32_t total_link_descs; 2546 2547 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 2548 struct dp_srng wbm_idle_link_ring; 2549 2550 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 2551 */ 2552 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 2553 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 2554 uint32_t num_scatter_bufs; 2555 2556 /* Tx SW descriptor pool */ 2557 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 2558 2559 /* Tx MSDU Extension descriptor pool */ 2560 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 2561 2562 /* Tx TSO descriptor pool */ 2563 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 2564 2565 /* Tx TSO Num of segments pool */ 2566 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 2567 2568 /* REO destination rings */ 2569 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 2570 2571 /* REO exception ring - See if should combine this with reo_dest_ring */ 2572 struct dp_srng reo_exception_ring; 2573 2574 /* REO reinjection ring */ 2575 struct dp_srng reo_reinject_ring; 2576 2577 /* REO command ring */ 2578 struct dp_srng reo_cmd_ring; 2579 2580 /* REO command status ring */ 2581 struct dp_srng reo_status_ring; 2582 2583 /* WBM Rx release ring */ 2584 struct dp_srng rx_rel_ring; 2585 2586 /* TCL data ring */ 2587 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 2588 2589 /* Number of Tx comp rings */ 2590 uint8_t num_tx_comp_rings; 2591 2592 /* Number of TCL data rings */ 2593 uint8_t num_tcl_data_rings; 2594 2595 /* TCL CMD_CREDIT ring */ 2596 bool init_tcl_cmd_cred_ring; 2597 2598 /* It is used as credit based ring on QCN9000 else command ring */ 2599 struct dp_srng tcl_cmd_credit_ring; 2600 2601 /* TCL command status ring */ 2602 struct dp_srng tcl_status_ring; 2603 2604 /* WBM Tx completion rings */ 2605 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 2606 2607 /* Common WBM link descriptor release ring (SW to WBM) */ 2608 struct dp_srng wbm_desc_rel_ring; 2609 2610 /* DP Interrupts */ 2611 struct dp_intr intr_ctx[WLAN_CFG_INT_NUM_CONTEXTS]; 2612 2613 /* Monitor mode mac id to dp_intr_id map */ 2614 int mon_intr_id_lmac_map[MAX_NUM_LMAC_HW]; 2615 /* Rx SW descriptor pool for RXDMA monitor buffer */ 2616 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 2617 2618 /* Rx SW descriptor pool for RXDMA status buffer */ 2619 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 2620 2621 /* Rx SW descriptor pool for RXDMA buffer */ 2622 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 2623 2624 /* Number of REO destination rings */ 2625 uint8_t num_reo_dest_rings; 2626 2627 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 2628 /* lock to control access to soc TX descriptors */ 2629 qdf_spinlock_t flow_pool_array_lock; 2630 2631 /* pause callback to pause TX queues as per flow control */ 2632 tx_pause_callback pause_cb; 2633 2634 /* flow pool related statistics */ 2635 struct dp_txrx_pool_stats pool_stats; 2636 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 2637 2638 notify_pre_reset_fw_callback notify_fw_callback; 2639 2640 unsigned long service_rings_running; 2641 2642 uint32_t wbm_idle_scatter_buf_size; 2643 2644 /* VDEVs on this SOC */ 2645 struct dp_vdev *vdev_id_map[MAX_VDEV_CNT]; 2646 2647 /* Tx H/W queues lock */ 2648 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 2649 2650 /* Tx ring map for interrupt processing */ 2651 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2652 2653 /* Rx ring map for interrupt processing */ 2654 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2655 2656 /* peer ID to peer object map (array of pointers to peer objects) */ 2657 struct dp_peer **peer_id_to_obj_map; 2658 2659 struct { 2660 unsigned mask; 2661 unsigned idx_bits; 2662 TAILQ_HEAD(, dp_peer) * bins; 2663 } peer_hash; 2664 2665 /* rx defrag state – TBD: do we need this per radio? */ 2666 struct { 2667 struct { 2668 TAILQ_HEAD(, dp_rx_tid_defrag) waitlist; 2669 uint32_t timeout_ms; 2670 uint32_t next_flush_ms; 2671 qdf_spinlock_t defrag_lock; 2672 } defrag; 2673 struct { 2674 int defrag_timeout_check; 2675 int dup_check; 2676 } flags; 2677 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 2678 qdf_spinlock_t reo_cmd_lock; 2679 } rx; 2680 2681 /* optional rx processing function */ 2682 void (*rx_opt_proc)( 2683 struct dp_vdev *vdev, 2684 struct dp_peer *peer, 2685 unsigned tid, 2686 qdf_nbuf_t msdu_list); 2687 2688 /* pool addr for mcast enhance buff */ 2689 struct { 2690 int size; 2691 uint32_t paddr; 2692 uint32_t *vaddr; 2693 struct dp_tx_me_buf_t *freelist; 2694 int buf_in_use; 2695 qdf_dma_mem_context(memctx); 2696 } me_buf; 2697 2698 /* Protect peer hash table */ 2699 DP_MUTEX_TYPE peer_hash_lock; 2700 /* Protect peer_id_to_objmap */ 2701 DP_MUTEX_TYPE peer_map_lock; 2702 2703 /* maximum number of suppoerted peers */ 2704 uint32_t max_peers; 2705 /* maximum value for peer_id */ 2706 uint32_t max_peer_id; 2707 2708 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH 2709 uint32_t peer_id_shift; 2710 uint32_t peer_id_mask; 2711 #endif 2712 2713 /* SoC level data path statistics */ 2714 struct dp_soc_stats stats; 2715 #ifdef WLAN_SYSFS_DP_STATS 2716 /* sysfs config for DP stats */ 2717 struct sysfs_stats_config *sysfs_config; 2718 #endif 2719 /* timestamp to keep track of msdu buffers received on reo err ring */ 2720 uint64_t rx_route_err_start_pkt_ts; 2721 2722 /* Num RX Route err in a given window to keep track of rate of errors */ 2723 uint32_t rx_route_err_in_window; 2724 2725 /* Enable processing of Tx completion status words */ 2726 bool process_tx_status; 2727 bool process_rx_status; 2728 struct dp_ast_entry **ast_table; 2729 struct { 2730 unsigned mask; 2731 unsigned idx_bits; 2732 TAILQ_HEAD(, dp_ast_entry) * bins; 2733 } ast_hash; 2734 2735 #ifdef DP_TX_HW_DESC_HISTORY 2736 struct dp_tx_hw_desc_history tx_hw_desc_history; 2737 #endif 2738 2739 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 2740 struct dp_rx_history *rx_ring_history[MAX_REO_DEST_RINGS]; 2741 struct dp_rx_refill_history *rx_refill_ring_history[MAX_PDEV_CNT]; 2742 struct dp_rx_err_history *rx_err_ring_history; 2743 struct dp_rx_reinject_history *rx_reinject_ring_history; 2744 #endif 2745 2746 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 2747 struct dp_mon_status_ring_history *mon_status_ring_history; 2748 #endif 2749 2750 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 2751 struct dp_tx_tcl_history tx_tcl_history; 2752 struct dp_tx_comp_history tx_comp_history; 2753 #endif 2754 2755 #ifdef WLAN_FEATURE_DP_CFG_EVENT_HISTORY 2756 struct dp_cfg_event_history cfg_event_history; 2757 #endif 2758 2759 qdf_spinlock_t ast_lock; 2760 /*Timer for AST entry ageout maintenance */ 2761 qdf_timer_t ast_aging_timer; 2762 2763 /*Timer counter for WDS AST entry ageout*/ 2764 uint8_t wds_ast_aging_timer_cnt; 2765 bool pending_ageout; 2766 bool ast_offload_support; 2767 bool host_ast_db_enable; 2768 uint32_t max_ast_ageout_count; 2769 uint8_t eapol_over_control_port; 2770 2771 uint8_t sta_mode_search_policy; 2772 qdf_timer_t lmac_reap_timer; 2773 uint8_t lmac_timer_init; 2774 qdf_timer_t int_timer; 2775 uint8_t intr_mode; 2776 uint8_t lmac_polled_mode; 2777 2778 qdf_list_t reo_desc_freelist; 2779 qdf_spinlock_t reo_desc_freelist_lock; 2780 2781 /* htt stats */ 2782 struct htt_t2h_stats htt_stats; 2783 2784 void *external_txrx_handle; /* External data path handle */ 2785 #ifdef IPA_OFFLOAD 2786 struct ipa_dp_tx_rsc ipa_uc_tx_rsc; 2787 #ifdef IPA_WDI3_TX_TWO_PIPES 2788 /* Resources for the alternative IPA TX pipe */ 2789 struct ipa_dp_tx_rsc ipa_uc_tx_rsc_alt; 2790 #endif 2791 2792 struct ipa_dp_rx_rsc ipa_uc_rx_rsc; 2793 #ifdef IPA_WDI3_VLAN_SUPPORT 2794 struct ipa_dp_rx_rsc ipa_uc_rx_rsc_alt; 2795 #endif 2796 qdf_atomic_t ipa_pipes_enabled; 2797 bool ipa_first_tx_db_access; 2798 qdf_spinlock_t ipa_rx_buf_map_lock; 2799 bool ipa_rx_buf_map_lock_initialized; 2800 uint8_t ipa_reo_ctx_lock_required[MAX_REO_DEST_RINGS]; 2801 #endif 2802 2803 #ifdef WLAN_FEATURE_STATS_EXT 2804 struct { 2805 uint32_t rx_mpdu_received; 2806 uint32_t rx_mpdu_missed; 2807 } ext_stats; 2808 qdf_event_t rx_hw_stats_event; 2809 qdf_spinlock_t rx_hw_stats_lock; 2810 bool is_last_stats_ctx_init; 2811 #endif /* WLAN_FEATURE_STATS_EXT */ 2812 2813 /* Indicates HTT map/unmap versions*/ 2814 uint8_t peer_map_unmap_versions; 2815 /* Per peer per Tid ba window size support */ 2816 uint8_t per_tid_basize_max_tid; 2817 /* Soc level flag to enable da_war */ 2818 uint8_t da_war_enabled; 2819 /* number of active ast entries */ 2820 uint32_t num_ast_entries; 2821 /* peer extended rate statistics context at soc level*/ 2822 struct cdp_soc_rate_stats_ctx *rate_stats_ctx; 2823 /* peer extended rate statistics control flag */ 2824 bool peerstats_enabled; 2825 2826 /* 8021p PCP-TID map values */ 2827 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 2828 /* TID map priority value */ 2829 uint8_t tidmap_prty; 2830 /* Pointer to global per ring type specific configuration table */ 2831 struct wlan_srng_cfg *wlan_srng_cfg; 2832 /* Num Tx outstanding on device */ 2833 qdf_atomic_t num_tx_outstanding; 2834 /* Num Tx exception on device */ 2835 qdf_atomic_t num_tx_exception; 2836 /* Num Tx allowed */ 2837 uint32_t num_tx_allowed; 2838 /* Num Regular Tx allowed */ 2839 uint32_t num_reg_tx_allowed; 2840 /* Num Tx allowed for special frames*/ 2841 uint32_t num_tx_spl_allowed; 2842 /* Preferred HW mode */ 2843 uint8_t preferred_hw_mode; 2844 2845 /** 2846 * Flag to indicate whether WAR to address single cache entry 2847 * invalidation bug is enabled or not 2848 */ 2849 bool is_rx_fse_full_cache_invalidate_war_enabled; 2850 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) || defined(WLAN_SUPPORT_RX_FISA) 2851 /** 2852 * Pointer to DP RX Flow FST at SOC level if 2853 * is_rx_flow_search_table_per_pdev is false 2854 * TBD: rx_fst[num_macs] if we decide to have per mac FST 2855 */ 2856 struct dp_rx_fst *rx_fst; 2857 #ifdef WLAN_SUPPORT_RX_FISA 2858 uint8_t fisa_enable; 2859 uint8_t fisa_lru_del_enable; 2860 /** 2861 * Params used for controlling the fisa aggregation dynamically 2862 */ 2863 struct { 2864 qdf_atomic_t skip_fisa; 2865 uint8_t fisa_force_flush[MAX_REO_DEST_RINGS]; 2866 } skip_fisa_param; 2867 2868 /** 2869 * CMEM address and size for FST in CMEM, This is the address 2870 * shared during init time. 2871 */ 2872 uint64_t fst_cmem_base; 2873 uint64_t fst_cmem_size; 2874 #endif 2875 #endif /* WLAN_SUPPORT_RX_FLOW_TAG || WLAN_SUPPORT_RX_FISA */ 2876 /* SG supported for msdu continued packets from wbm release ring */ 2877 bool wbm_release_desc_rx_sg_support; 2878 bool peer_map_attach_success; 2879 /* Flag to disable mac1 ring interrupts */ 2880 bool disable_mac1_intr; 2881 /* Flag to disable mac2 ring interrupts */ 2882 bool disable_mac2_intr; 2883 2884 struct { 2885 /* 1st msdu in sg for msdu continued packets in wbm rel ring */ 2886 bool wbm_is_first_msdu_in_sg; 2887 /* Wbm sg list head */ 2888 qdf_nbuf_t wbm_sg_nbuf_head; 2889 /* Wbm sg list tail */ 2890 qdf_nbuf_t wbm_sg_nbuf_tail; 2891 uint32_t wbm_sg_desc_msdu_len; 2892 } wbm_sg_param; 2893 /* Number of msdu exception descriptors */ 2894 uint32_t num_msdu_exception_desc; 2895 2896 /* RX buffer params */ 2897 struct rx_buff_pool rx_buff_pool[MAX_PDEV_CNT]; 2898 struct rx_refill_buff_pool rx_refill_buff_pool; 2899 /* Save recent operation related variable */ 2900 struct dp_last_op_info last_op_info; 2901 TAILQ_HEAD(, dp_peer) inactive_peer_list; 2902 qdf_spinlock_t inactive_peer_list_lock; 2903 TAILQ_HEAD(, dp_vdev) inactive_vdev_list; 2904 qdf_spinlock_t inactive_vdev_list_lock; 2905 /* lock to protect vdev_id_map table*/ 2906 qdf_spinlock_t vdev_map_lock; 2907 2908 /* Flow Search Table is in CMEM */ 2909 bool fst_in_cmem; 2910 2911 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 2912 struct dp_swlm swlm; 2913 #endif 2914 2915 #ifdef FEATURE_RUNTIME_PM 2916 /* DP Rx timestamp */ 2917 qdf_time_t rx_last_busy; 2918 /* Dp runtime refcount */ 2919 qdf_atomic_t dp_runtime_refcount; 2920 /* Dp tx pending count in RTPM */ 2921 qdf_atomic_t tx_pending_rtpm; 2922 #endif 2923 /* Invalid buffer that allocated for RX buffer */ 2924 qdf_nbuf_queue_t invalid_buf_queue; 2925 2926 #ifdef FEATURE_MEC 2927 /** @mec_lock: spinlock for MEC table */ 2928 qdf_spinlock_t mec_lock; 2929 /** @mec_cnt: number of active mec entries */ 2930 qdf_atomic_t mec_cnt; 2931 struct { 2932 /** @mask: mask bits */ 2933 uint32_t mask; 2934 /** @idx_bits: index to shift bits */ 2935 uint32_t idx_bits; 2936 /** @bins: MEC table */ 2937 TAILQ_HEAD(, dp_mec_entry) * bins; 2938 } mec_hash; 2939 #endif 2940 2941 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 2942 qdf_list_t reo_desc_deferred_freelist; 2943 qdf_spinlock_t reo_desc_deferred_freelist_lock; 2944 bool reo_desc_deferred_freelist_init; 2945 #endif 2946 /* BM id for first WBM2SW ring */ 2947 uint32_t wbm_sw0_bm_id; 2948 2949 /* Store arch_id from device_id */ 2950 uint16_t arch_id; 2951 2952 /* link desc ID start per device type */ 2953 uint32_t link_desc_id_start; 2954 2955 /* CMEM buffer target reserved for host usage */ 2956 uint64_t cmem_base; 2957 /* CMEM size in bytes */ 2958 uint64_t cmem_total_size; 2959 /* CMEM free size in bytes */ 2960 uint64_t cmem_avail_size; 2961 2962 /* SOC level feature flags */ 2963 struct dp_soc_features features; 2964 2965 #ifdef WIFI_MONITOR_SUPPORT 2966 struct dp_mon_soc *monitor_soc; 2967 #endif 2968 uint8_t rxdma2sw_rings_not_supported:1, 2969 wbm_sg_last_msdu_war:1, 2970 mec_fw_offload:1, 2971 multi_peer_grp_cmd_supported:1; 2972 2973 /* Number of Rx refill rings */ 2974 uint8_t num_rx_refill_buf_rings; 2975 #ifdef FEATURE_RUNTIME_PM 2976 /* flag to indicate vote for runtime_pm for high tput castt*/ 2977 qdf_atomic_t rtpm_high_tput_flag; 2978 #endif 2979 /* Buffer manager ID for idle link descs */ 2980 uint8_t idle_link_bm_id; 2981 qdf_atomic_t ref_count; 2982 2983 unsigned long vdev_stats_id_map; 2984 bool txmon_hw_support; 2985 2986 #ifdef DP_UMAC_HW_RESET_SUPPORT 2987 struct dp_soc_umac_reset_ctx umac_reset_ctx; 2988 #endif 2989 /* PPDU to link_id mapping parameters */ 2990 uint8_t link_id_offset; 2991 uint8_t link_id_bits; 2992 #ifdef FEATURE_RX_LINKSPEED_ROAM_TRIGGER 2993 /* A flag using to decide the switch of rx link speed */ 2994 bool high_throughput; 2995 #endif 2996 bool is_tx_pause; 2997 2998 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 2999 /* number of IPv4 flows inserted */ 3000 qdf_atomic_t ipv4_fse_cnt; 3001 /* number of IPv6 flows inserted */ 3002 qdf_atomic_t ipv6_fse_cnt; 3003 #endif 3004 }; 3005 3006 #ifdef IPA_OFFLOAD 3007 /** 3008 * struct dp_ipa_resources - Resources needed for IPA 3009 * @tx_ring: 3010 * @tx_num_alloc_buffer: 3011 * @tx_comp_ring: 3012 * @rx_rdy_ring: 3013 * @rx_refill_ring: 3014 * @tx_comp_doorbell_paddr: IPA UC doorbell registers paddr 3015 * @tx_comp_doorbell_vaddr: 3016 * @rx_ready_doorbell_paddr: 3017 * @is_db_ddr_mapped: 3018 * @tx_alt_ring: 3019 * @tx_alt_ring_num_alloc_buffer: 3020 * @tx_alt_comp_ring: 3021 * @tx_alt_comp_doorbell_paddr: IPA UC doorbell registers paddr 3022 * @tx_alt_comp_doorbell_vaddr: 3023 * @rx_alt_rdy_ring: 3024 * @rx_alt_refill_ring: 3025 * @rx_alt_ready_doorbell_paddr: 3026 */ 3027 struct dp_ipa_resources { 3028 qdf_shared_mem_t tx_ring; 3029 uint32_t tx_num_alloc_buffer; 3030 3031 qdf_shared_mem_t tx_comp_ring; 3032 qdf_shared_mem_t rx_rdy_ring; 3033 qdf_shared_mem_t rx_refill_ring; 3034 3035 /* IPA UC doorbell registers paddr */ 3036 qdf_dma_addr_t tx_comp_doorbell_paddr; 3037 uint32_t *tx_comp_doorbell_vaddr; 3038 qdf_dma_addr_t rx_ready_doorbell_paddr; 3039 3040 bool is_db_ddr_mapped; 3041 3042 #ifdef IPA_WDI3_TX_TWO_PIPES 3043 qdf_shared_mem_t tx_alt_ring; 3044 uint32_t tx_alt_ring_num_alloc_buffer; 3045 qdf_shared_mem_t tx_alt_comp_ring; 3046 3047 /* IPA UC doorbell registers paddr */ 3048 qdf_dma_addr_t tx_alt_comp_doorbell_paddr; 3049 uint32_t *tx_alt_comp_doorbell_vaddr; 3050 #endif 3051 #ifdef IPA_WDI3_VLAN_SUPPORT 3052 qdf_shared_mem_t rx_alt_rdy_ring; 3053 qdf_shared_mem_t rx_alt_refill_ring; 3054 qdf_dma_addr_t rx_alt_ready_doorbell_paddr; 3055 #endif 3056 }; 3057 #endif 3058 3059 #define MAX_RX_MAC_RINGS 2 3060 /* Same as NAC_MAX_CLENT */ 3061 #define DP_NAC_MAX_CLIENT 24 3062 3063 /* 3064 * 24 bits cookie size 3065 * 10 bits page id 0 ~ 1023 for MCL 3066 * 3 bits page id 0 ~ 7 for WIN 3067 * WBM Idle List Desc size = 128, 3068 * Num descs per page = 4096/128 = 32 for MCL 3069 * Num descs per page = 2MB/128 = 16384 for WIN 3070 */ 3071 /* 3072 * Macros to setup link descriptor cookies - for link descriptors, we just 3073 * need first 3 bits to store bank/page ID for WIN. The 3074 * remaining bytes will be used to set a unique ID, which will 3075 * be useful in debugging 3076 */ 3077 #ifdef MAX_ALLOC_PAGE_SIZE 3078 #if PAGE_SIZE == 4096 3079 #define LINK_DESC_PAGE_ID_MASK 0x007FE0 3080 #define LINK_DESC_ID_SHIFT 5 3081 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 3082 #elif PAGE_SIZE == 65536 3083 #define LINK_DESC_PAGE_ID_MASK 0x007E00 3084 #define LINK_DESC_ID_SHIFT 9 3085 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x800 3086 #else 3087 #error "Unsupported kernel PAGE_SIZE" 3088 #endif 3089 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 3090 ((((_page_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_desc_id)) 3091 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 3092 (((_cookie) & LINK_DESC_PAGE_ID_MASK) >> LINK_DESC_ID_SHIFT) 3093 #else 3094 #define LINK_DESC_PAGE_ID_MASK 0x7 3095 #define LINK_DESC_ID_SHIFT 3 3096 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 3097 ((((_desc_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_page_id)) 3098 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 3099 ((_cookie) & LINK_DESC_PAGE_ID_MASK) 3100 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 3101 #endif 3102 #define LINK_DESC_ID_START_20_BITS_COOKIE 0x4000 3103 3104 /* same as ieee80211_nac_param */ 3105 enum dp_nac_param_cmd { 3106 /* IEEE80211_NAC_PARAM_ADD */ 3107 DP_NAC_PARAM_ADD = 1, 3108 /* IEEE80211_NAC_PARAM_DEL */ 3109 DP_NAC_PARAM_DEL, 3110 /* IEEE80211_NAC_PARAM_LIST */ 3111 DP_NAC_PARAM_LIST, 3112 }; 3113 3114 /** 3115 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 3116 * @neighbour_peers_macaddr: neighbour peer's mac address 3117 * @vdev: associated vdev 3118 * @ast_entry: ast_entry for neighbour peer 3119 * @rssi: rssi value 3120 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 3121 */ 3122 struct dp_neighbour_peer { 3123 union dp_align_mac_addr neighbour_peers_macaddr; 3124 struct dp_vdev *vdev; 3125 struct dp_ast_entry *ast_entry; 3126 uint8_t rssi; 3127 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 3128 }; 3129 3130 #ifdef WLAN_TX_PKT_CAPTURE_ENH 3131 #define WLAN_TX_PKT_CAPTURE_ENH 1 3132 #define DP_TX_PPDU_PROC_THRESHOLD 8 3133 #define DP_TX_PPDU_PROC_TIMEOUT 10 3134 #endif 3135 3136 /** 3137 * struct ppdu_info - PPDU Status info descriptor 3138 * @ppdu_id: Unique ppduid assigned by firmware for every tx packet 3139 * @sched_cmdid: schedule command id, which will be same in a burst 3140 * @max_ppdu_id: wrap around for ppdu id 3141 * @tsf_l32: 3142 * @tlv_bitmap: 3143 * @last_tlv_cnt: Keep track for missing ppdu tlvs 3144 * @last_user: last ppdu processed for user 3145 * @is_ampdu: set if Ampdu aggregate 3146 * @nbuf: ppdu descriptor payload 3147 * @ppdu_desc: ppdu descriptor 3148 * @ulist: Union of lists 3149 * @ppdu_info_dlist_elem: linked list of ppdu tlvs 3150 * @ppdu_info_slist_elem: Singly linked list (queue) of ppdu tlvs 3151 * @ppdu_info_list_elem: linked list of ppdu tlvs 3152 * @ppdu_info_queue_elem: Singly linked list (queue) of ppdu tlvs 3153 * @compltn_common_tlv: Successful tlv counter from COMPLTN COMMON tlv 3154 * @ack_ba_tlv: Successful tlv counter from ACK BA tlv 3155 * @done: 3156 */ 3157 struct ppdu_info { 3158 uint32_t ppdu_id; 3159 uint32_t sched_cmdid; 3160 uint32_t max_ppdu_id; 3161 uint32_t tsf_l32; 3162 uint16_t tlv_bitmap; 3163 uint16_t last_tlv_cnt; 3164 uint16_t last_user:8, 3165 is_ampdu:1; 3166 qdf_nbuf_t nbuf; 3167 struct cdp_tx_completion_ppdu *ppdu_desc; 3168 #ifdef WLAN_TX_PKT_CAPTURE_ENH 3169 union { 3170 TAILQ_ENTRY(ppdu_info) ppdu_info_dlist_elem; 3171 STAILQ_ENTRY(ppdu_info) ppdu_info_slist_elem; 3172 } ulist; 3173 #define ppdu_info_list_elem ulist.ppdu_info_dlist_elem 3174 #define ppdu_info_queue_elem ulist.ppdu_info_slist_elem 3175 #else 3176 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 3177 #endif 3178 uint8_t compltn_common_tlv; 3179 uint8_t ack_ba_tlv; 3180 bool done; 3181 }; 3182 3183 /** 3184 * struct msdu_completion_info - wbm msdu completion info 3185 * @ppdu_id: Unique ppduid assigned by firmware for every tx packet 3186 * @peer_id: peer_id 3187 * @tid: tid which used during transmit 3188 * @first_msdu: first msdu indication 3189 * @last_msdu: last msdu indication 3190 * @msdu_part_of_amsdu: msdu part of amsdu 3191 * @transmit_cnt: retried count 3192 * @status: transmit status 3193 * @tsf: timestamp which it transmitted 3194 */ 3195 struct msdu_completion_info { 3196 uint32_t ppdu_id; 3197 uint16_t peer_id; 3198 uint8_t tid; 3199 uint8_t first_msdu:1, 3200 last_msdu:1, 3201 msdu_part_of_amsdu:1; 3202 uint8_t transmit_cnt; 3203 uint8_t status; 3204 uint32_t tsf; 3205 }; 3206 3207 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 3208 struct rx_protocol_tag_map { 3209 /* This is the user configured tag for the said protocol type */ 3210 uint16_t tag; 3211 }; 3212 3213 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 3214 /** 3215 * struct rx_protocol_tag_stats - protocol statistics 3216 * @tag_ctr: number of rx msdus matching this tag 3217 */ 3218 struct rx_protocol_tag_stats { 3219 uint32_t tag_ctr; 3220 }; 3221 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 3222 3223 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 3224 3225 #ifdef WLAN_RX_PKT_CAPTURE_ENH 3226 /* Template data to be set for Enhanced RX Monitor packets */ 3227 #define RX_MON_CAP_ENH_TRAILER 0xdeadc0dedeadda7a 3228 3229 /** 3230 * struct dp_rx_mon_enh_trailer_data - Data structure to set a known pattern 3231 * at end of each MSDU in monitor-lite mode 3232 * @reserved1: reserved for future use 3233 * @reserved2: reserved for future use 3234 * @flow_tag: flow tag value read from skb->cb 3235 * @protocol_tag: protocol tag value read from skb->cb 3236 */ 3237 struct dp_rx_mon_enh_trailer_data { 3238 uint16_t reserved1; 3239 uint16_t reserved2; 3240 uint16_t flow_tag; 3241 uint16_t protocol_tag; 3242 }; 3243 #endif /* WLAN_RX_PKT_CAPTURE_ENH */ 3244 3245 #ifdef HTT_STATS_DEBUGFS_SUPPORT 3246 /* Number of debugfs entries created for HTT stats */ 3247 #define PDEV_HTT_STATS_DBGFS_SIZE HTT_DBG_NUM_EXT_STATS 3248 3249 /** 3250 * struct pdev_htt_stats_dbgfs_priv - Structure to maintain debugfs information 3251 * of HTT stats 3252 * @pdev: dp pdev of debugfs entry 3253 * @stats_id: stats id of debugfs entry 3254 */ 3255 struct pdev_htt_stats_dbgfs_priv { 3256 struct dp_pdev *pdev; 3257 uint16_t stats_id; 3258 }; 3259 3260 /** 3261 * struct pdev_htt_stats_dbgfs_cfg - PDEV level data structure for debugfs 3262 * support for HTT stats 3263 * @debugfs_entry: qdf_debugfs directory entry 3264 * @m: qdf debugfs file handler 3265 * @pdev_htt_stats_dbgfs_ops: File operations of entry created 3266 * @priv: HTT stats debugfs private object 3267 * @htt_stats_dbgfs_event: HTT stats event for debugfs support 3268 * @lock: HTT stats debugfs lock 3269 * @htt_stats_dbgfs_msg_process: Function callback to print HTT stats 3270 */ 3271 struct pdev_htt_stats_dbgfs_cfg { 3272 qdf_dentry_t debugfs_entry[PDEV_HTT_STATS_DBGFS_SIZE]; 3273 qdf_debugfs_file_t m; 3274 struct qdf_debugfs_fops 3275 pdev_htt_stats_dbgfs_ops[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 3276 struct pdev_htt_stats_dbgfs_priv priv[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 3277 qdf_event_t htt_stats_dbgfs_event; 3278 qdf_mutex_t lock; 3279 void (*htt_stats_dbgfs_msg_process)(void *data, A_INT32 len); 3280 }; 3281 #endif /* HTT_STATS_DEBUGFS_SUPPORT */ 3282 3283 struct dp_srng_ring_state { 3284 enum hal_ring_type ring_type; 3285 uint32_t sw_head; 3286 uint32_t sw_tail; 3287 uint32_t hw_head; 3288 uint32_t hw_tail; 3289 3290 }; 3291 3292 struct dp_soc_srngs_state { 3293 uint32_t seq_num; 3294 uint32_t max_ring_id; 3295 struct dp_srng_ring_state ring_state[DP_MAX_SRNGS]; 3296 TAILQ_ENTRY(dp_soc_srngs_state) list_elem; 3297 }; 3298 3299 #ifdef WLAN_FEATURE_11BE_MLO 3300 /* struct dp_mlo_sync_timestamp - PDEV level data structure for storing 3301 * MLO timestamp received via HTT msg. 3302 * msg_type: This would be set to HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 3303 * pdev_id: pdev_id 3304 * chip_id: chip_id 3305 * mac_clk_freq: mac clock frequency of the mac HW block in MHz 3306 * sync_tstmp_lo_us: lower 32 bits of the WLAN global time stamp (in us) at 3307 * which last sync interrupt was received 3308 * sync_tstmp_hi_us: upper 32 bits of the WLAN global time stamp (in us) at 3309 * which last sync interrupt was received 3310 * mlo_offset_lo_us: lower 32 bits of the MLO time stamp offset in us 3311 * mlo_offset_hi_us: upper 32 bits of the MLO time stamp offset in us 3312 * mlo_offset_clks: MLO time stamp offset in clock ticks for sub us 3313 * mlo_comp_us: MLO time stamp compensation applied in us 3314 * mlo_comp_clks: MLO time stamp compensation applied in clock ticks 3315 * for sub us resolution 3316 * mlo_comp_timer: period of MLO compensation timer at which compensation 3317 * is applied, in us 3318 */ 3319 struct dp_mlo_sync_timestamp { 3320 uint32_t msg_type:8, 3321 pdev_id:2, 3322 chip_id:2, 3323 rsvd1:4, 3324 mac_clk_freq:16; 3325 uint32_t sync_tstmp_lo_us; 3326 uint32_t sync_tstmp_hi_us; 3327 uint32_t mlo_offset_lo_us; 3328 uint32_t mlo_offset_hi_us; 3329 uint32_t mlo_offset_clks; 3330 uint32_t mlo_comp_us:16, 3331 mlo_comp_clks:10, 3332 rsvd2:6; 3333 uint32_t mlo_comp_timer:22, 3334 rsvd3:10; 3335 }; 3336 #endif 3337 3338 /* PDEV level structure for data path */ 3339 struct dp_pdev { 3340 /** 3341 * Re-use Memory Section Starts 3342 */ 3343 3344 /* PDEV Id */ 3345 uint8_t pdev_id; 3346 3347 /* LMAC Id */ 3348 uint8_t lmac_id; 3349 3350 /* Target pdev Id */ 3351 uint8_t target_pdev_id; 3352 3353 bool pdev_deinit; 3354 3355 /* TXRX SOC handle */ 3356 struct dp_soc *soc; 3357 3358 /* pdev status down or up required to handle dynamic hw 3359 * mode switch between DBS and DBS_SBS. 3360 * 1 = down 3361 * 0 = up 3362 */ 3363 bool is_pdev_down; 3364 3365 /* Enhanced Stats is enabled */ 3366 bool enhanced_stats_en; 3367 3368 /* Flag to indicate fast RX */ 3369 bool rx_fast_flag; 3370 3371 /* Second ring used to replenish rx buffers */ 3372 struct dp_srng rx_refill_buf_ring2; 3373 #ifdef IPA_WDI3_VLAN_SUPPORT 3374 /* Third ring used to replenish rx buffers */ 3375 struct dp_srng rx_refill_buf_ring3; 3376 #endif 3377 3378 #ifdef FEATURE_DIRECT_LINK 3379 /* Fourth ring used to replenish rx buffers */ 3380 struct dp_srng rx_refill_buf_ring4; 3381 #endif 3382 3383 /* Empty ring used by firmware to post rx buffers to the MAC */ 3384 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 3385 3386 int ch_band_lmac_id_mapping[REG_BAND_UNKNOWN]; 3387 3388 /* wlan_cfg pdev ctxt*/ 3389 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 3390 3391 /** 3392 * TODO: See if we need a ring map here for LMAC rings. 3393 * 1. Monitor rings are currently planning to be processed on receiving 3394 * PPDU end interrupts and hence won't need ring based interrupts. 3395 * 2. Rx buffer rings will be replenished during REO destination 3396 * processing and doesn't require regular interrupt handling - we will 3397 * only handle low water mark interrupts which is not expected 3398 * frequently 3399 */ 3400 3401 /* VDEV list */ 3402 TAILQ_HEAD(, dp_vdev) vdev_list; 3403 3404 /* vdev list lock */ 3405 qdf_spinlock_t vdev_list_lock; 3406 3407 /* Number of vdevs this device have */ 3408 uint16_t vdev_count; 3409 3410 /* PDEV transmit lock */ 3411 qdf_spinlock_t tx_lock; 3412 3413 /*tx_mutex for me*/ 3414 DP_MUTEX_TYPE tx_mutex; 3415 3416 /* msdu chain head & tail */ 3417 qdf_nbuf_t invalid_peer_head_msdu; 3418 qdf_nbuf_t invalid_peer_tail_msdu; 3419 3420 /* Band steering */ 3421 /* TBD */ 3422 3423 /* PDEV level data path statistics */ 3424 struct cdp_pdev_stats stats; 3425 3426 /* Global RX decap mode for the device */ 3427 enum htt_pkt_type rx_decap_mode; 3428 3429 qdf_atomic_t num_tx_outstanding; 3430 int32_t tx_descs_max; 3431 3432 qdf_atomic_t num_tx_exception; 3433 3434 /* MCL specific local peer handle */ 3435 struct { 3436 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 3437 uint8_t freelist; 3438 qdf_spinlock_t lock; 3439 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 3440 } local_peer_ids; 3441 3442 /* dscp_tid_map_*/ 3443 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 3444 3445 /* operating channel */ 3446 struct { 3447 uint8_t num; 3448 uint8_t band; 3449 uint16_t freq; 3450 } operating_channel; 3451 3452 /* pool addr for mcast enhance buff */ 3453 struct { 3454 int size; 3455 uint32_t paddr; 3456 char *vaddr; 3457 struct dp_tx_me_buf_t *freelist; 3458 int buf_in_use; 3459 qdf_dma_mem_context(memctx); 3460 } me_buf; 3461 3462 bool hmmc_tid_override_en; 3463 uint8_t hmmc_tid; 3464 3465 /* Number of VAPs with mcast enhancement enabled */ 3466 qdf_atomic_t mc_num_vap_attached; 3467 3468 qdf_atomic_t stats_cmd_complete; 3469 3470 #ifdef IPA_OFFLOAD 3471 ipa_uc_op_cb_type ipa_uc_op_cb; 3472 void *usr_ctxt; 3473 struct dp_ipa_resources ipa_resource; 3474 #endif 3475 3476 /* TBD */ 3477 3478 /* map this pdev to a particular Reo Destination ring */ 3479 enum cdp_host_reo_dest_ring reo_dest; 3480 3481 /* WDI event handlers */ 3482 struct wdi_event_subscribe_t **wdi_event_list; 3483 3484 bool cfr_rcc_mode; 3485 3486 /* enable time latency check for tx completion */ 3487 bool latency_capture_enable; 3488 3489 /* enable calculation of delay stats*/ 3490 bool delay_stats_flag; 3491 void *dp_txrx_handle; /* Advanced data path handle */ 3492 uint32_t ppdu_id; 3493 bool first_nbuf; 3494 /* Current noise-floor reading for the pdev channel */ 3495 int16_t chan_noise_floor; 3496 3497 /* 3498 * For multiradio device, this flag indicates if 3499 * this radio is primary or secondary. 3500 * 3501 * For HK 1.0, this is used for WAR for the AST issue. 3502 * HK 1.x mandates creation of only 1 AST entry with same MAC address 3503 * across 2 radios. is_primary indicates the radio on which DP should 3504 * install HW AST entry if there is a request to add 2 AST entries 3505 * with same MAC address across 2 radios 3506 */ 3507 uint8_t is_primary; 3508 struct cdp_tx_sojourn_stats sojourn_stats; 3509 qdf_nbuf_t sojourn_buf; 3510 3511 union dp_rx_desc_list_elem_t *free_list_head; 3512 union dp_rx_desc_list_elem_t *free_list_tail; 3513 /* Cached peer_id from htt_peer_details_tlv */ 3514 uint16_t fw_stats_peer_id; 3515 3516 /* qdf_event for fw_peer_stats */ 3517 qdf_event_t fw_peer_stats_event; 3518 3519 /* qdf_event for fw_stats */ 3520 qdf_event_t fw_stats_event; 3521 3522 /* qdf_event for fw__obss_stats */ 3523 qdf_event_t fw_obss_stats_event; 3524 3525 /* To check if request is already sent for obss stats */ 3526 bool pending_fw_obss_stats_response; 3527 3528 /* User configured max number of tx buffers */ 3529 uint32_t num_tx_allowed; 3530 3531 /* 3532 * User configured max num of tx buffers excluding the 3533 * number of buffers reserved for handling special frames 3534 */ 3535 uint32_t num_reg_tx_allowed; 3536 3537 /* User configured max number of tx buffers for the special frames*/ 3538 uint32_t num_tx_spl_allowed; 3539 3540 /* unique cookie required for peer session */ 3541 uint32_t next_peer_cookie; 3542 3543 /* 3544 * Run time enabled when the first protocol tag is added, 3545 * run time disabled when the last protocol tag is deleted 3546 */ 3547 bool is_rx_protocol_tagging_enabled; 3548 3549 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 3550 /* 3551 * The protocol type is used as array index to save 3552 * user provided tag info 3553 */ 3554 struct rx_protocol_tag_map rx_proto_tag_map[RX_PROTOCOL_TAG_MAX]; 3555 3556 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 3557 /* 3558 * Track msdus received from each reo ring separately to avoid 3559 * simultaneous writes from different core 3560 */ 3561 struct rx_protocol_tag_stats 3562 reo_proto_tag_stats[MAX_REO_DEST_RINGS][RX_PROTOCOL_TAG_MAX]; 3563 /* Track msdus received from exception ring separately */ 3564 struct rx_protocol_tag_stats 3565 rx_err_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 3566 struct rx_protocol_tag_stats 3567 mon_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 3568 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 3569 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 3570 3571 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 3572 /** 3573 * Pointer to DP Flow FST at SOC level if 3574 * is_rx_flow_search_table_per_pdev is true 3575 */ 3576 struct dp_rx_fst *rx_fst; 3577 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 3578 3579 #ifdef FEATURE_TSO_STATS 3580 /* TSO Id to index into TSO packet information */ 3581 qdf_atomic_t tso_idx; 3582 #endif /* FEATURE_TSO_STATS */ 3583 3584 #ifdef WLAN_SUPPORT_DATA_STALL 3585 data_stall_detect_cb data_stall_detect_callback; 3586 #endif /* WLAN_SUPPORT_DATA_STALL */ 3587 3588 /* flag to indicate whether LRO hash command has been sent to FW */ 3589 uint8_t is_lro_hash_configured; 3590 3591 #ifdef HTT_STATS_DEBUGFS_SUPPORT 3592 /* HTT stats debugfs params */ 3593 struct pdev_htt_stats_dbgfs_cfg *dbgfs_cfg; 3594 #endif 3595 struct { 3596 qdf_work_t work; 3597 qdf_workqueue_t *work_queue; 3598 uint32_t seq_num; 3599 uint8_t queue_depth; 3600 qdf_spinlock_t list_lock; 3601 3602 TAILQ_HEAD(, dp_soc_srngs_state) list; 3603 } bkp_stats; 3604 #ifdef WIFI_MONITOR_SUPPORT 3605 struct dp_mon_pdev *monitor_pdev; 3606 #endif 3607 #ifdef WLAN_FEATURE_11BE_MLO 3608 struct dp_mlo_sync_timestamp timestamp; 3609 #endif 3610 /* Is isolation mode enabled */ 3611 bool isolation; 3612 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 3613 uint8_t is_first_wakeup_packet; 3614 #endif 3615 #ifdef CONNECTIVITY_PKTLOG 3616 /* packetdump callback functions */ 3617 ol_txrx_pktdump_cb dp_tx_packetdump_cb; 3618 ol_txrx_pktdump_cb dp_rx_packetdump_cb; 3619 #endif 3620 3621 /* Firmware Stats for TLV received from Firmware */ 3622 uint64_t fw_stats_tlv_bitmap_rcvd; 3623 3624 /* For Checking Pending Firmware Response */ 3625 bool pending_fw_stats_response; 3626 }; 3627 3628 struct dp_peer; 3629 3630 #ifdef DP_RX_UDP_OVER_PEER_ROAM 3631 #define WLAN_ROAM_PEER_AUTH_STATUS_NONE 0x0 3632 /* 3633 * This macro is equivalent to macro ROAM_AUTH_STATUS_AUTHENTICATED used 3634 * in connection mgr 3635 */ 3636 #define WLAN_ROAM_PEER_AUTH_STATUS_AUTHENTICATED 0x2 3637 #endif 3638 3639 /* VDEV structure for data path state */ 3640 struct dp_vdev { 3641 /* OS device abstraction */ 3642 qdf_device_t osdev; 3643 3644 /* physical device that is the parent of this virtual device */ 3645 struct dp_pdev *pdev; 3646 3647 /* VDEV operating mode */ 3648 enum wlan_op_mode opmode; 3649 3650 /* VDEV subtype */ 3651 enum wlan_op_subtype subtype; 3652 3653 /* Tx encapsulation type for this VAP */ 3654 enum htt_cmn_pkt_type tx_encap_type; 3655 3656 /* Rx Decapsulation type for this VAP */ 3657 enum htt_cmn_pkt_type rx_decap_type; 3658 3659 /* WDS enabled */ 3660 bool wds_enabled; 3661 3662 /* MEC enabled */ 3663 bool mec_enabled; 3664 3665 #ifdef QCA_SUPPORT_WDS_EXTENDED 3666 bool wds_ext_enabled; 3667 bool drop_tx_mcast; 3668 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 3669 bool drop_3addr_mcast; 3670 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 3671 bool skip_bar_update; 3672 unsigned long skip_bar_update_last_ts; 3673 #endif 3674 /* WDS Aging timer period */ 3675 uint32_t wds_aging_timer_val; 3676 3677 /* NAWDS enabled */ 3678 bool nawds_enabled; 3679 3680 /* Multicast enhancement enabled */ 3681 uint8_t mcast_enhancement_en; 3682 3683 /* IGMP multicast enhancement enabled */ 3684 uint8_t igmp_mcast_enhanc_en; 3685 3686 /* vdev_id - ID used to specify a particular vdev to the target */ 3687 uint8_t vdev_id; 3688 3689 /* Default HTT meta data for this VDEV */ 3690 /* TBD: check alignment constraints */ 3691 uint16_t htt_tcl_metadata; 3692 3693 /* vdev lmac_id */ 3694 uint8_t lmac_id; 3695 3696 /* vdev bank_id */ 3697 uint8_t bank_id; 3698 3699 /* Mesh mode vdev */ 3700 uint32_t mesh_vdev; 3701 3702 /* Mesh mode rx filter setting */ 3703 uint32_t mesh_rx_filter; 3704 3705 /* DSCP-TID mapping table ID */ 3706 uint8_t dscp_tid_map_id; 3707 3708 /* Address search type to be set in TX descriptor */ 3709 uint8_t search_type; 3710 3711 /* 3712 * Flag to indicate if s/w tid classification should be 3713 * skipped 3714 */ 3715 uint8_t skip_sw_tid_classification; 3716 3717 /* Flag to enable peer authorization */ 3718 uint8_t peer_authorize; 3719 3720 /* AST hash value for BSS peer in HW valid for STA VAP*/ 3721 uint16_t bss_ast_hash; 3722 3723 /* AST hash index for BSS peer in HW valid for STA VAP*/ 3724 uint16_t bss_ast_idx; 3725 3726 bool multipass_en; 3727 3728 /* Address search flags to be configured in HAL descriptor */ 3729 uint8_t hal_desc_addr_search_flags; 3730 3731 /* Handle to the OS shim SW's virtual device */ 3732 ol_osif_vdev_handle osif_vdev; 3733 3734 /* MAC address */ 3735 union dp_align_mac_addr mac_addr; 3736 3737 #ifdef WLAN_FEATURE_11BE_MLO 3738 /* MLO MAC address corresponding to vdev */ 3739 union dp_align_mac_addr mld_mac_addr; 3740 #if defined(WLAN_MLO_MULTI_CHIP) && defined(WLAN_MCAST_MLO) 3741 bool mlo_vdev; 3742 #endif 3743 #endif 3744 3745 /* node in the pdev's list of vdevs */ 3746 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 3747 3748 /* dp_peer list */ 3749 TAILQ_HEAD(, dp_peer) peer_list; 3750 /* to protect peer_list */ 3751 DP_MUTEX_TYPE peer_list_lock; 3752 3753 /* RX call back function to flush GRO packets*/ 3754 ol_txrx_rx_gro_flush_ind_fp osif_gro_flush; 3755 /* default RX call back function called by dp */ 3756 ol_txrx_rx_fp osif_rx; 3757 #ifdef QCA_SUPPORT_EAPOL_OVER_CONTROL_PORT 3758 /* callback to receive eapol frames */ 3759 ol_txrx_rx_fp osif_rx_eapol; 3760 #endif 3761 /* callback to deliver rx frames to the OS */ 3762 ol_txrx_rx_fp osif_rx_stack; 3763 /* Callback to handle rx fisa frames */ 3764 ol_txrx_fisa_rx_fp osif_fisa_rx; 3765 ol_txrx_fisa_flush_fp osif_fisa_flush; 3766 3767 /* call back function to flush out queued rx packets*/ 3768 ol_txrx_rx_flush_fp osif_rx_flush; 3769 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 3770 ol_txrx_get_key_fp osif_get_key; 3771 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 3772 3773 #ifdef notyet 3774 /* callback to check if the msdu is an WAI (WAPI) frame */ 3775 ol_rx_check_wai_fp osif_check_wai; 3776 #endif 3777 3778 /* proxy arp function */ 3779 ol_txrx_proxy_arp_fp osif_proxy_arp; 3780 3781 ol_txrx_mcast_me_fp me_convert; 3782 3783 /* completion function used by this vdev*/ 3784 ol_txrx_completion_fp tx_comp; 3785 3786 ol_txrx_get_tsf_time get_tsf_time; 3787 3788 /* callback to classify critical packets */ 3789 ol_txrx_classify_critical_pkt_fp tx_classify_critical_pkt_cb; 3790 3791 /* deferred vdev deletion state */ 3792 struct { 3793 /* VDEV delete pending */ 3794 int pending; 3795 /* 3796 * callback and a context argument to provide a 3797 * notification for when the vdev is deleted. 3798 */ 3799 ol_txrx_vdev_delete_cb callback; 3800 void *context; 3801 } delete; 3802 3803 /* tx data delivery notification callback function */ 3804 struct { 3805 ol_txrx_data_tx_cb func; 3806 void *ctxt; 3807 } tx_non_std_data_callback; 3808 3809 3810 /* safe mode control to bypass the encrypt and decipher process*/ 3811 uint32_t safemode; 3812 3813 /* rx filter related */ 3814 uint32_t drop_unenc; 3815 #ifdef notyet 3816 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 3817 uint32_t filters_num; 3818 #endif 3819 /* TDLS Link status */ 3820 bool tdls_link_connected; 3821 bool is_tdls_frame; 3822 3823 /* per vdev rx nbuf queue */ 3824 qdf_nbuf_queue_t rxq; 3825 3826 uint8_t tx_ring_id; 3827 struct dp_tx_desc_pool_s *tx_desc; 3828 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 3829 3830 /* Capture timestamp of previous tx packet enqueued */ 3831 uint64_t prev_tx_enq_tstamp; 3832 3833 /* Capture timestamp of previous rx packet delivered */ 3834 uint64_t prev_rx_deliver_tstamp; 3835 3836 /* VDEV Stats */ 3837 struct cdp_vdev_stats stats; 3838 3839 /* Is this a proxySTA VAP */ 3840 uint8_t proxysta_vdev : 1, /* Is this a proxySTA VAP */ 3841 wrap_vdev : 1, /* Is this a QWRAP AP VAP */ 3842 isolation_vdev : 1, /* Is this a QWRAP AP VAP */ 3843 reserved : 5; /* Reserved */ 3844 3845 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 3846 struct dp_tx_desc_pool_s *pool; 3847 #endif 3848 /* AP BRIDGE enabled */ 3849 bool ap_bridge_enabled; 3850 3851 enum cdp_sec_type sec_type; 3852 3853 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 3854 bool raw_mode_war; 3855 3856 3857 /* 8021p PCP-TID mapping table ID */ 3858 uint8_t tidmap_tbl_id; 3859 3860 /* 8021p PCP-TID map values */ 3861 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 3862 3863 /* TIDmap priority */ 3864 uint8_t tidmap_prty; 3865 3866 #ifdef QCA_MULTIPASS_SUPPORT 3867 uint16_t *iv_vlan_map; 3868 3869 /* dp_peer special list */ 3870 TAILQ_HEAD(, dp_txrx_peer) mpass_peer_list; 3871 DP_MUTEX_TYPE mpass_peer_mutex; 3872 #endif 3873 /* Extended data path handle */ 3874 struct cdp_ext_vdev *vdev_dp_ext_handle; 3875 #ifdef VDEV_PEER_PROTOCOL_COUNT 3876 /* 3877 * Rx-Ingress and Tx-Egress are in the lower level DP layer 3878 * Rx-Egress and Tx-ingress are handled in osif layer for DP 3879 * So 3880 * Rx-Egress and Tx-ingress mask definitions are in OSIF layer 3881 * Rx-Ingress and Tx-Egress definitions are here below 3882 */ 3883 #define VDEV_PEER_PROTOCOL_RX_INGRESS_MASK 1 3884 #define VDEV_PEER_PROTOCOL_TX_INGRESS_MASK 2 3885 #define VDEV_PEER_PROTOCOL_RX_EGRESS_MASK 4 3886 #define VDEV_PEER_PROTOCOL_TX_EGRESS_MASK 8 3887 bool peer_protocol_count_track; 3888 int peer_protocol_count_dropmask; 3889 #endif 3890 /* callback to collect connectivity stats */ 3891 ol_txrx_stats_rx_fp stats_cb; 3892 uint32_t num_peers; 3893 /* entry to inactive_list*/ 3894 TAILQ_ENTRY(dp_vdev) inactive_list_elem; 3895 3896 #ifdef WLAN_SUPPORT_RX_FISA 3897 /** 3898 * Params used for controlling the fisa aggregation dynamically 3899 */ 3900 uint8_t fisa_disallowed[MAX_REO_DEST_RINGS]; 3901 uint8_t fisa_force_flushed[MAX_REO_DEST_RINGS]; 3902 #endif 3903 /* 3904 * Refcount for VDEV currently incremented when 3905 * peer is created for VDEV 3906 */ 3907 qdf_atomic_t ref_cnt; 3908 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 3909 uint8_t num_latency_critical_conn; 3910 #ifdef WLAN_SUPPORT_MESH_LATENCY 3911 uint8_t peer_tid_latency_enabled; 3912 /* tid latency configuration parameters */ 3913 struct { 3914 uint32_t service_interval; 3915 uint32_t burst_size; 3916 uint8_t latency_tid; 3917 } mesh_tid_latency_config; 3918 #endif 3919 #ifdef WIFI_MONITOR_SUPPORT 3920 struct dp_mon_vdev *monitor_vdev; 3921 #endif 3922 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY) 3923 /* Delta between TQM clock and TSF clock */ 3924 uint32_t delta_tsf; 3925 #endif 3926 #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY 3927 /* Indicate if uplink delay report is enabled or not */ 3928 qdf_atomic_t ul_delay_report; 3929 /* accumulative delay for every TX completion */ 3930 qdf_atomic_t ul_delay_accum; 3931 /* accumulative number of packets delay has accumulated */ 3932 qdf_atomic_t ul_pkts_accum; 3933 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */ 3934 3935 /* vdev_stats_id - ID used for stats collection by FW from HW*/ 3936 uint8_t vdev_stats_id; 3937 #ifdef HW_TX_DELAY_STATS_ENABLE 3938 /* hw tx delay stats enable */ 3939 uint8_t hw_tx_delay_stats_enabled; 3940 #endif 3941 #ifdef DP_RX_UDP_OVER_PEER_ROAM 3942 uint32_t roaming_peer_status; 3943 union dp_align_mac_addr roaming_peer_mac; 3944 #endif 3945 #ifdef DP_TRAFFIC_END_INDICATION 3946 /* per vdev feature enable/disable status */ 3947 bool traffic_end_ind_en; 3948 /* per vdev nbuf queue for traffic end indication packets */ 3949 qdf_nbuf_queue_t end_ind_pkt_q; 3950 #endif 3951 #ifdef FEATURE_DIRECT_LINK 3952 /* Flag to indicate if to_fw should be set for tx pkts on this vdev */ 3953 bool to_fw; 3954 #endif 3955 }; 3956 3957 enum { 3958 dp_sec_mcast = 0, 3959 dp_sec_ucast 3960 }; 3961 3962 #ifdef WDS_VENDOR_EXTENSION 3963 typedef struct { 3964 uint8_t wds_tx_mcast_4addr:1, 3965 wds_tx_ucast_4addr:1, 3966 wds_rx_filter:1, /* enforce rx filter */ 3967 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 3968 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 3969 3970 } dp_ecm_policy; 3971 #endif 3972 3973 /** 3974 * struct dp_peer_cached_bufq - cached_bufq to enqueue rx packets 3975 * @cached_bufq: nbuff list to enqueue rx packets 3976 * @bufq_lock: spinlock for nbuff list access 3977 * @thresh: maximum threshold for number of rx buff to enqueue 3978 * @entries: number of entries 3979 * @dropped: number of packets dropped 3980 */ 3981 struct dp_peer_cached_bufq { 3982 qdf_list_t cached_bufq; 3983 qdf_spinlock_t bufq_lock; 3984 uint32_t thresh; 3985 uint32_t entries; 3986 uint32_t dropped; 3987 }; 3988 3989 /** 3990 * enum dp_peer_ast_flowq 3991 * @DP_PEER_AST_FLOWQ_HI_PRIO: Hi Priority flow queue 3992 * @DP_PEER_AST_FLOWQ_LOW_PRIO: Low priority flow queue 3993 * @DP_PEER_AST_FLOWQ_UDP: flow queue type is UDP 3994 * @DP_PEER_AST_FLOWQ_NON_UDP: flow queue type is Non UDP 3995 * @DP_PEER_AST_FLOWQ_MAX: max value 3996 */ 3997 enum dp_peer_ast_flowq { 3998 DP_PEER_AST_FLOWQ_HI_PRIO, 3999 DP_PEER_AST_FLOWQ_LOW_PRIO, 4000 DP_PEER_AST_FLOWQ_UDP, 4001 DP_PEER_AST_FLOWQ_NON_UDP, 4002 DP_PEER_AST_FLOWQ_MAX, 4003 }; 4004 4005 /** 4006 * struct dp_ast_flow_override_info - ast override info 4007 * @ast_idx: ast indexes in peer map message 4008 * @ast_valid_mask: ast valid mask for each ast index 4009 * @ast_flow_mask: ast flow mask for each ast index 4010 * @tid_valid_low_pri_mask: per tid mask for low priority flow 4011 * @tid_valid_hi_pri_mask: per tid mask for hi priority flow 4012 */ 4013 struct dp_ast_flow_override_info { 4014 uint16_t ast_idx[DP_PEER_AST_FLOWQ_MAX]; 4015 uint8_t ast_valid_mask; 4016 uint8_t ast_flow_mask[DP_PEER_AST_FLOWQ_MAX]; 4017 uint8_t tid_valid_low_pri_mask; 4018 uint8_t tid_valid_hi_pri_mask; 4019 }; 4020 4021 /** 4022 * struct dp_peer_ast_params - ast parameters for a msdu flow-queue 4023 * @ast_idx: ast index populated by FW 4024 * @is_valid: ast flow valid mask 4025 * @valid_tid_mask: per tid mask for this ast index 4026 * @flowQ: flow queue id associated with this ast index 4027 */ 4028 struct dp_peer_ast_params { 4029 uint16_t ast_idx; 4030 uint8_t is_valid; 4031 uint8_t valid_tid_mask; 4032 uint8_t flowQ; 4033 }; 4034 4035 #define DP_MLO_FLOW_INFO_MAX 3 4036 4037 /** 4038 * struct dp_mlo_flow_override_info - Flow override info 4039 * @ast_idx: Primary TCL AST Index 4040 * @ast_idx_valid: Is AST index valid 4041 * @chip_id: CHIP ID 4042 * @tidmask: tidmask 4043 * @cache_set_num: Cache set number 4044 */ 4045 struct dp_mlo_flow_override_info { 4046 uint16_t ast_idx; 4047 uint8_t ast_idx_valid; 4048 uint8_t chip_id; 4049 uint8_t tidmask; 4050 uint8_t cache_set_num; 4051 }; 4052 4053 /** 4054 * struct dp_mlo_link_info - Link info 4055 * @peer_chip_id: Peer Chip ID 4056 * @vdev_id: Vdev ID 4057 */ 4058 struct dp_mlo_link_info { 4059 uint8_t peer_chip_id; 4060 uint8_t vdev_id; 4061 }; 4062 4063 #ifdef WLAN_SUPPORT_MSCS 4064 /*MSCS Procedure based macros */ 4065 #define IEEE80211_MSCS_MAX_ELEM_SIZE 5 4066 #define IEEE80211_TCLAS_MASK_CLA_TYPE_4 4 4067 /** 4068 * struct dp_peer_mscs_parameter - MSCS database obtained from 4069 * MSCS Request and Response in the control path. This data is used 4070 * by the AP to find out what priority to set based on the tuple 4071 * classification during packet processing. 4072 * @user_priority_bitmap: User priority bitmap obtained during 4073 * handshake 4074 * @user_priority_limit: User priority limit obtained during 4075 * handshake 4076 * @classifier_mask: params to be compared during processing 4077 */ 4078 struct dp_peer_mscs_parameter { 4079 uint8_t user_priority_bitmap; 4080 uint8_t user_priority_limit; 4081 uint8_t classifier_mask; 4082 }; 4083 #endif 4084 4085 #ifdef QCA_SUPPORT_WDS_EXTENDED 4086 #define WDS_EXT_PEER_INIT_BIT 0 4087 4088 /** 4089 * struct dp_wds_ext_peer - wds ext peer structure 4090 * This is used when wds extended feature is enabled 4091 * both compile time and run time. It is created 4092 * when 1st 4 address frame is received from 4093 * wds backhaul. 4094 * @osif_peer: Handle to the OS shim SW's virtual device 4095 * @init: wds ext netdev state 4096 */ 4097 struct dp_wds_ext_peer { 4098 ol_osif_peer_handle osif_peer; 4099 unsigned long init; 4100 }; 4101 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 4102 4103 #ifdef WLAN_SUPPORT_MESH_LATENCY 4104 /*Advanced Mesh latency feature based macros */ 4105 4106 /** 4107 * struct dp_peer_mesh_latency_parameter - Mesh latency related 4108 * parameters. This data is updated per peer per TID based on 4109 * the flow tuple classification in external rule database 4110 * during packet processing. 4111 * @service_interval_dl: Service interval associated with TID in DL 4112 * @burst_size_dl: Burst size additive over multiple flows in DL 4113 * @service_interval_ul: Service interval associated with TID in UL 4114 * @burst_size_ul: Burst size additive over multiple flows in UL 4115 * @ac: custom ac derived from service interval 4116 * @msduq: MSDU queue number within TID 4117 */ 4118 struct dp_peer_mesh_latency_parameter { 4119 uint32_t service_interval_dl; 4120 uint32_t burst_size_dl; 4121 uint32_t service_interval_ul; 4122 uint32_t burst_size_ul; 4123 uint8_t ac; 4124 uint8_t msduq; 4125 }; 4126 #endif 4127 4128 #ifdef WLAN_FEATURE_11BE_MLO 4129 /* Max number of links for MLO connection */ 4130 #define DP_MAX_MLO_LINKS 3 4131 4132 /** 4133 * struct dp_peer_link_info - link peer information for MLO 4134 * @mac_addr: Mac address 4135 * @vdev_id: Vdev ID for current link peer 4136 * @is_valid: flag for link peer info valid or not 4137 * @chip_id: chip id 4138 */ 4139 struct dp_peer_link_info { 4140 union dp_align_mac_addr mac_addr; 4141 uint8_t vdev_id; 4142 uint8_t is_valid; 4143 uint8_t chip_id; 4144 }; 4145 4146 /** 4147 * struct dp_mld_link_peers - this structure is used to get link peers 4148 * pointer from mld peer 4149 * @link_peers: link peers pointer array 4150 * @num_links: number of link peers fetched 4151 */ 4152 struct dp_mld_link_peers { 4153 struct dp_peer *link_peers[DP_MAX_MLO_LINKS]; 4154 uint8_t num_links; 4155 }; 4156 #endif 4157 4158 typedef void *dp_txrx_ref_handle; 4159 4160 /** 4161 * struct dp_peer_per_pkt_tx_stats- Peer Tx stats updated in per pkt 4162 * Tx completion path 4163 * @ucast: Unicast Packet Count 4164 * @mcast: Multicast Packet Count 4165 * @bcast: Broadcast Packet Count 4166 * @nawds_mcast: NAWDS Multicast Packet Count 4167 * @tx_success: Successful Tx Packets 4168 * @nawds_mcast_drop: NAWDS Multicast Drop Count 4169 * @ofdma: Total Packets as ofdma 4170 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 4171 * @amsdu_cnt: Number of MSDUs part of AMSDU 4172 * @dropped: Dropped packet statistics 4173 * @dropped.fw_rem: Discarded by firmware 4174 * @dropped.fw_rem_notx: firmware_discard_untransmitted 4175 * @dropped.fw_rem_tx: firmware_discard_transmitted 4176 * @dropped.age_out: aged out in mpdu/msdu queues 4177 * @dropped.fw_reason1: discarded by firmware reason 1 4178 * @dropped.fw_reason2: discarded by firmware reason 2 4179 * @dropped.fw_reason3: discarded by firmware reason 3 4180 * @dropped.fw_rem_no_match: dropped due to fw no match command 4181 * @dropped.drop_threshold: dropped due to HW threshold 4182 * @dropped.drop_link_desc_na: dropped due resource not available in HW 4183 * @dropped.invalid_drop: Invalid msdu drop 4184 * @dropped.mcast_vdev_drop: MCAST drop configured for VDEV in HW 4185 * @dropped.invalid_rr: Invalid TQM release reason 4186 * @failed_retry_count: packets failed due to retry above 802.11 retry limit 4187 * @retry_count: packets successfully send after one or more retry 4188 * @multiple_retry_count: packets successfully sent after more than one retry 4189 * @no_ack_count: no ack pkt count for different protocols 4190 * @tx_success_twt: Successful Tx Packets in TWT session 4191 * @last_tx_ts: last timestamp in jiffies when tx comp occurred 4192 * @avg_sojourn_msdu: Avg sojourn msdu stat 4193 * @protocol_trace_cnt: per-peer protocol counter 4194 * @release_src_not_tqm: Counter to keep track of release source is not TQM 4195 * in TX completion status processing 4196 */ 4197 struct dp_peer_per_pkt_tx_stats { 4198 struct cdp_pkt_info ucast; 4199 struct cdp_pkt_info mcast; 4200 struct cdp_pkt_info bcast; 4201 struct cdp_pkt_info nawds_mcast; 4202 struct cdp_pkt_info tx_success; 4203 uint32_t nawds_mcast_drop; 4204 uint32_t ofdma; 4205 uint32_t non_amsdu_cnt; 4206 uint32_t amsdu_cnt; 4207 struct { 4208 struct cdp_pkt_info fw_rem; 4209 uint32_t fw_rem_notx; 4210 uint32_t fw_rem_tx; 4211 uint32_t age_out; 4212 uint32_t fw_reason1; 4213 uint32_t fw_reason2; 4214 uint32_t fw_reason3; 4215 uint32_t fw_rem_queue_disable; 4216 uint32_t fw_rem_no_match; 4217 uint32_t drop_threshold; 4218 uint32_t drop_link_desc_na; 4219 uint32_t invalid_drop; 4220 uint32_t mcast_vdev_drop; 4221 uint32_t invalid_rr; 4222 } dropped; 4223 uint32_t failed_retry_count; 4224 uint32_t retry_count; 4225 uint32_t multiple_retry_count; 4226 uint32_t no_ack_count[QDF_PROTO_SUBTYPE_MAX]; 4227 struct cdp_pkt_info tx_success_twt; 4228 unsigned long last_tx_ts; 4229 qdf_ewma_tx_lag avg_sojourn_msdu[CDP_DATA_TID_MAX]; 4230 #ifdef VDEV_PEER_PROTOCOL_COUNT 4231 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 4232 #endif 4233 uint32_t release_src_not_tqm; 4234 }; 4235 4236 /** 4237 * struct dp_peer_extd_tx_stats - Peer Tx stats updated in either 4238 * per pkt Tx completion path when macro QCA_ENHANCED_STATS_SUPPORT is 4239 * disabled or in HTT Tx PPDU completion path when macro is enabled 4240 * @stbc: Packets in STBC 4241 * @ldpc: Packets in LDPC 4242 * @retries: Packet retries 4243 * @pkt_type: pkt count for different .11 modes 4244 * @wme_ac_type: Wireless Multimedia type Count 4245 * @excess_retries_per_ac: Wireless Multimedia type Count 4246 * @ampdu_cnt: completion of aggregation 4247 * @non_ampdu_cnt: tx completion not aggregated 4248 * @num_ppdu_cookie_valid: no. of valid ppdu cookies rcvd from FW 4249 * @tx_ppdus: ppdus in tx 4250 * @tx_mpdus_success: mpdus successful in tx 4251 * @tx_mpdus_tried: mpdus tried in tx 4252 * @tx_rate: Tx Rate in kbps 4253 * @last_tx_rate: Last tx rate for unicast packets 4254 * @last_tx_rate_mcs: Tx rate mcs for unicast packets 4255 * @mcast_last_tx_rate: Last tx rate for multicast packets 4256 * @mcast_last_tx_rate_mcs: Last tx rate mcs for multicast 4257 * @rnd_avg_tx_rate: Rounded average tx rate 4258 * @avg_tx_rate: Average TX rate 4259 * @tx_ratecode: Tx rate code of last frame 4260 * @pream_punct_cnt: Preamble Punctured count 4261 * @sgi_count: SGI count 4262 * @nss: Packet count for different num_spatial_stream values 4263 * @bw: Packet Count for different bandwidths 4264 * @ru_start: RU start index 4265 * @ru_tones: RU tones size 4266 * @ru_loc: pkt info for RU location 26/ 52/ 106/ 242/ 484 counter 4267 * @transmit_type: pkt info for tx transmit type 4268 * @mu_group_id: mumimo mu group id 4269 * @last_ack_rssi: RSSI of last acked packet 4270 * @nss_info: NSS 1,2, ...8 4271 * @mcs_info: MCS index 4272 * @bw_info: Bandwidth 4273 * <enum 0 bw_20_MHz> 4274 * <enum 1 bw_40_MHz> 4275 * <enum 2 bw_80_MHz> 4276 * <enum 3 bw_160_MHz> 4277 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 4278 * <enum 1 0_4_us_sgi > Legacy short GI 4279 * <enum 2 1_6_us_sgi > HE related GI 4280 * <enum 3 3_2_us_sgi > HE 4281 * @preamble_info: preamble 4282 * @tx_ucast_total: total ucast count 4283 * @tx_ucast_success: total ucast success count 4284 * @retries_mpdu: mpdu number of successfully transmitted after retries 4285 * @mpdu_success_with_retries: mpdu retry count in case of successful tx 4286 * @su_be_ppdu_cnt: SU Tx packet count for 11BE 4287 * @mu_be_ppdu_cnt: MU Tx packet count for 11BE 4288 * @punc_bw: MSDU count for punctured bw 4289 * @rts_success: RTS success count 4290 * @rts_failure: RTS failure count 4291 * @bar_cnt: Block ACK Request frame count 4292 * @ndpa_cnt: NDP announcement frame count 4293 * @wme_ac_type_bytes: Wireless Multimedia bytes Count 4294 */ 4295 struct dp_peer_extd_tx_stats { 4296 uint32_t stbc; 4297 uint32_t ldpc; 4298 uint32_t retries; 4299 struct cdp_pkt_type pkt_type[DOT11_MAX]; 4300 uint32_t wme_ac_type[WME_AC_MAX]; 4301 uint32_t excess_retries_per_ac[WME_AC_MAX]; 4302 uint32_t ampdu_cnt; 4303 uint32_t non_ampdu_cnt; 4304 uint32_t num_ppdu_cookie_valid; 4305 uint32_t tx_ppdus; 4306 uint32_t tx_mpdus_success; 4307 uint32_t tx_mpdus_tried; 4308 4309 uint32_t tx_rate; 4310 uint32_t last_tx_rate; 4311 uint32_t last_tx_rate_mcs; 4312 uint32_t mcast_last_tx_rate; 4313 uint32_t mcast_last_tx_rate_mcs; 4314 uint64_t rnd_avg_tx_rate; 4315 uint64_t avg_tx_rate; 4316 uint16_t tx_ratecode; 4317 4318 uint32_t sgi_count[MAX_GI]; 4319 uint32_t pream_punct_cnt; 4320 uint32_t nss[SS_COUNT]; 4321 uint32_t bw[MAX_BW]; 4322 uint32_t ru_start; 4323 uint32_t ru_tones; 4324 struct cdp_tx_pkt_info ru_loc[MAX_RU_LOCATIONS]; 4325 4326 struct cdp_tx_pkt_info transmit_type[MAX_TRANSMIT_TYPES]; 4327 uint32_t mu_group_id[MAX_MU_GROUP_ID]; 4328 4329 uint32_t last_ack_rssi; 4330 4331 uint32_t nss_info:4, 4332 mcs_info:4, 4333 bw_info:4, 4334 gi_info:4, 4335 preamble_info:4; 4336 4337 uint32_t retries_mpdu; 4338 uint32_t mpdu_success_with_retries; 4339 struct cdp_pkt_info tx_ucast_total; 4340 struct cdp_pkt_info tx_ucast_success; 4341 #ifdef WLAN_FEATURE_11BE 4342 struct cdp_pkt_type su_be_ppdu_cnt; 4343 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 4344 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 4345 #endif 4346 uint32_t rts_success; 4347 uint32_t rts_failure; 4348 uint32_t bar_cnt; 4349 uint32_t ndpa_cnt; 4350 uint64_t wme_ac_type_bytes[WME_AC_MAX]; 4351 }; 4352 4353 /** 4354 * struct dp_peer_per_pkt_rx_stats - Peer Rx stats updated in per pkt Rx path 4355 * @rcvd_reo: Packets received on the reo ring 4356 * @rx_lmac: Packets received on each lmac 4357 * @unicast: Total unicast packets 4358 * @multicast: Total multicast packets 4359 * @bcast: Broadcast Packet Count 4360 * @raw: Raw Pakets received 4361 * @nawds_mcast_drop: Total NAWDS multicast packets dropped 4362 * @mec_drop: Total MEC packets dropped 4363 * @last_rx_ts: last timestamp in jiffies when RX happened 4364 * @intra_bss: Intra BSS statistics 4365 * @intra_bss.pkts: Intra BSS packets received 4366 * @intra_bss.fail: Intra BSS packets failed 4367 * @intra_bss.mdns_no_fws: Intra BSS MDNS packets not forwarded 4368 * @err: error counters 4369 * @err.mic_err: Rx MIC errors CCMP 4370 * @err.decrypt_err: Rx Decryption Errors CRC 4371 * @err.fcserr: rx MIC check failed (CCMP) 4372 * @err.pn_err: pn check failed 4373 * @err.oor_err: Rx OOR errors 4374 * @err.jump_2k_err: 2k jump errors 4375 * @err.rxdma_wifi_parse_err: rxdma wifi parse errors 4376 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 4377 * @amsdu_cnt: Number of MSDUs part of AMSDU 4378 * @rx_retries: retries of packet in rx 4379 * @multipass_rx_pkt_drop: Dropped multipass rx pkt 4380 * @peer_unauth_rx_pkt_drop: Unauth rx packet drops 4381 * @policy_check_drop: policy check drops 4382 * @to_stack_twt: Total packets sent up the stack in TWT session 4383 * @protocol_trace_cnt: per-peer protocol counters 4384 * @mcast_3addr_drop: 4385 * @rx_total: total rx count 4386 */ 4387 struct dp_peer_per_pkt_rx_stats { 4388 struct cdp_pkt_info rcvd_reo[CDP_MAX_RX_RINGS]; 4389 struct cdp_pkt_info rx_lmac[CDP_MAX_LMACS]; 4390 struct cdp_pkt_info unicast; 4391 struct cdp_pkt_info multicast; 4392 struct cdp_pkt_info bcast; 4393 struct cdp_pkt_info raw; 4394 uint32_t nawds_mcast_drop; 4395 struct cdp_pkt_info mec_drop; 4396 unsigned long last_rx_ts; 4397 struct { 4398 struct cdp_pkt_info pkts; 4399 struct cdp_pkt_info fail; 4400 uint32_t mdns_no_fwd; 4401 } intra_bss; 4402 struct { 4403 uint32_t mic_err; 4404 uint32_t decrypt_err; 4405 uint32_t fcserr; 4406 uint32_t pn_err; 4407 uint32_t oor_err; 4408 uint32_t jump_2k_err; 4409 uint32_t rxdma_wifi_parse_err; 4410 } err; 4411 uint32_t non_amsdu_cnt; 4412 uint32_t amsdu_cnt; 4413 uint32_t rx_retries; 4414 uint32_t multipass_rx_pkt_drop; 4415 uint32_t peer_unauth_rx_pkt_drop; 4416 uint32_t policy_check_drop; 4417 struct cdp_pkt_info to_stack_twt; 4418 #ifdef VDEV_PEER_PROTOCOL_COUNT 4419 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 4420 #endif 4421 uint32_t mcast_3addr_drop; 4422 #ifdef IPA_OFFLOAD 4423 struct cdp_pkt_info rx_total; 4424 #endif 4425 }; 4426 4427 /** 4428 * struct dp_peer_extd_rx_stats - Peer Rx stats updated in either 4429 * per pkt Rx path when macro QCA_ENHANCED_STATS_SUPPORT is disabled or in 4430 * Rx monitor patch when macro is enabled 4431 * @pkt_type: pkt counter for different .11 modes 4432 * @wme_ac_type: Wireless Multimedia type Count 4433 * @mpdu_cnt_fcs_ok: SU Rx success mpdu count 4434 * @mpdu_cnt_fcs_err: SU Rx fail mpdu count 4435 * @non_ampdu_cnt: Number of MSDUs with no MPDU level aggregation 4436 * @ampdu_cnt: Number of MSDUs part of AMSPU 4437 * @rx_mpdus: mpdu in rx 4438 * @rx_ppdus: ppdu in rx 4439 * @su_ax_ppdu_cnt: SU Rx packet count for .11ax 4440 * @rx_mu: Rx MU stats 4441 * @reception_type: Reception type of packets 4442 * @ppdu_cnt: PPDU packet count in reception type 4443 * @sgi_count: sgi count 4444 * @nss: packet count in spatiel Streams 4445 * @ppdu_nss: PPDU packet count in spatial streams 4446 * @bw: Packet Count in different bandwidths 4447 * @rx_mpdu_cnt: rx mpdu count per MCS rate 4448 * @rx_rate: Rx rate 4449 * @last_rx_rate: Previous rx rate 4450 * @rnd_avg_rx_rate: Rounded average rx rate 4451 * @avg_rx_rate: Average Rx rate 4452 * @rx_ratecode: Rx rate code of last frame 4453 * @avg_snr: Average snr 4454 * @rx_snr_measured_time: Time at which snr is measured 4455 * @snr: SNR of received signal 4456 * @last_snr: Previous snr 4457 * @nss_info: NSS 1,2, ...8 4458 * @mcs_info: MCS index 4459 * @bw_info: Bandwidth 4460 * <enum 0 bw_20_MHz> 4461 * <enum 1 bw_40_MHz> 4462 * <enum 2 bw_80_MHz> 4463 * <enum 3 bw_160_MHz> 4464 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 4465 * <enum 1 0_4_us_sgi > Legacy short GI 4466 * <enum 2 1_6_us_sgi > HE related GI 4467 * <enum 3 3_2_us_sgi > HE 4468 * @preamble_info: preamble 4469 * @mpdu_retry_cnt: retries of mpdu in rx 4470 * @su_be_ppdu_cnt: SU Rx packet count for BE 4471 * @mu_be_ppdu_cnt: MU rx packet count for BE 4472 * @punc_bw: MSDU count for punctured bw 4473 * @bar_cnt: Block ACK Request frame count 4474 * @ndpa_cnt: NDP announcement frame count 4475 * @wme_ac_type_bytes: Wireless Multimedia type Bytes Count 4476 */ 4477 struct dp_peer_extd_rx_stats { 4478 struct cdp_pkt_type pkt_type[DOT11_MAX]; 4479 uint32_t wme_ac_type[WME_AC_MAX]; 4480 uint32_t mpdu_cnt_fcs_ok; 4481 uint32_t mpdu_cnt_fcs_err; 4482 uint32_t non_ampdu_cnt; 4483 uint32_t ampdu_cnt; 4484 uint32_t rx_mpdus; 4485 uint32_t rx_ppdus; 4486 4487 struct cdp_pkt_type su_ax_ppdu_cnt; 4488 struct cdp_rx_mu rx_mu[TXRX_TYPE_MU_MAX]; 4489 uint32_t reception_type[MAX_RECEPTION_TYPES]; 4490 uint32_t ppdu_cnt[MAX_RECEPTION_TYPES]; 4491 4492 uint32_t sgi_count[MAX_GI]; 4493 uint32_t nss[SS_COUNT]; 4494 uint32_t ppdu_nss[SS_COUNT]; 4495 uint32_t bw[MAX_BW]; 4496 uint32_t rx_mpdu_cnt[MAX_MCS]; 4497 4498 uint32_t rx_rate; 4499 uint32_t last_rx_rate; 4500 uint32_t rnd_avg_rx_rate; 4501 uint32_t avg_rx_rate; 4502 uint32_t rx_ratecode; 4503 4504 uint32_t avg_snr; 4505 unsigned long rx_snr_measured_time; 4506 uint8_t snr; 4507 uint8_t last_snr; 4508 4509 uint32_t nss_info:4, 4510 mcs_info:4, 4511 bw_info:4, 4512 gi_info:4, 4513 preamble_info:4; 4514 4515 uint32_t mpdu_retry_cnt; 4516 #ifdef WLAN_FEATURE_11BE 4517 struct cdp_pkt_type su_be_ppdu_cnt; 4518 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 4519 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 4520 #endif 4521 uint32_t bar_cnt; 4522 uint32_t ndpa_cnt; 4523 uint64_t wme_ac_type_bytes[WME_AC_MAX]; 4524 }; 4525 4526 /** 4527 * struct dp_peer_per_pkt_stats - Per pkt stats for peer 4528 * @tx: Per pkt Tx stats 4529 * @rx: Per pkt Rx stats 4530 */ 4531 struct dp_peer_per_pkt_stats { 4532 struct dp_peer_per_pkt_tx_stats tx; 4533 struct dp_peer_per_pkt_rx_stats rx; 4534 }; 4535 4536 /** 4537 * struct dp_peer_extd_stats - Stats from extended path for peer 4538 * @tx: Extended path tx stats 4539 * @rx: Extended path rx stats 4540 */ 4541 struct dp_peer_extd_stats { 4542 struct dp_peer_extd_tx_stats tx; 4543 struct dp_peer_extd_rx_stats rx; 4544 }; 4545 4546 /** 4547 * struct dp_peer_stats - Peer stats 4548 * @per_pkt_stats: Per packet path stats 4549 * @extd_stats: Extended path stats 4550 */ 4551 struct dp_peer_stats { 4552 struct dp_peer_per_pkt_stats per_pkt_stats; 4553 #ifndef QCA_ENHANCED_STATS_SUPPORT 4554 struct dp_peer_extd_stats extd_stats; 4555 #endif 4556 }; 4557 4558 /** 4559 * struct dp_txrx_peer: DP txrx_peer structure used in per pkt path 4560 * @vdev: VDEV to which this peer is associated 4561 * @peer_id: peer ID for this peer 4562 * @authorize: Set when authorized 4563 * @in_twt: in TWT session 4564 * @hw_txrx_stats_en: Indicate HW offload vdev stats 4565 * @mld_peer:1: MLD peer 4566 * @tx_failed: Total Tx failure 4567 * @comp_pkt: Pkt Info for which completions were received 4568 * @to_stack: Total packets sent up the stack 4569 * @stats: Peer stats 4570 * @delay_stats: Peer delay stats 4571 * @jitter_stats: Peer jitter stats 4572 * @security: Security credentials 4573 * @nawds_enabled: NAWDS flag 4574 * @bss_peer: set for bss peer 4575 * @isolation: enable peer isolation for this peer 4576 * @wds_enabled: WDS peer 4577 * @wds_ecm: 4578 * @flush_in_progress: 4579 * @bufq_info: 4580 * @mpass_peer_list_elem: node in the special peer list element 4581 * @vlan_id: vlan id for key 4582 * @wds_ext: 4583 * @osif_rx: 4584 * @rx_tid: 4585 * @sawf_stats: 4586 * @bw: bandwidth of peer connection 4587 * @mpdu_retry_threshold: MPDU retry threshold to increment tx bad count 4588 */ 4589 struct dp_txrx_peer { 4590 struct dp_vdev *vdev; 4591 uint16_t peer_id; 4592 uint8_t authorize:1, 4593 in_twt:1, 4594 hw_txrx_stats_en:1, 4595 mld_peer:1; 4596 uint32_t tx_failed; 4597 struct cdp_pkt_info comp_pkt; 4598 struct cdp_pkt_info to_stack; 4599 4600 struct dp_peer_stats stats; 4601 4602 struct dp_peer_delay_stats *delay_stats; 4603 4604 struct cdp_peer_tid_stats *jitter_stats; 4605 4606 struct { 4607 enum cdp_sec_type sec_type; 4608 u_int32_t michael_key[2]; /* relevant for TKIP */ 4609 } security[2]; /* 0 -> multicast, 1 -> unicast */ 4610 4611 uint16_t nawds_enabled:1, 4612 bss_peer:1, 4613 isolation:1, 4614 wds_enabled:1; 4615 #ifdef WDS_VENDOR_EXTENSION 4616 dp_ecm_policy wds_ecm; 4617 #endif 4618 #ifdef PEER_CACHE_RX_PKTS 4619 qdf_atomic_t flush_in_progress; 4620 struct dp_peer_cached_bufq bufq_info; 4621 #endif 4622 #ifdef QCA_MULTIPASS_SUPPORT 4623 TAILQ_ENTRY(dp_txrx_peer) mpass_peer_list_elem; 4624 uint16_t vlan_id; 4625 #endif 4626 #ifdef QCA_SUPPORT_WDS_EXTENDED 4627 struct dp_wds_ext_peer wds_ext; 4628 ol_txrx_rx_fp osif_rx; 4629 #endif 4630 struct dp_rx_tid_defrag rx_tid[DP_MAX_TIDS]; 4631 #ifdef CONFIG_SAWF 4632 struct dp_peer_sawf_stats *sawf_stats; 4633 #endif 4634 #ifdef DP_PEER_EXTENDED_API 4635 enum cdp_peer_bw bw; 4636 uint8_t mpdu_retry_threshold; 4637 #endif 4638 }; 4639 4640 /* Peer structure for data path state */ 4641 struct dp_peer { 4642 struct dp_txrx_peer *txrx_peer; 4643 #ifdef WIFI_MONITOR_SUPPORT 4644 struct dp_mon_peer *monitor_peer; 4645 #endif 4646 /* peer ID for this peer */ 4647 uint16_t peer_id; 4648 4649 /* VDEV to which this peer is associated */ 4650 struct dp_vdev *vdev; 4651 4652 struct dp_ast_entry *self_ast_entry; 4653 4654 qdf_atomic_t ref_cnt; 4655 4656 union dp_align_mac_addr mac_addr; 4657 4658 /* node in the vdev's list of peers */ 4659 TAILQ_ENTRY(dp_peer) peer_list_elem; 4660 /* node in the hash table bin's list of peers */ 4661 TAILQ_ENTRY(dp_peer) hash_list_elem; 4662 4663 /* TID structures pointer */ 4664 struct dp_rx_tid *rx_tid; 4665 4666 /* TBD: No transmit TID state required? */ 4667 4668 struct { 4669 enum cdp_sec_type sec_type; 4670 u_int32_t michael_key[2]; /* relevant for TKIP */ 4671 } security[2]; /* 0 -> multicast, 1 -> unicast */ 4672 4673 /* NAWDS Flag and Bss Peer bit */ 4674 uint16_t bss_peer:1, /* set for bss peer */ 4675 authorize:1, /* Set when authorized */ 4676 valid:1, /* valid bit */ 4677 delete_in_progress:1, /* Indicate kickout sent */ 4678 sta_self_peer:1, /* Indicate STA self peer */ 4679 is_tdls_peer:1; /* Indicate TDLS peer */ 4680 4681 #ifdef WLAN_FEATURE_11BE_MLO 4682 uint8_t first_link:1, /* first link peer for MLO */ 4683 primary_link:1; /* primary link for MLO */ 4684 #endif 4685 4686 /* MCL specific peer local id */ 4687 uint16_t local_id; 4688 enum ol_txrx_peer_state state; 4689 qdf_spinlock_t peer_info_lock; 4690 4691 /* Peer calibrated stats */ 4692 struct cdp_calibr_stats stats; 4693 4694 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 4695 /* TBD */ 4696 4697 /* Active Block ack sessions */ 4698 uint16_t active_ba_session_cnt; 4699 4700 /* Current HW buffersize setting */ 4701 uint16_t hw_buffer_size; 4702 4703 /* 4704 * Flag to check if sessions with 256 buffersize 4705 * should be terminated. 4706 */ 4707 uint8_t kill_256_sessions; 4708 qdf_atomic_t is_default_route_set; 4709 4710 #ifdef QCA_PEER_MULTIQ_SUPPORT 4711 struct dp_peer_ast_params peer_ast_flowq_idx[DP_PEER_AST_FLOWQ_MAX]; 4712 #endif 4713 /* entry to inactive_list*/ 4714 TAILQ_ENTRY(dp_peer) inactive_list_elem; 4715 4716 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 4717 4718 uint8_t peer_state; 4719 qdf_spinlock_t peer_state_lock; 4720 #ifdef WLAN_SUPPORT_MSCS 4721 struct dp_peer_mscs_parameter mscs_ipv4_parameter, mscs_ipv6_parameter; 4722 bool mscs_active; 4723 #endif 4724 #ifdef WLAN_SUPPORT_MESH_LATENCY 4725 struct dp_peer_mesh_latency_parameter mesh_latency_params[DP_MAX_TIDS]; 4726 #endif 4727 #ifdef WLAN_FEATURE_11BE_MLO 4728 /* peer type */ 4729 enum cdp_peer_type peer_type; 4730 /*---------for link peer---------*/ 4731 struct dp_peer *mld_peer; 4732 /*---------for mld peer----------*/ 4733 struct dp_peer_link_info link_peers[DP_MAX_MLO_LINKS]; 4734 uint8_t num_links; 4735 DP_MUTEX_TYPE link_peers_info_lock; 4736 #endif 4737 #ifdef CONFIG_SAWF_DEF_QUEUES 4738 struct dp_peer_sawf *sawf; 4739 #endif 4740 /* AST hash index for peer in HW */ 4741 uint16_t ast_idx; 4742 4743 /* AST hash value for peer in HW */ 4744 uint16_t ast_hash; 4745 }; 4746 4747 /** 4748 * struct dp_invalid_peer_msg - Invalid peer message 4749 * @nbuf: data buffer 4750 * @wh: 802.11 header 4751 * @vdev_id: id of vdev 4752 */ 4753 struct dp_invalid_peer_msg { 4754 qdf_nbuf_t nbuf; 4755 struct ieee80211_frame *wh; 4756 uint8_t vdev_id; 4757 }; 4758 4759 /** 4760 * struct dp_tx_me_buf_t - ME buffer 4761 * @next: pointer to next buffer 4762 * @data: Destination Mac address 4763 * @paddr_macbuf: physical address for dest_mac 4764 */ 4765 struct dp_tx_me_buf_t { 4766 /* Note: ME buf pool initialization logic expects next pointer to 4767 * be the first element. Dont add anything before next */ 4768 struct dp_tx_me_buf_t *next; 4769 uint8_t data[QDF_MAC_ADDR_SIZE]; 4770 qdf_dma_addr_t paddr_macbuf; 4771 }; 4772 4773 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) || defined(WLAN_SUPPORT_RX_FISA) 4774 struct hal_rx_fst; 4775 4776 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 4777 struct dp_rx_fse { 4778 /* HAL Rx Flow Search Entry which matches HW definition */ 4779 void *hal_rx_fse; 4780 /* Toeplitz hash value */ 4781 uint32_t flow_hash; 4782 /* Flow index, equivalent to hash value truncated to FST size */ 4783 uint32_t flow_id; 4784 /* Stats tracking for this flow */ 4785 struct cdp_flow_stats stats; 4786 /* Flag indicating whether flow is IPv4 address tuple */ 4787 uint8_t is_ipv4_addr_entry; 4788 /* Flag indicating whether flow is valid */ 4789 uint8_t is_valid; 4790 }; 4791 4792 struct dp_rx_fst { 4793 /* Software (DP) FST */ 4794 uint8_t *base; 4795 /* Pointer to HAL FST */ 4796 struct hal_rx_fst *hal_rx_fst; 4797 /* Base physical address of HAL RX HW FST */ 4798 uint64_t hal_rx_fst_base_paddr; 4799 /* Maximum number of flows FSE supports */ 4800 uint16_t max_entries; 4801 /* Num entries in flow table */ 4802 uint16_t num_entries; 4803 /* SKID Length */ 4804 uint16_t max_skid_length; 4805 /* Hash mask to obtain legitimate hash entry */ 4806 uint32_t hash_mask; 4807 /* Timer for bundling of flows */ 4808 qdf_timer_t cache_invalidate_timer; 4809 /** 4810 * Flag which tracks whether cache update 4811 * is needed on timer expiry 4812 */ 4813 qdf_atomic_t is_cache_update_pending; 4814 /* Flag to indicate completion of FSE setup in HW/FW */ 4815 bool fse_setup_done; 4816 }; 4817 4818 #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_rx_fse) 4819 #elif WLAN_SUPPORT_RX_FISA 4820 4821 /** 4822 * struct dp_fisa_reo_mismatch_stats - reo mismatch sub-case stats for FISA 4823 * @allow_cce_match: packet allowed due to cce mismatch 4824 * @allow_fse_metdata_mismatch: packet allowed since it belongs to same flow, 4825 * only fse_metadata is not same. 4826 * @allow_non_aggr: packet allowed due to any other reason. 4827 */ 4828 struct dp_fisa_reo_mismatch_stats { 4829 uint32_t allow_cce_match; 4830 uint32_t allow_fse_metdata_mismatch; 4831 uint32_t allow_non_aggr; 4832 }; 4833 4834 struct dp_fisa_stats { 4835 /* flow index invalid from RX HW TLV */ 4836 uint32_t invalid_flow_index; 4837 /* workqueue deferred due to suspend */ 4838 uint32_t update_deferred; 4839 struct dp_fisa_reo_mismatch_stats reo_mismatch; 4840 }; 4841 4842 enum fisa_aggr_ret { 4843 FISA_AGGR_DONE, 4844 FISA_AGGR_NOT_ELIGIBLE, 4845 FISA_FLUSH_FLOW 4846 }; 4847 4848 /** 4849 * struct fisa_pkt_hist - FISA Packet history structure 4850 * @tlv_hist: array of TLV history 4851 * @ts_hist: array of timestamps of fisa packets 4852 * @idx: index indicating the next location to be used in the array. 4853 */ 4854 struct fisa_pkt_hist { 4855 uint8_t *tlv_hist; 4856 qdf_time_t ts_hist[FISA_FLOW_MAX_AGGR_COUNT]; 4857 uint32_t idx; 4858 }; 4859 4860 struct dp_fisa_rx_sw_ft { 4861 /* HAL Rx Flow Search Entry which matches HW definition */ 4862 void *hw_fse; 4863 /* hash value */ 4864 uint32_t flow_hash; 4865 /* toeplitz hash value*/ 4866 uint32_t flow_id_toeplitz; 4867 /* Flow index, equivalent to hash value truncated to FST size */ 4868 uint32_t flow_id; 4869 /* Stats tracking for this flow */ 4870 struct cdp_flow_stats stats; 4871 /* Flag indicating whether flow is IPv4 address tuple */ 4872 uint8_t is_ipv4_addr_entry; 4873 /* Flag indicating whether flow is valid */ 4874 uint8_t is_valid; 4875 uint8_t is_populated; 4876 uint8_t is_flow_udp; 4877 uint8_t is_flow_tcp; 4878 qdf_nbuf_t head_skb; 4879 uint16_t cumulative_l4_checksum; 4880 uint16_t adjusted_cumulative_ip_length; 4881 uint16_t cur_aggr; 4882 uint16_t napi_flush_cumulative_l4_checksum; 4883 uint16_t napi_flush_cumulative_ip_length; 4884 qdf_nbuf_t last_skb; 4885 uint32_t head_skb_ip_hdr_offset; 4886 uint32_t head_skb_l4_hdr_offset; 4887 struct cdp_rx_flow_tuple_info rx_flow_tuple_info; 4888 uint8_t napi_id; 4889 struct dp_vdev *vdev; 4890 uint64_t bytes_aggregated; 4891 uint32_t flush_count; 4892 uint32_t aggr_count; 4893 uint8_t do_not_aggregate; 4894 uint16_t hal_cumultive_ip_len; 4895 struct dp_soc *soc_hdl; 4896 /* last aggregate count fetched from RX PKT TLV */ 4897 uint32_t last_hal_aggr_count; 4898 uint32_t cur_aggr_gso_size; 4899 qdf_net_udphdr_t *head_skb_udp_hdr; 4900 uint16_t frags_cumulative_len; 4901 /* CMEM parameters */ 4902 uint32_t cmem_offset; 4903 uint32_t metadata; 4904 uint32_t reo_dest_indication; 4905 qdf_time_t flow_init_ts; 4906 qdf_time_t last_accessed_ts; 4907 #ifdef WLAN_SUPPORT_RX_FISA_HIST 4908 struct fisa_pkt_hist pkt_hist; 4909 #endif 4910 }; 4911 4912 #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_fisa_rx_sw_ft) 4913 #define MAX_FSE_CACHE_FL_HST 10 4914 /** 4915 * struct fse_cache_flush_history - Debug history cache flush 4916 * @timestamp: Entry update timestamp 4917 * @flows_added: Number of flows added for this flush 4918 * @flows_deleted: Number of flows deleted for this flush 4919 */ 4920 struct fse_cache_flush_history { 4921 uint64_t timestamp; 4922 uint32_t flows_added; 4923 uint32_t flows_deleted; 4924 }; 4925 4926 struct dp_rx_fst { 4927 /* Software (DP) FST */ 4928 uint8_t *base; 4929 /* Pointer to HAL FST */ 4930 struct hal_rx_fst *hal_rx_fst; 4931 /* Base physical address of HAL RX HW FST */ 4932 uint64_t hal_rx_fst_base_paddr; 4933 /* Maximum number of flows FSE supports */ 4934 uint16_t max_entries; 4935 /* Num entries in flow table */ 4936 uint16_t num_entries; 4937 /* SKID Length */ 4938 uint16_t max_skid_length; 4939 /* Hash mask to obtain legitimate hash entry */ 4940 uint32_t hash_mask; 4941 /* Lock for adding/deleting entries of FST */ 4942 qdf_spinlock_t dp_rx_fst_lock; 4943 uint32_t add_flow_count; 4944 uint32_t del_flow_count; 4945 uint32_t hash_collision_cnt; 4946 struct dp_soc *soc_hdl; 4947 qdf_atomic_t fse_cache_flush_posted; 4948 qdf_timer_t fse_cache_flush_timer; 4949 /* Allow FSE cache flush cmd to FW */ 4950 bool fse_cache_flush_allow; 4951 struct fse_cache_flush_history cache_fl_rec[MAX_FSE_CACHE_FL_HST]; 4952 /* FISA DP stats */ 4953 struct dp_fisa_stats stats; 4954 4955 /* CMEM params */ 4956 qdf_work_t fst_update_work; 4957 qdf_workqueue_t *fst_update_wq; 4958 qdf_list_t fst_update_list; 4959 uint32_t meta_counter; 4960 uint32_t cmem_ba; 4961 qdf_spinlock_t dp_rx_sw_ft_lock[MAX_REO_DEST_RINGS]; 4962 qdf_event_t cmem_resp_event; 4963 bool flow_deletion_supported; 4964 bool fst_in_cmem; 4965 qdf_atomic_t pm_suspended; 4966 bool fst_wq_defer; 4967 }; 4968 4969 #endif /* WLAN_SUPPORT_RX_FISA */ 4970 #endif /* WLAN_SUPPORT_RX_FLOW_TAG || WLAN_SUPPORT_RX_FISA */ 4971 4972 #ifdef WLAN_FEATURE_STATS_EXT 4973 /** 4974 * struct dp_req_rx_hw_stats_t - RX peer HW stats query structure 4975 * @pending_tid_stats_cnt: pending tid stats count which waits for REO status 4976 * @is_query_timeout: flag to show is stats query timeout 4977 */ 4978 struct dp_req_rx_hw_stats_t { 4979 qdf_atomic_t pending_tid_stats_cnt; 4980 bool is_query_timeout; 4981 }; 4982 #endif 4983 /* soc level structure to declare arch specific ops for DP */ 4984 4985 /** 4986 * dp_hw_link_desc_pool_banks_free() - Free h/w link desc pool banks 4987 * @soc: DP SOC handle 4988 * @mac_id: mac id 4989 * 4990 * Return: none 4991 */ 4992 void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, uint32_t mac_id); 4993 4994 /** 4995 * dp_hw_link_desc_pool_banks_alloc() - Allocate h/w link desc pool banks 4996 * @soc: DP SOC handle 4997 * @mac_id: mac id 4998 * 4999 * Allocates memory pages for link descriptors, the page size is 4K for 5000 * MCL and 2MB for WIN. if the mac_id is invalid link descriptor pages are 5001 * allocated for regular RX/TX and if the there is a proper mac_id link 5002 * descriptors are allocated for RX monitor mode. 5003 * 5004 * Return: QDF_STATUS_SUCCESS: Success 5005 * QDF_STATUS_E_FAILURE: Failure 5006 */ 5007 QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, 5008 uint32_t mac_id); 5009 5010 /** 5011 * dp_link_desc_ring_replenish() - Replenish hw link desc rings 5012 * @soc: DP SOC handle 5013 * @mac_id: mac id 5014 * 5015 * Return: None 5016 */ 5017 void dp_link_desc_ring_replenish(struct dp_soc *soc, uint32_t mac_id); 5018 5019 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 5020 void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc); 5021 #else 5022 static inline void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc) {} 5023 #endif 5024 5025 /** 5026 * dp_srng_alloc() - Allocate memory for SRNG 5027 * @soc : Data path soc handle 5028 * @srng : SRNG pointer 5029 * @ring_type : Ring Type 5030 * @num_entries: Number of entries 5031 * @cached: cached flag variable 5032 * 5033 * Return: QDF_STATUS 5034 */ 5035 QDF_STATUS dp_srng_alloc(struct dp_soc *soc, struct dp_srng *srng, 5036 int ring_type, uint32_t num_entries, 5037 bool cached); 5038 5039 /** 5040 * dp_srng_free() - Free SRNG memory 5041 * @soc: Data path soc handle 5042 * @srng: SRNG pointer 5043 * 5044 * Return: None 5045 */ 5046 void dp_srng_free(struct dp_soc *soc, struct dp_srng *srng); 5047 5048 /** 5049 * dp_srng_init() - Initialize SRNG 5050 * @soc : Data path soc handle 5051 * @srng : SRNG pointer 5052 * @ring_type : Ring Type 5053 * @ring_num: Ring number 5054 * @mac_id: mac_id 5055 * 5056 * Return: QDF_STATUS 5057 */ 5058 QDF_STATUS dp_srng_init(struct dp_soc *soc, struct dp_srng *srng, 5059 int ring_type, int ring_num, int mac_id); 5060 5061 /** 5062 * dp_srng_init_idx() - Initialize SRNG 5063 * @soc : Data path soc handle 5064 * @srng : SRNG pointer 5065 * @ring_type : Ring Type 5066 * @ring_num: Ring number 5067 * @mac_id: mac_id 5068 * @idx: ring index 5069 * 5070 * Return: QDF_STATUS 5071 */ 5072 QDF_STATUS dp_srng_init_idx(struct dp_soc *soc, struct dp_srng *srng, 5073 int ring_type, int ring_num, int mac_id, 5074 uint32_t idx); 5075 5076 /** 5077 * dp_srng_deinit() - Internal function to deinit SRNG rings used by data path 5078 * @soc: DP SOC handle 5079 * @srng: source ring structure 5080 * @ring_type: type of ring 5081 * @ring_num: ring number 5082 * 5083 * Return: None 5084 */ 5085 void dp_srng_deinit(struct dp_soc *soc, struct dp_srng *srng, 5086 int ring_type, int ring_num); 5087 5088 void dp_print_peer_txrx_stats_be(struct cdp_peer_stats *peer_stats, 5089 enum peer_stats_type stats_type); 5090 void dp_print_peer_txrx_stats_li(struct cdp_peer_stats *peer_stats, 5091 enum peer_stats_type stats_type); 5092 5093 /** 5094 * dp_should_timer_irq_yield() - Decide if the bottom half should yield 5095 * @soc: DP soc handle 5096 * @work_done: work done in softirq context 5097 * @start_time: start time for the softirq 5098 * 5099 * Return: enum with yield code 5100 */ 5101 enum timer_yield_status 5102 dp_should_timer_irq_yield(struct dp_soc *soc, uint32_t work_done, 5103 uint64_t start_time); 5104 5105 /** 5106 * dp_vdev_get_default_reo_hash() - get reo dest ring and hash values for a vdev 5107 * @vdev: Datapath VDEV handle 5108 * @reo_dest: pointer to default reo_dest ring for vdev to be populated 5109 * @hash_based: pointer to hash value (enabled/disabled) to be populated 5110 * 5111 * Return: None 5112 */ 5113 void dp_vdev_get_default_reo_hash(struct dp_vdev *vdev, 5114 enum cdp_host_reo_dest_ring *reo_dest, 5115 bool *hash_based); 5116 5117 /** 5118 * dp_reo_remap_config() - configure reo remap register value based 5119 * nss configuration. 5120 * @soc: DP soc handle 5121 * @remap0: output parameter indicates reo remap 0 register value 5122 * @remap1: output parameter indicates reo remap 1 register value 5123 * @remap2: output parameter indicates reo remap 2 register value 5124 * 5125 * based on offload_radio value below remap configuration 5126 * get applied. 5127 * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4) 5128 * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4) 5129 * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4) 5130 * 3 - both Radios handled by NSS (remap not required) 5131 * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3) 5132 * 5133 * Return: bool type, true if remap is configured else false. 5134 */ 5135 5136 bool dp_reo_remap_config(struct dp_soc *soc, uint32_t *remap0, 5137 uint32_t *remap1, uint32_t *remap2); 5138 5139 #ifdef QCA_DP_TX_HW_SW_NBUF_DESC_PREFETCH 5140 /** 5141 * dp_tx_comp_get_prefetched_params_from_hal_desc() - Get prefetched TX desc 5142 * @soc: DP soc handle 5143 * @tx_comp_hal_desc: HAL TX Comp Descriptor 5144 * @r_tx_desc: SW Tx Descriptor retrieved from HAL desc. 5145 * 5146 * Return: None 5147 */ 5148 void dp_tx_comp_get_prefetched_params_from_hal_desc( 5149 struct dp_soc *soc, 5150 void *tx_comp_hal_desc, 5151 struct dp_tx_desc_s **r_tx_desc); 5152 #endif 5153 #endif /* _DP_TYPES_H_ */ 5154