1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _DP_TYPES_H_ 21 #define _DP_TYPES_H_ 22 23 #include <qdf_types.h> 24 #include <qdf_nbuf.h> 25 #include <qdf_lock.h> 26 #include <qdf_atomic.h> 27 #include <qdf_util.h> 28 #include <qdf_list.h> 29 #include <qdf_lro.h> 30 #include <queue.h> 31 #include <htt_common.h> 32 #include <htt.h> 33 #include <htt_stats.h> 34 #include <cdp_txrx_cmn.h> 35 #ifdef DP_MOB_DEFS 36 #include <cds_ieee80211_common.h> 37 #endif 38 #include <wdi_event_api.h> /* WDI subscriber event list */ 39 40 #include "hal_hw_headers.h" 41 #include <hal_tx.h> 42 #include <hal_reo.h> 43 #include "wlan_cfg.h" 44 #include "hal_rx.h" 45 #include <hal_api.h> 46 #include <hal_api_mon.h> 47 #include "hal_rx.h" 48 49 #define dp_init_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_INIT, params) 50 #define dp_init_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_INIT, params) 51 #define dp_init_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_INIT, params) 52 #define dp_init_info(params...) \ 53 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_INIT, ## params) 54 #define dp_init_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_INIT, params) 55 56 #define dp_vdev_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_VDEV, params) 57 #define dp_vdev_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_VDEV, params) 58 #define dp_vdev_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_VDEV, params) 59 #define dp_vdev_info(params...) \ 60 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_VDEV, ## params) 61 #define dp_vdev_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_VDEV, params) 62 63 #define MAX_BW 8 64 #define MAX_RETRIES 4 65 #define MAX_RECEPTION_TYPES 4 66 67 #define MINIDUMP_STR_SIZE 25 68 #include <dp_umac_reset.h> 69 70 #define REPT_MU_MIMO 1 71 #define REPT_MU_OFDMA_MIMO 3 72 #define DP_VO_TID 6 73 /** MAX TID MAPS AVAILABLE PER PDEV */ 74 #define DP_MAX_TID_MAPS 16 75 /** pad DSCP_TID_MAP_MAX with 6 to fix oob issue */ 76 #define DSCP_TID_MAP_MAX (64 + 6) 77 #define DP_IP_DSCP_SHIFT 2 78 #define DP_IP_DSCP_MASK 0x3f 79 #define DP_FC0_SUBTYPE_QOS 0x80 80 #define DP_QOS_TID 0x0f 81 #define DP_IPV6_PRIORITY_SHIFT 20 82 #define MAX_MON_LINK_DESC_BANKS 2 83 #define DP_VDEV_ALL CDP_VDEV_ALL 84 85 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 86 #define WLAN_DP_RESET_MON_BUF_RING_FILTER 87 #define MAX_TXDESC_POOLS 6 88 #else 89 #define MAX_TXDESC_POOLS 4 90 #endif 91 92 /* Max no of descriptors to handle special frames like EAPOL */ 93 #define MAX_TX_SPL_DESC 1024 94 95 #define MAX_RXDESC_POOLS 4 96 #define MAX_PPE_TXDESC_POOLS 1 97 98 /* Max no. of VDEV per PSOC */ 99 #ifdef WLAN_PSOC_MAX_VDEVS 100 #define MAX_VDEV_CNT WLAN_PSOC_MAX_VDEVS 101 #else 102 #define MAX_VDEV_CNT 51 103 #endif 104 105 /* Max no. of VDEVs, a PDEV can support */ 106 #ifdef WLAN_PDEV_MAX_VDEVS 107 #define DP_PDEV_MAX_VDEVS WLAN_PDEV_MAX_VDEVS 108 #else 109 #define DP_PDEV_MAX_VDEVS 17 110 #endif 111 112 #define EXCEPTION_DEST_RING_ID 0 113 #define MAX_IDLE_SCATTER_BUFS 16 114 #define DP_MAX_IRQ_PER_CONTEXT 12 115 #define DEFAULT_HW_PEER_ID 0xffff 116 117 #define MAX_AST_AGEOUT_COUNT 128 118 119 #ifdef TX_ADDR_INDEX_SEARCH 120 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_INDEX_SEARCH 121 #else 122 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_SEARCH_DEFAULT 123 #endif 124 125 #define WBM_INT_ERROR_ALL 0 126 #define WBM_INT_ERROR_REO_NULL_BUFFER 1 127 #define WBM_INT_ERROR_REO_NULL_LINK_DESC 2 128 #define WBM_INT_ERROR_REO_NULL_MSDU_BUFF 3 129 #define WBM_INT_ERROR_REO_BUFF_REAPED 4 130 #define MAX_WBM_INT_ERROR_REASONS 5 131 132 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 133 /* Maximum retries for Delba per tid per peer */ 134 #define DP_MAX_DELBA_RETRY 3 135 136 #ifdef AST_OFFLOAD_ENABLE 137 #define AST_OFFLOAD_ENABLE_STATUS 1 138 #else 139 #define AST_OFFLOAD_ENABLE_STATUS 0 140 #endif 141 142 #ifdef FEATURE_MEC_OFFLOAD 143 #define FW_MEC_FW_OFFLOAD_ENABLED 1 144 #else 145 #define FW_MEC_FW_OFFLOAD_ENABLED 0 146 #endif 147 148 #define PCP_TID_MAP_MAX 8 149 #define MAX_MU_USERS 37 150 151 #define REO_CMD_EVENT_HIST_MAX 64 152 153 #define DP_MAX_SRNGS 64 154 155 /* 2G PHYB */ 156 #define PHYB_2G_LMAC_ID 2 157 #define PHYB_2G_TARGET_PDEV_ID 2 158 159 /* Flags for skippig s/w tid classification */ 160 #define DP_TX_HW_DSCP_TID_MAP_VALID 0x1 161 #define DP_TXRX_HLOS_TID_OVERRIDE_ENABLED 0x2 162 #define DP_TX_MESH_ENABLED 0x4 163 #define DP_TX_INVALID_QOS_TAG 0xf 164 165 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 166 #define DP_RX_REFILL_BUFF_POOL_BURST 64 167 #endif 168 169 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 170 #define DP_RX_FSE_FLOW_MATCH_SFE 0xAAAA 171 #endif 172 173 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 174 #define DP_SKIP_BAR_UPDATE_TIMEOUT 5000 175 #endif 176 177 #define DP_TX_MAGIC_PATTERN_INUSE 0xABCD1234 178 #define DP_TX_MAGIC_PATTERN_FREE 0xDEADBEEF 179 180 #define DP_INTR_POLL_TIMER_MS 5 181 182 #ifdef IPA_OFFLOAD 183 #define DP_PEER_REO_STATS_TID_SHIFT 16 184 #define DP_PEER_REO_STATS_TID_MASK 0xFFFF0000 185 #define DP_PEER_REO_STATS_PEER_ID_MASK 0x0000FFFF 186 #define DP_PEER_GET_REO_STATS_TID(comb_peer_id_tid) \ 187 ((comb_peer_id_tid & DP_PEER_REO_STATS_TID_MASK) >> \ 188 DP_PEER_REO_STATS_TID_SHIFT) 189 #define DP_PEER_GET_REO_STATS_PEER_ID(comb_peer_id_tid) \ 190 (comb_peer_id_tid & DP_PEER_REO_STATS_PEER_ID_MASK) 191 #endif 192 193 typedef void dp_ptnr_soc_iter_func(struct dp_soc *ptnr_soc, void *arg, 194 int chip_id); 195 196 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 197 #define DP_MLD_MODE_UNIFIED_NONBOND 0 198 #define DP_MLD_MODE_UNIFIED_BOND 1 199 #define DP_MLD_MODE_HYBRID_NONBOND 2 200 #define DP_MLD_MODE_MAX DP_MLD_MODE_HYBRID_NONBOND 201 202 #define DP_LINK_VDEV_ITER 1 203 #define DP_BRIDGE_VDEV_ITER 2 204 #define DP_ALL_VDEV_ITER 3 205 #define IS_LINK_VDEV_ITER_REQUIRED(type) (type & DP_LINK_VDEV_ITER) 206 #define IS_BRIDGE_VDEV_ITER_REQUIRED(type) (type & DP_BRIDGE_VDEV_ITER) 207 #define DP_VDEV_ITERATE_ALL 1 208 #define DP_VDEV_ITERATE_SKIP_SELF 0 209 #endif 210 211 /** 212 * enum dp_pkt_xmit_type - The type of ingress stats are being referred 213 * 214 * @DP_XMIT_LINK: Packet ingress-ed on Link 215 * @DP_XMIT_MLD: Packet ingress-ed on MLD 216 * @DP_XMIT_TOTAL: Packets ingress-ed on MLD and LINK 217 */ 218 enum dp_pkt_xmit_type { 219 DP_XMIT_LINK, 220 DP_XMIT_MLD, 221 DP_XMIT_TOTAL, 222 }; 223 224 enum rx_pktlog_mode { 225 DP_RX_PKTLOG_DISABLED = 0, 226 DP_RX_PKTLOG_FULL, 227 DP_RX_PKTLOG_LITE, 228 }; 229 230 /* enum m_copy_mode - Available mcopy mode 231 * 232 */ 233 enum m_copy_mode { 234 M_COPY_DISABLED = 0, 235 M_COPY = 2, 236 M_COPY_EXTENDED = 4, 237 }; 238 239 struct msdu_list { 240 qdf_nbuf_t head; 241 qdf_nbuf_t tail; 242 uint32_t sum_len; 243 }; 244 245 struct dp_soc_cmn; 246 struct dp_pdev; 247 struct dp_vdev; 248 struct dp_tx_desc_s; 249 struct dp_soc; 250 union dp_rx_desc_list_elem_t; 251 struct cdp_peer_rate_stats_ctx; 252 struct cdp_soc_rate_stats_ctx; 253 struct dp_rx_fst; 254 struct dp_mon_filter; 255 struct dp_mon_mpdu; 256 #ifdef BE_PKTLOG_SUPPORT 257 struct dp_mon_filter_be; 258 #endif 259 struct dp_peer; 260 struct dp_txrx_peer; 261 262 /** 263 * enum dp_peer_state - DP peer states 264 * @DP_PEER_STATE_NONE: 265 * @DP_PEER_STATE_INIT: 266 * @DP_PEER_STATE_ACTIVE: 267 * @DP_PEER_STATE_LOGICAL_DELETE: 268 * @DP_PEER_STATE_INACTIVE: 269 * @DP_PEER_STATE_FREED: 270 * @DP_PEER_STATE_INVALID: 271 */ 272 enum dp_peer_state { 273 DP_PEER_STATE_NONE, 274 DP_PEER_STATE_INIT, 275 DP_PEER_STATE_ACTIVE, 276 DP_PEER_STATE_LOGICAL_DELETE, 277 DP_PEER_STATE_INACTIVE, 278 DP_PEER_STATE_FREED, 279 DP_PEER_STATE_INVALID, 280 }; 281 282 /** 283 * enum dp_mod_id - DP module IDs 284 * @DP_MOD_ID_TX_RX: 285 * @DP_MOD_ID_TX_COMP: 286 * @DP_MOD_ID_RX: 287 * @DP_MOD_ID_HTT_COMP: 288 * @DP_MOD_ID_RX_ERR: 289 * @DP_MOD_ID_TX_PPDU_STATS: 290 * @DP_MOD_ID_RX_PPDU_STATS: 291 * @DP_MOD_ID_CDP: 292 * @DP_MOD_ID_GENERIC_STATS: 293 * @DP_MOD_ID_TX_MULTIPASS: 294 * @DP_MOD_ID_TX_CAPTURE: 295 * @DP_MOD_ID_NSS_OFFLOAD: 296 * @DP_MOD_ID_CONFIG: 297 * @DP_MOD_ID_HTT: 298 * @DP_MOD_ID_IPA: 299 * @DP_MOD_ID_AST: 300 * @DP_MOD_ID_MCAST2UCAST: 301 * @DP_MOD_ID_CHILD: 302 * @DP_MOD_ID_MESH: 303 * @DP_MOD_ID_TX_EXCEPTION: 304 * @DP_MOD_ID_TDLS: 305 * @DP_MOD_ID_MISC: 306 * @DP_MOD_ID_MSCS: 307 * @DP_MOD_ID_TX: 308 * @DP_MOD_ID_SAWF: 309 * @DP_MOD_ID_REINJECT: 310 * @DP_MOD_ID_SCS: 311 * @DP_MOD_ID_UMAC_RESET: 312 * @DP_MOD_ID_TX_MCAST: 313 * @DP_MOD_ID_DS: 314 * @DP_MOD_ID_MLO_DEV: 315 * @DP_MOD_ID_MAX: 316 */ 317 enum dp_mod_id { 318 DP_MOD_ID_TX_RX, 319 DP_MOD_ID_TX_COMP, 320 DP_MOD_ID_RX, 321 DP_MOD_ID_HTT_COMP, 322 DP_MOD_ID_RX_ERR, 323 DP_MOD_ID_TX_PPDU_STATS, 324 DP_MOD_ID_RX_PPDU_STATS, 325 DP_MOD_ID_CDP, 326 DP_MOD_ID_GENERIC_STATS, 327 DP_MOD_ID_TX_MULTIPASS, 328 DP_MOD_ID_TX_CAPTURE, 329 DP_MOD_ID_NSS_OFFLOAD, 330 DP_MOD_ID_CONFIG, 331 DP_MOD_ID_HTT, 332 DP_MOD_ID_IPA, 333 DP_MOD_ID_AST, 334 DP_MOD_ID_MCAST2UCAST, 335 DP_MOD_ID_CHILD, 336 DP_MOD_ID_MESH, 337 DP_MOD_ID_TX_EXCEPTION, 338 DP_MOD_ID_TDLS, 339 DP_MOD_ID_MISC, 340 DP_MOD_ID_MSCS, 341 DP_MOD_ID_TX, 342 DP_MOD_ID_SAWF, 343 DP_MOD_ID_REINJECT, 344 DP_MOD_ID_SCS, 345 DP_MOD_ID_UMAC_RESET, 346 DP_MOD_ID_TX_MCAST, 347 DP_MOD_ID_DS, 348 DP_MOD_ID_MLO_DEV, 349 DP_MOD_ID_MAX, 350 }; 351 352 /** 353 * enum dp_peer_type - DP peer type 354 * @DP_PEER_TYPE_LEGACY: 355 * @DP_PEER_TYPE_MLO_LINK: 356 * @DP_PEER_TYPE_MLO: 357 */ 358 enum dp_peer_type { 359 DP_PEER_TYPE_LEGACY, 360 DP_PEER_TYPE_MLO_LINK, 361 DP_PEER_TYPE_MLO, 362 }; 363 364 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 365 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 366 367 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 368 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 369 370 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 371 TAILQ_FOREACH_SAFE((_ase), &_peer->ast_entry_list, ase_list_elem, (_temp_ase)) 372 373 #define DP_MUTEX_TYPE qdf_spinlock_t 374 375 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 376 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 377 378 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 379 ((_a)[0] == 0x33 && \ 380 (_a)[1] == 0x33) 381 382 #define DP_FRAME_IS_BROADCAST(_a) \ 383 ((_a)[0] == 0xff && \ 384 (_a)[1] == 0xff && \ 385 (_a)[2] == 0xff && \ 386 (_a)[3] == 0xff && \ 387 (_a)[4] == 0xff && \ 388 (_a)[5] == 0xff) 389 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 390 (_llc)->llc_ssap == 0xaa && \ 391 (_llc)->llc_un.type_snap.control == 0x3) 392 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 393 #define DP_FRAME_FC0_TYPE_MASK 0x0c 394 #define DP_FRAME_FC0_TYPE_DATA 0x08 395 #define DP_FRAME_IS_DATA(_frame) \ 396 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 397 398 /* 399 * macros to convert hw mac id to sw mac id: 400 * mac ids used by hardware start from a value of 1 while 401 * those in host software start from a value of 0. Use the 402 * macros below to convert between mac ids used by software and 403 * hardware 404 */ 405 #define DP_SW2HW_MACID(id) ((id) + 1) 406 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 407 408 /* 409 * Number of Tx Queues 410 * enum and macro to define how many threshold levels is used 411 * for the AC based flow control 412 */ 413 #ifdef QCA_AC_BASED_FLOW_CONTROL 414 enum dp_fl_ctrl_threshold { 415 DP_TH_BE_BK = 0, 416 DP_TH_VI, 417 DP_TH_VO, 418 DP_TH_HI, 419 }; 420 421 #define FL_TH_MAX (4) 422 #define FL_TH_VI_PERCENTAGE (80) 423 #define FL_TH_VO_PERCENTAGE (60) 424 #define FL_TH_HI_PERCENTAGE (40) 425 #endif 426 427 /** 428 * enum dp_intr_mode 429 * @DP_INTR_INTEGRATED: Line interrupts 430 * @DP_INTR_MSI: MSI interrupts 431 * @DP_INTR_POLL: Polling 432 * @DP_INTR_LEGACY_VIRTUAL_IRQ: 433 */ 434 enum dp_intr_mode { 435 DP_INTR_INTEGRATED = 0, 436 DP_INTR_MSI, 437 DP_INTR_POLL, 438 DP_INTR_LEGACY_VIRTUAL_IRQ, 439 }; 440 441 /** 442 * enum dp_tx_frm_type 443 * @dp_tx_frm_std: Regular frame, no added header fragments 444 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 445 * @dp_tx_frm_sg: SG segment 446 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 447 * @dp_tx_frm_me: Multicast to Unicast Converted frame 448 * @dp_tx_frm_raw: Raw Frame 449 * @dp_tx_frm_rmnet: 450 */ 451 enum dp_tx_frm_type { 452 dp_tx_frm_std = 0, 453 dp_tx_frm_tso, 454 dp_tx_frm_sg, 455 dp_tx_frm_audio, 456 dp_tx_frm_me, 457 dp_tx_frm_raw, 458 dp_tx_frm_rmnet, 459 }; 460 461 /** 462 * enum dp_ast_type 463 * @dp_ast_type_wds: WDS peer AST type 464 * @dp_ast_type_static: static ast entry type 465 * @dp_ast_type_mec: Multicast echo ast entry type 466 */ 467 enum dp_ast_type { 468 dp_ast_type_wds = 0, 469 dp_ast_type_static, 470 dp_ast_type_mec, 471 }; 472 473 /** 474 * enum dp_nss_cfg 475 * @dp_nss_cfg_default: No radios are offloaded 476 * @dp_nss_cfg_first_radio: First radio offloaded 477 * @dp_nss_cfg_second_radio: Second radio offloaded 478 * @dp_nss_cfg_dbdc: Dual radios offloaded 479 * @dp_nss_cfg_dbtc: Three radios offloaded 480 * @dp_nss_cfg_max: max value 481 */ 482 enum dp_nss_cfg { 483 dp_nss_cfg_default = 0x0, 484 dp_nss_cfg_first_radio = 0x1, 485 dp_nss_cfg_second_radio = 0x2, 486 dp_nss_cfg_dbdc = 0x3, 487 dp_nss_cfg_dbtc = 0x7, 488 dp_nss_cfg_max 489 }; 490 491 #ifdef WLAN_TX_PKT_CAPTURE_ENH 492 #define DP_CPU_RING_MAP_1 1 493 #endif 494 495 /** 496 * enum dp_cpu_ring_map_types - dp tx cpu ring map 497 * @DP_NSS_DEFAULT_MAP: Default mode with no NSS offloaded 498 * @DP_NSS_FIRST_RADIO_OFFLOADED_MAP: Only First Radio is offloaded 499 * @DP_NSS_SECOND_RADIO_OFFLOADED_MAP: Only second radio is offloaded 500 * @DP_NSS_DBDC_OFFLOADED_MAP: Both radios are offloaded 501 * @DP_NSS_DBTC_OFFLOADED_MAP: All three radios are offloaded 502 * @DP_SINGLE_TX_RING_MAP: to avoid out of order all cpu mapped to single ring 503 * @DP_NSS_CPU_RING_MAP_MAX: Max cpu ring map val 504 */ 505 enum dp_cpu_ring_map_types { 506 DP_NSS_DEFAULT_MAP, 507 DP_NSS_FIRST_RADIO_OFFLOADED_MAP, 508 DP_NSS_SECOND_RADIO_OFFLOADED_MAP, 509 DP_NSS_DBDC_OFFLOADED_MAP, 510 DP_NSS_DBTC_OFFLOADED_MAP, 511 #ifdef WLAN_TX_PKT_CAPTURE_ENH 512 DP_SINGLE_TX_RING_MAP, 513 #endif 514 DP_NSS_CPU_RING_MAP_MAX 515 }; 516 517 /** 518 * struct dp_rx_nbuf_frag_info - Hold vaddr and paddr for a buffer 519 * 520 * @paddr: Physical address of buffer allocated. 521 * @virt_addr: union of virtual address representations 522 * @nbuf: Allocated nbuf in case of nbuf approach. 523 * @vaddr: Virtual address of frag allocated in case of frag approach. 524 */ 525 struct dp_rx_nbuf_frag_info { 526 qdf_dma_addr_t paddr; 527 union { 528 qdf_nbuf_t nbuf; 529 qdf_frag_t vaddr; 530 } virt_addr; 531 }; 532 533 /** 534 * enum dp_ctxt_type - context type 535 * @DP_PDEV_TYPE: PDEV context 536 * @DP_RX_RING_HIST_TYPE: Datapath rx ring history 537 * @DP_RX_ERR_RING_HIST_TYPE: Datapath rx error ring history 538 * @DP_RX_REINJECT_RING_HIST_TYPE: Datapath reinject ring history 539 * @DP_TX_TCL_HIST_TYPE: 540 * @DP_TX_COMP_HIST_TYPE: 541 * @DP_FISA_RX_FT_TYPE: 542 * @DP_RX_REFILL_RING_HIST_TYPE: Datapath rx refill ring history 543 * @DP_TX_HW_DESC_HIST_TYPE: Datapath TX HW descriptor history 544 * @DP_MON_SOC_TYPE: Datapath monitor soc context 545 * @DP_MON_PDEV_TYPE: Datapath monitor pdev context 546 * @DP_MON_STATUS_BUF_HIST_TYPE: DP monitor status buffer history 547 * @DP_CFG_EVENT_HIST_TYPE: DP config events history 548 * @DP_MON_TX_DESC_POOL_TYPE: DP TX desc pool buffer 549 * @DP_MON_RX_DESC_POOL_TYPE: DP RX desc pool buffer 550 */ 551 enum dp_ctxt_type { 552 DP_PDEV_TYPE, 553 DP_RX_RING_HIST_TYPE, 554 DP_RX_ERR_RING_HIST_TYPE, 555 DP_RX_REINJECT_RING_HIST_TYPE, 556 DP_TX_TCL_HIST_TYPE, 557 DP_TX_COMP_HIST_TYPE, 558 DP_FISA_RX_FT_TYPE, 559 DP_RX_REFILL_RING_HIST_TYPE, 560 DP_TX_HW_DESC_HIST_TYPE, 561 DP_MON_SOC_TYPE, 562 DP_MON_PDEV_TYPE, 563 DP_MON_STATUS_BUF_HIST_TYPE, 564 DP_CFG_EVENT_HIST_TYPE, 565 DP_MON_TX_DESC_POOL_TYPE, 566 DP_MON_RX_DESC_POOL_TYPE, 567 }; 568 569 /** 570 * struct rx_desc_pool 571 * @pool_size: number of RX descriptor in the pool 572 * @elem_size: Element size 573 * @desc_pages: Multi page descriptors 574 * @array: pointer to array of RX descriptor 575 * @freelist: pointer to free RX descriptor link list 576 * @lock: Protection for the RX descriptor pool 577 * @owner: owner for nbuf 578 * @buf_size: Buffer size 579 * @buf_alignment: Buffer alignment 580 * @rx_mon_dest_frag_enable: Enable frag processing for mon dest buffer 581 * @pf_cache: page frag cache 582 * @desc_type: type of desc this pool serves 583 */ 584 struct rx_desc_pool { 585 uint32_t pool_size; 586 #ifdef RX_DESC_MULTI_PAGE_ALLOC 587 uint16_t elem_size; 588 struct qdf_mem_multi_page_t desc_pages; 589 #else 590 union dp_rx_desc_list_elem_t *array; 591 #endif 592 union dp_rx_desc_list_elem_t *freelist; 593 qdf_spinlock_t lock; 594 uint8_t owner; 595 uint16_t buf_size; 596 uint8_t buf_alignment; 597 bool rx_mon_dest_frag_enable; 598 qdf_frag_cache_t pf_cache; 599 enum qdf_dp_desc_type desc_type; 600 }; 601 602 /** 603 * struct dp_tx_ext_desc_elem_s 604 * @next: next extension descriptor pointer 605 * @vaddr: hlos virtual address pointer 606 * @paddr: physical address pointer for descriptor 607 * @flags: mark features for extension descriptor 608 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 609 * Tx completion of ME packet 610 * @tso_desc: Pointer to Tso desc 611 * @tso_num_desc: Pointer to tso_num_desc 612 */ 613 struct dp_tx_ext_desc_elem_s { 614 struct dp_tx_ext_desc_elem_s *next; 615 void *vaddr; 616 qdf_dma_addr_t paddr; 617 uint16_t flags; 618 struct dp_tx_me_buf_t *me_buffer; 619 struct qdf_tso_seg_elem_t *tso_desc; 620 struct qdf_tso_num_seg_elem_t *tso_num_desc; 621 }; 622 623 /* 624 * NB: intentionally not using kernel-doc comment because the kernel-doc 625 * script does not handle the qdf_dma_mem_context macro 626 * struct dp_tx_ext_desc_pool_s - Tx Extension Descriptor Pool 627 * @elem_count: Number of descriptors in the pool 628 * @elem_size: Size of each descriptor 629 * @num_free: Number of free descriptors 630 * @desc_pages: multiple page allocation information for actual descriptors 631 * @link_elem_size: size of the link descriptor in cacheable memory used for 632 * chaining the extension descriptors 633 * @desc_link_pages: multiple page allocation information for link descriptors 634 * @freelist: 635 * @lock: 636 * @memctx: 637 */ 638 struct dp_tx_ext_desc_pool_s { 639 uint16_t elem_count; 640 int elem_size; 641 uint16_t num_free; 642 struct qdf_mem_multi_page_t desc_pages; 643 int link_elem_size; 644 struct qdf_mem_multi_page_t desc_link_pages; 645 struct dp_tx_ext_desc_elem_s *freelist; 646 qdf_spinlock_t lock; 647 qdf_dma_mem_context(memctx); 648 }; 649 650 /** 651 * struct dp_tx_desc_s - Tx Descriptor 652 * @next: Next in the chain of descriptors in freelist or in the completion list 653 * @nbuf: Buffer Address 654 * @length: 655 * @magic: 656 * @timestamp_tick: 657 * @flags: Flags to track the state of descriptor and special frame handling 658 * @id: Descriptor ID 659 * @dma_addr: 660 * @vdev_id: vdev_id of vdev over which the packet was transmitted 661 * @tx_status: 662 * @peer_id: 663 * @pdev: Handle to pdev 664 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 665 * This is maintained in descriptor to allow more efficient 666 * processing in completion event processing code. 667 * This field is filled in with the htt_pkt_type enum. 668 * @buffer_src: buffer source TQM, REO, FW etc. 669 * @reserved: 670 * @frm_type: Frame Type - ToDo check if this is redundant 671 * @pkt_offset: Offset from which the actual packet data starts 672 * @pool_id: Pool ID - used when releasing the descriptor 673 * @msdu_ext_desc: MSDU extension descriptor 674 * @timestamp: 675 * @driver_egress_ts: driver egress timestamp 676 * @driver_ingress_ts: driver ingress timestamp 677 * @comp: 678 * @tcl_cmd_vaddr: VADDR of the TCL descriptor, valid for soft-umac arch 679 * @tcl_cmd_paddr: PADDR of the TCL descriptor, valid for soft-umac arch 680 */ 681 struct dp_tx_desc_s { 682 struct dp_tx_desc_s *next; 683 qdf_nbuf_t nbuf; 684 uint16_t length; 685 #ifdef DP_TX_TRACKING 686 uint32_t magic; 687 uint64_t timestamp_tick; 688 #endif 689 uint32_t flags; 690 uint32_t id; 691 qdf_dma_addr_t dma_addr; 692 uint8_t vdev_id; 693 uint8_t tx_status; 694 uint16_t peer_id; 695 struct dp_pdev *pdev; 696 uint8_t tx_encap_type:2, 697 buffer_src:3, 698 reserved:3; 699 uint8_t frm_type; 700 uint8_t pkt_offset; 701 uint8_t pool_id; 702 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 703 qdf_ktime_t timestamp; 704 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 705 qdf_ktime_t driver_egress_ts; 706 qdf_ktime_t driver_ingress_ts; 707 #endif 708 struct hal_tx_desc_comp_s comp; 709 #ifdef WLAN_SOFTUMAC_SUPPORT 710 void *tcl_cmd_vaddr; 711 qdf_dma_addr_t tcl_cmd_paddr; 712 #endif 713 }; 714 715 #ifdef QCA_AC_BASED_FLOW_CONTROL 716 /** 717 * enum flow_pool_status - flow pool status 718 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 719 * and network queues are unpaused 720 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 721 * and network queues are paused 722 * @FLOW_POOL_BE_BK_PAUSED: 723 * @FLOW_POOL_VI_PAUSED: 724 * @FLOW_POOL_VO_PAUSED: 725 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 726 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 727 * @FLOW_POOL_ACTIVE_UNPAUSED_REATTACH: pool is reattached but network 728 * queues are not paused 729 */ 730 enum flow_pool_status { 731 FLOW_POOL_ACTIVE_UNPAUSED = 0, 732 FLOW_POOL_ACTIVE_PAUSED = 1, 733 FLOW_POOL_BE_BK_PAUSED = 2, 734 FLOW_POOL_VI_PAUSED = 3, 735 FLOW_POOL_VO_PAUSED = 4, 736 FLOW_POOL_INVALID = 5, 737 FLOW_POOL_INACTIVE = 6, 738 FLOW_POOL_ACTIVE_UNPAUSED_REATTACH = 7, 739 }; 740 741 #else 742 /** 743 * enum flow_pool_status - flow pool status 744 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 745 * and network queues are unpaused 746 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 747 * and network queues are paused 748 * @FLOW_POOL_BE_BK_PAUSED: 749 * @FLOW_POOL_VI_PAUSED: 750 * @FLOW_POOL_VO_PAUSED: 751 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 752 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 753 */ 754 enum flow_pool_status { 755 FLOW_POOL_ACTIVE_UNPAUSED = 0, 756 FLOW_POOL_ACTIVE_PAUSED = 1, 757 FLOW_POOL_BE_BK_PAUSED = 2, 758 FLOW_POOL_VI_PAUSED = 3, 759 FLOW_POOL_VO_PAUSED = 4, 760 FLOW_POOL_INVALID = 5, 761 FLOW_POOL_INACTIVE = 6, 762 }; 763 764 #endif 765 766 /** 767 * struct dp_tx_tso_seg_pool_s 768 * @pool_size: total number of pool elements 769 * @num_free: free element count 770 * @freelist: first free element pointer 771 * @desc_pages: multiple page allocation information for actual descriptors 772 * @lock: lock for accessing the pool 773 */ 774 struct dp_tx_tso_seg_pool_s { 775 uint16_t pool_size; 776 uint16_t num_free; 777 struct qdf_tso_seg_elem_t *freelist; 778 struct qdf_mem_multi_page_t desc_pages; 779 qdf_spinlock_t lock; 780 }; 781 782 /** 783 * struct dp_tx_tso_num_seg_pool_s - TSO Num seg pool 784 * @num_seg_pool_size: total number of pool elements 785 * @num_free: free element count 786 * @freelist: first free element pointer 787 * @desc_pages: multiple page allocation information for actual descriptors 788 * @lock: lock for accessing the pool 789 */ 790 791 struct dp_tx_tso_num_seg_pool_s { 792 uint16_t num_seg_pool_size; 793 uint16_t num_free; 794 struct qdf_tso_num_seg_elem_t *freelist; 795 struct qdf_mem_multi_page_t desc_pages; 796 /*tso mutex */ 797 qdf_spinlock_t lock; 798 }; 799 800 /** 801 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 802 * @elem_size: Size of each descriptor in the pool 803 * @num_allocated: Number of used descriptors 804 * @freelist: Chain of free descriptors 805 * @desc_pages: multiple page allocation information for actual descriptors 806 * @pool_size: Total number of descriptors in the pool 807 * @flow_pool_id: 808 * @num_invalid_bin: Deleted pool with pending Tx completions. 809 * @avail_desc: 810 * @status: 811 * @flow_type: 812 * @stop_th: 813 * @start_th: 814 * @max_pause_time: 815 * @latest_pause_time: 816 * @pkt_drop_no_desc: 817 * @flow_pool_lock: 818 * @pool_create_cnt: 819 * @pool_owner_ctx: 820 * @elem_count: 821 * @num_free: Number of free descriptors 822 * @lock: Lock for descriptor allocation/free from/to the pool 823 */ 824 struct dp_tx_desc_pool_s { 825 uint16_t elem_size; 826 uint32_t num_allocated; 827 struct dp_tx_desc_s *freelist; 828 struct qdf_mem_multi_page_t desc_pages; 829 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 830 uint16_t pool_size; 831 uint8_t flow_pool_id; 832 uint8_t num_invalid_bin; 833 uint16_t avail_desc; 834 enum flow_pool_status status; 835 enum htt_flow_type flow_type; 836 #ifdef QCA_AC_BASED_FLOW_CONTROL 837 uint16_t stop_th[FL_TH_MAX]; 838 uint16_t start_th[FL_TH_MAX]; 839 qdf_time_t max_pause_time[FL_TH_MAX]; 840 qdf_time_t latest_pause_time[FL_TH_MAX]; 841 #else 842 uint16_t stop_th; 843 uint16_t start_th; 844 #endif 845 uint16_t pkt_drop_no_desc; 846 qdf_spinlock_t flow_pool_lock; 847 uint8_t pool_create_cnt; 848 void *pool_owner_ctx; 849 #else 850 uint16_t elem_count; 851 uint32_t num_free; 852 qdf_spinlock_t lock; 853 #endif 854 }; 855 856 /** 857 * struct dp_txrx_pool_stats - flow pool related statistics 858 * @pool_map_count: flow pool map received 859 * @pool_unmap_count: flow pool unmap received 860 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 861 */ 862 struct dp_txrx_pool_stats { 863 uint16_t pool_map_count; 864 uint16_t pool_unmap_count; 865 uint16_t pkt_drop_no_pool; 866 }; 867 868 /** 869 * struct dp_srng - DP srng structure 870 * @hal_srng: hal_srng handle 871 * @base_vaddr_unaligned: un-aligned virtual base address of the srng ring 872 * @base_vaddr_aligned: aligned virtual base address of the srng ring 873 * @base_paddr_unaligned: un-aligned physical base address of the srng ring 874 * @base_paddr_aligned: aligned physical base address of the srng ring 875 * @alloc_size: size of the srng ring 876 * @cached: is the srng ring memory cached or un-cached memory 877 * @irq: irq number of the srng ring 878 * @num_entries: number of entries in the srng ring 879 * @stats: Structure to track the ring utilization stats 880 * @is_mem_prealloc: Is this srng memory pre-allocated 881 * @crit_thresh: Critical threshold for near-full processing of this srng 882 * @safe_thresh: Safe threshold for near-full processing of this srng 883 * @near_full: Flag to indicate srng is near-full 884 */ 885 struct dp_srng { 886 hal_ring_handle_t hal_srng; 887 void *base_vaddr_unaligned; 888 void *base_vaddr_aligned; 889 qdf_dma_addr_t base_paddr_unaligned; 890 qdf_dma_addr_t base_paddr_aligned; 891 uint32_t alloc_size; 892 uint8_t cached; 893 int irq; 894 uint32_t num_entries; 895 struct ring_util_stats stats; 896 #ifdef DP_MEM_PRE_ALLOC 897 uint8_t is_mem_prealloc; 898 #endif 899 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 900 uint16_t crit_thresh; 901 uint16_t safe_thresh; 902 qdf_atomic_t near_full; 903 #endif 904 }; 905 906 struct dp_rx_reorder_array_elem { 907 qdf_nbuf_t head; 908 qdf_nbuf_t tail; 909 }; 910 911 #define DP_RX_BA_INACTIVE 0 912 #define DP_RX_BA_ACTIVE 1 913 #define DP_RX_BA_IN_PROGRESS 2 914 struct dp_reo_cmd_info { 915 uint16_t cmd; 916 enum hal_reo_cmd_type cmd_type; 917 void *data; 918 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 919 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 920 }; 921 922 struct dp_peer_delay_stats { 923 struct cdp_delay_tid_stats delay_tid_stats[CDP_MAX_DATA_TIDS] 924 [CDP_MAX_TXRX_CTX]; 925 }; 926 927 /* Rx TID defrag*/ 928 struct dp_rx_tid_defrag { 929 /* TID */ 930 int tid; 931 932 /* only used for defrag right now */ 933 TAILQ_ENTRY(dp_rx_tid_defrag) defrag_waitlist_elem; 934 935 /* Store dst desc for reinjection */ 936 hal_ring_desc_t dst_ring_desc; 937 struct dp_rx_desc *head_frag_desc; 938 939 /* Sequence and fragments that are being processed currently */ 940 uint32_t curr_seq_num; 941 uint32_t curr_frag_num; 942 943 /* TODO: Check the following while adding defragmentation support */ 944 struct dp_rx_reorder_array_elem *array; 945 /* base - single rx reorder element used for non-aggr cases */ 946 struct dp_rx_reorder_array_elem base; 947 /* rx_tid lock */ 948 qdf_spinlock_t defrag_tid_lock; 949 950 /* head PN number */ 951 uint64_t pn128[2]; 952 953 uint32_t defrag_timeout_ms; 954 955 /* defrag usage only, dp_peer pointer related with this tid */ 956 struct dp_txrx_peer *defrag_peer; 957 }; 958 959 /* Rx TID */ 960 struct dp_rx_tid { 961 /* TID */ 962 int tid; 963 964 /* Num of addba requests */ 965 uint32_t num_of_addba_req; 966 967 /* Num of addba responses */ 968 uint32_t num_of_addba_resp; 969 970 /* Num of delba requests */ 971 uint32_t num_of_delba_req; 972 973 /* Num of addba responses successful */ 974 uint32_t num_addba_rsp_success; 975 976 /* Num of addba responses failed */ 977 uint32_t num_addba_rsp_failed; 978 979 /* pn size */ 980 uint8_t pn_size; 981 /* REO TID queue descriptors */ 982 void *hw_qdesc_vaddr_unaligned; 983 void *hw_qdesc_vaddr_aligned; 984 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 985 qdf_dma_addr_t hw_qdesc_paddr; 986 uint32_t hw_qdesc_alloc_size; 987 988 /* RX ADDBA session state */ 989 int ba_status; 990 991 /* RX BA window size */ 992 uint16_t ba_win_size; 993 994 /* Starting sequence number in Addba request */ 995 uint16_t startseqnum; 996 uint16_t dialogtoken; 997 uint16_t statuscode; 998 /* user defined ADDBA response status code */ 999 uint16_t userstatuscode; 1000 1001 /* rx_tid lock */ 1002 qdf_spinlock_t tid_lock; 1003 1004 /* Store ppdu_id when 2k exception is received */ 1005 uint32_t ppdu_id_2k; 1006 1007 /* Delba Tx completion status */ 1008 uint8_t delba_tx_status; 1009 1010 /* Delba Tx retry count */ 1011 uint8_t delba_tx_retry; 1012 1013 /* Delba stats */ 1014 uint32_t delba_tx_success_cnt; 1015 uint32_t delba_tx_fail_cnt; 1016 1017 /* Delba reason code for retries */ 1018 uint8_t delba_rcode; 1019 1020 /* Coex Override preserved windows size 1 based */ 1021 uint16_t rx_ba_win_size_override; 1022 #ifdef IPA_OFFLOAD 1023 /* rx msdu count per tid */ 1024 struct cdp_pkt_info rx_msdu_cnt; 1025 #endif 1026 1027 }; 1028 1029 /** 1030 * struct dp_intr_stats - DP Interrupt Stats for an interrupt context 1031 * @num_tx_ring_masks: interrupts with tx_ring_mask set 1032 * @num_rx_ring_masks: interrupts with rx_ring_mask set 1033 * @num_rx_mon_ring_masks: interrupts with rx_mon_ring_mask set 1034 * @num_rx_err_ring_masks: interrupts with rx_err_ring_mask set 1035 * @num_rx_wbm_rel_ring_masks: interrupts with rx_wbm_rel_ring_mask set 1036 * @num_reo_status_ring_masks: interrupts with reo_status_ring_mask set 1037 * @num_rxdma2host_ring_masks: interrupts with rxdma2host_ring_mask set 1038 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 1039 * @num_host2rxdma_mon_ring_masks: interrupts with host2rxdma_ring_mask set 1040 * @num_rx_ring_near_full_masks: Near-full interrupts for REO DST ring 1041 * @num_tx_comp_ring_near_full_masks: Near-full interrupts for TX completion 1042 * @num_rx_wbm_rel_ring_near_full_masks: total number of times the wbm rel ring 1043 * near full interrupt was received 1044 * @num_reo_status_ring_near_full_masks: total number of times the reo status 1045 * near full interrupt was received 1046 * @num_near_full_masks: total number of times the near full interrupt 1047 * was received 1048 * @num_masks: total number of times the interrupt was received 1049 * @num_host2txmon_ring__masks: interrupts with host2txmon_ring_mask set 1050 * @num_near_full_masks: total number of times the interrupt was received 1051 * @num_masks: total number of times the near full interrupt was received 1052 * @num_tx_mon_ring_masks: interrupts with num_tx_mon_ring_masks set 1053 * 1054 * Counter for individual masks are incremented only if there are any packets 1055 * on that ring. 1056 */ 1057 struct dp_intr_stats { 1058 uint32_t num_tx_ring_masks[MAX_TCL_DATA_RINGS]; 1059 uint32_t num_rx_ring_masks[MAX_REO_DEST_RINGS]; 1060 uint32_t num_rx_mon_ring_masks; 1061 uint32_t num_rx_err_ring_masks; 1062 uint32_t num_rx_wbm_rel_ring_masks; 1063 uint32_t num_reo_status_ring_masks; 1064 uint32_t num_rxdma2host_ring_masks; 1065 uint32_t num_host2rxdma_ring_masks; 1066 uint32_t num_host2rxdma_mon_ring_masks; 1067 uint32_t num_rx_ring_near_full_masks[MAX_REO_DEST_RINGS]; 1068 uint32_t num_tx_comp_ring_near_full_masks[MAX_TCL_DATA_RINGS]; 1069 uint32_t num_rx_wbm_rel_ring_near_full_masks; 1070 uint32_t num_reo_status_ring_near_full_masks; 1071 uint32_t num_host2txmon_ring__masks; 1072 uint32_t num_near_full_masks; 1073 uint32_t num_masks; 1074 uint32_t num_tx_mon_ring_masks; 1075 }; 1076 1077 #ifdef DP_UMAC_HW_RESET_SUPPORT 1078 /** 1079 * struct dp_intr_bkp - DP per interrupt context ring masks old state 1080 * @tx_ring_mask: WBM Tx completion rings (0-2) associated with this napi ctxt 1081 * @rx_ring_mask: Rx REO rings (0-3) associated with this interrupt context 1082 * @rx_mon_ring_mask: Rx monitor ring mask (0-2) 1083 * @rx_err_ring_mask: REO Exception Ring 1084 * @rx_wbm_rel_ring_mask: WBM2SW Rx Release Ring 1085 * @reo_status_ring_mask: REO command response ring 1086 * @rxdma2host_ring_mask: RXDMA to host destination ring 1087 * @host2rxdma_ring_mask: Host to RXDMA buffer ring 1088 * @host2rxdma_mon_ring_mask: Host to RXDMA monitor buffer ring 1089 * @host2txmon_ring_mask: Tx monitor buffer ring 1090 * @tx_mon_ring_mask: Tx monitor ring mask (0-2) 1091 * 1092 */ 1093 struct dp_intr_bkp { 1094 uint8_t tx_ring_mask; 1095 uint8_t rx_ring_mask; 1096 uint8_t rx_mon_ring_mask; 1097 uint8_t rx_err_ring_mask; 1098 uint8_t rx_wbm_rel_ring_mask; 1099 uint8_t reo_status_ring_mask; 1100 uint8_t rxdma2host_ring_mask; 1101 uint8_t host2rxdma_ring_mask; 1102 uint8_t host2rxdma_mon_ring_mask; 1103 uint8_t host2txmon_ring_mask; 1104 uint8_t tx_mon_ring_mask; 1105 }; 1106 #endif 1107 1108 /* per interrupt context */ 1109 struct dp_intr { 1110 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 1111 associated with this napi context */ 1112 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 1113 with this interrupt context */ 1114 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 1115 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 1116 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 1117 uint8_t reo_status_ring_mask; /* REO command response ring */ 1118 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 1119 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 1120 /* Host to RXDMA monitor buffer ring */ 1121 uint8_t host2rxdma_mon_ring_mask; 1122 /* RX REO rings near full interrupt mask */ 1123 uint8_t rx_near_full_grp_1_mask; 1124 /* RX REO rings near full interrupt mask */ 1125 uint8_t rx_near_full_grp_2_mask; 1126 /* WBM TX completion rings near full interrupt mask */ 1127 uint8_t tx_ring_near_full_mask; 1128 uint8_t host2txmon_ring_mask; /* Tx monitor buffer ring */ 1129 uint8_t tx_mon_ring_mask; /* Tx monitor ring mask (0-2) */ 1130 struct dp_soc *soc; /* Reference to SoC structure , 1131 to get DMA ring handles */ 1132 qdf_lro_ctx_t lro_ctx; 1133 uint8_t dp_intr_id; 1134 1135 /* Interrupt Stats for individual masks */ 1136 struct dp_intr_stats intr_stats; 1137 uint8_t umac_reset_intr_mask; /* UMAC reset interrupt mask */ 1138 }; 1139 1140 #define REO_DESC_FREELIST_SIZE 64 1141 #define REO_DESC_FREE_DEFER_MS 1000 1142 struct reo_desc_list_node { 1143 qdf_list_node_t node; 1144 unsigned long free_ts; 1145 struct dp_rx_tid rx_tid; 1146 bool resend_update_reo_cmd; 1147 uint32_t pending_ext_desc_size; 1148 #ifdef REO_QDESC_HISTORY 1149 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1150 #endif 1151 }; 1152 1153 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 1154 #define REO_DESC_DEFERRED_FREELIST_SIZE 256 1155 #define REO_DESC_DEFERRED_FREE_MS 30000 1156 1157 struct reo_desc_deferred_freelist_node { 1158 qdf_list_node_t node; 1159 unsigned long free_ts; 1160 void *hw_qdesc_vaddr_unaligned; 1161 qdf_dma_addr_t hw_qdesc_paddr; 1162 uint32_t hw_qdesc_alloc_size; 1163 #ifdef REO_QDESC_HISTORY 1164 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1165 #endif /* REO_QDESC_HISTORY */ 1166 }; 1167 #endif /* WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY */ 1168 1169 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1170 /** 1171 * struct reo_cmd_event_record: Elements to record for each reo command 1172 * @cmd_type: reo command type 1173 * @cmd_return_status: reo command post status 1174 * @timestamp: record timestamp for the reo command 1175 */ 1176 struct reo_cmd_event_record { 1177 enum hal_reo_cmd_type cmd_type; 1178 uint8_t cmd_return_status; 1179 uint64_t timestamp; 1180 }; 1181 1182 /** 1183 * struct reo_cmd_event_history: Account for reo cmd events 1184 * @index: record number 1185 * @cmd_record: list of records 1186 */ 1187 struct reo_cmd_event_history { 1188 qdf_atomic_t index; 1189 struct reo_cmd_event_record cmd_record[REO_CMD_EVENT_HIST_MAX]; 1190 }; 1191 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1192 1193 /* SoC level data path statistics */ 1194 struct dp_soc_stats { 1195 struct { 1196 uint32_t added; 1197 uint32_t deleted; 1198 uint32_t aged_out; 1199 uint32_t map_err; 1200 uint32_t ast_mismatch; 1201 } ast; 1202 1203 struct { 1204 uint32_t added; 1205 uint32_t deleted; 1206 } mec; 1207 1208 /* SOC level TX stats */ 1209 struct { 1210 /* Total packets transmitted */ 1211 struct cdp_pkt_info egress[MAX_TCL_DATA_RINGS]; 1212 /* Enqueues per tcl ring */ 1213 uint32_t tcl_enq[MAX_TCL_DATA_RINGS]; 1214 /* packets dropped on tx because of no peer */ 1215 struct cdp_pkt_info tx_invalid_peer; 1216 /* descriptors in each tcl ring */ 1217 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 1218 /* Descriptors in use at soc */ 1219 uint32_t desc_in_use; 1220 /* tqm_release_reason == FW removed */ 1221 uint32_t dropped_fw_removed; 1222 /* tx completion release_src != TQM or FW */ 1223 uint32_t invalid_release_source; 1224 /* TX descriptor from completion ring Desc is not valid */ 1225 uint32_t invalid_tx_comp_desc; 1226 /* tx completion wbm_internal_error */ 1227 uint32_t wbm_internal_error[MAX_WBM_INT_ERROR_REASONS]; 1228 /* tx completion non_wbm_internal_error */ 1229 uint32_t non_wbm_internal_err; 1230 /* TX Comp loop packet limit hit */ 1231 uint32_t tx_comp_loop_pkt_limit_hit; 1232 /* Head pointer Out of sync at the end of dp_tx_comp_handler */ 1233 uint32_t hp_oos2; 1234 /* tx desc freed as part of vdev detach */ 1235 uint32_t tx_comp_exception; 1236 /* TQM drops after/during peer delete */ 1237 uint64_t tqm_drop_no_peer; 1238 /* Number of tx completions reaped per WBM2SW release ring */ 1239 uint32_t tx_comp[MAX_TCL_DATA_RINGS]; 1240 /* Number of tx completions force freed */ 1241 uint32_t tx_comp_force_freed; 1242 /* Tx completion ring near full */ 1243 uint32_t near_full; 1244 /* Tx drops with buffer src as HAL_TX_COMP_RELEASE_SOURCE_FW */ 1245 uint32_t fw2wbm_tx_drop; 1246 } tx; 1247 1248 /* SOC level RX stats */ 1249 struct { 1250 /* Total rx packets count */ 1251 struct cdp_pkt_info ingress; 1252 /* Rx errors */ 1253 /* Total Packets in Rx Error ring */ 1254 uint32_t err_ring_pkts; 1255 /* No of Fragments */ 1256 uint32_t rx_frags; 1257 /* No of incomplete fragments in waitlist */ 1258 uint32_t rx_frag_wait; 1259 /* Fragments dropped due to errors */ 1260 uint32_t rx_frag_err; 1261 /* Fragments received OOR causing sequence num mismatch */ 1262 uint32_t rx_frag_oor; 1263 /* Fragments dropped due to len errors in skb */ 1264 uint32_t rx_frag_err_len_error; 1265 /* Fragments dropped due to no peer found */ 1266 uint32_t rx_frag_err_no_peer; 1267 /* No of reinjected packets */ 1268 uint32_t reo_reinject; 1269 /* Reap loop packet limit hit */ 1270 uint32_t reap_loop_pkt_limit_hit; 1271 /* Head pointer Out of sync at the end of dp_rx_process */ 1272 uint32_t hp_oos2; 1273 /* Rx ring near full */ 1274 uint32_t near_full; 1275 /* Break ring reaping as not all scattered msdu received */ 1276 uint32_t msdu_scatter_wait_break; 1277 /* Number of bar frames received */ 1278 uint32_t bar_frame; 1279 /* Number of frames routed from rxdma */ 1280 uint32_t rxdma2rel_route_drop; 1281 /* Number of frames routed from reo*/ 1282 uint32_t reo2rel_route_drop; 1283 uint64_t fast_recycled; 1284 /* Number of hw stats requested */ 1285 uint32_t rx_hw_stats_requested; 1286 /* Number of hw stats request timeout */ 1287 uint32_t rx_hw_stats_timeout; 1288 1289 struct { 1290 /* Invalid RBM error count */ 1291 uint32_t invalid_rbm; 1292 /* Invalid VDEV Error count */ 1293 uint32_t invalid_vdev; 1294 /* Invalid PDEV error count */ 1295 uint32_t invalid_pdev; 1296 1297 /* Packets delivered to stack that no related peer */ 1298 uint32_t pkt_delivered_no_peer; 1299 /* Defrag peer uninit error count */ 1300 uint32_t defrag_peer_uninit; 1301 /* Invalid sa_idx or da_idx*/ 1302 uint32_t invalid_sa_da_idx; 1303 /* MSDU DONE failures */ 1304 uint32_t msdu_done_fail; 1305 /* Invalid PEER Error count */ 1306 struct cdp_pkt_info rx_invalid_peer; 1307 /* Invalid PEER ID count */ 1308 struct cdp_pkt_info rx_invalid_peer_id; 1309 /* Invalid packet length */ 1310 struct cdp_pkt_info rx_invalid_pkt_len; 1311 /* HAL ring access Fail error count */ 1312 uint32_t hal_ring_access_fail; 1313 /* HAL ring access full Fail error count */ 1314 uint32_t hal_ring_access_full_fail; 1315 /* RX DMA error count */ 1316 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 1317 /* RX REO DEST Desc Invalid Magic count */ 1318 uint32_t rx_desc_invalid_magic; 1319 /* REO Error count */ 1320 uint32_t reo_error[HAL_REO_ERR_MAX]; 1321 /* HAL REO ERR Count */ 1322 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 1323 /* HAL REO DEST Duplicate count */ 1324 uint32_t hal_reo_dest_dup; 1325 /* HAL WBM RELEASE Duplicate count */ 1326 uint32_t hal_wbm_rel_dup; 1327 /* HAL RXDMA error Duplicate count */ 1328 uint32_t hal_rxdma_err_dup; 1329 /* ipa smmu map duplicate count */ 1330 uint32_t ipa_smmu_map_dup; 1331 /* ipa smmu unmap duplicate count */ 1332 uint32_t ipa_smmu_unmap_dup; 1333 /* ipa smmu unmap while ipa pipes is disabled */ 1334 uint32_t ipa_unmap_no_pipe; 1335 /* REO cmd send fail/requeue count */ 1336 uint32_t reo_cmd_send_fail; 1337 /* REO cmd send drain count */ 1338 uint32_t reo_cmd_send_drain; 1339 /* RX msdu drop count due to scatter */ 1340 uint32_t scatter_msdu; 1341 /* RX msdu drop count due to invalid cookie */ 1342 uint32_t invalid_cookie; 1343 /* Count of stale cookie read in RX path */ 1344 uint32_t stale_cookie; 1345 /* Delba sent count due to RX 2k jump */ 1346 uint32_t rx_2k_jump_delba_sent; 1347 /* RX 2k jump msdu indicated to stack count */ 1348 uint32_t rx_2k_jump_to_stack; 1349 /* RX 2k jump msdu dropped count */ 1350 uint32_t rx_2k_jump_drop; 1351 /* REO ERR msdu buffer received */ 1352 uint32_t reo_err_msdu_buf_rcved; 1353 /* REO ERR msdu buffer with invalid coookie received */ 1354 uint32_t reo_err_msdu_buf_invalid_cookie; 1355 /* REO OOR msdu drop count */ 1356 uint32_t reo_err_oor_drop; 1357 /* REO OOR msdu indicated to stack count */ 1358 uint32_t reo_err_oor_to_stack; 1359 /* REO OOR scattered msdu count */ 1360 uint32_t reo_err_oor_sg_count; 1361 /* RX msdu rejected count on delivery to vdev stack_fn*/ 1362 uint32_t rejected; 1363 /* Incorrect msdu count in MPDU desc info */ 1364 uint32_t msdu_count_mismatch; 1365 /* RX raw frame dropped count */ 1366 uint32_t raw_frm_drop; 1367 /* Stale link desc cookie count*/ 1368 uint32_t invalid_link_cookie; 1369 /* Nbuf sanity failure */ 1370 uint32_t nbuf_sanity_fail; 1371 /* Duplicate link desc refilled */ 1372 uint32_t dup_refill_link_desc; 1373 /* Incorrect msdu continuation bit in MSDU desc */ 1374 uint32_t msdu_continuation_err; 1375 /* count of start sequence (ssn) updates */ 1376 uint32_t ssn_update_count; 1377 /* count of bar handling fail */ 1378 uint32_t bar_handle_fail_count; 1379 /* EAPOL drop count in intrabss scenario */ 1380 uint32_t intrabss_eapol_drop; 1381 /* PN check failed for 2K-jump or OOR error */ 1382 uint32_t pn_in_dest_check_fail; 1383 /* MSDU len err count */ 1384 uint32_t msdu_len_err; 1385 /* Rx flush count */ 1386 uint32_t rx_flush_count; 1387 /* Rx invalid tid count */ 1388 uint32_t rx_invalid_tid_err; 1389 /* Invalid address1 in defrag path*/ 1390 uint32_t defrag_ad1_invalid; 1391 /* decrypt error drop */ 1392 uint32_t decrypt_err_drop; 1393 #ifdef GLOBAL_ASSERT_AVOIDANCE 1394 /* rx_desc NULL war count*/ 1395 uint32_t rx_desc_null; 1396 /* wbm err invalid release buffer type */ 1397 uint32_t wbm_err_buf_rel_type; 1398 /* Reo entry rx desc null */ 1399 uint32_t reo_err_rx_desc_null; 1400 /* Invalid chip id received in intrabss path */ 1401 uint64_t intra_bss_bad_chipid; 1402 #endif 1403 } err; 1404 1405 /* packet count per core - per ring */ 1406 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 1407 } rx; 1408 1409 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1410 struct reo_cmd_event_history cmd_event_history; 1411 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1412 }; 1413 1414 union dp_align_mac_addr { 1415 uint8_t raw[QDF_MAC_ADDR_SIZE]; 1416 struct { 1417 uint16_t bytes_ab; 1418 uint16_t bytes_cd; 1419 uint16_t bytes_ef; 1420 } align2; 1421 struct { 1422 uint32_t bytes_abcd; 1423 uint16_t bytes_ef; 1424 } align4; 1425 struct __attribute__((__packed__)) { 1426 uint16_t bytes_ab; 1427 uint32_t bytes_cdef; 1428 } align4_2; 1429 }; 1430 1431 /** 1432 * struct dp_ast_free_cb_params - HMWDS free callback cookie 1433 * @mac_addr: ast mac address 1434 * @peer_mac_addr: mac address of peer 1435 * @type: ast entry type 1436 * @vdev_id: vdev_id 1437 * @flags: ast flags 1438 */ 1439 struct dp_ast_free_cb_params { 1440 union dp_align_mac_addr mac_addr; 1441 union dp_align_mac_addr peer_mac_addr; 1442 enum cdp_txrx_ast_entry_type type; 1443 uint8_t vdev_id; 1444 uint32_t flags; 1445 }; 1446 1447 /** 1448 * struct dp_ast_entry - AST entry 1449 * 1450 * @ast_idx: Hardware AST Index 1451 * @peer_id: Next Hop peer_id (for non-WDS nodes, this will be point to 1452 * associated peer with this MAC address) 1453 * @mac_addr: MAC Address for this AST entry 1454 * @next_hop: Set to 1 if this is for a WDS node 1455 * @is_active: flag to indicate active data traffic on this node 1456 * (used for aging out/expiry) 1457 * @ase_list_elem: node in peer AST list 1458 * @is_bss: flag to indicate if entry corresponds to bss peer 1459 * @is_mapped: flag to indicate that we have mapped the AST entry 1460 * in ast_table 1461 * @pdev_id: pdev ID 1462 * @vdev_id: vdev ID 1463 * @ast_hash_value: hast value in HW 1464 * @ref_cnt: reference count 1465 * @type: flag to indicate type of the entry(static/WDS/MEC) 1466 * @delete_in_progress: Flag to indicate that delete commands send to FW 1467 * and host is waiting for response from FW 1468 * @callback: ast free/unmap callback 1469 * @cookie: argument to callback 1470 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 1471 */ 1472 struct dp_ast_entry { 1473 uint16_t ast_idx; 1474 uint16_t peer_id; 1475 union dp_align_mac_addr mac_addr; 1476 bool next_hop; 1477 bool is_active; 1478 bool is_mapped; 1479 uint8_t pdev_id; 1480 uint8_t vdev_id; 1481 uint16_t ast_hash_value; 1482 qdf_atomic_t ref_cnt; 1483 enum cdp_txrx_ast_entry_type type; 1484 bool delete_in_progress; 1485 txrx_ast_free_cb callback; 1486 void *cookie; 1487 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 1488 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 1489 }; 1490 1491 /** 1492 * struct dp_mec_entry - MEC entry 1493 * 1494 * @mac_addr: MAC Address for this MEC entry 1495 * @is_active: flag to indicate active data traffic on this node 1496 * (used for aging out/expiry) 1497 * @pdev_id: pdev ID 1498 * @vdev_id: vdev ID 1499 * @hash_list_elem: node in soc MEC hash list (mac address used as hash) 1500 */ 1501 struct dp_mec_entry { 1502 union dp_align_mac_addr mac_addr; 1503 bool is_active; 1504 uint8_t pdev_id; 1505 uint8_t vdev_id; 1506 1507 TAILQ_ENTRY(dp_mec_entry) hash_list_elem; 1508 }; 1509 1510 /* SOC level htt stats */ 1511 struct htt_t2h_stats { 1512 /* lock to protect htt_stats_msg update */ 1513 qdf_spinlock_t lock; 1514 1515 /* work queue to process htt stats */ 1516 qdf_work_t work; 1517 1518 /* T2H Ext stats message queue */ 1519 qdf_nbuf_queue_t msg; 1520 1521 /* number of completed stats in htt_stats_msg */ 1522 uint32_t num_stats; 1523 }; 1524 1525 struct link_desc_bank { 1526 void *base_vaddr_unaligned; 1527 void *base_vaddr; 1528 qdf_dma_addr_t base_paddr_unaligned; 1529 qdf_dma_addr_t base_paddr; 1530 uint32_t size; 1531 }; 1532 1533 struct rx_buff_pool { 1534 qdf_nbuf_queue_head_t emerg_nbuf_q; 1535 uint32_t nbuf_fail_cnt; 1536 bool is_initialized; 1537 }; 1538 1539 struct rx_refill_buff_pool { 1540 bool is_initialized; 1541 uint16_t head; 1542 uint16_t tail; 1543 struct dp_pdev *dp_pdev; 1544 uint16_t max_bufq_len; 1545 qdf_nbuf_t buf_elem[2048]; 1546 }; 1547 1548 #ifdef DP_TX_HW_DESC_HISTORY 1549 #define DP_TX_HW_DESC_HIST_MAX 6144 1550 #define DP_TX_HW_DESC_HIST_PER_SLOT_MAX 2048 1551 #define DP_TX_HW_DESC_HIST_MAX_SLOTS 3 1552 #define DP_TX_HW_DESC_HIST_SLOT_SHIFT 11 1553 1554 struct dp_tx_hw_desc_evt { 1555 uint8_t tcl_desc[HAL_TX_DESC_LEN_BYTES]; 1556 uint8_t tcl_ring_id; 1557 uint64_t posted; 1558 uint32_t hp; 1559 uint32_t tp; 1560 }; 1561 1562 /* struct dp_tx_hw_desc_history - TX HW desc hisotry 1563 * @index: Index where the last entry is written 1564 * @entry: history entries 1565 */ 1566 struct dp_tx_hw_desc_history { 1567 qdf_atomic_t index; 1568 uint16_t num_entries_per_slot; 1569 uint16_t allocated; 1570 struct dp_tx_hw_desc_evt *entry[DP_TX_HW_DESC_HIST_MAX_SLOTS]; 1571 }; 1572 #endif 1573 1574 /** 1575 * enum dp_mon_status_process_event - Events for monitor status buffer record 1576 * @DP_MON_STATUS_BUF_REAP: Monitor status buffer is reaped from ring 1577 * @DP_MON_STATUS_BUF_ENQUEUE: Status buffer is enqueued to local queue 1578 * @DP_MON_STATUS_BUF_DEQUEUE: Status buffer is dequeued from local queue 1579 */ 1580 enum dp_mon_status_process_event { 1581 DP_MON_STATUS_BUF_REAP, 1582 DP_MON_STATUS_BUF_ENQUEUE, 1583 DP_MON_STATUS_BUF_DEQUEUE, 1584 }; 1585 1586 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 1587 #define DP_MON_STATUS_HIST_MAX 2048 1588 1589 /** 1590 * struct dp_mon_stat_info_record - monitor stat ring buffer info 1591 * @hbi: HW ring buffer info 1592 * @timestamp: timestamp when this entry was recorded 1593 * @event: event 1594 * @rx_desc: RX descriptor corresponding to the received buffer 1595 * @nbuf: buffer attached to rx_desc, if event is REAP, else the buffer 1596 * which was enqueued or dequeued. 1597 * @rx_desc_nbuf_data: nbuf data pointer. 1598 */ 1599 struct dp_mon_stat_info_record { 1600 struct hal_buf_info hbi; 1601 uint64_t timestamp; 1602 enum dp_mon_status_process_event event; 1603 void *rx_desc; 1604 qdf_nbuf_t nbuf; 1605 uint8_t *rx_desc_nbuf_data; 1606 }; 1607 1608 /* struct dp_rx_history - rx ring hisotry 1609 * @index: Index where the last entry is written 1610 * @entry: history entries 1611 */ 1612 struct dp_mon_status_ring_history { 1613 qdf_atomic_t index; 1614 struct dp_mon_stat_info_record entry[DP_MON_STATUS_HIST_MAX]; 1615 }; 1616 #endif 1617 1618 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 1619 /* 1620 * The logic for get current index of these history is dependent on this 1621 * value being power of 2. 1622 */ 1623 #define DP_RX_HIST_MAX 2048 1624 #define DP_RX_ERR_HIST_MAX 2048 1625 #define DP_RX_REINJECT_HIST_MAX 1024 1626 #define DP_RX_REFILL_HIST_MAX 2048 1627 1628 QDF_COMPILE_TIME_ASSERT(rx_history_size, 1629 (DP_RX_HIST_MAX & 1630 (DP_RX_HIST_MAX - 1)) == 0); 1631 QDF_COMPILE_TIME_ASSERT(rx_err_history_size, 1632 (DP_RX_ERR_HIST_MAX & 1633 (DP_RX_ERR_HIST_MAX - 1)) == 0); 1634 QDF_COMPILE_TIME_ASSERT(rx_reinject_history_size, 1635 (DP_RX_REINJECT_HIST_MAX & 1636 (DP_RX_REINJECT_HIST_MAX - 1)) == 0); 1637 QDF_COMPILE_TIME_ASSERT(rx_refill_history_size, 1638 (DP_RX_REFILL_HIST_MAX & 1639 (DP_RX_REFILL_HIST_MAX - 1)) == 0); 1640 1641 1642 /** 1643 * struct dp_buf_info_record - ring buffer info 1644 * @hbi: HW ring buffer info 1645 * @timestamp: timestamp when this entry was recorded 1646 */ 1647 struct dp_buf_info_record { 1648 struct hal_buf_info hbi; 1649 uint64_t timestamp; 1650 }; 1651 1652 /** 1653 * struct dp_refill_info_record - ring refill buffer info 1654 * @hp: HP value after refill 1655 * @tp: cached tail value during refill 1656 * @num_req: number of buffers requested to refill 1657 * @num_refill: number of buffers refilled to ring 1658 * @timestamp: timestamp when this entry was recorded 1659 */ 1660 struct dp_refill_info_record { 1661 uint32_t hp; 1662 uint32_t tp; 1663 uint32_t num_req; 1664 uint32_t num_refill; 1665 uint64_t timestamp; 1666 }; 1667 1668 /** 1669 * struct dp_rx_history - rx ring hisotry 1670 * @index: Index where the last entry is written 1671 * @entry: history entries 1672 */ 1673 struct dp_rx_history { 1674 qdf_atomic_t index; 1675 struct dp_buf_info_record entry[DP_RX_HIST_MAX]; 1676 }; 1677 1678 /** 1679 * struct dp_rx_err_history - rx err ring hisotry 1680 * @index: Index where the last entry is written 1681 * @entry: history entries 1682 */ 1683 struct dp_rx_err_history { 1684 qdf_atomic_t index; 1685 struct dp_buf_info_record entry[DP_RX_ERR_HIST_MAX]; 1686 }; 1687 1688 /** 1689 * struct dp_rx_reinject_history - rx reinject ring hisotry 1690 * @index: Index where the last entry is written 1691 * @entry: history entries 1692 */ 1693 struct dp_rx_reinject_history { 1694 qdf_atomic_t index; 1695 struct dp_buf_info_record entry[DP_RX_REINJECT_HIST_MAX]; 1696 }; 1697 1698 /** 1699 * struct dp_rx_refill_history - rx buf refill hisotry 1700 * @index: Index where the last entry is written 1701 * @entry: history entries 1702 */ 1703 struct dp_rx_refill_history { 1704 qdf_atomic_t index; 1705 struct dp_refill_info_record entry[DP_RX_REFILL_HIST_MAX]; 1706 }; 1707 1708 #endif 1709 1710 /** 1711 * enum dp_cfg_event_type - Datapath config events type 1712 * @DP_CFG_EVENT_VDEV_ATTACH: vdev attach 1713 * @DP_CFG_EVENT_VDEV_DETACH: vdev detach 1714 * @DP_CFG_EVENT_VDEV_UNREF_DEL: vdev memory free after last ref is released 1715 * @DP_CFG_EVENT_PEER_CREATE: peer create 1716 * @DP_CFG_EVENT_PEER_DELETE: peer delete 1717 * @DP_CFG_EVENT_PEER_UNREF_DEL: peer memory free after last ref is released 1718 * @DP_CFG_EVENT_PEER_SETUP: peer setup 1719 * @DP_CFG_EVENT_MLO_ADD_LINK: add link peer to mld peer 1720 * @DP_CFG_EVENT_MLO_DEL_LINK: delete link peer from mld peer 1721 * @DP_CFG_EVENT_MLO_SETUP: MLO peer setup 1722 * @DP_CFG_EVENT_MLO_SETUP_VDEV_UPDATE: MLD peer vdev update 1723 * @DP_CFG_EVENT_PEER_MAP: peer map 1724 * @DP_CFG_EVENT_PEER_UNMAP: peer unmap 1725 * @DP_CFG_EVENT_MLO_PEER_MAP: MLD peer map 1726 * @DP_CFG_EVENT_MLO_PEER_UNMAP: MLD peer unmap 1727 */ 1728 enum dp_cfg_event_type { 1729 DP_CFG_EVENT_VDEV_ATTACH, 1730 DP_CFG_EVENT_VDEV_DETACH, 1731 DP_CFG_EVENT_VDEV_UNREF_DEL, 1732 DP_CFG_EVENT_PEER_CREATE, 1733 DP_CFG_EVENT_PEER_DELETE, 1734 DP_CFG_EVENT_PEER_UNREF_DEL, 1735 DP_CFG_EVENT_PEER_SETUP, 1736 DP_CFG_EVENT_MLO_ADD_LINK, 1737 DP_CFG_EVENT_MLO_DEL_LINK, 1738 DP_CFG_EVENT_MLO_SETUP, 1739 DP_CFG_EVENT_MLO_SETUP_VDEV_UPDATE, 1740 DP_CFG_EVENT_PEER_MAP, 1741 DP_CFG_EVENT_PEER_UNMAP, 1742 DP_CFG_EVENT_MLO_PEER_MAP, 1743 DP_CFG_EVENT_MLO_PEER_UNMAP, 1744 }; 1745 1746 #ifdef WLAN_FEATURE_DP_CFG_EVENT_HISTORY 1747 /* Size must be in 2 power, for bitwise index rotation */ 1748 #define DP_CFG_EVT_HISTORY_SIZE 0x800 1749 #define DP_CFG_EVT_HIST_PER_SLOT_MAX 256 1750 #define DP_CFG_EVT_HIST_MAX_SLOTS 8 1751 #define DP_CFG_EVT_HIST_SLOT_SHIFT 8 1752 1753 /** 1754 * struct dp_vdev_attach_detach_desc - vdev ops descriptor 1755 * @vdev: DP vdev handle 1756 * @mac_addr: vdev mac address 1757 * @vdev_id: vdev id 1758 * @ref_count: vdev ref count 1759 */ 1760 struct dp_vdev_attach_detach_desc { 1761 struct dp_vdev *vdev; 1762 union dp_align_mac_addr mac_addr; 1763 uint8_t vdev_id; 1764 int32_t ref_count; 1765 }; 1766 1767 /** 1768 * struct dp_peer_cmn_ops_desc - peer events descriptor 1769 * @vdev_id: vdev_id of the vdev on which peer exists 1770 * @is_reuse: indicates if its a peer reuse case, during peer create 1771 * @peer: DP peer handle 1772 * @vdev: DP vdev handle on which peer exists 1773 * @mac_addr: peer mac address 1774 * @vdev_mac_addr: vdev mac address 1775 * @vdev_ref_count: vdev ref count 1776 * @peer_ref_count: peer ref count 1777 */ 1778 struct dp_peer_cmn_ops_desc { 1779 uint8_t vdev_id : 5, 1780 is_reuse : 1; 1781 struct dp_peer *peer; 1782 struct dp_vdev *vdev; 1783 union dp_align_mac_addr mac_addr; 1784 union dp_align_mac_addr vdev_mac_addr; 1785 int32_t vdev_ref_count; 1786 int32_t peer_ref_count; 1787 }; 1788 1789 /** 1790 * struct dp_mlo_add_del_link_desc - MLO add/del link event descriptor 1791 * @idx: index at which link peer got added in MLD peer's list 1792 * @num_links: num links added in the MLD peer's list 1793 * @action_result: add/del was success or not 1794 * @reserved: reserved bit 1795 * @link_peer: link peer handle 1796 * @mld_peer: MLD peer handle 1797 * @link_mac_addr: link peer mac address 1798 * @mld_mac_addr: MLD peer mac address 1799 */ 1800 struct dp_mlo_add_del_link_desc { 1801 uint8_t idx : 3, 1802 num_links : 3, 1803 action_result : 1, 1804 reserved : 1; 1805 struct dp_peer *link_peer; 1806 struct dp_peer *mld_peer; 1807 union dp_align_mac_addr link_mac_addr; 1808 union dp_align_mac_addr mld_mac_addr; 1809 }; 1810 1811 /** 1812 * struct dp_mlo_setup_vdev_update_desc - MLD peer vdev update event desc 1813 * @mld_peer: MLD peer handle 1814 * @prev_vdev: previous vdev handle 1815 * @new_vdev: new vdev handle 1816 */ 1817 struct dp_mlo_setup_vdev_update_desc { 1818 struct dp_peer *mld_peer; 1819 struct dp_vdev *prev_vdev; 1820 struct dp_vdev *new_vdev; 1821 }; 1822 1823 /** 1824 * struct dp_rx_peer_map_unmap_desc - peer map/unmap event descriptor 1825 * @peer_id: peer id 1826 * @ml_peer_id: ML peer id, if its an MLD peer 1827 * @hw_peer_id: hw peer id 1828 * @vdev_id: vdev id of the peer 1829 * @is_ml_peer: is this MLD peer 1830 * @mac_addr: mac address of the peer 1831 * @peer: peer handle 1832 */ 1833 struct dp_rx_peer_map_unmap_desc { 1834 uint16_t peer_id; 1835 uint16_t ml_peer_id; 1836 uint16_t hw_peer_id; 1837 uint8_t vdev_id; 1838 uint8_t is_ml_peer; 1839 union dp_align_mac_addr mac_addr; 1840 struct dp_peer *peer; 1841 }; 1842 1843 /** 1844 * struct dp_peer_setup_desc - peer setup event descriptor 1845 * @peer: DP peer handle 1846 * @vdev: vdev handle on which peer exists 1847 * @vdev_ref_count: vdev ref count 1848 * @mac_addr: peer mac address 1849 * @mld_mac_addr: MLD mac address 1850 * @is_first_link: is the current link the first link created 1851 * @is_primary_link: is the current link primary link 1852 * @vdev_id: vdev id of the vdev on which the current link peer exists 1853 * @reserved: reserved bit 1854 */ 1855 struct dp_peer_setup_desc { 1856 struct dp_peer *peer; 1857 struct dp_vdev *vdev; 1858 int32_t vdev_ref_count; 1859 union dp_align_mac_addr mac_addr; 1860 union dp_align_mac_addr mld_mac_addr; 1861 uint8_t is_first_link : 1, 1862 is_primary_link : 1, 1863 vdev_id : 5, 1864 reserved : 1; 1865 }; 1866 1867 /** 1868 * union dp_cfg_event_desc - DP config event descriptor 1869 * @vdev_evt: vdev events desc 1870 * @peer_cmn_evt: common peer events desc 1871 * @peer_setup_evt: peer setup event desc 1872 * @mlo_link_delink_evt: MLO link/delink event desc 1873 * @mlo_setup_vdev_update: MLD peer vdev update event desc 1874 * @peer_map_unmap_evt: peer map/unmap event desc 1875 */ 1876 union dp_cfg_event_desc { 1877 struct dp_vdev_attach_detach_desc vdev_evt; 1878 struct dp_peer_cmn_ops_desc peer_cmn_evt; 1879 struct dp_peer_setup_desc peer_setup_evt; 1880 struct dp_mlo_add_del_link_desc mlo_link_delink_evt; 1881 struct dp_mlo_setup_vdev_update_desc mlo_setup_vdev_update; 1882 struct dp_rx_peer_map_unmap_desc peer_map_unmap_evt; 1883 }; 1884 1885 /** 1886 * struct dp_cfg_event - DP config event descriptor 1887 * @timestamp: timestamp at which event was recorded 1888 * @type: event type 1889 * @event_desc: event descriptor 1890 */ 1891 struct dp_cfg_event { 1892 uint64_t timestamp; 1893 enum dp_cfg_event_type type; 1894 union dp_cfg_event_desc event_desc; 1895 }; 1896 1897 /** 1898 * struct dp_cfg_event_history - DP config event history 1899 * @index: current index 1900 * @num_entries_per_slot: number of entries per slot 1901 * @allocated: Is the history allocated or not 1902 * @entry: event history descriptors 1903 */ 1904 struct dp_cfg_event_history { 1905 qdf_atomic_t index; 1906 uint16_t num_entries_per_slot; 1907 uint16_t allocated; 1908 struct dp_cfg_event *entry[DP_CFG_EVT_HIST_MAX_SLOTS]; 1909 }; 1910 #endif 1911 1912 enum dp_tx_event_type { 1913 DP_TX_DESC_INVAL_EVT = 0, 1914 DP_TX_DESC_MAP, 1915 DP_TX_DESC_COOKIE, 1916 DP_TX_DESC_FLUSH, 1917 DP_TX_DESC_UNMAP, 1918 DP_TX_COMP_UNMAP, 1919 DP_TX_COMP_UNMAP_ERR, 1920 DP_TX_COMP_MSDU_EXT, 1921 }; 1922 1923 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 1924 /* Size must be in 2 power, for bitwise index rotation */ 1925 #define DP_TX_TCL_HISTORY_SIZE 0x4000 1926 #define DP_TX_TCL_HIST_PER_SLOT_MAX 2048 1927 #define DP_TX_TCL_HIST_MAX_SLOTS 8 1928 #define DP_TX_TCL_HIST_SLOT_SHIFT 11 1929 1930 /* Size must be in 2 power, for bitwise index rotation */ 1931 #define DP_TX_COMP_HISTORY_SIZE 0x4000 1932 #define DP_TX_COMP_HIST_PER_SLOT_MAX 2048 1933 #define DP_TX_COMP_HIST_MAX_SLOTS 8 1934 #define DP_TX_COMP_HIST_SLOT_SHIFT 11 1935 1936 struct dp_tx_desc_event { 1937 qdf_nbuf_t skb; 1938 dma_addr_t paddr; 1939 uint32_t sw_cookie; 1940 enum dp_tx_event_type type; 1941 uint64_t ts; 1942 }; 1943 1944 struct dp_tx_tcl_history { 1945 qdf_atomic_t index; 1946 uint16_t num_entries_per_slot; 1947 uint16_t allocated; 1948 struct dp_tx_desc_event *entry[DP_TX_TCL_HIST_MAX_SLOTS]; 1949 }; 1950 1951 struct dp_tx_comp_history { 1952 qdf_atomic_t index; 1953 uint16_t num_entries_per_slot; 1954 uint16_t allocated; 1955 struct dp_tx_desc_event *entry[DP_TX_COMP_HIST_MAX_SLOTS]; 1956 }; 1957 #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */ 1958 1959 /* structure to record recent operation related variable */ 1960 struct dp_last_op_info { 1961 /* last link desc buf info through WBM release ring */ 1962 struct hal_buf_info wbm_rel_link_desc; 1963 /* last link desc buf info through REO reinject ring */ 1964 struct hal_buf_info reo_reinject_link_desc; 1965 }; 1966 1967 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 1968 1969 /** 1970 * struct dp_swlm_tcl_data - params for tcl register write coalescing 1971 * decision making 1972 * @nbuf: TX packet 1973 * @tid: tid for transmitting the current packet 1974 * @num_ll_connections: Number of low latency connections on this vdev 1975 * @ring_id: TCL ring id 1976 * @pkt_len: Packet length 1977 * 1978 * This structure contains the information required by the software 1979 * latency manager to decide on whether to coalesce the current TCL 1980 * register write or not. 1981 */ 1982 struct dp_swlm_tcl_data { 1983 qdf_nbuf_t nbuf; 1984 uint8_t tid; 1985 uint8_t num_ll_connections; 1986 uint8_t ring_id; 1987 uint32_t pkt_len; 1988 }; 1989 1990 /** 1991 * union swlm_data - SWLM query data 1992 * @tcl_data: data for TCL query in SWLM 1993 */ 1994 union swlm_data { 1995 struct dp_swlm_tcl_data *tcl_data; 1996 }; 1997 1998 /** 1999 * struct dp_swlm_ops - SWLM ops 2000 * @tcl_wr_coalesce_check: handler to check if the current TCL register 2001 * write can be coalesced or not 2002 */ 2003 struct dp_swlm_ops { 2004 int (*tcl_wr_coalesce_check)(struct dp_soc *soc, 2005 struct dp_swlm_tcl_data *tcl_data); 2006 }; 2007 2008 /** 2009 * struct dp_swlm_stats - Stats for Software Latency manager. 2010 * @tcl: TCL stats 2011 * @tcl.timer_flush_success: Num TCL HP writes success from timer context 2012 * @tcl.timer_flush_fail: Num TCL HP writes failure from timer context 2013 * @tcl.tid_fail: Num TCL register write coalescing skips, since the pkt 2014 * was being transmitted on a TID above coalescing threshold 2015 * @tcl.sp_frames: Num TCL register write coalescing skips, since the pkt 2016 * being transmitted was a special frame 2017 * @tcl.ll_connection: Num TCL register write coalescing skips, since the 2018 * vdev has low latency connections 2019 * @tcl.bytes_thresh_reached: Num TCL HP writes flush after the coalescing 2020 * bytes threshold was reached 2021 * @tcl.time_thresh_reached: Num TCL HP writes flush after the coalescing 2022 * session time expired 2023 * @tcl.tput_criteria_fail: Num TCL HP writes coalescing fails, since the 2024 * throughput did not meet session threshold 2025 * @tcl.coalesce_success: Num of TCL HP writes coalesced successfully. 2026 * @tcl.coalesce_fail: Num of TCL HP writes coalesces failed 2027 */ 2028 struct dp_swlm_stats { 2029 struct { 2030 uint32_t timer_flush_success; 2031 uint32_t timer_flush_fail; 2032 uint32_t tid_fail; 2033 uint32_t sp_frames; 2034 uint32_t ll_connection; 2035 uint32_t bytes_thresh_reached; 2036 uint32_t time_thresh_reached; 2037 uint32_t tput_criteria_fail; 2038 uint32_t coalesce_success; 2039 uint32_t coalesce_fail; 2040 } tcl[MAX_TCL_DATA_RINGS]; 2041 }; 2042 2043 /** 2044 * struct dp_swlm_tcl_params: Parameters based on TCL for different modules 2045 * in the Software latency manager. 2046 * @soc: DP soc reference 2047 * @ring_id: TCL ring id 2048 * @flush_timer: Timer for flushing the coalesced TCL HP writes 2049 * @sampling_session_tx_bytes: Num bytes transmitted in the sampling time 2050 * @bytes_flush_thresh: Bytes threshold to flush the TCL HP register write 2051 * @coalesce_end_time: End timestamp for current coalescing session 2052 * @bytes_coalesced: Num bytes coalesced in the current session 2053 * @prev_tx_packets: Previous TX packets accounted 2054 * @prev_tx_bytes: Previous TX bytes accounted 2055 * @prev_rx_bytes: Previous RX bytes accounted 2056 * @expire_time: expiry time for sample 2057 * @tput_pass_cnt: threshold throughput pass counter 2058 */ 2059 struct dp_swlm_tcl_params { 2060 struct dp_soc *soc; 2061 uint32_t ring_id; 2062 qdf_timer_t flush_timer; 2063 uint32_t sampling_session_tx_bytes; 2064 uint32_t bytes_flush_thresh; 2065 uint64_t coalesce_end_time; 2066 uint32_t bytes_coalesced; 2067 uint32_t prev_tx_packets; 2068 uint32_t prev_tx_bytes; 2069 uint32_t prev_rx_bytes; 2070 uint64_t expire_time; 2071 uint32_t tput_pass_cnt; 2072 }; 2073 2074 /** 2075 * struct dp_swlm_params: Parameters for different modules in the 2076 * Software latency manager. 2077 * @rx_traffic_thresh: Threshold for RX traffic, to begin TCL register 2078 * write coalescing 2079 * @tx_traffic_thresh: Threshold for TX traffic, to begin TCL register 2080 * write coalescing 2081 * @sampling_time: Sampling time to test the throughput threshold 2082 * @time_flush_thresh: Time threshold to flush the TCL HP register write 2083 * @tx_thresh_multiplier: Multiplier to deduce the bytes threshold after 2084 * which the TCL HP register is written, thereby 2085 * ending the coalescing. 2086 * @tx_pkt_thresh: Threshold for TX packet count, to begin TCL register 2087 * write coalescing 2088 * @tcl: TCL ring specific params 2089 */ 2090 2091 struct dp_swlm_params { 2092 uint32_t rx_traffic_thresh; 2093 uint32_t tx_traffic_thresh; 2094 uint32_t sampling_time; 2095 uint32_t time_flush_thresh; 2096 uint32_t tx_thresh_multiplier; 2097 uint32_t tx_pkt_thresh; 2098 struct dp_swlm_tcl_params tcl[MAX_TCL_DATA_RINGS]; 2099 }; 2100 2101 /** 2102 * struct dp_swlm - Software latency manager context 2103 * @ops: SWLM ops pointers 2104 * @is_enabled: SWLM enabled/disabled 2105 * @is_init: SWLM module initialized 2106 * @stats: SWLM stats 2107 * @params: SWLM SRNG params 2108 * @tcl_flush_timer: flush timer for TCL register writes 2109 */ 2110 struct dp_swlm { 2111 struct dp_swlm_ops *ops; 2112 uint8_t is_enabled:1, 2113 is_init:1; 2114 struct dp_swlm_stats stats; 2115 struct dp_swlm_params params; 2116 }; 2117 #endif 2118 2119 #ifdef IPA_OFFLOAD 2120 /* IPA uC datapath offload Wlan Tx resources */ 2121 struct ipa_dp_tx_rsc { 2122 /* Resource info to be passed to IPA */ 2123 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 2124 void *ipa_tcl_ring_base_vaddr; 2125 uint32_t ipa_tcl_ring_size; 2126 qdf_dma_addr_t ipa_tcl_hp_paddr; 2127 uint32_t alloc_tx_buf_cnt; 2128 2129 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 2130 void *ipa_wbm_ring_base_vaddr; 2131 uint32_t ipa_wbm_ring_size; 2132 qdf_dma_addr_t ipa_wbm_tp_paddr; 2133 /* WBM2SW HP shadow paddr */ 2134 qdf_dma_addr_t ipa_wbm_hp_shadow_paddr; 2135 2136 /* TX buffers populated into the WBM ring */ 2137 void **tx_buf_pool_vaddr_unaligned; 2138 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 2139 }; 2140 2141 /* IPA uC datapath offload Wlan Rx resources */ 2142 struct ipa_dp_rx_rsc { 2143 /* Resource info to be passed to IPA */ 2144 qdf_dma_addr_t ipa_reo_ring_base_paddr; 2145 void *ipa_reo_ring_base_vaddr; 2146 uint32_t ipa_reo_ring_size; 2147 qdf_dma_addr_t ipa_reo_tp_paddr; 2148 2149 /* Resource info to be passed to firmware and IPA */ 2150 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 2151 void *ipa_rx_refill_buf_ring_base_vaddr; 2152 uint32_t ipa_rx_refill_buf_ring_size; 2153 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 2154 }; 2155 #endif 2156 2157 struct dp_tx_msdu_info_s; 2158 /** 2159 * enum dp_context_type- DP Context Type 2160 * @DP_CONTEXT_TYPE_SOC: Context type DP SOC 2161 * @DP_CONTEXT_TYPE_PDEV: Context type DP PDEV 2162 * @DP_CONTEXT_TYPE_VDEV: Context type DP VDEV 2163 * @DP_CONTEXT_TYPE_PEER: Context type DP PEER 2164 * @DP_CONTEXT_TYPE_MON_SOC: Context type DP MON SOC 2165 * @DP_CONTEXT_TYPE_MON_PDEV: Context type DP MON PDEV 2166 * 2167 * Helper enums to be used to retrieve the size of the corresponding 2168 * data structure by passing the type. 2169 */ 2170 enum dp_context_type { 2171 DP_CONTEXT_TYPE_SOC, 2172 DP_CONTEXT_TYPE_PDEV, 2173 DP_CONTEXT_TYPE_VDEV, 2174 DP_CONTEXT_TYPE_PEER, 2175 DP_CONTEXT_TYPE_MON_SOC, 2176 DP_CONTEXT_TYPE_MON_PDEV 2177 }; 2178 2179 /** 2180 * struct dp_arch_ops - DP target specific arch ops 2181 * @txrx_soc_attach: 2182 * @txrx_soc_detach: 2183 * @txrx_soc_init: 2184 * @txrx_soc_deinit: 2185 * @txrx_soc_srng_alloc: 2186 * @txrx_soc_srng_init: 2187 * @txrx_soc_srng_deinit: 2188 * @txrx_soc_srng_free: 2189 * @txrx_pdev_attach: 2190 * @txrx_pdev_detach: 2191 * @txrx_vdev_attach: 2192 * @txrx_vdev_detach: 2193 * @txrx_peer_map_attach: 2194 * @txrx_peer_map_detach: 2195 * @dp_rxdma_ring_sel_cfg: 2196 * @soc_cfg_attach: 2197 * @txrx_peer_setup: 2198 * @peer_get_reo_hash: 2199 * @reo_remap_config: 2200 * @tx_hw_enqueue: enqueue TX data to HW 2201 * @tx_comp_get_params_from_hal_desc: get software tx descriptor and release 2202 * source from HAL desc for wbm release ring 2203 * @dp_tx_mlo_mcast_send: Tx send handler for MLO multicast enhance 2204 * @dp_tx_process_htt_completion: 2205 * @dp_rx_process: 2206 * @dp_tx_send_fast: 2207 * @dp_tx_desc_pool_init: 2208 * @dp_tx_desc_pool_deinit: 2209 * @dp_rx_desc_pool_init: 2210 * @dp_rx_desc_pool_deinit: 2211 * @dp_wbm_get_rx_desc_from_hal_desc: 2212 * @dp_rx_intrabss_mcast_handler: 2213 * @dp_rx_word_mask_subscribe: 2214 * @dp_rx_desc_cookie_2_va: 2215 * @dp_service_near_full_srngs: Handler for servicing the near full IRQ 2216 * @tx_implicit_rbm_set: 2217 * @dp_rx_peer_metadata_peer_id_get: 2218 * @dp_rx_chain_msdus: 2219 * @txrx_set_vdev_param: target specific ops while setting vdev params 2220 * @txrx_get_vdev_mcast_param: target specific ops for getting vdev 2221 * params related to multicast 2222 * @txrx_get_context_size: 2223 * @txrx_get_mon_context_size: 2224 * @dp_srng_test_and_update_nf_params: Check if the srng is in near full state 2225 * and set the near-full params. 2226 * @dp_tx_mcast_handler: 2227 * @dp_rx_mcast_handler: 2228 * @dp_tx_is_mcast_primary: 2229 * @dp_soc_get_by_idle_bm_id: 2230 * @mlo_peer_find_hash_detach: 2231 * @mlo_peer_find_hash_attach: 2232 * @mlo_peer_find_hash_add: 2233 * @mlo_peer_find_hash_remove: 2234 * @mlo_peer_find_hash_find: 2235 * @mlo_get_chip_id: get the MLO chip id 2236 * @mlo_link_peer_find_hash_find_by_chip_id: return the link peer on the chip 2237 * @get_hw_link_id: 2238 * @dp_rx_peer_set_link_id: set link id in nbuf cb 2239 * @get_reo_qdesc_addr: 2240 * @get_rx_hash_key: 2241 * @dp_set_rx_fst: 2242 * @dp_get_rx_fst: 2243 * @dp_rx_fst_deref: 2244 * @dp_rx_fst_ref: 2245 * @txrx_print_peer_stats: 2246 * @dp_peer_rx_reorder_queue_setup: Dp peer reorder queue setup 2247 * @dp_bank_reconfig: 2248 * @dp_get_soc_by_chip_id: Get soc by chip id 2249 * @dp_soc_get_num_soc: 2250 * @dp_reconfig_tx_vdev_mcast_ctrl: 2251 * @dp_cc_reg_cfg_init: 2252 * @dp_tx_compute_hw_delay: 2253 * @print_mlo_ast_stats: 2254 * @dp_partner_chips_map: 2255 * @dp_partner_chips_unmap: 2256 * @ipa_get_bank_id: Get TCL bank id used by IPA 2257 * @ipa_get_wdi_ver: Get WDI version 2258 * @dp_txrx_ppeds_rings_status: 2259 * @dp_tx_ppeds_inuse_desc: 2260 * @dp_ppeds_clear_stats: Clear ppeds related stats 2261 * @dp_tx_ppeds_cfg_astidx_cache_mapping: 2262 * @dp_txrx_ppeds_rings_stats: Printing the util stats of ring 2263 * @dp_txrx_ppeds_clear_rings_stats: Clearing the ring util stats 2264 * @txrx_soc_ppeds_start: 2265 * @txrx_soc_ppeds_stop: 2266 * @dp_register_ppeds_interrupts: 2267 * @dp_free_ppeds_interrupts: 2268 * @dp_rx_wbm_err_reap_desc: Reap WBM Error Ring Descriptor 2269 * @dp_rx_null_q_desc_handle: Handle Null Queue Exception Error 2270 * @dp_tx_desc_pool_alloc: Allocate arch specific TX descriptor pool 2271 * @dp_tx_desc_pool_free: Free arch specific TX descriptor pool 2272 * @txrx_srng_init: Init txrx srng 2273 * @dp_get_vdev_stats_for_unmap_peer: Get vdev stats pointer for unmap peer 2274 * @dp_get_interface_stats: Get interface stats 2275 * @ppeds_handle_attached: 2276 * @txrx_soc_ppeds_interrupt_stop: 2277 * @txrx_soc_ppeds_interrupt_start: 2278 * @txrx_soc_ppeds_service_status_update: 2279 * @txrx_soc_ppeds_enabled_check: 2280 * @txrx_soc_ppeds_txdesc_pool_reset: 2281 * @dp_update_ring_hptp: Update rings hptp during suspend/resume 2282 * @dp_get_fst_cmem_base: Get CMEM base address for FISA 2283 * @dp_flush_tx_ring: Flush TCL ring HP 2284 * @dp_mlo_print_ptnr_info: print partner vdev info 2285 * @dp_soc_interrupt_attach: DP interrupt attach 2286 * @dp_soc_attach_poll: DP poll attach 2287 * @dp_soc_interrupt_detach: DP interrupt detach 2288 * @dp_service_srngs: Service DP interrupts 2289 */ 2290 struct dp_arch_ops { 2291 /* INIT/DEINIT Arch Ops */ 2292 QDF_STATUS (*txrx_soc_attach)(struct dp_soc *soc, 2293 struct cdp_soc_attach_params *params); 2294 QDF_STATUS (*txrx_soc_detach)(struct dp_soc *soc); 2295 void* (*txrx_soc_init)(struct dp_soc *soc, HTC_HANDLE htc_handle, 2296 struct hif_opaque_softc *hif_handle); 2297 QDF_STATUS (*txrx_soc_deinit)(struct dp_soc *soc); 2298 QDF_STATUS (*txrx_soc_srng_alloc)(struct dp_soc *soc); 2299 QDF_STATUS (*txrx_soc_srng_init)(struct dp_soc *soc); 2300 void (*txrx_soc_srng_deinit)(struct dp_soc *soc); 2301 void (*txrx_soc_srng_free)(struct dp_soc *soc); 2302 QDF_STATUS (*txrx_pdev_attach)(struct dp_pdev *pdev, 2303 struct cdp_pdev_attach_params *params); 2304 QDF_STATUS (*txrx_pdev_detach)(struct dp_pdev *pdev); 2305 QDF_STATUS (*txrx_vdev_attach)(struct dp_soc *soc, 2306 struct dp_vdev *vdev); 2307 QDF_STATUS (*txrx_vdev_detach)(struct dp_soc *soc, 2308 struct dp_vdev *vdev); 2309 QDF_STATUS (*txrx_peer_map_attach)(struct dp_soc *soc); 2310 void (*txrx_peer_map_detach)(struct dp_soc *soc); 2311 QDF_STATUS (*dp_rxdma_ring_sel_cfg)(struct dp_soc *soc); 2312 void (*soc_cfg_attach)(struct dp_soc *soc); 2313 QDF_STATUS (*txrx_peer_setup)(struct cdp_soc_t *soc_hdl, 2314 uint8_t vdev_id, uint8_t *peer_mac, 2315 struct cdp_peer_setup_info *setup_info); 2316 void (*peer_get_reo_hash)(struct dp_vdev *vdev, 2317 struct cdp_peer_setup_info *setup_info, 2318 enum cdp_host_reo_dest_ring *reo_dest, 2319 bool *hash_based, 2320 uint8_t *lmac_peer_id_msb); 2321 bool (*reo_remap_config)(struct dp_soc *soc, uint32_t *remap0, 2322 uint32_t *remap1, uint32_t *remap2); 2323 2324 /* TX RX Arch Ops */ 2325 QDF_STATUS (*tx_hw_enqueue)(struct dp_soc *soc, struct dp_vdev *vdev, 2326 struct dp_tx_desc_s *tx_desc, 2327 uint16_t fw_metadata, 2328 struct cdp_tx_exception_metadata *metadata, 2329 struct dp_tx_msdu_info_s *msdu_info); 2330 2331 QDF_STATUS (*tx_comp_get_params_from_hal_desc)( 2332 struct dp_soc *soc, void *tx_comp_hal_desc, 2333 struct dp_tx_desc_s **desc); 2334 2335 qdf_nbuf_t (*dp_tx_mlo_mcast_send)(struct dp_soc *soc, 2336 struct dp_vdev *vdev, 2337 qdf_nbuf_t nbuf, 2338 struct cdp_tx_exception_metadata 2339 *tx_exc_metadata); 2340 2341 void (*dp_tx_process_htt_completion)(struct dp_soc *soc, 2342 struct dp_tx_desc_s *tx_desc, 2343 uint8_t *status, 2344 uint8_t ring_id); 2345 2346 uint32_t (*dp_rx_process)(struct dp_intr *int_ctx, 2347 hal_ring_handle_t hal_ring_hdl, 2348 uint8_t reo_ring_num, uint32_t quota); 2349 2350 qdf_nbuf_t (*dp_tx_send_fast)(struct cdp_soc_t *soc_hdl, 2351 uint8_t vdev_id, 2352 qdf_nbuf_t nbuf); 2353 2354 QDF_STATUS (*dp_tx_desc_pool_init)(struct dp_soc *soc, 2355 uint32_t num_elem, 2356 uint8_t pool_id, 2357 bool spcl_tx_desc); 2358 void (*dp_tx_desc_pool_deinit)( 2359 struct dp_soc *soc, 2360 struct dp_tx_desc_pool_s *tx_desc_pool, 2361 uint8_t pool_id, 2362 bool spcl_tx_desc); 2363 2364 QDF_STATUS (*dp_rx_desc_pool_init)(struct dp_soc *soc, 2365 struct rx_desc_pool *rx_desc_pool, 2366 uint32_t pool_id); 2367 void (*dp_rx_desc_pool_deinit)(struct dp_soc *soc, 2368 struct rx_desc_pool *rx_desc_pool, 2369 uint32_t pool_id); 2370 2371 QDF_STATUS (*dp_wbm_get_rx_desc_from_hal_desc)( 2372 struct dp_soc *soc, 2373 void *ring_desc, 2374 struct dp_rx_desc **r_rx_desc); 2375 2376 bool 2377 (*dp_rx_intrabss_mcast_handler)(struct dp_soc *soc, 2378 struct dp_txrx_peer *ta_txrx_peer, 2379 qdf_nbuf_t nbuf_copy, 2380 struct cdp_tid_rx_stats *tid_stats, 2381 uint8_t link_id); 2382 2383 void (*dp_rx_word_mask_subscribe)( 2384 struct dp_soc *soc, 2385 uint32_t *msg_word, 2386 void *rx_filter); 2387 2388 struct dp_rx_desc *(*dp_rx_desc_cookie_2_va)(struct dp_soc *soc, 2389 uint32_t cookie); 2390 uint32_t (*dp_service_near_full_srngs)(struct dp_soc *soc, 2391 struct dp_intr *int_ctx, 2392 uint32_t dp_budget); 2393 void (*tx_implicit_rbm_set)(struct dp_soc *soc, uint8_t tx_ring_id, 2394 uint8_t bm_id); 2395 uint16_t (*dp_rx_peer_metadata_peer_id_get)(struct dp_soc *soc, 2396 uint32_t peer_metadata); 2397 bool (*dp_rx_chain_msdus)(struct dp_soc *soc, qdf_nbuf_t nbuf, 2398 uint8_t *rx_tlv_hdr, uint8_t mac_id); 2399 /* Control Arch Ops */ 2400 QDF_STATUS (*txrx_set_vdev_param)(struct dp_soc *soc, 2401 struct dp_vdev *vdev, 2402 enum cdp_vdev_param_type param, 2403 cdp_config_param_type val); 2404 2405 QDF_STATUS (*txrx_get_vdev_mcast_param)(struct dp_soc *soc, 2406 struct dp_vdev *vdev, 2407 cdp_config_param_type *val); 2408 2409 /* Misc Arch Ops */ 2410 qdf_size_t (*txrx_get_context_size)(enum dp_context_type); 2411 #ifdef WIFI_MONITOR_SUPPORT 2412 qdf_size_t (*txrx_get_mon_context_size)(enum dp_context_type); 2413 #endif 2414 int (*dp_srng_test_and_update_nf_params)(struct dp_soc *soc, 2415 struct dp_srng *dp_srng, 2416 int *max_reap_limit); 2417 2418 /* MLO ops */ 2419 #ifdef WLAN_FEATURE_11BE_MLO 2420 #ifdef WLAN_MCAST_MLO 2421 void (*dp_tx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 2422 qdf_nbuf_t nbuf); 2423 bool (*dp_rx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 2424 struct dp_txrx_peer *peer, qdf_nbuf_t nbuf, 2425 uint8_t link_id); 2426 bool (*dp_tx_is_mcast_primary)(struct dp_soc *soc, 2427 struct dp_vdev *vdev); 2428 #endif 2429 struct dp_soc * (*dp_soc_get_by_idle_bm_id)(struct dp_soc *soc, 2430 uint8_t bm_id); 2431 2432 void (*mlo_peer_find_hash_detach)(struct dp_soc *soc); 2433 QDF_STATUS (*mlo_peer_find_hash_attach)(struct dp_soc *soc); 2434 void (*mlo_peer_find_hash_add)(struct dp_soc *soc, 2435 struct dp_peer *peer); 2436 void (*mlo_peer_find_hash_remove)(struct dp_soc *soc, 2437 struct dp_peer *peer); 2438 2439 struct dp_peer *(*mlo_peer_find_hash_find)(struct dp_soc *soc, 2440 uint8_t *peer_mac_addr, 2441 int mac_addr_is_aligned, 2442 enum dp_mod_id mod_id, 2443 uint8_t vdev_id); 2444 #ifdef WLAN_MLO_MULTI_CHIP 2445 uint8_t (*mlo_get_chip_id)(struct dp_soc *soc); 2446 struct dp_peer *(*mlo_link_peer_find_hash_find_by_chip_id) 2447 (struct dp_soc *soc, 2448 uint8_t *peer_mac_addr, 2449 int mac_addr_is_aligned, 2450 uint8_t vdev_id, 2451 uint8_t chip_id, 2452 enum dp_mod_id mod_id); 2453 #endif 2454 #endif 2455 uint8_t (*get_hw_link_id)(struct dp_pdev *pdev); 2456 void (*dp_rx_peer_set_link_id)(qdf_nbuf_t nbuf, uint32_t peer_mdata); 2457 uint64_t (*get_reo_qdesc_addr)(hal_soc_handle_t hal_soc_hdl, 2458 uint8_t *dst_ring_desc, 2459 uint8_t *buf, 2460 struct dp_txrx_peer *peer, 2461 unsigned int tid); 2462 void (*get_rx_hash_key)(struct dp_soc *soc, 2463 struct cdp_lro_hash_config *lro_hash); 2464 void (*dp_set_rx_fst)(struct dp_rx_fst *fst); 2465 struct dp_rx_fst *(*dp_get_rx_fst)(void); 2466 uint32_t (*dp_rx_fst_deref)(void); 2467 void (*dp_rx_fst_ref)(void); 2468 void (*txrx_print_peer_stats)(struct cdp_peer_stats *peer_stats, 2469 enum peer_stats_type stats_type); 2470 QDF_STATUS (*dp_peer_rx_reorder_queue_setup)(struct dp_soc *soc, 2471 struct dp_peer *peer, 2472 uint32_t tid_bitmap, 2473 uint32_t ba_window_size); 2474 void (*dp_bank_reconfig)(struct dp_soc *soc, struct dp_vdev *vdev); 2475 2476 struct dp_soc * (*dp_get_soc_by_chip_id)(struct dp_soc *soc, 2477 uint8_t chip_id); 2478 2479 uint8_t (*dp_soc_get_num_soc)(struct dp_soc *soc); 2480 void (*dp_reconfig_tx_vdev_mcast_ctrl)(struct dp_soc *soc, 2481 struct dp_vdev *vdev); 2482 2483 void (*dp_cc_reg_cfg_init)(struct dp_soc *soc, bool is_4k_align); 2484 2485 QDF_STATUS 2486 (*dp_tx_compute_hw_delay)(struct dp_soc *soc, 2487 struct dp_vdev *vdev, 2488 struct hal_tx_completion_status *ts, 2489 uint32_t *delay_us); 2490 void (*print_mlo_ast_stats)(struct dp_soc *soc); 2491 void (*dp_partner_chips_map)(struct dp_soc *soc, 2492 struct dp_peer *peer, 2493 uint16_t peer_id); 2494 void (*dp_partner_chips_unmap)(struct dp_soc *soc, 2495 uint16_t peer_id); 2496 2497 #ifdef IPA_OFFLOAD 2498 int8_t (*ipa_get_bank_id)(struct dp_soc *soc); 2499 void (*ipa_get_wdi_ver)(uint8_t *wdi_ver); 2500 #endif 2501 #ifdef WLAN_SUPPORT_PPEDS 2502 void (*dp_txrx_ppeds_rings_status)(struct dp_soc *soc); 2503 void (*dp_tx_ppeds_inuse_desc)(struct dp_soc *soc); 2504 void (*dp_ppeds_clear_stats)(struct dp_soc *soc); 2505 void (*dp_tx_ppeds_cfg_astidx_cache_mapping)(struct dp_soc *soc, 2506 struct dp_vdev *vdev, 2507 bool peer_map); 2508 void (*dp_txrx_ppeds_rings_stats)(struct dp_soc *soc); 2509 void (*dp_txrx_ppeds_clear_rings_stats)(struct dp_soc *soc); 2510 #endif 2511 bool (*ppeds_handle_attached)(struct dp_soc *soc); 2512 QDF_STATUS (*txrx_soc_ppeds_start)(struct dp_soc *soc); 2513 void (*txrx_soc_ppeds_stop)(struct dp_soc *soc); 2514 int (*dp_register_ppeds_interrupts)(struct dp_soc *soc, 2515 struct dp_srng *srng, int vector, 2516 int ring_type, int ring_num); 2517 void (*dp_free_ppeds_interrupts)(struct dp_soc *soc, 2518 struct dp_srng *srng, int ring_type, 2519 int ring_num); 2520 qdf_nbuf_t (*dp_rx_wbm_err_reap_desc)(struct dp_intr *int_ctx, 2521 struct dp_soc *soc, 2522 hal_ring_handle_t hal_ring_hdl, 2523 uint32_t quota, 2524 uint32_t *rx_bufs_used); 2525 QDF_STATUS (*dp_rx_null_q_desc_handle)(struct dp_soc *soc, 2526 qdf_nbuf_t nbuf, 2527 uint8_t *rx_tlv_hdr, 2528 uint8_t pool_id, 2529 struct dp_txrx_peer *txrx_peer, 2530 bool is_reo_exception, 2531 uint8_t link_id); 2532 2533 QDF_STATUS (*dp_tx_desc_pool_alloc)(struct dp_soc *soc, 2534 uint32_t num_elem, 2535 uint8_t pool_id); 2536 void (*dp_tx_desc_pool_free)(struct dp_soc *soc, uint8_t pool_id); 2537 2538 QDF_STATUS (*txrx_srng_init)(struct dp_soc *soc, struct dp_srng *srng, 2539 int ring_type, int ring_num, int mac_id); 2540 2541 void (*dp_get_vdev_stats_for_unmap_peer)( 2542 struct dp_vdev *vdev, 2543 struct dp_peer *peer); 2544 QDF_STATUS (*dp_get_interface_stats)(struct cdp_soc_t *soc_hdl, 2545 uint8_t vdev_id, 2546 void *buf, 2547 bool is_aggregate); 2548 #ifdef WLAN_SUPPORT_PPEDS 2549 void (*txrx_soc_ppeds_interrupt_stop)(struct dp_soc *soc); 2550 void (*txrx_soc_ppeds_interrupt_start)(struct dp_soc *soc); 2551 void (*txrx_soc_ppeds_service_status_update)(struct dp_soc *soc, 2552 bool enable); 2553 bool (*txrx_soc_ppeds_enabled_check)(struct dp_soc *soc); 2554 void (*txrx_soc_ppeds_txdesc_pool_reset)(struct dp_soc *soc, 2555 qdf_nbuf_t *nbuf_list); 2556 #endif 2557 void (*dp_update_ring_hptp)(struct dp_soc *soc, bool force_flush_tx); 2558 uint64_t (*dp_get_fst_cmem_base)(struct dp_soc *soc, uint64_t size); 2559 int (*dp_flush_tx_ring)(struct dp_pdev *pdev, int ring_id); 2560 void (*dp_mlo_print_ptnr_info)(struct dp_vdev *vdev); 2561 QDF_STATUS (*dp_soc_interrupt_attach)(struct cdp_soc_t *txrx_soc); 2562 QDF_STATUS (*dp_soc_attach_poll)(struct cdp_soc_t *txrx_soc); 2563 void (*dp_soc_interrupt_detach)(struct cdp_soc_t *txrx_soc); 2564 uint32_t (*dp_service_srngs)(void *dp_ctx, uint32_t dp_budget, int cpu); 2565 }; 2566 2567 /** 2568 * struct dp_soc_features: Data structure holding the SOC level feature flags. 2569 * @pn_in_reo_dest: PN provided by hardware in the REO destination ring. 2570 * @dmac_cmn_src_rxbuf_ring_enabled: Flag to indicate DMAC mode common Rx 2571 * buffer source rings 2572 * @rssi_dbm_conv_support: Rssi dbm conversion support param. 2573 * @umac_hw_reset_support: UMAC HW reset support 2574 * @wds_ext_ast_override_enable: 2575 * @multi_rx_reorder_q_setup_support: multi rx reorder q setup at a time support 2576 */ 2577 struct dp_soc_features { 2578 uint8_t pn_in_reo_dest:1, 2579 dmac_cmn_src_rxbuf_ring_enabled:1; 2580 bool rssi_dbm_conv_support; 2581 bool umac_hw_reset_support; 2582 bool wds_ext_ast_override_enable; 2583 bool multi_rx_reorder_q_setup_support; 2584 }; 2585 2586 enum sysfs_printing_mode { 2587 PRINTING_MODE_DISABLED = 0, 2588 PRINTING_MODE_ENABLED 2589 }; 2590 2591 /** 2592 * typedef notify_pre_reset_fw_callback() - pre-reset callback 2593 * @soc: DP SoC 2594 */ 2595 typedef void (*notify_pre_reset_fw_callback)(struct dp_soc *soc); 2596 2597 #ifdef WLAN_SYSFS_DP_STATS 2598 /** 2599 * struct sysfs_stats_config: Data structure holding stats sysfs config. 2600 * @rw_stats_lock: Lock to read and write to stat_type and pdev_id. 2601 * @sysfs_read_lock: Lock held while another stat req is being executed. 2602 * @sysfs_write_user_buffer: Lock to change buff len, max buf len 2603 * and *buf. 2604 * @sysfs_txrx_fw_request_done: Event to wait for firmware response. 2605 * @stat_type_requested: stat type requested. 2606 * @mac_id: mac id for which stat type are requested. 2607 * @printing_mode: Should a print go through. 2608 * @process_id: Process allowed to write to buffer. 2609 * @curr_buffer_length: Curr length of buffer written 2610 * @max_buffer_length: Max buffer length. 2611 * @buf: Sysfs buffer. 2612 */ 2613 struct sysfs_stats_config { 2614 /* lock held to read stats */ 2615 qdf_spinlock_t rw_stats_lock; 2616 qdf_mutex_t sysfs_read_lock; 2617 qdf_spinlock_t sysfs_write_user_buffer; 2618 qdf_event_t sysfs_txrx_fw_request_done; 2619 uint32_t stat_type_requested; 2620 uint32_t mac_id; 2621 enum sysfs_printing_mode printing_mode; 2622 int process_id; 2623 uint16_t curr_buffer_length; 2624 uint16_t max_buffer_length; 2625 char *buf; 2626 }; 2627 #endif 2628 2629 struct test_mem_free { 2630 unsigned long ts_qdesc_mem_hdl; 2631 qdf_dma_addr_t hw_qdesc_paddr; 2632 void *hw_qdesc_vaddr_align; 2633 void *hw_qdesc_vaddr_unalign; 2634 uint32_t peer_id; 2635 uint32_t tid; 2636 uint8_t chip_id; 2637 unsigned long ts_hw_flush_back; 2638 }; 2639 2640 struct test_qaddr_del { 2641 unsigned long ts_qaddr_del; 2642 uint32_t peer_id; 2643 uint32_t paddr; 2644 uint32_t tid; 2645 uint8_t chip_id; 2646 }; 2647 2648 #ifdef DP_RX_MSDU_DONE_FAIL_HISTORY 2649 2650 #define DP_MSDU_DONE_FAIL_HIST_MAX 128 2651 2652 struct dp_msdu_done_fail_entry { 2653 qdf_dma_addr_t paddr; 2654 uint32_t sw_cookie; 2655 }; 2656 2657 struct dp_msdu_done_fail_history { 2658 qdf_atomic_t index; 2659 struct dp_msdu_done_fail_entry entry[DP_MSDU_DONE_FAIL_HIST_MAX]; 2660 }; 2661 #endif 2662 2663 #ifdef DP_RX_PEEK_MSDU_DONE_WAR 2664 #define DP_MSDU_DONE_FAIL_DESCS_MAX 64 2665 2666 struct dp_rx_msdu_done_fail_desc_list { 2667 qdf_atomic_t index; 2668 struct dp_rx_desc *msdu_done_fail_descs[DP_MSDU_DONE_FAIL_DESCS_MAX]; 2669 }; 2670 #endif 2671 2672 /* SOC level structure for data path */ 2673 struct dp_soc { 2674 /** 2675 * re-use memory section starts 2676 */ 2677 2678 /* Common base structure - Should be the first member */ 2679 struct cdp_soc_t cdp_soc; 2680 2681 /* SoC Obj */ 2682 struct cdp_ctrl_objmgr_psoc *ctrl_psoc; 2683 2684 /* OS device abstraction */ 2685 qdf_device_t osdev; 2686 2687 /*cce disable*/ 2688 bool cce_disable; 2689 2690 /* WLAN config context */ 2691 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 2692 2693 /* HTT handle for host-fw interaction */ 2694 struct htt_soc *htt_handle; 2695 2696 /* Commint init done */ 2697 qdf_atomic_t cmn_init_done; 2698 2699 /* Opaque hif handle */ 2700 struct hif_opaque_softc *hif_handle; 2701 2702 /* PDEVs on this SOC */ 2703 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 2704 2705 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 2706 struct dp_srng rx_refill_buf_ring[MAX_PDEV_CNT]; 2707 2708 struct dp_srng rxdma_mon_desc_ring[MAX_NUM_LMAC_HW]; 2709 2710 /* RXDMA error destination ring */ 2711 struct dp_srng rxdma_err_dst_ring[MAX_NUM_LMAC_HW]; 2712 2713 /* RXDMA monitor buffer replenish ring */ 2714 struct dp_srng rxdma_mon_buf_ring[MAX_NUM_LMAC_HW]; 2715 2716 /* RXDMA monitor destination ring */ 2717 struct dp_srng rxdma_mon_dst_ring[MAX_NUM_LMAC_HW]; 2718 2719 /* RXDMA monitor status ring. TBD: Check format of this ring */ 2720 struct dp_srng rxdma_mon_status_ring[MAX_NUM_LMAC_HW]; 2721 2722 /* Ring to handover links to hw in monitor mode for SOFTUMAC arch */ 2723 struct dp_srng sw2rxdma_link_ring[MAX_NUM_LMAC_HW]; 2724 2725 /* Number of PDEVs */ 2726 uint8_t pdev_count; 2727 2728 /*ast override support in HW*/ 2729 bool ast_override_support; 2730 2731 /*number of hw dscp tid map*/ 2732 uint8_t num_hw_dscp_tid_map; 2733 2734 /* HAL SOC handle */ 2735 hal_soc_handle_t hal_soc; 2736 2737 /* rx monitor pkt tlv size */ 2738 uint16_t rx_mon_pkt_tlv_size; 2739 /* rx pkt tlv size */ 2740 uint16_t rx_pkt_tlv_size; 2741 /* rx pkt tlv size in current operation mode */ 2742 uint16_t curr_rx_pkt_tlv_size; 2743 2744 /* enable/disable dp debug logs */ 2745 bool dp_debug_log_en; 2746 2747 struct dp_arch_ops arch_ops; 2748 2749 /* Device ID coming from Bus sub-system */ 2750 uint32_t device_id; 2751 2752 /* Link descriptor pages */ 2753 struct qdf_mem_multi_page_t link_desc_pages; 2754 2755 /* total link descriptors for regular RX and TX */ 2756 uint32_t total_link_descs; 2757 2758 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 2759 struct dp_srng wbm_idle_link_ring; 2760 2761 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 2762 */ 2763 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 2764 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 2765 uint32_t num_scatter_bufs; 2766 2767 /* Tx SW descriptor pool */ 2768 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 2769 2770 /* Tx MSDU Extension descriptor pool */ 2771 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 2772 2773 /* Tx TSO descriptor pool */ 2774 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 2775 2776 /* Tx TSO Num of segments pool */ 2777 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 2778 2779 /* REO destination rings */ 2780 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 2781 2782 /* REO exception ring - See if should combine this with reo_dest_ring */ 2783 struct dp_srng reo_exception_ring; 2784 2785 /* REO reinjection ring */ 2786 struct dp_srng reo_reinject_ring; 2787 2788 /* REO command ring */ 2789 struct dp_srng reo_cmd_ring; 2790 2791 /* REO command status ring */ 2792 struct dp_srng reo_status_ring; 2793 2794 /* WBM Rx release ring */ 2795 struct dp_srng rx_rel_ring; 2796 2797 /* TCL data ring */ 2798 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 2799 2800 /* Number of Tx comp rings */ 2801 uint8_t num_tx_comp_rings; 2802 2803 /* Number of TCL data rings */ 2804 uint8_t num_tcl_data_rings; 2805 2806 /* TCL CMD_CREDIT ring */ 2807 bool init_tcl_cmd_cred_ring; 2808 2809 /* It is used as credit based ring on QCN9000 else command ring */ 2810 struct dp_srng tcl_cmd_credit_ring; 2811 2812 /* TCL command status ring */ 2813 struct dp_srng tcl_status_ring; 2814 2815 /* WBM Tx completion rings */ 2816 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 2817 2818 /* Common WBM link descriptor release ring (SW to WBM) */ 2819 struct dp_srng wbm_desc_rel_ring; 2820 2821 /* DP Interrupts */ 2822 struct dp_intr intr_ctx[WLAN_CFG_INT_NUM_CONTEXTS]; 2823 2824 /* Monitor mode mac id to dp_intr_id map */ 2825 int mon_intr_id_lmac_map[MAX_NUM_LMAC_HW]; 2826 /* Rx SW descriptor pool for RXDMA monitor buffer */ 2827 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 2828 2829 /* Rx SW descriptor pool for RXDMA status buffer */ 2830 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 2831 2832 /* Rx SW descriptor pool for RXDMA buffer */ 2833 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 2834 2835 /* Number of REO destination rings */ 2836 uint8_t num_reo_dest_rings; 2837 2838 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 2839 /* lock to control access to soc TX descriptors */ 2840 qdf_spinlock_t flow_pool_array_lock; 2841 2842 /* pause callback to pause TX queues as per flow control */ 2843 tx_pause_callback pause_cb; 2844 2845 /* flow pool related statistics */ 2846 struct dp_txrx_pool_stats pool_stats; 2847 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 2848 2849 notify_pre_reset_fw_callback notify_fw_callback; 2850 2851 unsigned long service_rings_running; 2852 2853 uint32_t wbm_idle_scatter_buf_size; 2854 2855 /* VDEVs on this SOC */ 2856 struct dp_vdev *vdev_id_map[MAX_VDEV_CNT]; 2857 2858 uint8_t hw_txrx_stats_en:1; 2859 2860 /* Tx H/W queues lock */ 2861 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 2862 2863 /* Tx ring map for interrupt processing */ 2864 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2865 2866 /* Rx ring map for interrupt processing */ 2867 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2868 2869 /* peer ID to peer object map (array of pointers to peer objects) */ 2870 struct dp_peer **peer_id_to_obj_map; 2871 2872 struct { 2873 unsigned mask; 2874 unsigned idx_bits; 2875 TAILQ_HEAD(, dp_peer) * bins; 2876 } peer_hash; 2877 2878 /* rx defrag state – TBD: do we need this per radio? */ 2879 struct { 2880 struct { 2881 TAILQ_HEAD(, dp_rx_tid_defrag) waitlist; 2882 uint32_t timeout_ms; 2883 uint32_t next_flush_ms; 2884 qdf_spinlock_t defrag_lock; 2885 } defrag; 2886 struct { 2887 int defrag_timeout_check; 2888 int dup_check; 2889 } flags; 2890 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 2891 qdf_spinlock_t reo_cmd_lock; 2892 } rx; 2893 2894 /* optional rx processing function */ 2895 void (*rx_opt_proc)( 2896 struct dp_vdev *vdev, 2897 struct dp_peer *peer, 2898 unsigned tid, 2899 qdf_nbuf_t msdu_list); 2900 2901 /* pool addr for mcast enhance buff */ 2902 struct { 2903 int size; 2904 uint32_t paddr; 2905 uint32_t *vaddr; 2906 struct dp_tx_me_buf_t *freelist; 2907 int buf_in_use; 2908 qdf_dma_mem_context(memctx); 2909 } me_buf; 2910 2911 /* Protect peer hash table */ 2912 DP_MUTEX_TYPE peer_hash_lock; 2913 /* Protect peer_id_to_objmap */ 2914 DP_MUTEX_TYPE peer_map_lock; 2915 2916 /* maximum number of suppoerted peers */ 2917 uint32_t max_peers; 2918 /* maximum value for peer_id */ 2919 uint32_t max_peer_id; 2920 2921 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH 2922 uint32_t peer_id_shift; 2923 uint32_t peer_id_mask; 2924 #endif 2925 2926 /* rx peer metadata field shift and mask configuration */ 2927 uint8_t htt_peer_id_s; 2928 uint32_t htt_peer_id_m; 2929 uint8_t htt_vdev_id_s; 2930 uint32_t htt_vdev_id_m; 2931 uint8_t htt_mld_peer_valid_s; 2932 uint32_t htt_mld_peer_valid_m; 2933 /* rx peer metadata version */ 2934 uint8_t rx_peer_metadata_ver; 2935 2936 /* SoC level data path statistics */ 2937 struct dp_soc_stats stats; 2938 #ifdef WLAN_SYSFS_DP_STATS 2939 /* sysfs config for DP stats */ 2940 struct sysfs_stats_config *sysfs_config; 2941 #endif 2942 /* timestamp to keep track of msdu buffers received on reo err ring */ 2943 uint64_t rx_route_err_start_pkt_ts; 2944 2945 /* Num RX Route err in a given window to keep track of rate of errors */ 2946 uint32_t rx_route_err_in_window; 2947 2948 /* Enable processing of Tx completion status words */ 2949 bool process_tx_status; 2950 bool process_rx_status; 2951 struct dp_ast_entry **ast_table; 2952 struct { 2953 unsigned mask; 2954 unsigned idx_bits; 2955 TAILQ_HEAD(, dp_ast_entry) * bins; 2956 } ast_hash; 2957 2958 #ifdef DP_TX_HW_DESC_HISTORY 2959 struct dp_tx_hw_desc_history tx_hw_desc_history; 2960 #endif 2961 2962 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 2963 struct dp_rx_history *rx_ring_history[MAX_REO_DEST_RINGS]; 2964 struct dp_rx_refill_history *rx_refill_ring_history[MAX_PDEV_CNT]; 2965 struct dp_rx_err_history *rx_err_ring_history; 2966 struct dp_rx_reinject_history *rx_reinject_ring_history; 2967 #endif 2968 2969 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 2970 struct dp_mon_status_ring_history *mon_status_ring_history; 2971 #endif 2972 2973 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 2974 struct dp_tx_tcl_history tx_tcl_history; 2975 struct dp_tx_comp_history tx_comp_history; 2976 #endif 2977 2978 #ifdef WLAN_FEATURE_DP_CFG_EVENT_HISTORY 2979 struct dp_cfg_event_history cfg_event_history; 2980 #endif 2981 2982 qdf_spinlock_t ast_lock; 2983 /*Timer for AST entry ageout maintenance */ 2984 qdf_timer_t ast_aging_timer; 2985 2986 /*Timer counter for WDS AST entry ageout*/ 2987 uint8_t wds_ast_aging_timer_cnt; 2988 bool pending_ageout; 2989 bool ast_offload_support; 2990 bool host_ast_db_enable; 2991 uint32_t max_ast_ageout_count; 2992 uint8_t eapol_over_control_port; 2993 2994 uint8_t sta_mode_search_policy; 2995 qdf_timer_t lmac_reap_timer; 2996 uint8_t lmac_timer_init; 2997 qdf_timer_t int_timer; 2998 uint8_t intr_mode; 2999 uint8_t lmac_polled_mode; 3000 3001 qdf_list_t reo_desc_freelist; 3002 qdf_spinlock_t reo_desc_freelist_lock; 3003 3004 /* htt stats */ 3005 struct htt_t2h_stats htt_stats; 3006 3007 void *external_txrx_handle; /* External data path handle */ 3008 qdf_atomic_t ipa_map_allowed; 3009 #ifdef IPA_OFFLOAD 3010 struct ipa_dp_tx_rsc ipa_uc_tx_rsc; 3011 #ifdef IPA_WDI3_TX_TWO_PIPES 3012 /* Resources for the alternative IPA TX pipe */ 3013 struct ipa_dp_tx_rsc ipa_uc_tx_rsc_alt; 3014 #endif 3015 3016 struct ipa_dp_rx_rsc ipa_uc_rx_rsc; 3017 #ifdef IPA_WDI3_VLAN_SUPPORT 3018 struct ipa_dp_rx_rsc ipa_uc_rx_rsc_alt; 3019 #endif 3020 qdf_atomic_t ipa_pipes_enabled; 3021 bool ipa_first_tx_db_access; 3022 qdf_spinlock_t ipa_rx_buf_map_lock; 3023 bool ipa_rx_buf_map_lock_initialized; 3024 uint8_t ipa_reo_ctx_lock_required[MAX_REO_DEST_RINGS]; 3025 #endif 3026 3027 #ifdef WLAN_FEATURE_STATS_EXT 3028 struct { 3029 uint32_t rx_mpdu_received; 3030 uint32_t rx_mpdu_missed; 3031 } ext_stats; 3032 qdf_event_t rx_hw_stats_event; 3033 qdf_spinlock_t rx_hw_stats_lock; 3034 bool is_last_stats_ctx_init; 3035 struct dp_req_rx_hw_stats_t *rx_hw_stats; 3036 #endif /* WLAN_FEATURE_STATS_EXT */ 3037 3038 /* Indicates HTT map/unmap versions*/ 3039 uint8_t peer_map_unmap_versions; 3040 /* Per peer per Tid ba window size support */ 3041 uint8_t per_tid_basize_max_tid; 3042 /* Soc level flag to enable da_war */ 3043 uint8_t da_war_enabled; 3044 /* number of active ast entries */ 3045 uint32_t num_ast_entries; 3046 /* peer extended rate statistics context at soc level*/ 3047 struct cdp_soc_rate_stats_ctx *rate_stats_ctx; 3048 /* peer extended rate statistics control flag */ 3049 bool peerstats_enabled; 3050 3051 /* 8021p PCP-TID map values */ 3052 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 3053 /* TID map priority value */ 3054 uint8_t tidmap_prty; 3055 /* Pointer to global per ring type specific configuration table */ 3056 struct wlan_srng_cfg *wlan_srng_cfg; 3057 /* Num Tx outstanding on device */ 3058 qdf_atomic_t num_tx_outstanding; 3059 /* Num Tx exception on device */ 3060 qdf_atomic_t num_tx_exception; 3061 /* Num Tx allowed */ 3062 uint32_t num_tx_allowed; 3063 /* Num Regular Tx allowed */ 3064 uint32_t num_reg_tx_allowed; 3065 /* Num Tx allowed for special frames*/ 3066 uint32_t num_tx_spl_allowed; 3067 /* Preferred HW mode */ 3068 uint8_t preferred_hw_mode; 3069 3070 /** 3071 * Flag to indicate whether WAR to address single cache entry 3072 * invalidation bug is enabled or not 3073 */ 3074 bool is_rx_fse_full_cache_invalidate_war_enabled; 3075 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) 3076 /** 3077 * Pointer to DP RX Flow FST at SOC level if 3078 * is_rx_flow_search_table_per_pdev is false 3079 * TBD: rx_fst[num_macs] if we decide to have per mac FST 3080 */ 3081 struct dp_rx_fst *rx_fst; 3082 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 3083 /* SG supported for msdu continued packets from wbm release ring */ 3084 bool wbm_release_desc_rx_sg_support; 3085 bool peer_map_attach_success; 3086 /* Flag to disable mac1 ring interrupts */ 3087 bool disable_mac1_intr; 3088 /* Flag to disable mac2 ring interrupts */ 3089 bool disable_mac2_intr; 3090 3091 struct { 3092 /* 1st msdu in sg for msdu continued packets in wbm rel ring */ 3093 bool wbm_is_first_msdu_in_sg; 3094 /* Wbm sg list head */ 3095 qdf_nbuf_t wbm_sg_nbuf_head; 3096 /* Wbm sg list tail */ 3097 qdf_nbuf_t wbm_sg_nbuf_tail; 3098 uint32_t wbm_sg_desc_msdu_len; 3099 } wbm_sg_param; 3100 /* Number of msdu exception descriptors */ 3101 uint32_t num_msdu_exception_desc; 3102 3103 /* RX buffer params */ 3104 struct rx_buff_pool rx_buff_pool[MAX_PDEV_CNT]; 3105 struct rx_refill_buff_pool rx_refill_buff_pool; 3106 /* Save recent operation related variable */ 3107 struct dp_last_op_info last_op_info; 3108 TAILQ_HEAD(, dp_peer) inactive_peer_list; 3109 qdf_spinlock_t inactive_peer_list_lock; 3110 TAILQ_HEAD(, dp_vdev) inactive_vdev_list; 3111 qdf_spinlock_t inactive_vdev_list_lock; 3112 /* lock to protect vdev_id_map table*/ 3113 qdf_spinlock_t vdev_map_lock; 3114 3115 /* Flow Search Table is in CMEM */ 3116 bool fst_in_cmem; 3117 3118 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 3119 struct dp_swlm swlm; 3120 #endif 3121 3122 #ifdef FEATURE_RUNTIME_PM 3123 /* DP Rx timestamp */ 3124 qdf_time_t rx_last_busy; 3125 /* Dp runtime refcount */ 3126 qdf_atomic_t dp_runtime_refcount; 3127 /* Dp tx pending count in RTPM */ 3128 qdf_atomic_t tx_pending_rtpm; 3129 #endif 3130 /* Invalid buffer that allocated for RX buffer */ 3131 qdf_nbuf_queue_t invalid_buf_queue; 3132 3133 #ifdef FEATURE_MEC 3134 /** @mec_lock: spinlock for MEC table */ 3135 qdf_spinlock_t mec_lock; 3136 /** @mec_cnt: number of active mec entries */ 3137 qdf_atomic_t mec_cnt; 3138 struct { 3139 /** @mask: mask bits */ 3140 uint32_t mask; 3141 /** @idx_bits: index to shift bits */ 3142 uint32_t idx_bits; 3143 /** @bins: MEC table */ 3144 TAILQ_HEAD(, dp_mec_entry) * bins; 3145 } mec_hash; 3146 #endif 3147 3148 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 3149 qdf_list_t reo_desc_deferred_freelist; 3150 qdf_spinlock_t reo_desc_deferred_freelist_lock; 3151 bool reo_desc_deferred_freelist_init; 3152 #endif 3153 /* BM id for first WBM2SW ring */ 3154 uint32_t wbm_sw0_bm_id; 3155 3156 /* Store arch_id from device_id */ 3157 uint16_t arch_id; 3158 3159 /* link desc ID start per device type */ 3160 uint32_t link_desc_id_start; 3161 3162 /* CMEM buffer target reserved for host usage */ 3163 uint64_t cmem_base; 3164 /* CMEM size in bytes */ 3165 uint64_t cmem_total_size; 3166 /* CMEM free size in bytes */ 3167 uint64_t cmem_avail_size; 3168 3169 /* SOC level feature flags */ 3170 struct dp_soc_features features; 3171 3172 #ifdef WIFI_MONITOR_SUPPORT 3173 struct dp_mon_soc *monitor_soc; 3174 #endif 3175 uint8_t rxdma2sw_rings_not_supported:1, 3176 wbm_sg_last_msdu_war:1, 3177 mec_fw_offload:1, 3178 multi_peer_grp_cmd_supported:1, 3179 umac_reset_supported:1; 3180 3181 /* Number of Rx refill rings */ 3182 uint8_t num_rx_refill_buf_rings; 3183 #ifdef FEATURE_RUNTIME_PM 3184 /* flag to indicate vote for runtime_pm for high tput castt*/ 3185 qdf_atomic_t rtpm_high_tput_flag; 3186 #endif 3187 /* Buffer manager ID for idle link descs */ 3188 uint8_t idle_link_bm_id; 3189 qdf_atomic_t ref_count; 3190 3191 unsigned long vdev_stats_id_map; 3192 bool txmon_hw_support; 3193 3194 #ifdef DP_UMAC_HW_RESET_SUPPORT 3195 struct dp_soc_umac_reset_ctx umac_reset_ctx; 3196 #endif 3197 /* PPDU to link_id mapping parameters */ 3198 uint8_t link_id_offset; 3199 uint8_t link_id_bits; 3200 #ifdef FEATURE_RX_LINKSPEED_ROAM_TRIGGER 3201 /* A flag using to decide the switch of rx link speed */ 3202 bool high_throughput; 3203 #endif 3204 bool is_tx_pause; 3205 3206 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 3207 /* number of IPv4 flows inserted */ 3208 qdf_atomic_t ipv4_fse_cnt; 3209 /* number of IPv6 flows inserted */ 3210 qdf_atomic_t ipv6_fse_cnt; 3211 #endif 3212 /* Reo queue ref table items */ 3213 struct reo_queue_ref_table reo_qref; 3214 #ifdef DP_TX_PACKET_INSPECT_FOR_ILP 3215 /* Flag to show if TX ILP is enabled */ 3216 bool tx_ilp_enable; 3217 #endif 3218 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 3219 uint8_t mld_mode_ap; 3220 #endif 3221 struct test_qaddr_del *list_shared_qaddr_del; 3222 struct test_qaddr_del *reo_write_list; 3223 struct test_mem_free *list_qdesc_addr_free; 3224 struct test_mem_free *list_qdesc_addr_alloc; 3225 uint64_t free_addr_list_idx; 3226 uint64_t alloc_addr_list_idx; 3227 uint64_t shared_qaddr_del_idx; 3228 uint64_t write_paddr_list_idx; 3229 3230 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 3231 /* callback function for tx latency stats */ 3232 cdp_tx_latency_cb tx_latency_cb; 3233 #endif 3234 3235 #ifdef DP_TX_COMP_RING_DESC_SANITY_CHECK 3236 struct { 3237 uint32_t detected; 3238 uint64_t start_time; 3239 } stale_entry[MAX_TCL_DATA_RINGS]; 3240 #endif 3241 #ifdef DP_RX_MSDU_DONE_FAIL_HISTORY 3242 struct dp_msdu_done_fail_history *msdu_done_fail_hist; 3243 #endif 3244 #ifdef DP_RX_PEEK_MSDU_DONE_WAR 3245 struct dp_rx_msdu_done_fail_desc_list msdu_done_fail_desc_list; 3246 #endif 3247 }; 3248 3249 #ifdef IPA_OFFLOAD 3250 /** 3251 * struct dp_ipa_resources - Resources needed for IPA 3252 * @tx_ring: 3253 * @tx_num_alloc_buffer: 3254 * @tx_comp_ring: 3255 * @rx_rdy_ring: 3256 * @rx_refill_ring: 3257 * @tx_comp_doorbell_paddr: IPA UC doorbell registers paddr 3258 * @tx_comp_doorbell_vaddr: 3259 * @rx_ready_doorbell_paddr: 3260 * @is_db_ddr_mapped: 3261 * @tx_alt_ring: 3262 * @tx_alt_ring_num_alloc_buffer: 3263 * @tx_alt_comp_ring: 3264 * @tx_alt_comp_doorbell_paddr: IPA UC doorbell registers paddr 3265 * @tx_alt_comp_doorbell_vaddr: 3266 * @rx_alt_rdy_ring: 3267 * @rx_alt_refill_ring: 3268 * @rx_alt_ready_doorbell_paddr: 3269 */ 3270 struct dp_ipa_resources { 3271 qdf_shared_mem_t tx_ring; 3272 uint32_t tx_num_alloc_buffer; 3273 3274 qdf_shared_mem_t tx_comp_ring; 3275 qdf_shared_mem_t rx_rdy_ring; 3276 qdf_shared_mem_t rx_refill_ring; 3277 3278 /* IPA UC doorbell registers paddr */ 3279 qdf_dma_addr_t tx_comp_doorbell_paddr; 3280 uint32_t *tx_comp_doorbell_vaddr; 3281 qdf_dma_addr_t rx_ready_doorbell_paddr; 3282 3283 bool is_db_ddr_mapped; 3284 3285 #ifdef IPA_WDI3_TX_TWO_PIPES 3286 qdf_shared_mem_t tx_alt_ring; 3287 uint32_t tx_alt_ring_num_alloc_buffer; 3288 qdf_shared_mem_t tx_alt_comp_ring; 3289 3290 /* IPA UC doorbell registers paddr */ 3291 qdf_dma_addr_t tx_alt_comp_doorbell_paddr; 3292 uint32_t *tx_alt_comp_doorbell_vaddr; 3293 #endif 3294 #ifdef IPA_WDI3_VLAN_SUPPORT 3295 qdf_shared_mem_t rx_alt_rdy_ring; 3296 qdf_shared_mem_t rx_alt_refill_ring; 3297 qdf_dma_addr_t rx_alt_ready_doorbell_paddr; 3298 #endif 3299 }; 3300 #endif 3301 3302 #define MAX_RX_MAC_RINGS 2 3303 /* Same as NAC_MAX_CLENT */ 3304 #define DP_NAC_MAX_CLIENT 24 3305 3306 /* 3307 * 24 bits cookie size 3308 * 10 bits page id 0 ~ 1023 for MCL 3309 * 3 bits page id 0 ~ 7 for WIN 3310 * WBM Idle List Desc size = 128, 3311 * Num descs per page = 4096/128 = 32 for MCL 3312 * Num descs per page = 2MB/128 = 16384 for WIN 3313 */ 3314 /* 3315 * Macros to setup link descriptor cookies - for link descriptors, we just 3316 * need first 3 bits to store bank/page ID for WIN. The 3317 * remaining bytes will be used to set a unique ID, which will 3318 * be useful in debugging 3319 */ 3320 #ifdef MAX_ALLOC_PAGE_SIZE 3321 #if PAGE_SIZE == 4096 3322 #define LINK_DESC_PAGE_ID_MASK 0x007FE0 3323 #define LINK_DESC_ID_SHIFT 5 3324 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 3325 #elif PAGE_SIZE == 65536 3326 #define LINK_DESC_PAGE_ID_MASK 0x007E00 3327 #define LINK_DESC_ID_SHIFT 9 3328 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x800 3329 #else 3330 #error "Unsupported kernel PAGE_SIZE" 3331 #endif 3332 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 3333 ((((_page_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_desc_id)) 3334 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 3335 (((_cookie) & LINK_DESC_PAGE_ID_MASK) >> LINK_DESC_ID_SHIFT) 3336 #else 3337 #define LINK_DESC_PAGE_ID_MASK 0x7 3338 #define LINK_DESC_ID_SHIFT 3 3339 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 3340 ((((_desc_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_page_id)) 3341 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 3342 ((_cookie) & LINK_DESC_PAGE_ID_MASK) 3343 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 3344 #endif 3345 #define LINK_DESC_ID_START_20_BITS_COOKIE 0x4000 3346 3347 /* same as ieee80211_nac_param */ 3348 enum dp_nac_param_cmd { 3349 /* IEEE80211_NAC_PARAM_ADD */ 3350 DP_NAC_PARAM_ADD = 1, 3351 /* IEEE80211_NAC_PARAM_DEL */ 3352 DP_NAC_PARAM_DEL, 3353 /* IEEE80211_NAC_PARAM_LIST */ 3354 DP_NAC_PARAM_LIST, 3355 }; 3356 3357 /** 3358 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 3359 * @neighbour_peers_macaddr: neighbour peer's mac address 3360 * @vdev: associated vdev 3361 * @ast_entry: ast_entry for neighbour peer 3362 * @rssi: rssi value 3363 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 3364 */ 3365 struct dp_neighbour_peer { 3366 union dp_align_mac_addr neighbour_peers_macaddr; 3367 struct dp_vdev *vdev; 3368 struct dp_ast_entry *ast_entry; 3369 uint8_t rssi; 3370 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 3371 }; 3372 3373 #ifdef WLAN_TX_PKT_CAPTURE_ENH 3374 #define WLAN_TX_PKT_CAPTURE_ENH 1 3375 #define DP_TX_PPDU_PROC_THRESHOLD 8 3376 #define DP_TX_PPDU_PROC_TIMEOUT 10 3377 #endif 3378 3379 /** 3380 * struct ppdu_info - PPDU Status info descriptor 3381 * @ppdu_id: Unique ppduid assigned by firmware for every tx packet 3382 * @sched_cmdid: schedule command id, which will be same in a burst 3383 * @max_ppdu_id: wrap around for ppdu id 3384 * @tsf_l32: 3385 * @tlv_bitmap: 3386 * @last_tlv_cnt: Keep track for missing ppdu tlvs 3387 * @last_user: last ppdu processed for user 3388 * @is_ampdu: set if Ampdu aggregate 3389 * @nbuf: ppdu descriptor payload 3390 * @ppdu_desc: ppdu descriptor 3391 * @ulist: Union of lists 3392 * @ppdu_info_dlist_elem: linked list of ppdu tlvs 3393 * @ppdu_info_slist_elem: Singly linked list (queue) of ppdu tlvs 3394 * @ppdu_info_list_elem: linked list of ppdu tlvs 3395 * @ppdu_info_queue_elem: Singly linked list (queue) of ppdu tlvs 3396 * @compltn_common_tlv: Successful tlv counter from COMPLTN COMMON tlv 3397 * @ack_ba_tlv: Successful tlv counter from ACK BA tlv 3398 * @done: 3399 */ 3400 struct ppdu_info { 3401 uint32_t ppdu_id; 3402 uint32_t sched_cmdid; 3403 uint32_t max_ppdu_id; 3404 uint32_t tsf_l32; 3405 uint16_t tlv_bitmap; 3406 uint16_t last_tlv_cnt; 3407 uint16_t last_user:8, 3408 is_ampdu:1; 3409 qdf_nbuf_t nbuf; 3410 struct cdp_tx_completion_ppdu *ppdu_desc; 3411 #ifdef WLAN_TX_PKT_CAPTURE_ENH 3412 union { 3413 TAILQ_ENTRY(ppdu_info) ppdu_info_dlist_elem; 3414 STAILQ_ENTRY(ppdu_info) ppdu_info_slist_elem; 3415 } ulist; 3416 #define ppdu_info_list_elem ulist.ppdu_info_dlist_elem 3417 #define ppdu_info_queue_elem ulist.ppdu_info_slist_elem 3418 #else 3419 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 3420 #endif 3421 uint8_t compltn_common_tlv; 3422 uint8_t ack_ba_tlv; 3423 bool done; 3424 }; 3425 3426 /** 3427 * struct msdu_completion_info - wbm msdu completion info 3428 * @ppdu_id: Unique ppduid assigned by firmware for every tx packet 3429 * @peer_id: peer_id 3430 * @tid: tid which used during transmit 3431 * @first_msdu: first msdu indication 3432 * @last_msdu: last msdu indication 3433 * @msdu_part_of_amsdu: msdu part of amsdu 3434 * @transmit_cnt: retried count 3435 * @status: transmit status 3436 * @tsf: timestamp which it transmitted 3437 */ 3438 struct msdu_completion_info { 3439 uint32_t ppdu_id; 3440 uint16_t peer_id; 3441 uint8_t tid; 3442 uint8_t first_msdu:1, 3443 last_msdu:1, 3444 msdu_part_of_amsdu:1; 3445 uint8_t transmit_cnt; 3446 uint8_t status; 3447 uint32_t tsf; 3448 }; 3449 3450 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 3451 struct rx_protocol_tag_map { 3452 /* This is the user configured tag for the said protocol type */ 3453 uint16_t tag; 3454 }; 3455 3456 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 3457 /** 3458 * struct rx_protocol_tag_stats - protocol statistics 3459 * @tag_ctr: number of rx msdus matching this tag 3460 */ 3461 struct rx_protocol_tag_stats { 3462 uint32_t tag_ctr; 3463 }; 3464 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 3465 3466 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 3467 3468 #ifdef WLAN_RX_PKT_CAPTURE_ENH 3469 /* Template data to be set for Enhanced RX Monitor packets */ 3470 #define RX_MON_CAP_ENH_TRAILER 0xdeadc0dedeadda7a 3471 3472 /** 3473 * struct dp_rx_mon_enh_trailer_data - Data structure to set a known pattern 3474 * at end of each MSDU in monitor-lite mode 3475 * @reserved1: reserved for future use 3476 * @reserved2: reserved for future use 3477 * @flow_tag: flow tag value read from skb->cb 3478 * @protocol_tag: protocol tag value read from skb->cb 3479 */ 3480 struct dp_rx_mon_enh_trailer_data { 3481 uint16_t reserved1; 3482 uint16_t reserved2; 3483 uint16_t flow_tag; 3484 uint16_t protocol_tag; 3485 }; 3486 #endif /* WLAN_RX_PKT_CAPTURE_ENH */ 3487 3488 #ifdef HTT_STATS_DEBUGFS_SUPPORT 3489 /* Number of debugfs entries created for HTT stats */ 3490 #define PDEV_HTT_STATS_DBGFS_SIZE HTT_DBG_NUM_EXT_STATS 3491 3492 /** 3493 * struct pdev_htt_stats_dbgfs_priv - Structure to maintain debugfs information 3494 * of HTT stats 3495 * @pdev: dp pdev of debugfs entry 3496 * @stats_id: stats id of debugfs entry 3497 */ 3498 struct pdev_htt_stats_dbgfs_priv { 3499 struct dp_pdev *pdev; 3500 uint16_t stats_id; 3501 }; 3502 3503 /** 3504 * struct pdev_htt_stats_dbgfs_cfg - PDEV level data structure for debugfs 3505 * support for HTT stats 3506 * @debugfs_entry: qdf_debugfs directory entry 3507 * @m: qdf debugfs file handler 3508 * @pdev_htt_stats_dbgfs_ops: File operations of entry created 3509 * @priv: HTT stats debugfs private object 3510 * @htt_stats_dbgfs_event: HTT stats event for debugfs support 3511 * @lock: HTT stats debugfs lock 3512 * @htt_stats_dbgfs_msg_process: Function callback to print HTT stats 3513 */ 3514 struct pdev_htt_stats_dbgfs_cfg { 3515 qdf_dentry_t debugfs_entry[PDEV_HTT_STATS_DBGFS_SIZE]; 3516 qdf_debugfs_file_t m; 3517 struct qdf_debugfs_fops 3518 pdev_htt_stats_dbgfs_ops[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 3519 struct pdev_htt_stats_dbgfs_priv priv[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 3520 qdf_event_t htt_stats_dbgfs_event; 3521 qdf_mutex_t lock; 3522 void (*htt_stats_dbgfs_msg_process)(void *data, A_INT32 len); 3523 }; 3524 #endif /* HTT_STATS_DEBUGFS_SUPPORT */ 3525 3526 struct dp_srng_ring_state { 3527 enum hal_ring_type ring_type; 3528 uint32_t sw_head; 3529 uint32_t sw_tail; 3530 uint32_t hw_head; 3531 uint32_t hw_tail; 3532 3533 }; 3534 3535 struct dp_soc_srngs_state { 3536 uint32_t seq_num; 3537 uint32_t max_ring_id; 3538 struct dp_srng_ring_state ring_state[DP_MAX_SRNGS]; 3539 TAILQ_ENTRY(dp_soc_srngs_state) list_elem; 3540 }; 3541 3542 #ifdef WLAN_FEATURE_11BE_MLO 3543 /* struct dp_mlo_sync_timestamp - PDEV level data structure for storing 3544 * MLO timestamp received via HTT msg. 3545 * msg_type: This would be set to HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 3546 * pdev_id: pdev_id 3547 * chip_id: chip_id 3548 * mac_clk_freq: mac clock frequency of the mac HW block in MHz 3549 * sync_tstmp_lo_us: lower 32 bits of the WLAN global time stamp (in us) at 3550 * which last sync interrupt was received 3551 * sync_tstmp_hi_us: upper 32 bits of the WLAN global time stamp (in us) at 3552 * which last sync interrupt was received 3553 * mlo_offset_lo_us: lower 32 bits of the MLO time stamp offset in us 3554 * mlo_offset_hi_us: upper 32 bits of the MLO time stamp offset in us 3555 * mlo_offset_clks: MLO time stamp offset in clock ticks for sub us 3556 * mlo_comp_us: MLO time stamp compensation applied in us 3557 * mlo_comp_clks: MLO time stamp compensation applied in clock ticks 3558 * for sub us resolution 3559 * mlo_comp_timer: period of MLO compensation timer at which compensation 3560 * is applied, in us 3561 */ 3562 struct dp_mlo_sync_timestamp { 3563 uint32_t msg_type:8, 3564 pdev_id:2, 3565 chip_id:2, 3566 rsvd1:4, 3567 mac_clk_freq:16; 3568 uint32_t sync_tstmp_lo_us; 3569 uint32_t sync_tstmp_hi_us; 3570 uint32_t mlo_offset_lo_us; 3571 uint32_t mlo_offset_hi_us; 3572 uint32_t mlo_offset_clks; 3573 uint32_t mlo_comp_us:16, 3574 mlo_comp_clks:10, 3575 rsvd2:6; 3576 uint32_t mlo_comp_timer:22, 3577 rsvd3:10; 3578 }; 3579 #endif 3580 3581 /* PDEV level structure for data path */ 3582 struct dp_pdev { 3583 /** 3584 * Re-use Memory Section Starts 3585 */ 3586 3587 /* PDEV Id */ 3588 uint8_t pdev_id; 3589 3590 /* LMAC Id */ 3591 uint8_t lmac_id; 3592 3593 /* Target pdev Id */ 3594 uint8_t target_pdev_id; 3595 3596 bool pdev_deinit; 3597 3598 /* TXRX SOC handle */ 3599 struct dp_soc *soc; 3600 3601 /* pdev status down or up required to handle dynamic hw 3602 * mode switch between DBS and DBS_SBS. 3603 * 1 = down 3604 * 0 = up 3605 */ 3606 bool is_pdev_down; 3607 3608 /* Enhanced Stats is enabled */ 3609 uint8_t enhanced_stats_en:1, 3610 link_peer_stats:1; 3611 3612 /* Flag to indicate fast path Tx flags */ 3613 uint32_t tx_fast_flag; 3614 3615 /* Flag to indicate fast RX */ 3616 bool rx_fast_flag; 3617 3618 /* Second ring used to replenish rx buffers */ 3619 struct dp_srng rx_refill_buf_ring2; 3620 #ifdef IPA_WDI3_VLAN_SUPPORT 3621 /* Third ring used to replenish rx buffers */ 3622 struct dp_srng rx_refill_buf_ring3; 3623 #endif 3624 3625 #ifdef FEATURE_DIRECT_LINK 3626 /* Fourth ring used to replenish rx buffers */ 3627 struct dp_srng rx_refill_buf_ring4; 3628 #endif 3629 3630 /* Empty ring used by firmware to post rx buffers to the MAC */ 3631 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 3632 3633 int ch_band_lmac_id_mapping[REG_BAND_UNKNOWN]; 3634 3635 /* wlan_cfg pdev ctxt*/ 3636 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 3637 3638 /** 3639 * TODO: See if we need a ring map here for LMAC rings. 3640 * 1. Monitor rings are currently planning to be processed on receiving 3641 * PPDU end interrupts and hence won't need ring based interrupts. 3642 * 2. Rx buffer rings will be replenished during REO destination 3643 * processing and doesn't require regular interrupt handling - we will 3644 * only handle low water mark interrupts which is not expected 3645 * frequently 3646 */ 3647 3648 /* VDEV list */ 3649 TAILQ_HEAD(, dp_vdev) vdev_list; 3650 3651 /* vdev list lock */ 3652 qdf_spinlock_t vdev_list_lock; 3653 3654 /* Number of vdevs this device have */ 3655 uint16_t vdev_count; 3656 3657 /* PDEV transmit lock */ 3658 qdf_spinlock_t tx_lock; 3659 3660 /*tx_mutex for me*/ 3661 DP_MUTEX_TYPE tx_mutex; 3662 3663 /* msdu chain head & tail */ 3664 qdf_nbuf_t invalid_peer_head_msdu; 3665 qdf_nbuf_t invalid_peer_tail_msdu; 3666 3667 /* Band steering */ 3668 /* TBD */ 3669 3670 /* PDEV level data path statistics */ 3671 struct cdp_pdev_stats stats; 3672 3673 /* Global RX decap mode for the device */ 3674 enum htt_pkt_type rx_decap_mode; 3675 3676 qdf_atomic_t num_tx_outstanding; 3677 int32_t tx_descs_max; 3678 3679 qdf_atomic_t num_tx_exception; 3680 3681 /* MCL specific local peer handle */ 3682 struct { 3683 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 3684 uint8_t freelist; 3685 qdf_spinlock_t lock; 3686 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 3687 } local_peer_ids; 3688 3689 /* dscp_tid_map_*/ 3690 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 3691 3692 /* operating channel */ 3693 struct { 3694 uint8_t num; 3695 uint8_t band; 3696 uint16_t freq; 3697 } operating_channel; 3698 3699 /* pool addr for mcast enhance buff */ 3700 struct { 3701 int size; 3702 uint32_t paddr; 3703 char *vaddr; 3704 struct dp_tx_me_buf_t *freelist; 3705 int buf_in_use; 3706 qdf_dma_mem_context(memctx); 3707 } me_buf; 3708 3709 bool hmmc_tid_override_en; 3710 uint8_t hmmc_tid; 3711 3712 /* Number of VAPs with mcast enhancement enabled */ 3713 qdf_atomic_t mc_num_vap_attached; 3714 3715 qdf_atomic_t stats_cmd_complete; 3716 3717 #ifdef IPA_OFFLOAD 3718 ipa_uc_op_cb_type ipa_uc_op_cb; 3719 void *usr_ctxt; 3720 struct dp_ipa_resources ipa_resource; 3721 #endif 3722 3723 /* TBD */ 3724 3725 /* map this pdev to a particular Reo Destination ring */ 3726 enum cdp_host_reo_dest_ring reo_dest; 3727 3728 /* WDI event handlers */ 3729 struct wdi_event_subscribe_t **wdi_event_list; 3730 3731 bool cfr_rcc_mode; 3732 3733 /* enable time latency check for tx completion */ 3734 bool latency_capture_enable; 3735 3736 /* enable calculation of delay stats*/ 3737 bool delay_stats_flag; 3738 /* vow stats */ 3739 bool vow_stats; 3740 void *dp_txrx_handle; /* Advanced data path handle */ 3741 uint32_t ppdu_id; 3742 bool first_nbuf; 3743 /* Current noise-floor reading for the pdev channel */ 3744 int16_t chan_noise_floor; 3745 3746 /* 3747 * For multiradio device, this flag indicates if 3748 * this radio is primary or secondary. 3749 * 3750 * For HK 1.0, this is used for WAR for the AST issue. 3751 * HK 1.x mandates creation of only 1 AST entry with same MAC address 3752 * across 2 radios. is_primary indicates the radio on which DP should 3753 * install HW AST entry if there is a request to add 2 AST entries 3754 * with same MAC address across 2 radios 3755 */ 3756 uint8_t is_primary; 3757 struct cdp_tx_sojourn_stats sojourn_stats; 3758 qdf_nbuf_t sojourn_buf; 3759 3760 union dp_rx_desc_list_elem_t *free_list_head; 3761 union dp_rx_desc_list_elem_t *free_list_tail; 3762 /* Cached peer_id from htt_peer_details_tlv */ 3763 uint16_t fw_stats_peer_id; 3764 3765 /* qdf_event for fw_peer_stats */ 3766 qdf_event_t fw_peer_stats_event; 3767 3768 /* qdf_event for fw_stats */ 3769 qdf_event_t fw_stats_event; 3770 3771 /* qdf_event for fw__obss_stats */ 3772 qdf_event_t fw_obss_stats_event; 3773 3774 /* To check if request is already sent for obss stats */ 3775 bool pending_fw_obss_stats_response; 3776 3777 /* User configured max number of tx buffers */ 3778 uint32_t num_tx_allowed; 3779 3780 /* 3781 * User configured max num of tx buffers excluding the 3782 * number of buffers reserved for handling special frames 3783 */ 3784 uint32_t num_reg_tx_allowed; 3785 3786 /* User configured max number of tx buffers for the special frames*/ 3787 uint32_t num_tx_spl_allowed; 3788 3789 /* unique cookie required for peer session */ 3790 uint32_t next_peer_cookie; 3791 3792 /* 3793 * Run time enabled when the first protocol tag is added, 3794 * run time disabled when the last protocol tag is deleted 3795 */ 3796 bool is_rx_protocol_tagging_enabled; 3797 3798 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 3799 /* 3800 * The protocol type is used as array index to save 3801 * user provided tag info 3802 */ 3803 struct rx_protocol_tag_map rx_proto_tag_map[RX_PROTOCOL_TAG_MAX]; 3804 3805 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 3806 /* 3807 * Track msdus received from each reo ring separately to avoid 3808 * simultaneous writes from different core 3809 */ 3810 struct rx_protocol_tag_stats 3811 reo_proto_tag_stats[MAX_REO_DEST_RINGS][RX_PROTOCOL_TAG_MAX]; 3812 /* Track msdus received from exception ring separately */ 3813 struct rx_protocol_tag_stats 3814 rx_err_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 3815 struct rx_protocol_tag_stats 3816 mon_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 3817 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 3818 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 3819 3820 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 3821 /** 3822 * Pointer to DP Flow FST at SOC level if 3823 * is_rx_flow_search_table_per_pdev is true 3824 */ 3825 struct dp_rx_fst *rx_fst; 3826 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 3827 3828 #ifdef FEATURE_TSO_STATS 3829 /* TSO Id to index into TSO packet information */ 3830 qdf_atomic_t tso_idx; 3831 #endif /* FEATURE_TSO_STATS */ 3832 3833 #ifdef WLAN_SUPPORT_DATA_STALL 3834 data_stall_detect_cb data_stall_detect_callback; 3835 #endif /* WLAN_SUPPORT_DATA_STALL */ 3836 3837 /* flag to indicate whether LRO hash command has been sent to FW */ 3838 uint8_t is_lro_hash_configured; 3839 3840 #ifdef HTT_STATS_DEBUGFS_SUPPORT 3841 /* HTT stats debugfs params */ 3842 struct pdev_htt_stats_dbgfs_cfg *dbgfs_cfg; 3843 #endif 3844 struct { 3845 qdf_work_t work; 3846 qdf_workqueue_t *work_queue; 3847 uint32_t seq_num; 3848 uint8_t queue_depth; 3849 qdf_spinlock_t list_lock; 3850 3851 TAILQ_HEAD(, dp_soc_srngs_state) list; 3852 } bkp_stats; 3853 #ifdef WIFI_MONITOR_SUPPORT 3854 struct dp_mon_pdev *monitor_pdev; 3855 #endif 3856 #ifdef WLAN_FEATURE_11BE_MLO 3857 struct dp_mlo_sync_timestamp timestamp; 3858 #endif 3859 /* Is isolation mode enabled */ 3860 bool isolation; 3861 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 3862 uint8_t is_first_wakeup_packet; 3863 #endif 3864 #ifdef CONNECTIVITY_PKTLOG 3865 /* packetdump callback functions */ 3866 ol_txrx_pktdump_cb dp_tx_packetdump_cb; 3867 ol_txrx_pktdump_cb dp_rx_packetdump_cb; 3868 #endif 3869 3870 /* Firmware Stats for TLV received from Firmware */ 3871 uint64_t fw_stats_tlv_bitmap_rcvd; 3872 3873 /* For Checking Pending Firmware Response */ 3874 bool pending_fw_stats_response; 3875 }; 3876 3877 struct dp_peer; 3878 3879 #ifdef DP_RX_UDP_OVER_PEER_ROAM 3880 #define WLAN_ROAM_PEER_AUTH_STATUS_NONE 0x0 3881 /* 3882 * This macro is equivalent to macro ROAM_AUTH_STATUS_AUTHENTICATED used 3883 * in connection mgr 3884 */ 3885 #define WLAN_ROAM_PEER_AUTH_STATUS_AUTHENTICATED 0x2 3886 #endif 3887 3888 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 3889 /** 3890 * struct dp_tx_latency_config - configuration for per-link transmit latency 3891 * statistics 3892 * @enabled: the feature is enabled or not 3893 * @report: async report is enabled or not 3894 * @granularity: granularity(in microseconds) of the distribution for the types 3895 */ 3896 struct dp_tx_latency_config { 3897 qdf_atomic_t enabled; 3898 qdf_atomic_t report; 3899 qdf_atomic_t granularity[CDP_TX_LATENCY_TYPE_MAX]; 3900 }; 3901 3902 /** 3903 * struct dp_tx_latency_stats - transmit latency distribution for a type 3904 * @latency_accum: accumulated latencies 3905 * @msdus_accum: accumulated number of msdus 3906 * @distribution: distribution of latencies 3907 */ 3908 struct dp_tx_latency_stats { 3909 qdf_atomic_t latency_accum; 3910 qdf_atomic_t msdus_accum; 3911 qdf_atomic_t distribution[CDP_TX_LATENCY_DISTR_LV_MAX]; 3912 }; 3913 3914 /** 3915 * struct dp_tx_latency - transmit latency statistics for remote link peer 3916 * @cur_idx: current row index of the 2D stats array 3917 * @stats: two-dimensional array, to store the transmit latency statistics. 3918 * one row is used to store the stats of the current cycle, it's indicated 3919 * by cur_idx, the other is for the last cycle. 3920 */ 3921 struct dp_tx_latency { 3922 uint8_t cur_idx; 3923 struct dp_tx_latency_stats stats[2][CDP_TX_LATENCY_TYPE_MAX]; 3924 }; 3925 #endif 3926 3927 /** 3928 * struct dp_vdev_stats - vdev stats structure for dp vdev 3929 * @tx_i: ingress tx stats, contains legacy and MLO ingress tx stats 3930 * @rx_i: ingress rx stats 3931 * @tx: cdp tx stats 3932 * @rx: cdp rx stats 3933 * @tso_stats: tso stats 3934 * @tid_tx_stats: tid tx stats 3935 */ 3936 struct dp_vdev_stats { 3937 struct cdp_tx_ingress_stats tx_i[DP_INGRESS_STATS_MAX_SIZE]; 3938 struct cdp_rx_ingress_stats rx_i; 3939 struct cdp_tx_stats tx; 3940 struct cdp_rx_stats rx; 3941 struct cdp_tso_stats tso_stats; 3942 #ifdef HW_TX_DELAY_STATS_ENABLE 3943 struct cdp_tid_tx_stats tid_tx_stats[CDP_MAX_TX_COMP_RINGS] 3944 [CDP_MAX_DATA_TIDS]; 3945 #endif 3946 }; 3947 3948 /* VDEV structure for data path state */ 3949 struct dp_vdev { 3950 /* OS device abstraction */ 3951 qdf_device_t osdev; 3952 3953 /* physical device that is the parent of this virtual device */ 3954 struct dp_pdev *pdev; 3955 3956 /* VDEV operating mode */ 3957 enum wlan_op_mode opmode; 3958 3959 /* VDEV subtype */ 3960 enum wlan_op_subtype subtype; 3961 3962 /* Tx encapsulation type for this VAP */ 3963 enum htt_cmn_pkt_type tx_encap_type; 3964 3965 /* Rx Decapsulation type for this VAP */ 3966 enum htt_cmn_pkt_type rx_decap_type; 3967 3968 /* WDS enabled */ 3969 bool wds_enabled; 3970 3971 /* MEC enabled */ 3972 bool mec_enabled; 3973 3974 #ifdef QCA_SUPPORT_WDS_EXTENDED 3975 bool wds_ext_enabled; 3976 bool drop_tx_mcast; 3977 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 3978 bool drop_3addr_mcast; 3979 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 3980 bool skip_bar_update; 3981 unsigned long skip_bar_update_last_ts; 3982 #endif 3983 /* WDS Aging timer period */ 3984 uint32_t wds_aging_timer_val; 3985 3986 /* NAWDS enabled */ 3987 bool nawds_enabled; 3988 3989 /* Multicast enhancement enabled */ 3990 uint8_t mcast_enhancement_en; 3991 3992 /* IGMP multicast enhancement enabled */ 3993 uint8_t igmp_mcast_enhanc_en; 3994 3995 /* vdev_id - ID used to specify a particular vdev to the target */ 3996 uint8_t vdev_id; 3997 3998 /* Default HTT meta data for this VDEV */ 3999 /* TBD: check alignment constraints */ 4000 uint16_t htt_tcl_metadata; 4001 4002 /* vdev lmac_id */ 4003 uint8_t lmac_id; 4004 4005 /* vdev bank_id */ 4006 uint8_t bank_id; 4007 4008 /* Mesh mode vdev */ 4009 uint32_t mesh_vdev; 4010 4011 /* Mesh mode rx filter setting */ 4012 uint32_t mesh_rx_filter; 4013 4014 /* DSCP-TID mapping table ID */ 4015 uint8_t dscp_tid_map_id; 4016 4017 /* Address search type to be set in TX descriptor */ 4018 uint8_t search_type; 4019 4020 /* 4021 * Flag to indicate if s/w tid classification should be 4022 * skipped 4023 */ 4024 uint8_t skip_sw_tid_classification; 4025 4026 /* Flag to enable peer authorization */ 4027 uint8_t peer_authorize; 4028 4029 /* AST hash value for BSS peer in HW valid for STA VAP*/ 4030 uint16_t bss_ast_hash; 4031 4032 /* AST hash index for BSS peer in HW valid for STA VAP*/ 4033 uint16_t bss_ast_idx; 4034 4035 bool multipass_en; 4036 4037 /* Address search flags to be configured in HAL descriptor */ 4038 uint8_t hal_desc_addr_search_flags; 4039 4040 /* Handle to the OS shim SW's virtual device */ 4041 ol_osif_vdev_handle osif_vdev; 4042 4043 /* MAC address */ 4044 union dp_align_mac_addr mac_addr; 4045 4046 #ifdef WLAN_FEATURE_11BE_MLO 4047 /* MLO MAC address corresponding to vdev */ 4048 union dp_align_mac_addr mld_mac_addr; 4049 #if defined(WLAN_MLO_MULTI_CHIP) && defined(WLAN_MCAST_MLO) 4050 uint8_t mlo_vdev:1, 4051 is_bridge_vdev:1, 4052 reserved_1:6; 4053 #endif 4054 #endif 4055 4056 /* node in the pdev's list of vdevs */ 4057 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 4058 4059 /* dp_peer list */ 4060 TAILQ_HEAD(, dp_peer) peer_list; 4061 /* to protect peer_list */ 4062 DP_MUTEX_TYPE peer_list_lock; 4063 4064 /* RX call back function to flush GRO packets*/ 4065 ol_txrx_rx_gro_flush_ind_fp osif_gro_flush; 4066 /* default RX call back function called by dp */ 4067 ol_txrx_rx_fp osif_rx; 4068 #ifdef QCA_SUPPORT_EAPOL_OVER_CONTROL_PORT 4069 /* callback to receive eapol frames */ 4070 ol_txrx_rx_fp osif_rx_eapol; 4071 #endif 4072 /* callback to deliver rx frames to the OS */ 4073 ol_txrx_rx_fp osif_rx_stack; 4074 /* Callback to handle rx fisa frames */ 4075 ol_txrx_fisa_rx_fp osif_fisa_rx; 4076 ol_txrx_fisa_flush_fp osif_fisa_flush; 4077 4078 /* call back function to flush out queued rx packets*/ 4079 ol_txrx_rx_flush_fp osif_rx_flush; 4080 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 4081 ol_txrx_get_key_fp osif_get_key; 4082 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 4083 4084 #ifdef notyet 4085 /* callback to check if the msdu is an WAI (WAPI) frame */ 4086 ol_rx_check_wai_fp osif_check_wai; 4087 #endif 4088 4089 /* proxy arp function */ 4090 ol_txrx_proxy_arp_fp osif_proxy_arp; 4091 4092 ol_txrx_mcast_me_fp me_convert; 4093 4094 /* completion function used by this vdev*/ 4095 ol_txrx_completion_fp tx_comp; 4096 4097 ol_txrx_get_tsf_time get_tsf_time; 4098 4099 /* callback to classify critical packets */ 4100 ol_txrx_classify_critical_pkt_fp tx_classify_critical_pkt_cb; 4101 4102 /* deferred vdev deletion state */ 4103 struct { 4104 /* VDEV delete pending */ 4105 int pending; 4106 /* 4107 * callback and a context argument to provide a 4108 * notification for when the vdev is deleted. 4109 */ 4110 ol_txrx_vdev_delete_cb callback; 4111 void *context; 4112 } delete; 4113 4114 /* tx data delivery notification callback function */ 4115 struct { 4116 ol_txrx_data_tx_cb func; 4117 void *ctxt; 4118 } tx_non_std_data_callback; 4119 4120 4121 /* safe mode control to bypass the encrypt and decipher process*/ 4122 uint32_t safemode; 4123 4124 /* rx filter related */ 4125 uint32_t drop_unenc; 4126 #ifdef notyet 4127 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 4128 uint32_t filters_num; 4129 #endif 4130 /* TDLS Link status */ 4131 bool tdls_link_connected; 4132 bool is_tdls_frame; 4133 4134 /* per vdev rx nbuf queue */ 4135 qdf_nbuf_queue_t rxq; 4136 4137 uint8_t tx_ring_id; 4138 struct dp_tx_desc_pool_s *tx_desc; 4139 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 4140 4141 /* Capture timestamp of previous tx packet enqueued */ 4142 uint64_t prev_tx_enq_tstamp; 4143 4144 /* Capture timestamp of previous rx packet delivered */ 4145 uint64_t prev_rx_deliver_tstamp; 4146 4147 /* VDEV Stats */ 4148 struct dp_vdev_stats stats; 4149 4150 /* Is this a proxySTA VAP */ 4151 uint8_t proxysta_vdev : 1, /* Is this a proxySTA VAP */ 4152 wrap_vdev : 1, /* Is this a QWRAP AP VAP */ 4153 isolation_vdev : 1, /* Is this a QWRAP AP VAP */ 4154 reserved : 5; /* Reserved */ 4155 4156 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 4157 struct dp_tx_desc_pool_s *pool; 4158 #endif 4159 /* AP BRIDGE enabled */ 4160 bool ap_bridge_enabled; 4161 4162 enum cdp_sec_type sec_type; 4163 4164 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 4165 bool raw_mode_war; 4166 4167 4168 /* 8021p PCP-TID mapping table ID */ 4169 uint8_t tidmap_tbl_id; 4170 4171 /* 8021p PCP-TID map values */ 4172 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 4173 4174 /* TIDmap priority */ 4175 uint8_t tidmap_prty; 4176 4177 #ifdef QCA_MULTIPASS_SUPPORT 4178 uint16_t *iv_vlan_map; 4179 4180 /* dp_peer special list */ 4181 TAILQ_HEAD(, dp_txrx_peer) mpass_peer_list; 4182 DP_MUTEX_TYPE mpass_peer_mutex; 4183 #endif 4184 /* Extended data path handle */ 4185 struct cdp_ext_vdev *vdev_dp_ext_handle; 4186 #ifdef VDEV_PEER_PROTOCOL_COUNT 4187 /* 4188 * Rx-Ingress and Tx-Egress are in the lower level DP layer 4189 * Rx-Egress and Tx-ingress are handled in osif layer for DP 4190 * So 4191 * Rx-Egress and Tx-ingress mask definitions are in OSIF layer 4192 * Rx-Ingress and Tx-Egress definitions are here below 4193 */ 4194 #define VDEV_PEER_PROTOCOL_RX_INGRESS_MASK 1 4195 #define VDEV_PEER_PROTOCOL_TX_INGRESS_MASK 2 4196 #define VDEV_PEER_PROTOCOL_RX_EGRESS_MASK 4 4197 #define VDEV_PEER_PROTOCOL_TX_EGRESS_MASK 8 4198 bool peer_protocol_count_track; 4199 int peer_protocol_count_dropmask; 4200 #endif 4201 /* callback to collect connectivity stats */ 4202 ol_txrx_stats_rx_fp stats_cb; 4203 uint32_t num_peers; 4204 /* entry to inactive_list*/ 4205 TAILQ_ENTRY(dp_vdev) inactive_list_elem; 4206 4207 #ifdef WLAN_SUPPORT_RX_FISA 4208 /** 4209 * Params used for controlling the fisa aggregation dynamically 4210 */ 4211 uint8_t fisa_disallowed[MAX_REO_DEST_RINGS]; 4212 uint8_t fisa_force_flushed[MAX_REO_DEST_RINGS]; 4213 #endif 4214 /* 4215 * Refcount for VDEV currently incremented when 4216 * peer is created for VDEV 4217 */ 4218 qdf_atomic_t ref_cnt; 4219 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 4220 uint8_t num_latency_critical_conn; 4221 #ifdef WLAN_SUPPORT_MESH_LATENCY 4222 uint8_t peer_tid_latency_enabled; 4223 /* tid latency configuration parameters */ 4224 struct { 4225 uint32_t service_interval; 4226 uint32_t burst_size; 4227 uint8_t latency_tid; 4228 } mesh_tid_latency_config; 4229 #endif 4230 #ifdef WIFI_MONITOR_SUPPORT 4231 struct dp_mon_vdev *monitor_vdev; 4232 #endif 4233 #if defined(WLAN_FEATURE_TSF_AUTO_REPORT) || defined(WLAN_CONFIG_TX_DELAY) 4234 /* Delta between TQM clock and TSF clock */ 4235 uint32_t delta_tsf; 4236 #endif 4237 #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY 4238 /* Indicate if uplink delay report is enabled or not */ 4239 qdf_atomic_t ul_delay_report; 4240 /* accumulative delay for every TX completion */ 4241 qdf_atomic_t ul_delay_accum; 4242 /* accumulative number of packets delay has accumulated */ 4243 qdf_atomic_t ul_pkts_accum; 4244 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */ 4245 4246 /* vdev_stats_id - ID used for stats collection by FW from HW*/ 4247 uint8_t vdev_stats_id; 4248 #ifdef HW_TX_DELAY_STATS_ENABLE 4249 /* hw tx delay stats enable */ 4250 uint8_t hw_tx_delay_stats_enabled; 4251 #endif 4252 #ifdef DP_RX_UDP_OVER_PEER_ROAM 4253 uint32_t roaming_peer_status; 4254 union dp_align_mac_addr roaming_peer_mac; 4255 #endif 4256 #ifdef DP_TRAFFIC_END_INDICATION 4257 /* per vdev feature enable/disable status */ 4258 bool traffic_end_ind_en; 4259 /* per vdev nbuf queue for traffic end indication packets */ 4260 qdf_nbuf_queue_t end_ind_pkt_q; 4261 #endif 4262 #ifdef FEATURE_DIRECT_LINK 4263 /* Flag to indicate if to_fw should be set for tx pkts on this vdev */ 4264 bool to_fw; 4265 #endif 4266 /* QDF VDEV operating mode */ 4267 enum QDF_OPMODE qdf_opmode; 4268 4269 #ifdef WLAN_TX_PKT_CAPTURE_ENH 4270 /* TX capture feature to over ride return buffer manager */ 4271 bool is_override_rbm_id; 4272 /* Return buffer manager ID */ 4273 uint8_t rbm_id; 4274 #endif 4275 4276 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 4277 /* configuration for tx latency stats */ 4278 struct dp_tx_latency_config tx_latency_cfg; 4279 #endif 4280 }; 4281 4282 enum { 4283 dp_sec_mcast = 0, 4284 dp_sec_ucast 4285 }; 4286 4287 #ifdef WDS_VENDOR_EXTENSION 4288 typedef struct { 4289 uint8_t wds_tx_mcast_4addr:1, 4290 wds_tx_ucast_4addr:1, 4291 wds_rx_filter:1, /* enforce rx filter */ 4292 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 4293 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 4294 4295 } dp_ecm_policy; 4296 #endif 4297 4298 /** 4299 * struct dp_peer_cached_bufq - cached_bufq to enqueue rx packets 4300 * @cached_bufq: nbuff list to enqueue rx packets 4301 * @bufq_lock: spinlock for nbuff list access 4302 * @thresh: maximum threshold for number of rx buff to enqueue 4303 * @entries: number of entries 4304 * @dropped: number of packets dropped 4305 */ 4306 struct dp_peer_cached_bufq { 4307 qdf_list_t cached_bufq; 4308 qdf_spinlock_t bufq_lock; 4309 uint32_t thresh; 4310 uint32_t entries; 4311 uint32_t dropped; 4312 }; 4313 4314 /** 4315 * enum dp_peer_ast_flowq 4316 * @DP_PEER_AST_FLOWQ_HI_PRIO: Hi Priority flow queue 4317 * @DP_PEER_AST_FLOWQ_LOW_PRIO: Low priority flow queue 4318 * @DP_PEER_AST_FLOWQ_UDP: flow queue type is UDP 4319 * @DP_PEER_AST_FLOWQ_NON_UDP: flow queue type is Non UDP 4320 * @DP_PEER_AST_FLOWQ_MAX: max value 4321 */ 4322 enum dp_peer_ast_flowq { 4323 DP_PEER_AST_FLOWQ_HI_PRIO, 4324 DP_PEER_AST_FLOWQ_LOW_PRIO, 4325 DP_PEER_AST_FLOWQ_UDP, 4326 DP_PEER_AST_FLOWQ_NON_UDP, 4327 DP_PEER_AST_FLOWQ_MAX, 4328 }; 4329 4330 /** 4331 * struct dp_ast_flow_override_info - ast override info 4332 * @ast_idx: ast indexes in peer map message 4333 * @ast_valid_mask: ast valid mask for each ast index 4334 * @ast_flow_mask: ast flow mask for each ast index 4335 * @tid_valid_low_pri_mask: per tid mask for low priority flow 4336 * @tid_valid_hi_pri_mask: per tid mask for hi priority flow 4337 */ 4338 struct dp_ast_flow_override_info { 4339 uint16_t ast_idx[DP_PEER_AST_FLOWQ_MAX]; 4340 uint8_t ast_valid_mask; 4341 uint8_t ast_flow_mask[DP_PEER_AST_FLOWQ_MAX]; 4342 uint8_t tid_valid_low_pri_mask; 4343 uint8_t tid_valid_hi_pri_mask; 4344 }; 4345 4346 #if defined(WLAN_FEATURE_11BE_MLO) && defined(DP_MLO_LINK_STATS_SUPPORT) 4347 /** 4348 * struct dp_peer_ext_evt_info - peer extended event info 4349 * @peer_id: peer_id from firmware 4350 * @vdev_id: vdev ID 4351 * @link_id: Link ID 4352 * @link_id_valid: link_id_valid 4353 * @peer_mac_addr: mac address of the peer 4354 */ 4355 struct dp_peer_ext_evt_info { 4356 uint16_t peer_id; 4357 uint8_t vdev_id; 4358 uint8_t link_id; 4359 bool link_id_valid; 4360 uint8_t *peer_mac_addr; 4361 }; 4362 #endif 4363 4364 /** 4365 * struct dp_peer_ast_params - ast parameters for a msdu flow-queue 4366 * @ast_idx: ast index populated by FW 4367 * @is_valid: ast flow valid mask 4368 * @valid_tid_mask: per tid mask for this ast index 4369 * @flowQ: flow queue id associated with this ast index 4370 */ 4371 struct dp_peer_ast_params { 4372 uint16_t ast_idx; 4373 uint8_t is_valid; 4374 uint8_t valid_tid_mask; 4375 uint8_t flowQ; 4376 }; 4377 4378 #define DP_MLO_FLOW_INFO_MAX 3 4379 4380 /** 4381 * struct dp_mlo_flow_override_info - Flow override info 4382 * @ast_idx: Primary TCL AST Index 4383 * @ast_idx_valid: Is AST index valid 4384 * @chip_id: CHIP ID 4385 * @tidmask: tidmask 4386 * @cache_set_num: Cache set number 4387 */ 4388 struct dp_mlo_flow_override_info { 4389 uint16_t ast_idx; 4390 uint8_t ast_idx_valid; 4391 uint8_t chip_id; 4392 uint8_t tidmask; 4393 uint8_t cache_set_num; 4394 }; 4395 4396 /** 4397 * struct dp_mlo_link_info - Link info 4398 * @peer_chip_id: Peer Chip ID 4399 * @vdev_id: Vdev ID 4400 */ 4401 struct dp_mlo_link_info { 4402 uint8_t peer_chip_id; 4403 uint8_t vdev_id; 4404 }; 4405 4406 #ifdef WLAN_SUPPORT_MSCS 4407 /*MSCS Procedure based macros */ 4408 #define IEEE80211_MSCS_MAX_ELEM_SIZE 5 4409 #define IEEE80211_TCLAS_MASK_CLA_TYPE_4 4 4410 /** 4411 * struct dp_peer_mscs_parameter - MSCS database obtained from 4412 * MSCS Request and Response in the control path. This data is used 4413 * by the AP to find out what priority to set based on the tuple 4414 * classification during packet processing. 4415 * @user_priority_bitmap: User priority bitmap obtained during 4416 * handshake 4417 * @user_priority_limit: User priority limit obtained during 4418 * handshake 4419 * @classifier_mask: params to be compared during processing 4420 */ 4421 struct dp_peer_mscs_parameter { 4422 uint8_t user_priority_bitmap; 4423 uint8_t user_priority_limit; 4424 uint8_t classifier_mask; 4425 }; 4426 #endif 4427 4428 #ifdef QCA_SUPPORT_WDS_EXTENDED 4429 #define WDS_EXT_PEER_INIT_BIT 0 4430 4431 /** 4432 * struct dp_wds_ext_peer - wds ext peer structure 4433 * This is used when wds extended feature is enabled 4434 * both compile time and run time. It is created 4435 * when 1st 4 address frame is received from 4436 * wds backhaul. 4437 * @osif_peer: Handle to the OS shim SW's virtual device 4438 * @init: wds ext netdev state 4439 */ 4440 struct dp_wds_ext_peer { 4441 ol_osif_peer_handle osif_peer; 4442 unsigned long init; 4443 }; 4444 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 4445 4446 #ifdef WLAN_SUPPORT_MESH_LATENCY 4447 /*Advanced Mesh latency feature based macros */ 4448 4449 /** 4450 * struct dp_peer_mesh_latency_parameter - Mesh latency related 4451 * parameters. This data is updated per peer per TID based on 4452 * the flow tuple classification in external rule database 4453 * during packet processing. 4454 * @service_interval_dl: Service interval associated with TID in DL 4455 * @burst_size_dl: Burst size additive over multiple flows in DL 4456 * @service_interval_ul: Service interval associated with TID in UL 4457 * @burst_size_ul: Burst size additive over multiple flows in UL 4458 * @ac: custom ac derived from service interval 4459 * @msduq: MSDU queue number within TID 4460 */ 4461 struct dp_peer_mesh_latency_parameter { 4462 uint32_t service_interval_dl; 4463 uint32_t burst_size_dl; 4464 uint32_t service_interval_ul; 4465 uint32_t burst_size_ul; 4466 uint8_t ac; 4467 uint8_t msduq; 4468 }; 4469 #endif 4470 4471 #ifdef WLAN_FEATURE_11BE_MLO 4472 /* Max number of links for MLO connection */ 4473 #define DP_MAX_MLO_LINKS 4 4474 4475 /** 4476 * struct dp_peer_link_info - link peer information for MLO 4477 * @mac_addr: Mac address 4478 * @vdev_id: Vdev ID for current link peer 4479 * @is_valid: flag for link peer info valid or not 4480 * @chip_id: chip id 4481 * @is_bridge_peer: flag to indicate if peer is bridge peer 4482 */ 4483 struct dp_peer_link_info { 4484 union dp_align_mac_addr mac_addr; 4485 uint8_t vdev_id; 4486 uint8_t is_valid; 4487 uint8_t chip_id; 4488 uint8_t is_bridge_peer; 4489 }; 4490 4491 /** 4492 * struct dp_mld_link_peers - this structure is used to get link peers 4493 * pointer from mld peer 4494 * @link_peers: link peers pointer array 4495 * @num_links: number of link peers fetched 4496 */ 4497 struct dp_mld_link_peers { 4498 struct dp_peer *link_peers[DP_MAX_MLO_LINKS]; 4499 uint8_t num_links; 4500 }; 4501 #else 4502 #define DP_MAX_MLO_LINKS 0 4503 #endif 4504 4505 typedef void *dp_txrx_ref_handle; 4506 4507 /** 4508 * struct dp_peer_per_pkt_tx_stats- Peer Tx stats updated in per pkt 4509 * Tx completion path 4510 * @ucast: Unicast Packet Count 4511 * @mcast: Multicast Packet Count 4512 * @bcast: Broadcast Packet Count 4513 * @nawds_mcast: NAWDS Multicast Packet Count 4514 * @tx_success: Successful Tx Packets 4515 * @nawds_mcast_drop: NAWDS Multicast Drop Count 4516 * @ofdma: Total Packets as ofdma 4517 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 4518 * @amsdu_cnt: Number of MSDUs part of AMSDU 4519 * @dropped: Dropped packet statistics 4520 * @dropped.fw_rem: Discarded by firmware 4521 * @dropped.fw_rem_notx: firmware_discard_untransmitted 4522 * @dropped.fw_rem_tx: firmware_discard_transmitted 4523 * @dropped.age_out: aged out in mpdu/msdu queues 4524 * @dropped.fw_reason1: discarded by firmware reason 1 4525 * @dropped.fw_reason2: discarded by firmware reason 2 4526 * @dropped.fw_reason3: discarded by firmware reason 3 4527 * @dropped.fw_rem_no_match: dropped due to fw no match command 4528 * @dropped.drop_threshold: dropped due to HW threshold 4529 * @dropped.drop_link_desc_na: dropped due resource not available in HW 4530 * @dropped.invalid_drop: Invalid msdu drop 4531 * @dropped.mcast_vdev_drop: MCAST drop configured for VDEV in HW 4532 * @dropped.invalid_rr: Invalid TQM release reason 4533 * @failed_retry_count: packets failed due to retry above 802.11 retry limit 4534 * @retry_count: packets successfully send after one or more retry 4535 * @multiple_retry_count: packets successfully sent after more than one retry 4536 * @no_ack_count: no ack pkt count for different protocols 4537 * @tx_success_twt: Successful Tx Packets in TWT session 4538 * @last_tx_ts: last timestamp in jiffies when tx comp occurred 4539 * @avg_sojourn_msdu: Avg sojourn msdu stat 4540 * @protocol_trace_cnt: per-peer protocol counter 4541 * @release_src_not_tqm: Counter to keep track of release source is not TQM 4542 * in TX completion status processing 4543 * @inval_link_id_pkt_cnt: Counter to capture Invalid Link Id 4544 */ 4545 struct dp_peer_per_pkt_tx_stats { 4546 struct cdp_pkt_info ucast; 4547 struct cdp_pkt_info mcast; 4548 struct cdp_pkt_info bcast; 4549 struct cdp_pkt_info nawds_mcast; 4550 struct cdp_pkt_info tx_success; 4551 uint32_t nawds_mcast_drop; 4552 uint32_t ofdma; 4553 uint32_t non_amsdu_cnt; 4554 uint32_t amsdu_cnt; 4555 struct { 4556 struct cdp_pkt_info fw_rem; 4557 uint32_t fw_rem_notx; 4558 uint32_t fw_rem_tx; 4559 uint32_t age_out; 4560 uint32_t fw_reason1; 4561 uint32_t fw_reason2; 4562 uint32_t fw_reason3; 4563 uint32_t fw_rem_queue_disable; 4564 uint32_t fw_rem_no_match; 4565 uint32_t drop_threshold; 4566 uint32_t drop_link_desc_na; 4567 uint32_t invalid_drop; 4568 uint32_t mcast_vdev_drop; 4569 uint32_t invalid_rr; 4570 } dropped; 4571 uint32_t failed_retry_count; 4572 uint32_t retry_count; 4573 uint32_t multiple_retry_count; 4574 uint32_t no_ack_count[QDF_PROTO_SUBTYPE_MAX]; 4575 struct cdp_pkt_info tx_success_twt; 4576 unsigned long last_tx_ts; 4577 qdf_ewma_tx_lag avg_sojourn_msdu[CDP_DATA_TID_MAX]; 4578 #ifdef VDEV_PEER_PROTOCOL_COUNT 4579 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 4580 #endif 4581 uint32_t release_src_not_tqm; 4582 uint32_t inval_link_id_pkt_cnt; 4583 }; 4584 4585 /** 4586 * struct dp_peer_extd_tx_stats - Peer Tx stats updated in either 4587 * per pkt Tx completion path when macro QCA_ENHANCED_STATS_SUPPORT is 4588 * disabled or in HTT Tx PPDU completion path when macro is enabled 4589 * @stbc: Packets in STBC 4590 * @ldpc: Packets in LDPC 4591 * @retries: Packet retries 4592 * @pkt_type: pkt count for different .11 modes 4593 * @wme_ac_type: Wireless Multimedia type Count 4594 * @excess_retries_per_ac: Wireless Multimedia type Count 4595 * @ampdu_cnt: completion of aggregation 4596 * @non_ampdu_cnt: tx completion not aggregated 4597 * @num_ppdu_cookie_valid: no. of valid ppdu cookies rcvd from FW 4598 * @tx_ppdus: ppdus in tx 4599 * @tx_mpdus_success: mpdus successful in tx 4600 * @tx_mpdus_tried: mpdus tried in tx 4601 * @tx_rate: Tx Rate in kbps 4602 * @last_tx_rate: Last tx rate for unicast packets 4603 * @last_tx_rate_mcs: Tx rate mcs for unicast packets 4604 * @mcast_last_tx_rate: Last tx rate for multicast packets 4605 * @mcast_last_tx_rate_mcs: Last tx rate mcs for multicast 4606 * @rnd_avg_tx_rate: Rounded average tx rate 4607 * @avg_tx_rate: Average TX rate 4608 * @tx_ratecode: Tx rate code of last frame 4609 * @pream_punct_cnt: Preamble Punctured count 4610 * @sgi_count: SGI count 4611 * @nss: Packet count for different num_spatial_stream values 4612 * @bw: Packet Count for different bandwidths 4613 * @ru_start: RU start index 4614 * @ru_tones: RU tones size 4615 * @ru_loc: pkt info for RU location 26/ 52/ 106/ 242/ 484 counter 4616 * @transmit_type: pkt info for tx transmit type 4617 * @mu_group_id: mumimo mu group id 4618 * @last_ack_rssi: RSSI of last acked packet 4619 * @nss_info: NSS 1,2, ...8 4620 * @mcs_info: MCS index 4621 * @bw_info: Bandwidth 4622 * <enum 0 bw_20_MHz> 4623 * <enum 1 bw_40_MHz> 4624 * <enum 2 bw_80_MHz> 4625 * <enum 3 bw_160_MHz> 4626 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 4627 * <enum 1 0_4_us_sgi > Legacy short GI 4628 * <enum 2 1_6_us_sgi > HE related GI 4629 * <enum 3 3_2_us_sgi > HE 4630 * @preamble_info: preamble 4631 * @tx_ucast_total: total ucast count 4632 * @tx_ucast_success: total ucast success count 4633 * @retries_mpdu: mpdu number of successfully transmitted after retries 4634 * @mpdu_success_with_retries: mpdu retry count in case of successful tx 4635 * @su_be_ppdu_cnt: SU Tx packet count for 11BE 4636 * @mu_be_ppdu_cnt: MU Tx packet count for 11BE 4637 * @punc_bw: MSDU count for punctured bw 4638 * @rts_success: RTS success count 4639 * @rts_failure: RTS failure count 4640 * @bar_cnt: Block ACK Request frame count 4641 * @ndpa_cnt: NDP announcement frame count 4642 * @rssi_chain: rssi chain 4643 * @wme_ac_type_bytes: Wireless Multimedia bytes Count 4644 */ 4645 struct dp_peer_extd_tx_stats { 4646 uint32_t stbc; 4647 uint32_t ldpc; 4648 uint32_t retries; 4649 struct cdp_pkt_type pkt_type[DOT11_MAX]; 4650 uint32_t wme_ac_type[WME_AC_MAX]; 4651 uint32_t excess_retries_per_ac[WME_AC_MAX]; 4652 uint32_t ampdu_cnt; 4653 uint32_t non_ampdu_cnt; 4654 uint32_t num_ppdu_cookie_valid; 4655 uint32_t tx_ppdus; 4656 uint32_t tx_mpdus_success; 4657 uint32_t tx_mpdus_tried; 4658 4659 uint32_t tx_rate; 4660 uint32_t last_tx_rate; 4661 uint32_t last_tx_rate_mcs; 4662 uint32_t mcast_last_tx_rate; 4663 uint32_t mcast_last_tx_rate_mcs; 4664 uint64_t rnd_avg_tx_rate; 4665 uint64_t avg_tx_rate; 4666 uint16_t tx_ratecode; 4667 4668 uint32_t sgi_count[MAX_GI]; 4669 uint32_t pream_punct_cnt; 4670 uint32_t nss[SS_COUNT]; 4671 uint32_t bw[MAX_BW]; 4672 uint32_t ru_start; 4673 uint32_t ru_tones; 4674 struct cdp_tx_pkt_info ru_loc[MAX_RU_LOCATIONS]; 4675 4676 struct cdp_tx_pkt_info transmit_type[MAX_TRANSMIT_TYPES]; 4677 uint32_t mu_group_id[MAX_MU_GROUP_ID]; 4678 4679 uint32_t last_ack_rssi; 4680 4681 uint32_t nss_info:4, 4682 mcs_info:4, 4683 bw_info:4, 4684 gi_info:4, 4685 preamble_info:4; 4686 4687 uint32_t retries_mpdu; 4688 uint32_t mpdu_success_with_retries; 4689 struct cdp_pkt_info tx_ucast_total; 4690 struct cdp_pkt_info tx_ucast_success; 4691 #ifdef WLAN_FEATURE_11BE 4692 struct cdp_pkt_type su_be_ppdu_cnt; 4693 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 4694 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 4695 #endif 4696 uint32_t rts_success; 4697 uint32_t rts_failure; 4698 uint32_t bar_cnt; 4699 uint32_t ndpa_cnt; 4700 int32_t rssi_chain[CDP_RSSI_CHAIN_LEN]; 4701 uint64_t wme_ac_type_bytes[WME_AC_MAX]; 4702 }; 4703 4704 /** 4705 * struct dp_peer_per_pkt_rx_stats - Peer Rx stats updated in per pkt Rx path 4706 * @rcvd_reo: Packets received on the reo ring 4707 * @rx_lmac: Packets received on each lmac 4708 * @unicast: Total unicast packets 4709 * @multicast: Total multicast packets 4710 * @bcast: Broadcast Packet Count 4711 * @raw: Raw Pakets received 4712 * @nawds_mcast_drop: Total NAWDS multicast packets dropped 4713 * @mec_drop: Total MEC packets dropped 4714 * @ppeds_drop: Total DS packets dropped 4715 * @last_rx_ts: last timestamp in jiffies when RX happened 4716 * @intra_bss: Intra BSS statistics 4717 * @intra_bss.pkts: Intra BSS packets received 4718 * @intra_bss.fail: Intra BSS packets failed 4719 * @intra_bss.mdns_no_fws: Intra BSS MDNS packets not forwarded 4720 * @err: error counters 4721 * @err.mic_err: Rx MIC errors CCMP 4722 * @err.decrypt_err: Rx Decryption Errors CRC 4723 * @err.fcserr: rx MIC check failed (CCMP) 4724 * @err.pn_err: pn check failed 4725 * @err.oor_err: Rx OOR errors 4726 * @err.jump_2k_err: 2k jump errors 4727 * @err.rxdma_wifi_parse_err: rxdma wifi parse errors 4728 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 4729 * @amsdu_cnt: Number of MSDUs part of AMSDU 4730 * @rx_retries: retries of packet in rx 4731 * @multipass_rx_pkt_drop: Dropped multipass rx pkt 4732 * @peer_unauth_rx_pkt_drop: Unauth rx packet drops 4733 * @policy_check_drop: policy check drops 4734 * @to_stack_twt: Total packets sent up the stack in TWT session 4735 * @rx_success: Total RX success count 4736 * @protocol_trace_cnt: per-peer protocol counters 4737 * @mcast_3addr_drop: 4738 * @rx_total: total rx count 4739 * @inval_link_id_pkt_cnt: Counter to capture Invalid Link Id 4740 */ 4741 struct dp_peer_per_pkt_rx_stats { 4742 struct cdp_pkt_info rcvd_reo[CDP_MAX_RX_RINGS]; 4743 struct cdp_pkt_info rx_lmac[CDP_MAX_LMACS]; 4744 struct cdp_pkt_info unicast; 4745 struct cdp_pkt_info multicast; 4746 struct cdp_pkt_info bcast; 4747 struct cdp_pkt_info raw; 4748 uint32_t nawds_mcast_drop; 4749 struct cdp_pkt_info mec_drop; 4750 struct cdp_pkt_info ppeds_drop; 4751 unsigned long last_rx_ts; 4752 struct { 4753 struct cdp_pkt_info pkts; 4754 struct cdp_pkt_info fail; 4755 uint32_t mdns_no_fwd; 4756 } intra_bss; 4757 struct { 4758 uint32_t mic_err; 4759 uint32_t decrypt_err; 4760 uint32_t fcserr; 4761 uint32_t pn_err; 4762 uint32_t oor_err; 4763 uint32_t jump_2k_err; 4764 uint32_t rxdma_wifi_parse_err; 4765 } err; 4766 uint32_t non_amsdu_cnt; 4767 uint32_t amsdu_cnt; 4768 uint32_t rx_retries; 4769 uint32_t multipass_rx_pkt_drop; 4770 uint32_t peer_unauth_rx_pkt_drop; 4771 uint32_t policy_check_drop; 4772 struct cdp_pkt_info to_stack_twt; 4773 struct cdp_pkt_info rx_success; 4774 #ifdef VDEV_PEER_PROTOCOL_COUNT 4775 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 4776 #endif 4777 uint32_t mcast_3addr_drop; 4778 #ifdef IPA_OFFLOAD 4779 struct cdp_pkt_info rx_total; 4780 #endif 4781 uint32_t inval_link_id_pkt_cnt; 4782 }; 4783 4784 /** 4785 * struct dp_peer_extd_rx_stats - Peer Rx stats updated in either 4786 * per pkt Rx path when macro QCA_ENHANCED_STATS_SUPPORT is disabled or in 4787 * Rx monitor patch when macro is enabled 4788 * @pkt_type: pkt counter for different .11 modes 4789 * @wme_ac_type: Wireless Multimedia type Count 4790 * @mpdu_cnt_fcs_ok: SU Rx success mpdu count 4791 * @mpdu_cnt_fcs_err: SU Rx fail mpdu count 4792 * @non_ampdu_cnt: Number of MSDUs with no MPDU level aggregation 4793 * @ampdu_cnt: Number of MSDUs part of AMSPU 4794 * @rx_mpdus: mpdu in rx 4795 * @rx_ppdus: ppdu in rx 4796 * @su_ax_ppdu_cnt: SU Rx packet count for .11ax 4797 * @rx_mu: Rx MU stats 4798 * @reception_type: Reception type of packets 4799 * @ppdu_cnt: PPDU packet count in reception type 4800 * @sgi_count: sgi count 4801 * @nss: packet count in spatiel Streams 4802 * @ppdu_nss: PPDU packet count in spatial streams 4803 * @bw: Packet Count in different bandwidths 4804 * @rx_mpdu_cnt: rx mpdu count per MCS rate 4805 * @rx_rate: Rx rate 4806 * @last_rx_rate: Previous rx rate 4807 * @rnd_avg_rx_rate: Rounded average rx rate 4808 * @avg_rx_rate: Average Rx rate 4809 * @rx_ratecode: Rx rate code of last frame 4810 * @avg_snr: Average snr 4811 * @rx_snr_measured_time: Time at which snr is measured 4812 * @snr: SNR of received signal 4813 * @last_snr: Previous snr 4814 * @nss_info: NSS 1,2, ...8 4815 * @mcs_info: MCS index 4816 * @bw_info: Bandwidth 4817 * <enum 0 bw_20_MHz> 4818 * <enum 1 bw_40_MHz> 4819 * <enum 2 bw_80_MHz> 4820 * <enum 3 bw_160_MHz> 4821 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 4822 * <enum 1 0_4_us_sgi > Legacy short GI 4823 * <enum 2 1_6_us_sgi > HE related GI 4824 * <enum 3 3_2_us_sgi > HE 4825 * @preamble_info: preamble 4826 * @mpdu_retry_cnt: retries of mpdu in rx 4827 * @su_be_ppdu_cnt: SU Rx packet count for BE 4828 * @mu_be_ppdu_cnt: MU rx packet count for BE 4829 * @punc_bw: MSDU count for punctured bw 4830 * @bar_cnt: Block ACK Request frame count 4831 * @ndpa_cnt: NDP announcement frame count 4832 * @wme_ac_type_bytes: Wireless Multimedia type Bytes Count 4833 */ 4834 struct dp_peer_extd_rx_stats { 4835 struct cdp_pkt_type pkt_type[DOT11_MAX]; 4836 uint32_t wme_ac_type[WME_AC_MAX]; 4837 uint32_t mpdu_cnt_fcs_ok; 4838 uint32_t mpdu_cnt_fcs_err; 4839 uint32_t non_ampdu_cnt; 4840 uint32_t ampdu_cnt; 4841 uint32_t rx_mpdus; 4842 uint32_t rx_ppdus; 4843 4844 struct cdp_pkt_type su_ax_ppdu_cnt; 4845 struct cdp_rx_mu rx_mu[TXRX_TYPE_MU_MAX]; 4846 uint32_t reception_type[MAX_RECEPTION_TYPES]; 4847 uint32_t ppdu_cnt[MAX_RECEPTION_TYPES]; 4848 4849 uint32_t sgi_count[MAX_GI]; 4850 uint32_t nss[SS_COUNT]; 4851 uint32_t ppdu_nss[SS_COUNT]; 4852 uint32_t bw[MAX_BW]; 4853 uint32_t rx_mpdu_cnt[MAX_MCS]; 4854 4855 uint32_t rx_rate; 4856 uint32_t last_rx_rate; 4857 uint32_t rnd_avg_rx_rate; 4858 uint32_t avg_rx_rate; 4859 uint32_t rx_ratecode; 4860 4861 uint32_t avg_snr; 4862 unsigned long rx_snr_measured_time; 4863 uint8_t snr; 4864 uint8_t last_snr; 4865 4866 uint32_t nss_info:4, 4867 mcs_info:4, 4868 bw_info:4, 4869 gi_info:4, 4870 preamble_info:4; 4871 4872 uint32_t mpdu_retry_cnt; 4873 #ifdef WLAN_FEATURE_11BE 4874 struct cdp_pkt_type su_be_ppdu_cnt; 4875 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 4876 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 4877 #endif 4878 uint32_t bar_cnt; 4879 uint32_t ndpa_cnt; 4880 uint64_t wme_ac_type_bytes[WME_AC_MAX]; 4881 }; 4882 4883 /** 4884 * struct dp_peer_per_pkt_stats - Per pkt stats for peer 4885 * @tx: Per pkt Tx stats 4886 * @rx: Per pkt Rx stats 4887 */ 4888 struct dp_peer_per_pkt_stats { 4889 struct dp_peer_per_pkt_tx_stats tx; 4890 struct dp_peer_per_pkt_rx_stats rx; 4891 }; 4892 4893 /** 4894 * struct dp_peer_extd_stats - Stats from extended path for peer 4895 * @tx: Extended path tx stats 4896 * @rx: Extended path rx stats 4897 */ 4898 struct dp_peer_extd_stats { 4899 struct dp_peer_extd_tx_stats tx; 4900 struct dp_peer_extd_rx_stats rx; 4901 }; 4902 4903 /** 4904 * struct dp_peer_stats - Peer stats 4905 * @per_pkt_stats: Per packet path stats 4906 * @extd_stats: Extended path stats 4907 * @tx_latency: transmit latency stats 4908 */ 4909 struct dp_peer_stats { 4910 struct dp_peer_per_pkt_stats per_pkt_stats; 4911 #ifndef QCA_ENHANCED_STATS_SUPPORT 4912 struct dp_peer_extd_stats extd_stats; 4913 #endif 4914 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 4915 struct dp_tx_latency tx_latency; 4916 #endif 4917 }; 4918 4919 /** 4920 * struct dp_local_link_id_peer_map - Mapping table entry for link peer mac 4921 * address to local_link_id 4922 * @in_use: set if this entry is having valid mapping between local_link_id 4923 * and the link peer mac address. 4924 * @local_link_id: local_link_id assigned to the link peer 4925 * @mac_addr: link peer mac address 4926 */ 4927 struct dp_local_link_id_peer_map { 4928 uint8_t in_use; 4929 uint8_t local_link_id; 4930 union dp_align_mac_addr mac_addr; 4931 }; 4932 4933 /** 4934 * struct dp_txrx_peer: DP txrx_peer structure used in per pkt path 4935 * @vdev: VDEV to which this peer is associated 4936 * @peer_id: peer ID for this peer 4937 * @authorize: Set when authorized 4938 * @in_twt: in TWT session 4939 * @hw_txrx_stats_en: Indicate HW offload vdev stats 4940 * @is_mld_peer:1: MLD peer 4941 * @tx_failed: Total Tx failure 4942 * @comp_pkt: Pkt Info for which completions were received 4943 * @to_stack: Total packets sent up the stack 4944 * @delay_stats: Peer delay stats 4945 * @jitter_stats: Peer jitter stats 4946 * @security: Security credentials 4947 * @nawds_enabled: NAWDS flag 4948 * @bss_peer: set for bss peer 4949 * @isolation: enable peer isolation for this peer 4950 * @wds_enabled: WDS peer 4951 * @wds_ecm: 4952 * @flush_in_progress: 4953 * @bufq_info: 4954 * @mpass_peer_list_elem: node in the special peer list element 4955 * @vlan_id: vlan id for key 4956 * @wds_ext: 4957 * @osif_rx: 4958 * @rx_tid: 4959 * @sawf_stats: 4960 * @bw: bandwidth of peer connection 4961 * @mpdu_retry_threshold: MPDU retry threshold to increment tx bad count 4962 * @band: Link ID to band mapping 4963 * @ll_id_peer_map: Mapping table for link peer mac address to local_link_id 4964 * @ll_band: Local link id band mapping 4965 * @stats_arr_size: peer stats array size 4966 * @stats: Peer link and mld statistics 4967 */ 4968 struct dp_txrx_peer { 4969 struct dp_vdev *vdev; 4970 uint16_t peer_id; 4971 uint8_t authorize:1, 4972 in_twt:1, 4973 hw_txrx_stats_en:1, 4974 is_mld_peer:1; 4975 uint32_t tx_failed; 4976 struct cdp_pkt_info comp_pkt; 4977 struct cdp_pkt_info to_stack; 4978 4979 struct dp_peer_delay_stats *delay_stats; 4980 4981 struct cdp_peer_tid_stats *jitter_stats; 4982 4983 struct { 4984 enum cdp_sec_type sec_type; 4985 u_int32_t michael_key[2]; /* relevant for TKIP */ 4986 } security[2]; /* 0 -> multicast, 1 -> unicast */ 4987 4988 uint16_t nawds_enabled:1, 4989 bss_peer:1, 4990 isolation:1, 4991 wds_enabled:1; 4992 #ifdef WDS_VENDOR_EXTENSION 4993 dp_ecm_policy wds_ecm; 4994 #endif 4995 #ifdef PEER_CACHE_RX_PKTS 4996 qdf_atomic_t flush_in_progress; 4997 struct dp_peer_cached_bufq bufq_info; 4998 #endif 4999 #ifdef QCA_MULTIPASS_SUPPORT 5000 TAILQ_ENTRY(dp_txrx_peer) mpass_peer_list_elem; 5001 uint16_t vlan_id; 5002 #endif 5003 #ifdef QCA_SUPPORT_WDS_EXTENDED 5004 struct dp_wds_ext_peer wds_ext; 5005 ol_txrx_rx_fp osif_rx; 5006 #endif 5007 struct dp_rx_tid_defrag rx_tid[DP_MAX_TIDS]; 5008 #ifdef CONFIG_SAWF 5009 struct dp_peer_sawf_stats *sawf_stats; 5010 #endif 5011 #ifdef DP_PEER_EXTENDED_API 5012 enum cdp_peer_bw bw; 5013 uint8_t mpdu_retry_threshold; 5014 #endif 5015 #if defined WLAN_FEATURE_11BE_MLO && defined DP_MLO_LINK_STATS_SUPPORT 5016 /* Link ID to band mapping, (1 MLD + DP_MAX_MLO_LINKS) */ 5017 uint8_t band[DP_MAX_MLO_LINKS + 1]; 5018 5019 struct dp_local_link_id_peer_map ll_id_peer_map[DP_MAX_MLO_LINKS]; 5020 uint8_t ll_band[DP_MAX_MLO_LINKS + 1]; 5021 #endif 5022 uint8_t stats_arr_size; 5023 5024 /* dp_peer_stats should be the last member in the structure */ 5025 struct dp_peer_stats stats[]; 5026 }; 5027 5028 /* Peer structure for data path state */ 5029 struct dp_peer { 5030 struct dp_txrx_peer *txrx_peer; 5031 #ifdef WIFI_MONITOR_SUPPORT 5032 struct dp_mon_peer *monitor_peer; 5033 #endif 5034 /* peer ID for this peer */ 5035 uint16_t peer_id; 5036 5037 /* VDEV to which this peer is associated */ 5038 struct dp_vdev *vdev; 5039 5040 struct dp_ast_entry *self_ast_entry; 5041 5042 qdf_atomic_t ref_cnt; 5043 5044 union dp_align_mac_addr mac_addr; 5045 5046 /* node in the vdev's list of peers */ 5047 TAILQ_ENTRY(dp_peer) peer_list_elem; 5048 /* node in the hash table bin's list of peers */ 5049 TAILQ_ENTRY(dp_peer) hash_list_elem; 5050 5051 /* TID structures pointer */ 5052 struct dp_rx_tid *rx_tid; 5053 5054 /* TBD: No transmit TID state required? */ 5055 5056 struct { 5057 enum cdp_sec_type sec_type; 5058 u_int32_t michael_key[2]; /* relevant for TKIP */ 5059 } security[2]; /* 0 -> multicast, 1 -> unicast */ 5060 5061 /* NAWDS Flag and Bss Peer bit */ 5062 uint16_t bss_peer:1, /* set for bss peer */ 5063 authorize:1, /* Set when authorized */ 5064 valid:1, /* valid bit */ 5065 delete_in_progress:1, /* Indicate kickout sent */ 5066 sta_self_peer:1, /* Indicate STA self peer */ 5067 is_tdls_peer:1; /* Indicate TDLS peer */ 5068 5069 #ifdef WLAN_FEATURE_11BE_MLO 5070 uint8_t first_link:1, /* first link peer for MLO */ 5071 primary_link:1; /* primary link for MLO */ 5072 #endif 5073 5074 /* MCL specific peer local id */ 5075 uint16_t local_id; 5076 enum ol_txrx_peer_state state; 5077 qdf_spinlock_t peer_info_lock; 5078 5079 /* Peer calibrated stats */ 5080 struct cdp_calibr_stats stats; 5081 5082 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 5083 /* TBD */ 5084 5085 /* Active Block ack sessions */ 5086 uint16_t active_ba_session_cnt; 5087 5088 /* Current HW buffersize setting */ 5089 uint16_t hw_buffer_size; 5090 5091 /* 5092 * Flag to check if sessions with 256 buffersize 5093 * should be terminated. 5094 */ 5095 uint8_t kill_256_sessions; 5096 qdf_atomic_t is_default_route_set; 5097 5098 #ifdef QCA_PEER_MULTIQ_SUPPORT 5099 struct dp_peer_ast_params peer_ast_flowq_idx[DP_PEER_AST_FLOWQ_MAX]; 5100 #endif 5101 /* entry to inactive_list*/ 5102 TAILQ_ENTRY(dp_peer) inactive_list_elem; 5103 5104 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 5105 5106 uint8_t peer_state; 5107 qdf_spinlock_t peer_state_lock; 5108 #ifdef WLAN_SUPPORT_MSCS 5109 struct dp_peer_mscs_parameter mscs_ipv4_parameter, mscs_ipv6_parameter; 5110 bool mscs_active; 5111 #endif 5112 #ifdef WLAN_SUPPORT_MESH_LATENCY 5113 struct dp_peer_mesh_latency_parameter mesh_latency_params[DP_MAX_TIDS]; 5114 #endif 5115 #ifdef WLAN_FEATURE_11BE_MLO 5116 /* peer type */ 5117 enum cdp_peer_type peer_type; 5118 /*---------for link peer---------*/ 5119 struct dp_peer *mld_peer; 5120 5121 /*Link ID of link peer*/ 5122 uint8_t link_id; 5123 bool link_id_valid; 5124 uint8_t local_link_id; 5125 5126 /*---------for mld peer----------*/ 5127 struct dp_peer_link_info link_peers[DP_MAX_MLO_LINKS]; 5128 uint8_t num_links; 5129 DP_MUTEX_TYPE link_peers_info_lock; 5130 #ifdef WLAN_FEATURE_11BE_MLO_3_LINK_TX 5131 uint32_t flow_cnt[CDP_DATA_TID_MAX]; 5132 #endif 5133 #endif 5134 #ifdef CONFIG_SAWF_DEF_QUEUES 5135 struct dp_peer_sawf *sawf; 5136 #endif 5137 /* AST hash index for peer in HW */ 5138 uint16_t ast_idx; 5139 5140 /* AST hash value for peer in HW */ 5141 uint16_t ast_hash; 5142 5143 /* Peer Frequency */ 5144 uint32_t freq; 5145 }; 5146 5147 /** 5148 * struct dp_invalid_peer_msg - Invalid peer message 5149 * @nbuf: data buffer 5150 * @wh: 802.11 header 5151 * @vdev_id: id of vdev 5152 */ 5153 struct dp_invalid_peer_msg { 5154 qdf_nbuf_t nbuf; 5155 struct ieee80211_frame *wh; 5156 uint8_t vdev_id; 5157 }; 5158 5159 /** 5160 * struct dp_tx_me_buf_t - ME buffer 5161 * @next: pointer to next buffer 5162 * @data: Destination Mac address 5163 * @paddr_macbuf: physical address for dest_mac 5164 */ 5165 struct dp_tx_me_buf_t { 5166 /* Note: ME buf pool initialization logic expects next pointer to 5167 * be the first element. Dont add anything before next */ 5168 struct dp_tx_me_buf_t *next; 5169 uint8_t data[QDF_MAC_ADDR_SIZE]; 5170 qdf_dma_addr_t paddr_macbuf; 5171 }; 5172 5173 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) || defined(WLAN_SUPPORT_RX_FISA) 5174 struct hal_rx_fst; 5175 #endif /* WLAN_SUPPORT_RX_FLOW_TAG || WLAN_SUPPORT_RX_FISA */ 5176 5177 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 5178 struct dp_rx_fse { 5179 /* HAL Rx Flow Search Entry which matches HW definition */ 5180 void *hal_rx_fse; 5181 /* Toeplitz hash value */ 5182 uint32_t flow_hash; 5183 /* Flow index, equivalent to hash value truncated to FST size */ 5184 uint32_t flow_id; 5185 /* Stats tracking for this flow */ 5186 struct cdp_flow_stats stats; 5187 /* Flag indicating whether flow is IPv4 address tuple */ 5188 uint8_t is_ipv4_addr_entry; 5189 /* Flag indicating whether flow is valid */ 5190 uint8_t is_valid; 5191 }; 5192 5193 struct dp_rx_fst { 5194 /* Software (DP) FST */ 5195 uint8_t *base; 5196 /* Pointer to HAL FST */ 5197 struct hal_rx_fst *hal_rx_fst; 5198 /* Base physical address of HAL RX HW FST */ 5199 uint64_t hal_rx_fst_base_paddr; 5200 /* Maximum number of flows FSE supports */ 5201 uint16_t max_entries; 5202 /* Num entries in flow table */ 5203 uint16_t num_entries; 5204 /* SKID Length */ 5205 uint16_t max_skid_length; 5206 /* Hash mask to obtain legitimate hash entry */ 5207 uint32_t hash_mask; 5208 /* Timer for bundling of flows */ 5209 qdf_timer_t cache_invalidate_timer; 5210 /** 5211 * Flag which tracks whether cache update 5212 * is needed on timer expiry 5213 */ 5214 qdf_atomic_t is_cache_update_pending; 5215 /* Flag to indicate completion of FSE setup in HW/FW */ 5216 bool fse_setup_done; 5217 /* Last ring id used to add a flow */ 5218 uint8_t ring_id; 5219 }; 5220 5221 #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_rx_fse) 5222 5223 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 5224 5225 #ifdef WLAN_FEATURE_STATS_EXT 5226 /** 5227 * struct dp_req_rx_hw_stats_t - RX peer HW stats query structure 5228 * @pending_tid_stats_cnt: pending tid stats count which waits for REO status 5229 * @is_query_timeout: flag to show is stats query timeout 5230 */ 5231 struct dp_req_rx_hw_stats_t { 5232 qdf_atomic_t pending_tid_stats_cnt; 5233 bool is_query_timeout; 5234 }; 5235 #endif 5236 /* soc level structure to declare arch specific ops for DP */ 5237 5238 #ifndef WLAN_SOFTUMAC_SUPPORT 5239 /** 5240 * dp_hw_link_desc_pool_banks_free() - Free h/w link desc pool banks 5241 * @soc: DP SOC handle 5242 * @mac_id: mac id 5243 * 5244 * Return: none 5245 */ 5246 void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, uint32_t mac_id); 5247 5248 /** 5249 * dp_hw_link_desc_pool_banks_alloc() - Allocate h/w link desc pool banks 5250 * @soc: DP SOC handle 5251 * @mac_id: mac id 5252 * 5253 * Allocates memory pages for link descriptors, the page size is 4K for 5254 * MCL and 2MB for WIN. if the mac_id is invalid link descriptor pages are 5255 * allocated for regular RX/TX and if the there is a proper mac_id link 5256 * descriptors are allocated for RX monitor mode. 5257 * 5258 * Return: QDF_STATUS_SUCCESS: Success 5259 * QDF_STATUS_E_FAILURE: Failure 5260 */ 5261 QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, 5262 uint32_t mac_id); 5263 #else 5264 static inline void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, 5265 uint32_t mac_id) 5266 { 5267 } 5268 5269 static inline QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, 5270 uint32_t mac_id) 5271 { 5272 return QDF_STATUS_SUCCESS; 5273 } 5274 #endif 5275 5276 /** 5277 * dp_link_desc_ring_replenish() - Replenish hw link desc rings 5278 * @soc: DP SOC handle 5279 * @mac_id: mac id 5280 * 5281 * Return: None 5282 */ 5283 void dp_link_desc_ring_replenish(struct dp_soc *soc, uint32_t mac_id); 5284 5285 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 5286 void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc); 5287 #else 5288 static inline void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc) {} 5289 #endif 5290 5291 /** 5292 * dp_srng_alloc() - Allocate memory for SRNG 5293 * @soc : Data path soc handle 5294 * @srng : SRNG pointer 5295 * @ring_type : Ring Type 5296 * @num_entries: Number of entries 5297 * @cached: cached flag variable 5298 * 5299 * Return: QDF_STATUS 5300 */ 5301 QDF_STATUS dp_srng_alloc(struct dp_soc *soc, struct dp_srng *srng, 5302 int ring_type, uint32_t num_entries, 5303 bool cached); 5304 5305 /** 5306 * dp_srng_free() - Free SRNG memory 5307 * @soc: Data path soc handle 5308 * @srng: SRNG pointer 5309 * 5310 * Return: None 5311 */ 5312 void dp_srng_free(struct dp_soc *soc, struct dp_srng *srng); 5313 5314 /** 5315 * dp_srng_init() - Initialize SRNG 5316 * @soc : Data path soc handle 5317 * @srng : SRNG pointer 5318 * @ring_type : Ring Type 5319 * @ring_num: Ring number 5320 * @mac_id: mac_id 5321 * 5322 * Return: QDF_STATUS 5323 */ 5324 QDF_STATUS dp_srng_init(struct dp_soc *soc, struct dp_srng *srng, 5325 int ring_type, int ring_num, int mac_id); 5326 5327 /** 5328 * dp_srng_init_idx() - Initialize SRNG 5329 * @soc : Data path soc handle 5330 * @srng : SRNG pointer 5331 * @ring_type : Ring Type 5332 * @ring_num: Ring number 5333 * @mac_id: mac_id 5334 * @idx: ring index 5335 * 5336 * Return: QDF_STATUS 5337 */ 5338 QDF_STATUS dp_srng_init_idx(struct dp_soc *soc, struct dp_srng *srng, 5339 int ring_type, int ring_num, int mac_id, 5340 uint32_t idx); 5341 5342 /** 5343 * dp_srng_deinit() - Internal function to deinit SRNG rings used by data path 5344 * @soc: DP SOC handle 5345 * @srng: source ring structure 5346 * @ring_type: type of ring 5347 * @ring_num: ring number 5348 * 5349 * Return: None 5350 */ 5351 void dp_srng_deinit(struct dp_soc *soc, struct dp_srng *srng, 5352 int ring_type, int ring_num); 5353 5354 void dp_print_peer_txrx_stats_be(struct cdp_peer_stats *peer_stats, 5355 enum peer_stats_type stats_type); 5356 void dp_print_peer_txrx_stats_li(struct cdp_peer_stats *peer_stats, 5357 enum peer_stats_type stats_type); 5358 5359 void dp_print_peer_txrx_stats_rh(struct cdp_peer_stats *peer_stats, 5360 enum peer_stats_type stats_type); 5361 5362 /** 5363 * dp_should_timer_irq_yield() - Decide if the bottom half should yield 5364 * @soc: DP soc handle 5365 * @work_done: work done in softirq context 5366 * @start_time: start time for the softirq 5367 * 5368 * Return: enum with yield code 5369 */ 5370 enum timer_yield_status 5371 dp_should_timer_irq_yield(struct dp_soc *soc, uint32_t work_done, 5372 uint64_t start_time); 5373 5374 /** 5375 * dp_vdev_get_default_reo_hash() - get reo dest ring and hash values for a vdev 5376 * @vdev: Datapath VDEV handle 5377 * @reo_dest: pointer to default reo_dest ring for vdev to be populated 5378 * @hash_based: pointer to hash value (enabled/disabled) to be populated 5379 * 5380 * Return: None 5381 */ 5382 void dp_vdev_get_default_reo_hash(struct dp_vdev *vdev, 5383 enum cdp_host_reo_dest_ring *reo_dest, 5384 bool *hash_based); 5385 5386 /** 5387 * dp_reo_remap_config() - configure reo remap register value based 5388 * nss configuration. 5389 * @soc: DP soc handle 5390 * @remap0: output parameter indicates reo remap 0 register value 5391 * @remap1: output parameter indicates reo remap 1 register value 5392 * @remap2: output parameter indicates reo remap 2 register value 5393 * 5394 * based on offload_radio value below remap configuration 5395 * get applied. 5396 * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4) 5397 * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4) 5398 * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4) 5399 * 3 - both Radios handled by NSS (remap not required) 5400 * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3) 5401 * 5402 * Return: bool type, true if remap is configured else false. 5403 */ 5404 5405 bool dp_reo_remap_config(struct dp_soc *soc, uint32_t *remap0, 5406 uint32_t *remap1, uint32_t *remap2); 5407 5408 #ifdef QCA_DP_TX_HW_SW_NBUF_DESC_PREFETCH 5409 /** 5410 * dp_tx_comp_get_prefetched_params_from_hal_desc() - Get prefetched TX desc 5411 * @soc: DP soc handle 5412 * @tx_comp_hal_desc: HAL TX Comp Descriptor 5413 * @r_tx_desc: SW Tx Descriptor retrieved from HAL desc. 5414 * 5415 * Return: None 5416 */ 5417 void dp_tx_comp_get_prefetched_params_from_hal_desc( 5418 struct dp_soc *soc, 5419 void *tx_comp_hal_desc, 5420 struct dp_tx_desc_s **r_tx_desc); 5421 #endif 5422 #endif /* _DP_TYPES_H_ */ 5423