1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DP_TYPES_H_ 20 #define _DP_TYPES_H_ 21 22 #include <qdf_types.h> 23 #include <qdf_nbuf.h> 24 #include <qdf_lock.h> 25 #include <qdf_atomic.h> 26 #include <qdf_util.h> 27 #include <qdf_list.h> 28 #include <qdf_lro.h> 29 #include <queue.h> 30 #include <htt_common.h> 31 32 #include <cdp_txrx_cmn.h> 33 #ifdef CONFIG_MCL 34 #include <cds_ieee80211_common.h> 35 #else 36 #include <linux/ieee80211.h> 37 #endif 38 39 #ifndef CONFIG_WIN 40 #include <wdi_event_api.h> /* WDI subscriber event list */ 41 #endif 42 43 #include "hal_hw_headers.h" 44 #include <hal_tx.h> 45 #include <hal_reo.h> 46 #include "wlan_cfg.h" 47 #include "hal_rx.h" 48 #include <hal_api.h> 49 #include <hal_api_mon.h> 50 #include "hal_rx.h" 51 52 #define MAX_BW 7 53 #define MAX_RETRIES 4 54 #define MAX_RECEPTION_TYPES 4 55 56 #ifndef REMOVE_PKT_LOG 57 #include <pktlog.h> 58 #endif 59 60 #define REPT_MU_MIMO 1 61 #define REPT_MU_OFDMA_MIMO 3 62 #define DP_VO_TID 6 63 /** MAX TID MAPS AVAILABLE PER PDEV */ 64 #define DP_MAX_TID_MAPS 16 65 /** pad DSCP_TID_MAP_MAX with 6 to fix oob issue */ 66 #define DSCP_TID_MAP_MAX (64 + 6) 67 #define DP_IP_DSCP_SHIFT 2 68 #define DP_IP_DSCP_MASK 0x3f 69 #define DP_FC0_SUBTYPE_QOS 0x80 70 #define DP_QOS_TID 0x0f 71 #define DP_IPV6_PRIORITY_SHIFT 20 72 #define MAX_MON_LINK_DESC_BANKS 2 73 #define DP_VDEV_ALL 0xff 74 75 #if defined(CONFIG_MCL) 76 #define MAX_PDEV_CNT 1 77 #else 78 #define MAX_PDEV_CNT 3 79 #endif 80 81 #define MAX_LINK_DESC_BANKS 8 82 #define MAX_TXDESC_POOLS 4 83 #define MAX_RXDESC_POOLS 4 84 #define MAX_REO_DEST_RINGS 4 85 #define MAX_TCL_DATA_RINGS 4 86 #define MAX_IDLE_SCATTER_BUFS 16 87 #define DP_MAX_IRQ_PER_CONTEXT 12 88 #define DEFAULT_HW_PEER_ID 0xffff 89 90 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 91 92 93 /* Maximum retries for Delba per tid per peer */ 94 #define DP_MAX_DELBA_RETRY 3 95 96 #ifndef REMOVE_PKT_LOG 97 enum rx_pktlog_mode { 98 DP_RX_PKTLOG_DISABLED = 0, 99 DP_RX_PKTLOG_FULL, 100 DP_RX_PKTLOG_LITE, 101 }; 102 #endif 103 104 struct dp_soc_cmn; 105 struct dp_pdev; 106 struct dp_vdev; 107 struct dp_tx_desc_s; 108 struct dp_soc; 109 union dp_rx_desc_list_elem_t; 110 111 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 112 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 113 114 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 115 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 116 117 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 118 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 119 120 #define DP_MUTEX_TYPE qdf_spinlock_t 121 122 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 123 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 124 125 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 126 ((_a)[0] == 0x33 && \ 127 (_a)[1] == 0x33) 128 129 #define DP_FRAME_IS_BROADCAST(_a) \ 130 ((_a)[0] == 0xff && \ 131 (_a)[1] == 0xff && \ 132 (_a)[2] == 0xff && \ 133 (_a)[3] == 0xff && \ 134 (_a)[4] == 0xff && \ 135 (_a)[5] == 0xff) 136 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 137 (_llc)->llc_ssap == 0xaa && \ 138 (_llc)->llc_un.type_snap.control == 0x3) 139 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 140 #define DP_FRAME_FC0_TYPE_MASK 0x0c 141 #define DP_FRAME_FC0_TYPE_DATA 0x08 142 #define DP_FRAME_IS_DATA(_frame) \ 143 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 144 145 /** 146 * macros to convert hw mac id to sw mac id: 147 * mac ids used by hardware start from a value of 1 while 148 * those in host software start from a value of 0. Use the 149 * macros below to convert between mac ids used by software and 150 * hardware 151 */ 152 #define DP_SW2HW_MACID(id) ((id) + 1) 153 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 154 #define DP_MAC_ADDR_LEN 6 155 156 /** 157 * Number of Tx Queues 158 * enum and macro to define how many threshold levels is used 159 * for the AC based flow control 160 */ 161 #ifdef QCA_AC_BASED_FLOW_CONTROL 162 enum dp_fl_ctrl_threshold { 163 DP_TH_BE_BK = 0, 164 DP_TH_VI, 165 DP_TH_VO, 166 DP_TH_HI, 167 }; 168 169 #define FL_TH_MAX (4) 170 #define FL_TH_VI_PERCENTAGE (80) 171 #define FL_TH_VO_PERCENTAGE (60) 172 #define FL_TH_HI_PERCENTAGE (40) 173 #endif 174 175 /** 176 * enum dp_intr_mode 177 * @DP_INTR_LEGACY: Legacy/Line interrupts, for WIN 178 * @DP_INTR_MSI: MSI interrupts, for MCL 179 * @DP_INTR_POLL: Polling 180 */ 181 enum dp_intr_mode { 182 DP_INTR_LEGACY = 0, 183 DP_INTR_MSI, 184 DP_INTR_POLL, 185 }; 186 187 /** 188 * enum dp_tx_frm_type 189 * @dp_tx_frm_std: Regular frame, no added header fragments 190 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 191 * @dp_tx_frm_sg: SG segment 192 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 193 * @dp_tx_frm_me: Multicast to Unicast Converted frame 194 * @dp_tx_frm_raw: Raw Frame 195 */ 196 enum dp_tx_frm_type { 197 dp_tx_frm_std = 0, 198 dp_tx_frm_tso, 199 dp_tx_frm_sg, 200 dp_tx_frm_audio, 201 dp_tx_frm_me, 202 dp_tx_frm_raw, 203 }; 204 205 /** 206 * enum dp_ast_type 207 * @dp_ast_type_wds: WDS peer AST type 208 * @dp_ast_type_static: static ast entry type 209 * @dp_ast_type_mec: Multicast echo ast entry type 210 */ 211 enum dp_ast_type { 212 dp_ast_type_wds = 0, 213 dp_ast_type_static, 214 dp_ast_type_mec, 215 }; 216 217 /** 218 * enum dp_nss_cfg 219 * @dp_nss_cfg_default: No radios are offloaded 220 * @dp_nss_cfg_first_radio: First radio offloaded 221 * @dp_nss_cfg_second_radio: Second radio offloaded 222 * @dp_nss_cfg_dbdc: Dual radios offloaded 223 * @dp_nss_cfg_dbtc: Three radios offloaded 224 */ 225 enum dp_nss_cfg { 226 dp_nss_cfg_default = 0x0, 227 dp_nss_cfg_first_radio = 0x1, 228 dp_nss_cfg_second_radio = 0x2, 229 dp_nss_cfg_dbdc = 0x3, 230 dp_nss_cfg_dbtc = 0x7, 231 dp_nss_cfg_max 232 }; 233 234 /** 235 * struct rx_desc_pool 236 * @pool_size: number of RX descriptor in the pool 237 * @array: pointer to array of RX descriptor 238 * @freelist: pointer to free RX descriptor link list 239 * @lock: Protection for the RX descriptor pool 240 * @owner: owner for nbuf 241 */ 242 struct rx_desc_pool { 243 uint32_t pool_size; 244 union dp_rx_desc_list_elem_t *array; 245 union dp_rx_desc_list_elem_t *freelist; 246 qdf_spinlock_t lock; 247 uint8_t owner; 248 }; 249 250 /** 251 * struct dp_tx_ext_desc_elem_s 252 * @next: next extension descriptor pointer 253 * @vaddr: hlos virtual address pointer 254 * @paddr: physical address pointer for descriptor 255 */ 256 struct dp_tx_ext_desc_elem_s { 257 struct dp_tx_ext_desc_elem_s *next; 258 void *vaddr; 259 qdf_dma_addr_t paddr; 260 }; 261 262 /** 263 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 264 * @elem_count: Number of descriptors in the pool 265 * @elem_size: Size of each descriptor 266 * @num_free: Number of free descriptors 267 * @msdu_ext_desc: MSDU extension descriptor 268 * @desc_pages: multiple page allocation information for actual descriptors 269 * @link_elem_size: size of the link descriptor in cacheable memory used for 270 * chaining the extension descriptors 271 * @desc_link_pages: multiple page allocation information for link descriptors 272 */ 273 struct dp_tx_ext_desc_pool_s { 274 uint16_t elem_count; 275 int elem_size; 276 uint16_t num_free; 277 struct qdf_mem_multi_page_t desc_pages; 278 int link_elem_size; 279 struct qdf_mem_multi_page_t desc_link_pages; 280 struct dp_tx_ext_desc_elem_s *freelist; 281 qdf_spinlock_t lock; 282 qdf_dma_mem_context(memctx); 283 }; 284 285 /** 286 * struct dp_tx_desc_s - Tx Descriptor 287 * @next: Next in the chain of descriptors in freelist or in the completion list 288 * @nbuf: Buffer Address 289 * @msdu_ext_desc: MSDU extension descriptor 290 * @id: Descriptor ID 291 * @vdev: vdev over which the packet was transmitted 292 * @pdev: Handle to pdev 293 * @pool_id: Pool ID - used when releasing the descriptor 294 * @flags: Flags to track the state of descriptor and special frame handling 295 * @comp: Pool ID - used when releasing the descriptor 296 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 297 * This is maintained in descriptor to allow more efficient 298 * processing in completion event processing code. 299 * This field is filled in with the htt_pkt_type enum. 300 * @frm_type: Frame Type - ToDo check if this is redundant 301 * @pkt_offset: Offset from which the actual packet data starts 302 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 303 * Tx completion of ME packet 304 * @pool: handle to flow_pool this descriptor belongs to. 305 */ 306 struct dp_tx_desc_s { 307 struct dp_tx_desc_s *next; 308 qdf_nbuf_t nbuf; 309 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 310 uint32_t id; 311 struct dp_vdev *vdev; 312 struct dp_pdev *pdev; 313 uint8_t pool_id; 314 uint16_t flags; 315 struct hal_tx_desc_comp_s comp; 316 uint16_t tx_encap_type; 317 uint8_t frm_type; 318 uint8_t pkt_offset; 319 void *me_buffer; 320 void *tso_desc; 321 void *tso_num_desc; 322 uint64_t timestamp; 323 }; 324 325 /** 326 * enum flow_pool_status - flow pool status 327 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 328 * and network queues are unpaused 329 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 330 * and network queues are paused 331 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 332 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 333 */ 334 enum flow_pool_status { 335 FLOW_POOL_ACTIVE_UNPAUSED = 0, 336 FLOW_POOL_ACTIVE_PAUSED = 1, 337 FLOW_POOL_BE_BK_PAUSED = 2, 338 FLOW_POOL_VI_PAUSED = 3, 339 FLOW_POOL_VO_PAUSED = 4, 340 FLOW_POOL_INVALID = 5, 341 FLOW_POOL_INACTIVE = 6, 342 }; 343 344 /** 345 * struct dp_tx_tso_seg_pool_s 346 * @pool_size: total number of pool elements 347 * @num_free: free element count 348 * @freelist: first free element pointer 349 * @desc_pages: multiple page allocation information for actual descriptors 350 * @lock: lock for accessing the pool 351 */ 352 struct dp_tx_tso_seg_pool_s { 353 uint16_t pool_size; 354 uint16_t num_free; 355 struct qdf_tso_seg_elem_t *freelist; 356 struct qdf_mem_multi_page_t desc_pages; 357 qdf_spinlock_t lock; 358 }; 359 360 /** 361 * struct dp_tx_tso_num_seg_pool_s { 362 * @num_seg_pool_size: total number of pool elements 363 * @num_free: free element count 364 * @freelist: first free element pointer 365 * @desc_pages: multiple page allocation information for actual descriptors 366 * @lock: lock for accessing the pool 367 */ 368 369 struct dp_tx_tso_num_seg_pool_s { 370 uint16_t num_seg_pool_size; 371 uint16_t num_free; 372 struct qdf_tso_num_seg_elem_t *freelist; 373 struct qdf_mem_multi_page_t desc_pages; 374 /*tso mutex */ 375 qdf_spinlock_t lock; 376 }; 377 378 /** 379 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 380 * @elem_size: Size of each descriptor in the pool 381 * @pool_size: Total number of descriptors in the pool 382 * @num_free: Number of free descriptors 383 * @num_allocated: Number of used descriptors 384 * @freelist: Chain of free descriptors 385 * @desc_pages: multiple page allocation information for actual descriptors 386 * @num_invalid_bin: Deleted pool with pending Tx completions. 387 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 388 * @flow_pool_array: List of allocated flow pools 389 * @lock- Lock for descriptor allocation/free from/to the pool 390 */ 391 struct dp_tx_desc_pool_s { 392 uint16_t elem_size; 393 uint32_t num_allocated; 394 struct dp_tx_desc_s *freelist; 395 struct qdf_mem_multi_page_t desc_pages; 396 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 397 uint16_t pool_size; 398 uint8_t flow_pool_id; 399 uint8_t num_invalid_bin; 400 uint16_t avail_desc; 401 enum flow_pool_status status; 402 enum htt_flow_type flow_type; 403 #ifdef QCA_AC_BASED_FLOW_CONTROL 404 uint16_t stop_th[FL_TH_MAX]; 405 uint16_t start_th[FL_TH_MAX]; 406 qdf_time_t max_pause_time[FL_TH_MAX]; 407 qdf_time_t latest_pause_time[FL_TH_MAX]; 408 #else 409 uint16_t stop_th; 410 uint16_t start_th; 411 #endif 412 uint16_t pkt_drop_no_desc; 413 qdf_spinlock_t flow_pool_lock; 414 uint8_t pool_create_cnt; 415 void *pool_owner_ctx; 416 #else 417 uint16_t elem_count; 418 uint32_t num_free; 419 qdf_spinlock_t lock; 420 #endif 421 }; 422 423 /** 424 * struct dp_txrx_pool_stats - flow pool related statistics 425 * @pool_map_count: flow pool map received 426 * @pool_unmap_count: flow pool unmap received 427 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 428 */ 429 struct dp_txrx_pool_stats { 430 uint16_t pool_map_count; 431 uint16_t pool_unmap_count; 432 uint16_t pkt_drop_no_pool; 433 }; 434 435 struct dp_srng { 436 void *hal_srng; 437 void *base_vaddr_unaligned; 438 qdf_dma_addr_t base_paddr_unaligned; 439 uint32_t alloc_size; 440 int irq; 441 uint32_t num_entries; 442 }; 443 444 struct dp_rx_reorder_array_elem { 445 qdf_nbuf_t head; 446 qdf_nbuf_t tail; 447 }; 448 449 #define DP_RX_BA_INACTIVE 0 450 #define DP_RX_BA_ACTIVE 1 451 #define DP_RX_BA_IN_PROGRESS 2 452 struct dp_reo_cmd_info { 453 uint16_t cmd; 454 enum hal_reo_cmd_type cmd_type; 455 void *data; 456 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 457 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 458 }; 459 460 /* Rx TID */ 461 struct dp_rx_tid { 462 /* TID */ 463 int tid; 464 465 /* Num of addba requests */ 466 uint32_t num_of_addba_req; 467 468 /* Num of addba responses */ 469 uint32_t num_of_addba_resp; 470 471 /* Num of delba requests */ 472 uint32_t num_of_delba_req; 473 474 /* Num of addba responses successful */ 475 uint32_t num_addba_rsp_success; 476 477 /* Num of addba responses failed */ 478 uint32_t num_addba_rsp_failed; 479 480 /* pn size */ 481 uint8_t pn_size; 482 /* REO TID queue descriptors */ 483 void *hw_qdesc_vaddr_unaligned; 484 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 485 qdf_dma_addr_t hw_qdesc_paddr; 486 uint32_t hw_qdesc_alloc_size; 487 488 /* RX ADDBA session state */ 489 int ba_status; 490 491 /* RX BA window size */ 492 uint16_t ba_win_size; 493 494 /* Starting sequence number in Addba request */ 495 uint16_t startseqnum; 496 497 /* TODO: Check the following while adding defragmentation support */ 498 struct dp_rx_reorder_array_elem *array; 499 /* base - single rx reorder element used for non-aggr cases */ 500 struct dp_rx_reorder_array_elem base; 501 502 /* only used for defrag right now */ 503 TAILQ_ENTRY(dp_rx_tid) defrag_waitlist_elem; 504 505 /* Store dst desc for reinjection */ 506 void *dst_ring_desc; 507 struct dp_rx_desc *head_frag_desc; 508 509 /* rx_tid lock */ 510 qdf_spinlock_t tid_lock; 511 512 /* Sequence and fragments that are being processed currently */ 513 uint32_t curr_seq_num; 514 uint32_t curr_frag_num; 515 516 uint32_t defrag_timeout_ms; 517 uint16_t dialogtoken; 518 uint16_t statuscode; 519 /* user defined ADDBA response status code */ 520 uint16_t userstatuscode; 521 522 /* Store ppdu_id when 2k exception is received */ 523 uint32_t ppdu_id_2k; 524 525 /* Delba Tx completion status */ 526 uint8_t delba_tx_status; 527 528 /* Delba Tx retry count */ 529 uint8_t delba_tx_retry; 530 531 /* Delba stats */ 532 uint32_t delba_tx_success_cnt; 533 uint32_t delba_tx_fail_cnt; 534 535 /* Delba reason code for retries */ 536 uint8_t delba_rcode; 537 538 }; 539 540 /* per interrupt context */ 541 struct dp_intr { 542 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 543 associated with this napi context */ 544 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 545 with this interrupt context */ 546 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 547 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 548 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 549 uint8_t reo_status_ring_mask; /* REO command response ring */ 550 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 551 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 552 /* Host to RXDMA monitor buffer ring */ 553 uint8_t host2rxdma_mon_ring_mask; 554 struct dp_soc *soc; /* Reference to SoC structure , 555 to get DMA ring handles */ 556 qdf_lro_ctx_t lro_ctx; 557 uint8_t dp_intr_id; 558 }; 559 560 #define REO_DESC_FREELIST_SIZE 64 561 #define REO_DESC_FREE_DEFER_MS 1000 562 struct reo_desc_list_node { 563 qdf_list_node_t node; 564 unsigned long free_ts; 565 struct dp_rx_tid rx_tid; 566 }; 567 568 /* SoC level data path statistics */ 569 struct dp_soc_stats { 570 struct { 571 uint32_t added; 572 uint32_t deleted; 573 uint32_t aged_out; 574 } ast; 575 576 /* SOC level TX stats */ 577 struct { 578 /* packets dropped on tx because of no peer */ 579 struct cdp_pkt_info tx_invalid_peer; 580 /* descriptors in each tcl ring */ 581 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 582 /* Descriptors in use at soc */ 583 uint32_t desc_in_use; 584 /* tqm_release_reason == FW removed */ 585 uint32_t dropped_fw_removed; 586 587 } tx; 588 589 /* SOC level RX stats */ 590 struct { 591 /* Rx errors */ 592 /* Total Packets in Rx Error ring */ 593 uint32_t err_ring_pkts; 594 /* No of Fragments */ 595 uint32_t rx_frags; 596 /* No of incomplete fragments in waitlist */ 597 uint32_t rx_frag_wait; 598 /* Fragments dropped due to errors */ 599 uint32_t rx_frag_err; 600 /* No of reinjected packets */ 601 uint32_t reo_reinject; 602 /* Head pointer Out of sync */ 603 uint32_t hp_oos; 604 struct { 605 /* Invalid RBM error count */ 606 uint32_t invalid_rbm; 607 /* Invalid VDEV Error count */ 608 uint32_t invalid_vdev; 609 /* Invalid PDEV error count */ 610 uint32_t invalid_pdev; 611 /* Invalid sa_idx or da_idx*/ 612 uint32_t invalid_sa_da_idx; 613 /* Invalid PEER Error count */ 614 struct cdp_pkt_info rx_invalid_peer; 615 /* Invalid PEER ID count */ 616 struct cdp_pkt_info rx_invalid_peer_id; 617 /* HAL ring access Fail error count */ 618 uint32_t hal_ring_access_fail; 619 /* RX DMA error count */ 620 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 621 /* REO Error count */ 622 uint32_t reo_error[HAL_REO_ERR_MAX]; 623 /* HAL REO ERR Count */ 624 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 625 /* HAL REO DEST Duplicate count */ 626 uint32_t hal_reo_dest_dup; 627 /* HAL WBM RELEASE Duplicate count */ 628 uint32_t hal_wbm_rel_dup; 629 } err; 630 631 /* packet count per core - per ring */ 632 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 633 } rx; 634 }; 635 636 #define DP_MAC_ADDR_LEN 6 637 union dp_align_mac_addr { 638 uint8_t raw[DP_MAC_ADDR_LEN]; 639 struct { 640 uint16_t bytes_ab; 641 uint16_t bytes_cd; 642 uint16_t bytes_ef; 643 } align2; 644 struct { 645 uint32_t bytes_abcd; 646 uint16_t bytes_ef; 647 } align4; 648 struct __attribute__((__packed__)) { 649 uint16_t bytes_ab; 650 uint32_t bytes_cdef; 651 } align4_2; 652 }; 653 654 /** 655 * struct dp_ast_free_cb_params - HMWDS free callback cookie 656 * @mac_addr: ast mac address 657 * @peer_mac_addr: mac address of peer 658 * @type: ast entry type 659 * @vdev_id: vdev_id 660 * @flags: ast flags 661 */ 662 struct dp_ast_free_cb_params { 663 union dp_align_mac_addr mac_addr; 664 union dp_align_mac_addr peer_mac_addr; 665 enum cdp_txrx_ast_entry_type type; 666 uint8_t vdev_id; 667 uint32_t flags; 668 }; 669 670 /* 671 * dp_ast_entry 672 * 673 * @ast_idx: Hardware AST Index 674 * @mac_addr: MAC Address for this AST entry 675 * @peer: Next Hop peer (for non-WDS nodes, this will be point to 676 * associated peer with this MAC address) 677 * @next_hop: Set to 1 if this is for a WDS node 678 * @is_active: flag to indicate active data traffic on this node 679 * (used for aging out/expiry) 680 * @ase_list_elem: node in peer AST list 681 * @is_bss: flag to indicate if entry corresponds to bss peer 682 * @is_mapped: flag to indicate that we have mapped the AST entry 683 * in ast_table 684 * @pdev_id: pdev ID 685 * @vdev_id: vdev ID 686 * @ast_hash_value: hast value in HW 687 * @ref_cnt: reference count 688 * @type: flag to indicate type of the entry(static/WDS/MEC) 689 * @delete_in_progress: Flag to indicate that delete commands send to FW 690 * and host is waiting for response from FW 691 * @callback: ast free/unmap callback 692 * @cookie: argument to callback 693 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 694 */ 695 struct dp_ast_entry { 696 uint16_t ast_idx; 697 union dp_align_mac_addr mac_addr; 698 struct dp_peer *peer; 699 bool next_hop; 700 bool is_active; 701 bool is_bss; 702 bool is_mapped; 703 uint8_t pdev_id; 704 uint8_t vdev_id; 705 uint16_t ast_hash_value; 706 qdf_atomic_t ref_cnt; 707 enum cdp_txrx_ast_entry_type type; 708 bool delete_in_progress; 709 txrx_ast_free_cb callback; 710 void *cookie; 711 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 712 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 713 }; 714 715 /* SOC level htt stats */ 716 struct htt_t2h_stats { 717 /* lock to protect htt_stats_msg update */ 718 qdf_spinlock_t lock; 719 720 /* work queue to process htt stats */ 721 qdf_work_t work; 722 723 /* T2H Ext stats message queue */ 724 qdf_nbuf_queue_t msg; 725 726 /* number of completed stats in htt_stats_msg */ 727 uint32_t num_stats; 728 }; 729 730 /* SOC level structure for data path */ 731 struct dp_soc { 732 /** 733 * re-use memory section starts 734 */ 735 736 /* Common base structure - Should be the first member */ 737 struct cdp_soc_t cdp_soc; 738 739 /* SoC Obj */ 740 void *ctrl_psoc; 741 742 /* OS device abstraction */ 743 qdf_device_t osdev; 744 745 /* WLAN config context */ 746 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 747 748 /* HTT handle for host-fw interaction */ 749 void *htt_handle; 750 751 /* Commint init done */ 752 qdf_atomic_t cmn_init_done; 753 754 /* Opaque hif handle */ 755 struct hif_opaque_softc *hif_handle; 756 757 /* PDEVs on this SOC */ 758 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 759 760 /* Number of PDEVs */ 761 uint8_t pdev_count; 762 763 /*cce disable*/ 764 bool cce_disable; 765 766 /*ast override support in HW*/ 767 bool ast_override_support; 768 769 /*number of hw dscp tid map*/ 770 uint8_t num_hw_dscp_tid_map; 771 772 /* HAL SOC handle */ 773 void *hal_soc; 774 775 /* Device ID coming from Bus sub-system */ 776 uint32_t device_id; 777 778 /* Link descriptor memory banks */ 779 struct { 780 void *base_vaddr_unaligned; 781 void *base_vaddr; 782 qdf_dma_addr_t base_paddr_unaligned; 783 qdf_dma_addr_t base_paddr; 784 uint32_t size; 785 } link_desc_banks[MAX_LINK_DESC_BANKS]; 786 787 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 788 struct dp_srng wbm_idle_link_ring; 789 790 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 791 */ 792 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 793 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 794 795 /* Tx SW descriptor pool */ 796 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 797 798 /* Tx MSDU Extension descriptor pool */ 799 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 800 801 /* Tx TSO descriptor pool */ 802 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 803 804 /* Tx TSO Num of segments pool */ 805 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 806 807 /* REO destination rings */ 808 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 809 810 /* REO exception ring - See if should combine this with reo_dest_ring */ 811 struct dp_srng reo_exception_ring; 812 813 /* REO reinjection ring */ 814 struct dp_srng reo_reinject_ring; 815 816 /* REO command ring */ 817 struct dp_srng reo_cmd_ring; 818 819 /* REO command status ring */ 820 struct dp_srng reo_status_ring; 821 822 /* WBM Rx release ring */ 823 struct dp_srng rx_rel_ring; 824 825 /* TCL data ring */ 826 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 827 828 /* Number of TCL data rings */ 829 uint8_t num_tcl_data_rings; 830 831 /* TCL command ring */ 832 struct dp_srng tcl_cmd_ring; 833 834 /* TCL command status ring */ 835 struct dp_srng tcl_status_ring; 836 837 /* WBM Tx completion rings */ 838 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 839 840 /* Common WBM link descriptor release ring (SW to WBM) */ 841 struct dp_srng wbm_desc_rel_ring; 842 843 /* DP Interrupts */ 844 struct dp_intr intr_ctx[WLAN_CFG_INT_NUM_CONTEXTS]; 845 846 /* Rx SW descriptor pool for RXDMA monitor buffer */ 847 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 848 849 /* Rx SW descriptor pool for RXDMA status buffer */ 850 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 851 852 /* Rx SW descriptor pool for RXDMA buffer */ 853 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 854 855 /* Number of REO destination rings */ 856 uint8_t num_reo_dest_rings; 857 858 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 859 /* lock to control access to soc TX descriptors */ 860 qdf_spinlock_t flow_pool_array_lock; 861 862 /* pause callback to pause TX queues as per flow control */ 863 tx_pause_callback pause_cb; 864 865 /* flow pool related statistics */ 866 struct dp_txrx_pool_stats pool_stats; 867 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 868 869 /* 870 * Re-use memory section ends. reuse memory indicator. 871 * Everything above this variable "dp_soc_reinit" is retained across 872 * WiFi up/down for AP use-cases. 873 * Everything below this variable "dp_soc_reinit" is reset during 874 * dp_soc_deinit. 875 */ 876 bool dp_soc_reinit; 877 878 uint32_t wbm_idle_scatter_buf_size; 879 880 /* Tx H/W queues lock */ 881 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 882 883 /* Tx ring map for interrupt processing */ 884 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 885 886 /* Rx ring map for interrupt processing */ 887 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 888 889 /* peer ID to peer object map (array of pointers to peer objects) */ 890 struct dp_peer **peer_id_to_obj_map; 891 892 struct { 893 unsigned mask; 894 unsigned idx_bits; 895 TAILQ_HEAD(, dp_peer) * bins; 896 } peer_hash; 897 898 /* rx defrag state – TBD: do we need this per radio? */ 899 struct { 900 struct { 901 TAILQ_HEAD(, dp_rx_tid) waitlist; 902 uint32_t timeout_ms; 903 uint32_t next_flush_ms; 904 qdf_spinlock_t defrag_lock; 905 } defrag; 906 struct { 907 int defrag_timeout_check; 908 int dup_check; 909 } flags; 910 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 911 qdf_spinlock_t reo_cmd_lock; 912 } rx; 913 914 /* optional rx processing function */ 915 void (*rx_opt_proc)( 916 struct dp_vdev *vdev, 917 struct dp_peer *peer, 918 unsigned tid, 919 qdf_nbuf_t msdu_list); 920 921 /* pool addr for mcast enhance buff */ 922 struct { 923 int size; 924 uint32_t paddr; 925 uint32_t *vaddr; 926 struct dp_tx_me_buf_t *freelist; 927 int buf_in_use; 928 qdf_dma_mem_context(memctx); 929 } me_buf; 930 931 /** 932 * peer ref mutex: 933 * 1. Protect peer object lookups until the returned peer object's 934 * reference count is incremented. 935 * 2. Provide mutex when accessing peer object lookup structures. 936 */ 937 DP_MUTEX_TYPE peer_ref_mutex; 938 939 /* maximum value for peer_id */ 940 uint32_t max_peers; 941 942 /* SoC level data path statistics */ 943 struct dp_soc_stats stats; 944 945 /* Enable processing of Tx completion status words */ 946 bool process_tx_status; 947 bool process_rx_status; 948 struct dp_ast_entry *ast_table[WLAN_UMAC_PSOC_MAX_PEERS * 2]; 949 struct { 950 unsigned mask; 951 unsigned idx_bits; 952 TAILQ_HEAD(, dp_ast_entry) * bins; 953 } ast_hash; 954 955 qdf_spinlock_t ast_lock; 956 /*Timer for AST entry ageout maintainance */ 957 qdf_timer_t ast_aging_timer; 958 959 /*Timer counter for WDS AST entry ageout*/ 960 uint8_t wds_ast_aging_timer_cnt; 961 962 /*interrupt timer*/ 963 qdf_timer_t mon_reap_timer; 964 uint8_t reap_timer_init; 965 qdf_timer_t int_timer; 966 uint8_t intr_mode; 967 968 qdf_list_t reo_desc_freelist; 969 qdf_spinlock_t reo_desc_freelist_lock; 970 971 /* htt stats */ 972 struct htt_t2h_stats htt_stats; 973 974 void *external_txrx_handle; /* External data path handle */ 975 #ifdef IPA_OFFLOAD 976 /* IPA uC datapath offload Wlan Tx resources */ 977 struct { 978 /* Resource info to be passed to IPA */ 979 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 980 void *ipa_tcl_ring_base_vaddr; 981 uint32_t ipa_tcl_ring_size; 982 qdf_dma_addr_t ipa_tcl_hp_paddr; 983 uint32_t alloc_tx_buf_cnt; 984 985 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 986 void *ipa_wbm_ring_base_vaddr; 987 uint32_t ipa_wbm_ring_size; 988 qdf_dma_addr_t ipa_wbm_tp_paddr; 989 990 /* TX buffers populated into the WBM ring */ 991 void **tx_buf_pool_vaddr_unaligned; 992 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 993 } ipa_uc_tx_rsc; 994 995 /* IPA uC datapath offload Wlan Rx resources */ 996 struct { 997 /* Resource info to be passed to IPA */ 998 qdf_dma_addr_t ipa_reo_ring_base_paddr; 999 void *ipa_reo_ring_base_vaddr; 1000 uint32_t ipa_reo_ring_size; 1001 qdf_dma_addr_t ipa_reo_tp_paddr; 1002 1003 /* Resource info to be passed to firmware and IPA */ 1004 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 1005 void *ipa_rx_refill_buf_ring_base_vaddr; 1006 uint32_t ipa_rx_refill_buf_ring_size; 1007 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 1008 } ipa_uc_rx_rsc; 1009 #endif 1010 1011 /* Smart monitor capability for HKv2 */ 1012 uint8_t hw_nac_monitor_support; 1013 /* Flag to indicate if HTT v2 is enabled*/ 1014 bool is_peer_map_unmap_v2; 1015 /* Per peer per Tid ba window size support */ 1016 uint8_t per_tid_basize_max_tid; 1017 /* Soc level flag to enable da_war */ 1018 uint8_t da_war_enabled; 1019 /* number of active ast entries */ 1020 uint32_t num_ast_entries; 1021 }; 1022 1023 #ifdef IPA_OFFLOAD 1024 /** 1025 * dp_ipa_resources - Resources needed for IPA 1026 */ 1027 struct dp_ipa_resources { 1028 qdf_dma_addr_t tx_ring_base_paddr; 1029 uint32_t tx_ring_size; 1030 uint32_t tx_num_alloc_buffer; 1031 1032 qdf_dma_addr_t tx_comp_ring_base_paddr; 1033 uint32_t tx_comp_ring_size; 1034 1035 qdf_dma_addr_t rx_rdy_ring_base_paddr; 1036 uint32_t rx_rdy_ring_size; 1037 1038 qdf_dma_addr_t rx_refill_ring_base_paddr; 1039 uint32_t rx_refill_ring_size; 1040 1041 /* IPA UC doorbell registers paddr */ 1042 qdf_dma_addr_t tx_comp_doorbell_paddr; 1043 uint32_t *tx_comp_doorbell_vaddr; 1044 qdf_dma_addr_t rx_ready_doorbell_paddr; 1045 }; 1046 #endif 1047 1048 #define MAX_RX_MAC_RINGS 2 1049 /* Same as NAC_MAX_CLENT */ 1050 #define DP_NAC_MAX_CLIENT 24 1051 1052 /* 1053 * Macros to setup link descriptor cookies - for link descriptors, we just 1054 * need first 3 bits to store bank ID. The remaining bytes will be used set a 1055 * unique ID, which will be useful in debugging 1056 */ 1057 #define LINK_DESC_BANK_ID_MASK 0x7 1058 #define LINK_DESC_ID_SHIFT 3 1059 #define LINK_DESC_ID_START 0x8000 1060 1061 #define LINK_DESC_COOKIE(_desc_id, _bank_id) \ 1062 ((((_desc_id) + LINK_DESC_ID_START) << LINK_DESC_ID_SHIFT) | (_bank_id)) 1063 1064 #define LINK_DESC_COOKIE_BANK_ID(_cookie) \ 1065 ((_cookie) & LINK_DESC_BANK_ID_MASK) 1066 1067 /* same as ieee80211_nac_param */ 1068 enum dp_nac_param_cmd { 1069 /* IEEE80211_NAC_PARAM_ADD */ 1070 DP_NAC_PARAM_ADD = 1, 1071 /* IEEE80211_NAC_PARAM_DEL */ 1072 DP_NAC_PARAM_DEL, 1073 /* IEEE80211_NAC_PARAM_LIST */ 1074 DP_NAC_PARAM_LIST, 1075 }; 1076 1077 /** 1078 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 1079 * @neighbour_peers_macaddr: neighbour peer's mac address 1080 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 1081 * @ast_entry: ast_entry for neighbour peer 1082 * @rssi: rssi value 1083 */ 1084 struct dp_neighbour_peer { 1085 /* MAC address of neighbour's peer */ 1086 union dp_align_mac_addr neighbour_peers_macaddr; 1087 struct dp_vdev *vdev; 1088 struct dp_ast_entry *ast_entry; 1089 uint8_t rssi; 1090 /* node in the list of neighbour's peer */ 1091 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 1092 }; 1093 1094 /** 1095 * struct ppdu_info - PPDU Status info descriptor 1096 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 1097 * @max_ppdu_id - wrap around for ppdu id 1098 * @last_tlv_cnt - Keep track for missing ppdu tlvs 1099 * @last_user - last ppdu processed for user 1100 * @is_ampdu - set if Ampdu aggregate 1101 * @nbuf - ppdu descriptor payload 1102 * @ppdu_desc - ppdu descriptor 1103 * @ppdu_info_list_elem - linked list of ppdu tlvs 1104 */ 1105 struct ppdu_info { 1106 uint32_t ppdu_id; 1107 uint32_t max_ppdu_id; 1108 uint16_t tlv_bitmap; 1109 uint16_t last_tlv_cnt; 1110 uint16_t last_user:8, 1111 is_ampdu:1; 1112 qdf_nbuf_t nbuf; 1113 struct cdp_tx_completion_ppdu *ppdu_desc; 1114 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 1115 }; 1116 1117 /* PDEV level structure for data path */ 1118 struct dp_pdev { 1119 /** 1120 * Re-use Memory Section Starts 1121 */ 1122 /* PDEV handle from OSIF layer TBD: see if we really need osif_pdev */ 1123 struct cdp_ctrl_objmgr_pdev *ctrl_pdev; 1124 1125 /* PDEV Id */ 1126 int pdev_id; 1127 1128 /* LMAC Id */ 1129 int lmac_id; 1130 1131 /* TXRX SOC handle */ 1132 struct dp_soc *soc; 1133 1134 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 1135 struct dp_srng rx_refill_buf_ring; 1136 1137 /* RXDMA error destination ring */ 1138 struct dp_srng rxdma_err_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1139 1140 /* Link descriptor memory banks */ 1141 struct { 1142 void *base_vaddr_unaligned; 1143 void *base_vaddr; 1144 qdf_dma_addr_t base_paddr_unaligned; 1145 qdf_dma_addr_t base_paddr; 1146 uint32_t size; 1147 } link_desc_banks[NUM_RXDMA_RINGS_PER_PDEV][MAX_MON_LINK_DESC_BANKS]; 1148 1149 /* RXDMA monitor buffer replenish ring */ 1150 struct dp_srng rxdma_mon_buf_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1151 1152 /* RXDMA monitor destination ring */ 1153 struct dp_srng rxdma_mon_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1154 1155 /* RXDMA monitor status ring. TBD: Check format of this ring */ 1156 struct dp_srng rxdma_mon_status_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1157 1158 struct dp_srng rxdma_mon_desc_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1159 1160 /* 1161 * re-use memory section ends 1162 * reuse memory/deinit indicator 1163 * 1164 * DO NOT CHANGE NAME OR MOVE THIS VARIABLE 1165 */ 1166 bool pdev_deinit; 1167 1168 /* Second ring used to replenish rx buffers */ 1169 struct dp_srng rx_refill_buf_ring2; 1170 1171 /* Empty ring used by firmware to post rx buffers to the MAC */ 1172 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 1173 1174 /* wlan_cfg pdev ctxt*/ 1175 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 1176 1177 /** 1178 * TODO: See if we need a ring map here for LMAC rings. 1179 * 1. Monitor rings are currently planning to be processed on receiving 1180 * PPDU end interrupts and hence wont need ring based interrupts. 1181 * 2. Rx buffer rings will be replenished during REO destination 1182 * processing and doesn't require regular interrupt handling - we will 1183 * only handle low water mark interrupts which is not expected 1184 * frequently 1185 */ 1186 1187 /* VDEV list */ 1188 TAILQ_HEAD(, dp_vdev) vdev_list; 1189 1190 /* vdev list lock */ 1191 qdf_spinlock_t vdev_list_lock; 1192 1193 /* Number of vdevs this device have */ 1194 uint16_t vdev_count; 1195 1196 /* PDEV transmit lock */ 1197 qdf_spinlock_t tx_lock; 1198 1199 #ifndef REMOVE_PKT_LOG 1200 bool pkt_log_init; 1201 /* Pktlog pdev */ 1202 struct pktlog_dev_t *pl_dev; 1203 #endif /* #ifndef REMOVE_PKT_LOG */ 1204 1205 /* Monitor mode interface and status storage */ 1206 struct dp_vdev *monitor_vdev; 1207 1208 /* monitor mode lock */ 1209 qdf_spinlock_t mon_lock; 1210 1211 /*tx_mutex for me*/ 1212 DP_MUTEX_TYPE tx_mutex; 1213 1214 /* monitor */ 1215 bool monitor_configured; 1216 1217 /* Smart Mesh */ 1218 bool filter_neighbour_peers; 1219 1220 /*flag to indicate neighbour_peers_list not empty */ 1221 bool neighbour_peers_added; 1222 /* smart mesh mutex */ 1223 qdf_spinlock_t neighbour_peer_mutex; 1224 /* Neighnour peer list */ 1225 TAILQ_HEAD(, dp_neighbour_peer) neighbour_peers_list; 1226 /* msdu chain head & tail */ 1227 qdf_nbuf_t invalid_peer_head_msdu; 1228 qdf_nbuf_t invalid_peer_tail_msdu; 1229 1230 /* Band steering */ 1231 /* TBD */ 1232 1233 /* PDEV level data path statistics */ 1234 struct cdp_pdev_stats stats; 1235 1236 /* Global RX decap mode for the device */ 1237 enum htt_pkt_type rx_decap_mode; 1238 1239 /* Enhanced Stats is enabled */ 1240 bool enhanced_stats_en; 1241 1242 /* advance filter mode and type*/ 1243 uint8_t mon_filter_mode; 1244 uint16_t fp_mgmt_filter; 1245 uint16_t fp_ctrl_filter; 1246 uint16_t fp_data_filter; 1247 uint16_t mo_mgmt_filter; 1248 uint16_t mo_ctrl_filter; 1249 uint16_t mo_data_filter; 1250 uint16_t md_data_filter; 1251 1252 qdf_atomic_t num_tx_outstanding; 1253 1254 qdf_atomic_t num_tx_exception; 1255 1256 /* MCL specific local peer handle */ 1257 struct { 1258 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 1259 uint8_t freelist; 1260 qdf_spinlock_t lock; 1261 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 1262 } local_peer_ids; 1263 1264 /* dscp_tid_map_*/ 1265 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 1266 1267 struct hal_rx_ppdu_info ppdu_info; 1268 1269 /* operating channel */ 1270 uint8_t operating_channel; 1271 1272 qdf_nbuf_queue_t rx_status_q; 1273 uint32_t mon_ppdu_status; 1274 struct cdp_mon_status rx_mon_recv_status; 1275 /* monitor mode status/destination ring PPDU and MPDU count */ 1276 struct cdp_pdev_mon_stats rx_mon_stats; 1277 /* to track duplicate link descriptor indications by HW for a WAR */ 1278 uint64_t mon_last_linkdesc_paddr; 1279 /* to track duplicate buffer indications by HW for a WAR */ 1280 uint32_t mon_last_buf_cookie; 1281 1282 /* pool addr for mcast enhance buff */ 1283 struct { 1284 int size; 1285 uint32_t paddr; 1286 char *vaddr; 1287 struct dp_tx_me_buf_t *freelist; 1288 int buf_in_use; 1289 qdf_dma_mem_context(memctx); 1290 } me_buf; 1291 1292 bool hmmc_tid_override_en; 1293 uint8_t hmmc_tid; 1294 1295 /* Number of VAPs with mcast enhancement enabled */ 1296 qdf_atomic_t mc_num_vap_attached; 1297 1298 qdf_atomic_t stats_cmd_complete; 1299 1300 #ifdef IPA_OFFLOAD 1301 ipa_uc_op_cb_type ipa_uc_op_cb; 1302 void *usr_ctxt; 1303 struct dp_ipa_resources ipa_resource; 1304 #endif 1305 1306 /* TBD */ 1307 1308 /* map this pdev to a particular Reo Destination ring */ 1309 enum cdp_host_reo_dest_ring reo_dest; 1310 1311 #ifndef REMOVE_PKT_LOG 1312 /* Packet log mode */ 1313 uint8_t rx_pktlog_mode; 1314 #endif 1315 1316 /* WDI event handlers */ 1317 struct wdi_event_subscribe_t **wdi_event_list; 1318 1319 /* ppdu_id of last received HTT TX stats */ 1320 uint32_t last_ppdu_id; 1321 struct { 1322 uint8_t last_user; 1323 qdf_nbuf_t buf; 1324 } tx_ppdu_info; 1325 1326 bool tx_sniffer_enable; 1327 /* mirror copy mode */ 1328 bool mcopy_mode; 1329 bool bpr_enable; 1330 struct { 1331 uint16_t tx_ppdu_id; 1332 uint16_t tx_peer_id; 1333 uint16_t rx_ppdu_id; 1334 } m_copy_id; 1335 1336 /* To check if PPDU Tx stats are enabled for Pktlog */ 1337 bool pktlog_ppdu_stats; 1338 1339 void *dp_txrx_handle; /* Advanced data path handle */ 1340 1341 #ifdef ATH_SUPPORT_NAC_RSSI 1342 bool nac_rssi_filtering; 1343 #endif 1344 /* list of ppdu tlvs */ 1345 TAILQ_HEAD(, ppdu_info) ppdu_info_list; 1346 uint32_t tlv_count; 1347 uint32_t list_depth; 1348 uint32_t ppdu_id; 1349 bool first_nbuf; 1350 struct { 1351 uint8_t *mgmt_buf; /* Ptr to mgmt. payload in HTT ppdu stats */ 1352 uint32_t mgmt_buf_len; /* Len of mgmt. payload in ppdu stats */ 1353 uint32_t ppdu_id; 1354 } mgmtctrl_frm_info; 1355 1356 /* Current noise-floor reading for the pdev channel */ 1357 int16_t chan_noise_floor; 1358 1359 /* 1360 * For multiradio device, this flag indicates if 1361 * this radio is primary or secondary. 1362 * 1363 * For HK 1.0, this is used for WAR for the AST issue. 1364 * HK 1.x mandates creation of only 1 AST entry with same MAC address 1365 * across 2 radios. is_primary indicates the radio on which DP should 1366 * install HW AST entry if there is a request to add 2 AST entries 1367 * with same MAC address across 2 radios 1368 */ 1369 uint8_t is_primary; 1370 /* Context of cal client timer */ 1371 void *cal_client_ctx; 1372 struct cdp_tx_sojourn_stats sojourn_stats; 1373 qdf_nbuf_t sojourn_buf; 1374 1375 /* peer pointer for collecting invalid peer stats */ 1376 struct dp_peer *invalid_peer; 1377 1378 union dp_rx_desc_list_elem_t *free_list_head; 1379 union dp_rx_desc_list_elem_t *free_list_tail; 1380 /* Pdev level flag to check peer based pktlog enabled or 1381 * disabled 1382 */ 1383 uint8_t dp_peer_based_pktlog; 1384 1385 /* Cached peer_id from htt_peer_details_tlv */ 1386 uint8_t fw_stats_peer_id; 1387 1388 /* qdf_event for fw_peer_stats */ 1389 qdf_event_t fw_peer_stats_event; 1390 }; 1391 1392 struct dp_peer; 1393 1394 /* VDEV structure for data path state */ 1395 struct dp_vdev { 1396 /* OS device abstraction */ 1397 qdf_device_t osdev; 1398 /* physical device that is the parent of this virtual device */ 1399 struct dp_pdev *pdev; 1400 1401 /* Handle to the OS shim SW's virtual device */ 1402 ol_osif_vdev_handle osif_vdev; 1403 1404 /* Handle to the UMAC handle */ 1405 struct cdp_ctrl_objmgr_vdev *ctrl_vdev; 1406 /* vdev_id - ID used to specify a particular vdev to the target */ 1407 uint8_t vdev_id; 1408 1409 /* MAC address */ 1410 union dp_align_mac_addr mac_addr; 1411 1412 /* node in the pdev's list of vdevs */ 1413 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 1414 1415 /* dp_peer list */ 1416 TAILQ_HEAD(, dp_peer) peer_list; 1417 1418 /* default RX call back function called by dp */ 1419 ol_txrx_rx_fp osif_rx; 1420 /* callback to deliver rx frames to the OS */ 1421 ol_txrx_rx_fp osif_rx_stack; 1422 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 1423 ol_txrx_get_key_fp osif_get_key; 1424 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 1425 1426 #ifdef notyet 1427 /* callback to check if the msdu is an WAI (WAPI) frame */ 1428 ol_rx_check_wai_fp osif_check_wai; 1429 #endif 1430 1431 /* proxy arp function */ 1432 ol_txrx_proxy_arp_fp osif_proxy_arp; 1433 1434 /* callback to hand rx monitor 802.11 MPDU to the OS shim */ 1435 ol_txrx_rx_mon_fp osif_rx_mon; 1436 1437 ol_txrx_mcast_me_fp me_convert; 1438 1439 /* completion function used by this vdev*/ 1440 ol_txrx_completion_fp tx_comp; 1441 1442 /* deferred vdev deletion state */ 1443 struct { 1444 /* VDEV delete pending */ 1445 int pending; 1446 /* 1447 * callback and a context argument to provide a 1448 * notification for when the vdev is deleted. 1449 */ 1450 ol_txrx_vdev_delete_cb callback; 1451 void *context; 1452 } delete; 1453 1454 /* tx data delivery notification callback function */ 1455 struct { 1456 ol_txrx_data_tx_cb func; 1457 void *ctxt; 1458 } tx_non_std_data_callback; 1459 1460 1461 /* safe mode control to bypass the encrypt and decipher process*/ 1462 uint32_t safemode; 1463 1464 /* rx filter related */ 1465 uint32_t drop_unenc; 1466 #ifdef notyet 1467 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 1468 uint32_t filters_num; 1469 #endif 1470 /* TDLS Link status */ 1471 bool tdls_link_connected; 1472 bool is_tdls_frame; 1473 1474 1475 /* VDEV operating mode */ 1476 enum wlan_op_mode opmode; 1477 1478 /* Tx encapsulation type for this VAP */ 1479 enum htt_cmn_pkt_type tx_encap_type; 1480 /* Rx Decapsulation type for this VAP */ 1481 enum htt_cmn_pkt_type rx_decap_type; 1482 1483 /* BSS peer */ 1484 struct dp_peer *vap_bss_peer; 1485 1486 /* WDS enabled */ 1487 bool wds_enabled; 1488 1489 /* MEC enabled */ 1490 bool mec_enabled; 1491 1492 /* WDS Aging timer period */ 1493 uint32_t wds_aging_timer_val; 1494 1495 /* NAWDS enabled */ 1496 bool nawds_enabled; 1497 1498 /* Default HTT meta data for this VDEV */ 1499 /* TBD: check alignment constraints */ 1500 uint16_t htt_tcl_metadata; 1501 1502 /* Mesh mode vdev */ 1503 uint32_t mesh_vdev; 1504 1505 /* Mesh mode rx filter setting */ 1506 uint32_t mesh_rx_filter; 1507 1508 /* DSCP-TID mapping table ID */ 1509 uint8_t dscp_tid_map_id; 1510 1511 /* Multicast enhancement enabled */ 1512 uint8_t mcast_enhancement_en; 1513 1514 /* per vdev rx nbuf queue */ 1515 qdf_nbuf_queue_t rxq; 1516 1517 uint8_t tx_ring_id; 1518 struct dp_tx_desc_pool_s *tx_desc; 1519 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 1520 1521 /* VDEV Stats */ 1522 struct cdp_vdev_stats stats; 1523 1524 /* Is this a proxySTA VAP */ 1525 bool proxysta_vdev; 1526 /* Is isolation mode enabled */ 1527 bool isolation_vdev; 1528 1529 /* Address search flags to be configured in HAL descriptor */ 1530 uint8_t hal_desc_addr_search_flags; 1531 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1532 struct dp_tx_desc_pool_s *pool; 1533 #endif 1534 /* AP BRIDGE enabled */ 1535 uint32_t ap_bridge_enabled; 1536 1537 enum cdp_sec_type sec_type; 1538 1539 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 1540 bool raw_mode_war; 1541 1542 /* Address search type to be set in TX descriptor */ 1543 uint8_t search_type; 1544 1545 /* AST hash value for BSS peer in HW valid for STA VAP*/ 1546 uint16_t bss_ast_hash; 1547 }; 1548 1549 1550 enum { 1551 dp_sec_mcast = 0, 1552 dp_sec_ucast 1553 }; 1554 1555 #ifdef WDS_VENDOR_EXTENSION 1556 typedef struct { 1557 uint8_t wds_tx_mcast_4addr:1, 1558 wds_tx_ucast_4addr:1, 1559 wds_rx_filter:1, /* enforce rx filter */ 1560 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 1561 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 1562 1563 } dp_ecm_policy; 1564 #endif 1565 1566 /* Peer structure for data path state */ 1567 struct dp_peer { 1568 /* VDEV to which this peer is associated */ 1569 struct dp_vdev *vdev; 1570 1571 struct cdp_ctrl_objmgr_peer *ctrl_peer; 1572 1573 struct dp_ast_entry *self_ast_entry; 1574 1575 qdf_atomic_t ref_cnt; 1576 1577 /* TODO: See if multiple peer IDs are required in wifi3.0 */ 1578 /* peer ID(s) for this peer */ 1579 uint16_t peer_ids[MAX_NUM_PEER_ID_PER_PEER]; 1580 1581 union dp_align_mac_addr mac_addr; 1582 1583 /* node in the vdev's list of peers */ 1584 TAILQ_ENTRY(dp_peer) peer_list_elem; 1585 /* node in the hash table bin's list of peers */ 1586 TAILQ_ENTRY(dp_peer) hash_list_elem; 1587 1588 /* TID structures */ 1589 struct dp_rx_tid rx_tid[DP_MAX_TIDS]; 1590 1591 /* TBD: No transmit TID state required? */ 1592 1593 struct { 1594 enum cdp_sec_type sec_type; 1595 u_int32_t michael_key[2]; /* relevant for TKIP */ 1596 } security[2]; /* 0 -> multicast, 1 -> unicast */ 1597 1598 /* 1599 * rx proc function: this either is a copy of pdev's rx_opt_proc for 1600 * regular rx processing, or has been redirected to a /dev/null discard 1601 * function when peer deletion is in progress. 1602 */ 1603 void (*rx_opt_proc)(struct dp_vdev *vdev, struct dp_peer *peer, 1604 unsigned tid, qdf_nbuf_t msdu_list); 1605 1606 /* set when node is authorized */ 1607 uint8_t authorize:1; 1608 1609 u_int8_t nac; 1610 1611 /* Band steering: Set when node is inactive */ 1612 uint8_t peer_bs_inact_flag:1; 1613 u_int16_t peer_bs_inact; /* inactivity mark count */ 1614 1615 /* NAWDS Flag and Bss Peer bit */ 1616 uint8_t nawds_enabled:1, 1617 bss_peer:1, 1618 wapi:1, 1619 wds_enabled:1; 1620 1621 /* MCL specific peer local id */ 1622 uint16_t local_id; 1623 enum ol_txrx_peer_state state; 1624 qdf_spinlock_t peer_info_lock; 1625 1626 qdf_time_t last_assoc_rcvd; 1627 qdf_time_t last_disassoc_rcvd; 1628 qdf_time_t last_deauth_rcvd; 1629 /* Peer Stats */ 1630 struct cdp_peer_stats stats; 1631 1632 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 1633 /* TBD */ 1634 1635 #ifdef WDS_VENDOR_EXTENSION 1636 dp_ecm_policy wds_ecm; 1637 #endif 1638 bool delete_in_progress; 1639 1640 /* Active Block ack sessions */ 1641 uint16_t active_ba_session_cnt; 1642 1643 /* Current HW buffersize setting */ 1644 uint16_t hw_buffer_size; 1645 1646 /* 1647 * Flag to check if sessions with 256 buffersize 1648 * should be terminated. 1649 */ 1650 uint8_t kill_256_sessions; 1651 qdf_atomic_t is_default_route_set; 1652 /* Peer level flag to check peer based pktlog enabled or 1653 * disabled 1654 */ 1655 uint8_t peer_based_pktlog_filter; 1656 }; 1657 1658 #ifdef CONFIG_WIN 1659 /* 1660 * dp_invalid_peer_msg 1661 * @nbuf: data buffer 1662 * @wh: 802.11 header 1663 * @vdev_id: id of vdev 1664 */ 1665 struct dp_invalid_peer_msg { 1666 qdf_nbuf_t nbuf; 1667 struct ieee80211_frame *wh; 1668 uint8_t vdev_id; 1669 }; 1670 #endif 1671 1672 /* 1673 * dp_tx_me_buf_t: ME buffer 1674 * next: pointer to next buffer 1675 * data: Destination Mac address 1676 */ 1677 struct dp_tx_me_buf_t { 1678 /* Note: ME buf pool initialization logic expects next pointer to 1679 * be the first element. Dont add anything before next */ 1680 struct dp_tx_me_buf_t *next; 1681 uint8_t data[DP_MAC_ADDR_LEN]; 1682 }; 1683 1684 #endif /* _DP_TYPES_H_ */ 1685