1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DP_TYPES_H_ 20 #define _DP_TYPES_H_ 21 22 #include <qdf_types.h> 23 #include <qdf_nbuf.h> 24 #include <qdf_lock.h> 25 #include <qdf_atomic.h> 26 #include <qdf_util.h> 27 #include <qdf_list.h> 28 #include <qdf_lro.h> 29 #include <queue.h> 30 #include <htt_common.h> 31 32 #include <cdp_txrx_cmn.h> 33 #ifdef DP_MOB_DEFS 34 #include <cds_ieee80211_common.h> 35 #endif 36 #include <wdi_event_api.h> /* WDI subscriber event list */ 37 38 #include "hal_hw_headers.h" 39 #include <hal_tx.h> 40 #include <hal_reo.h> 41 #include "wlan_cfg.h" 42 #include "hal_rx.h" 43 #include <hal_api.h> 44 #include <hal_api_mon.h> 45 #include "hal_rx.h" 46 //#include "hal_rx_flow.h" 47 48 #define MAX_BW 7 49 #define MAX_RETRIES 4 50 #define MAX_RECEPTION_TYPES 4 51 52 #ifndef REMOVE_PKT_LOG 53 #include <pktlog.h> 54 #endif 55 56 #ifdef WLAN_TX_PKT_CAPTURE_ENH 57 #include "dp_tx_capture.h" 58 #endif 59 60 #define REPT_MU_MIMO 1 61 #define REPT_MU_OFDMA_MIMO 3 62 #define DP_VO_TID 6 63 /** MAX TID MAPS AVAILABLE PER PDEV */ 64 #define DP_MAX_TID_MAPS 16 65 /** pad DSCP_TID_MAP_MAX with 6 to fix oob issue */ 66 #define DSCP_TID_MAP_MAX (64 + 6) 67 #define DP_IP_DSCP_SHIFT 2 68 #define DP_IP_DSCP_MASK 0x3f 69 #define DP_FC0_SUBTYPE_QOS 0x80 70 #define DP_QOS_TID 0x0f 71 #define DP_IPV6_PRIORITY_SHIFT 20 72 #define MAX_MON_LINK_DESC_BANKS 2 73 #define DP_VDEV_ALL 0xff 74 75 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 76 #define MAX_PDEV_CNT 1 77 #else 78 #define MAX_PDEV_CNT 3 79 #endif 80 81 /* Max no. of VDEV per PSOC */ 82 #ifdef WLAN_PSOC_MAX_VDEVS 83 #define MAX_VDEV_CNT WLAN_PSOC_MAX_VDEVS 84 #else 85 #define MAX_VDEV_CNT 51 86 #endif 87 88 #define MAX_LINK_DESC_BANKS 8 89 #define MAX_TXDESC_POOLS 4 90 #define MAX_RXDESC_POOLS 4 91 #define MAX_REO_DEST_RINGS 4 92 #define EXCEPTION_DEST_RING_ID 0 93 #define MAX_TCL_DATA_RINGS 4 94 #define MAX_IDLE_SCATTER_BUFS 16 95 #define DP_MAX_IRQ_PER_CONTEXT 12 96 #define DEFAULT_HW_PEER_ID 0xffff 97 98 #define WBM_INT_ERROR_ALL 0 99 #define WBM_INT_ERROR_REO_NULL_BUFFER 1 100 #define WBM_INT_ERROR_REO_NULL_LINK_DESC 2 101 #define WBM_INT_ERROR_REO_NULL_MSDU_BUFF 3 102 #define WBM_INT_ERROR_REO_BUFF_REAPED 4 103 #define MAX_WBM_INT_ERROR_REASONS 5 104 105 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 106 /* Maximum retries for Delba per tid per peer */ 107 #define DP_MAX_DELBA_RETRY 3 108 109 #define PCP_TID_MAP_MAX 8 110 #define MAX_MU_USERS 37 111 112 #define REO_CMD_EVENT_HIST_MAX 64 113 114 #ifndef REMOVE_PKT_LOG 115 enum rx_pktlog_mode { 116 DP_RX_PKTLOG_DISABLED = 0, 117 DP_RX_PKTLOG_FULL, 118 DP_RX_PKTLOG_LITE, 119 }; 120 #endif 121 122 struct msdu_list { 123 qdf_nbuf_t head; 124 qdf_nbuf_t tail; 125 uint32 sum_len; 126 }; 127 128 struct dp_soc_cmn; 129 struct dp_pdev; 130 struct dp_vdev; 131 struct dp_tx_desc_s; 132 struct dp_soc; 133 union dp_rx_desc_list_elem_t; 134 struct cdp_peer_rate_stats_ctx; 135 struct cdp_soc_rate_stats_ctx; 136 struct dp_rx_fst; 137 138 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 139 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 140 141 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 142 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 143 144 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 145 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 146 147 #define DP_MUTEX_TYPE qdf_spinlock_t 148 149 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 150 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 151 152 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 153 ((_a)[0] == 0x33 && \ 154 (_a)[1] == 0x33) 155 156 #define DP_FRAME_IS_BROADCAST(_a) \ 157 ((_a)[0] == 0xff && \ 158 (_a)[1] == 0xff && \ 159 (_a)[2] == 0xff && \ 160 (_a)[3] == 0xff && \ 161 (_a)[4] == 0xff && \ 162 (_a)[5] == 0xff) 163 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 164 (_llc)->llc_ssap == 0xaa && \ 165 (_llc)->llc_un.type_snap.control == 0x3) 166 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 167 #define DP_FRAME_FC0_TYPE_MASK 0x0c 168 #define DP_FRAME_FC0_TYPE_DATA 0x08 169 #define DP_FRAME_IS_DATA(_frame) \ 170 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 171 172 /** 173 * macros to convert hw mac id to sw mac id: 174 * mac ids used by hardware start from a value of 1 while 175 * those in host software start from a value of 0. Use the 176 * macros below to convert between mac ids used by software and 177 * hardware 178 */ 179 #define DP_SW2HW_MACID(id) ((id) + 1) 180 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 181 182 /** 183 * Number of Tx Queues 184 * enum and macro to define how many threshold levels is used 185 * for the AC based flow control 186 */ 187 #ifdef QCA_AC_BASED_FLOW_CONTROL 188 enum dp_fl_ctrl_threshold { 189 DP_TH_BE_BK = 0, 190 DP_TH_VI, 191 DP_TH_VO, 192 DP_TH_HI, 193 }; 194 195 #define FL_TH_MAX (4) 196 #define FL_TH_VI_PERCENTAGE (80) 197 #define FL_TH_VO_PERCENTAGE (60) 198 #define FL_TH_HI_PERCENTAGE (40) 199 #endif 200 201 /** 202 * enum dp_intr_mode 203 * @DP_INTR_LEGACY: Legacy/Line interrupts, for WIN 204 * @DP_INTR_MSI: MSI interrupts, for MCL 205 * @DP_INTR_POLL: Polling 206 */ 207 enum dp_intr_mode { 208 DP_INTR_LEGACY = 0, 209 DP_INTR_MSI, 210 DP_INTR_POLL, 211 }; 212 213 /** 214 * enum dp_tx_frm_type 215 * @dp_tx_frm_std: Regular frame, no added header fragments 216 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 217 * @dp_tx_frm_sg: SG segment 218 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 219 * @dp_tx_frm_me: Multicast to Unicast Converted frame 220 * @dp_tx_frm_raw: Raw Frame 221 */ 222 enum dp_tx_frm_type { 223 dp_tx_frm_std = 0, 224 dp_tx_frm_tso, 225 dp_tx_frm_sg, 226 dp_tx_frm_audio, 227 dp_tx_frm_me, 228 dp_tx_frm_raw, 229 }; 230 231 /** 232 * enum dp_ast_type 233 * @dp_ast_type_wds: WDS peer AST type 234 * @dp_ast_type_static: static ast entry type 235 * @dp_ast_type_mec: Multicast echo ast entry type 236 */ 237 enum dp_ast_type { 238 dp_ast_type_wds = 0, 239 dp_ast_type_static, 240 dp_ast_type_mec, 241 }; 242 243 /** 244 * enum dp_nss_cfg 245 * @dp_nss_cfg_default: No radios are offloaded 246 * @dp_nss_cfg_first_radio: First radio offloaded 247 * @dp_nss_cfg_second_radio: Second radio offloaded 248 * @dp_nss_cfg_dbdc: Dual radios offloaded 249 * @dp_nss_cfg_dbtc: Three radios offloaded 250 */ 251 enum dp_nss_cfg { 252 dp_nss_cfg_default = 0x0, 253 dp_nss_cfg_first_radio = 0x1, 254 dp_nss_cfg_second_radio = 0x2, 255 dp_nss_cfg_dbdc = 0x3, 256 dp_nss_cfg_dbtc = 0x7, 257 dp_nss_cfg_max 258 }; 259 260 #ifdef WLAN_TX_PKT_CAPTURE_ENH 261 #define DP_CPU_RING_MAP_1 1 262 #endif 263 264 /** 265 * dp_cpu_ring_map_type - dp tx cpu ring map 266 * @DP_NSS_DEFAULT_MAP: Default mode with no NSS offloaded 267 * @DP_NSS_FIRST_RADIO_OFFLOADED_MAP: Only First Radio is offloaded 268 * @DP_NSS_SECOND_RADIO_OFFLOADED_MAP: Only second radio is offloaded 269 * @DP_NSS_DBDC_OFFLOADED_MAP: Both radios are offloaded 270 * @DP_NSS_DBTC_OFFLOADED_MAP: All three radios are offloaded 271 * @DP_SINGLE_TX_RING_MAP: to avoid out of order all cpu mapped to single ring 272 * @DP_NSS_CPU_RING_MAP_MAX: Max cpu ring map val 273 */ 274 enum dp_cpu_ring_map_types { 275 DP_NSS_DEFAULT_MAP, 276 DP_NSS_FIRST_RADIO_OFFLOADED_MAP, 277 DP_NSS_SECOND_RADIO_OFFLOADED_MAP, 278 DP_NSS_DBDC_OFFLOADED_MAP, 279 DP_NSS_DBTC_OFFLOADED_MAP, 280 #ifdef WLAN_TX_PKT_CAPTURE_ENH 281 DP_SINGLE_TX_RING_MAP, 282 #endif 283 DP_NSS_CPU_RING_MAP_MAX 284 }; 285 286 /** 287 * struct rx_desc_pool 288 * @pool_size: number of RX descriptor in the pool 289 * @elem_size: Element size 290 * @desc_pages: Multi page descriptors 291 * @array: pointer to array of RX descriptor 292 * @freelist: pointer to free RX descriptor link list 293 * @lock: Protection for the RX descriptor pool 294 * @owner: owner for nbuf 295 */ 296 struct rx_desc_pool { 297 uint32_t pool_size; 298 #ifdef RX_DESC_MULTI_PAGE_ALLOC 299 uint16_t elem_size; 300 struct qdf_mem_multi_page_t desc_pages; 301 #else 302 union dp_rx_desc_list_elem_t *array; 303 #endif 304 union dp_rx_desc_list_elem_t *freelist; 305 qdf_spinlock_t lock; 306 uint8_t owner; 307 }; 308 309 /** 310 * struct dp_tx_ext_desc_elem_s 311 * @next: next extension descriptor pointer 312 * @vaddr: hlos virtual address pointer 313 * @paddr: physical address pointer for descriptor 314 */ 315 struct dp_tx_ext_desc_elem_s { 316 struct dp_tx_ext_desc_elem_s *next; 317 void *vaddr; 318 qdf_dma_addr_t paddr; 319 }; 320 321 /** 322 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 323 * @elem_count: Number of descriptors in the pool 324 * @elem_size: Size of each descriptor 325 * @num_free: Number of free descriptors 326 * @msdu_ext_desc: MSDU extension descriptor 327 * @desc_pages: multiple page allocation information for actual descriptors 328 * @link_elem_size: size of the link descriptor in cacheable memory used for 329 * chaining the extension descriptors 330 * @desc_link_pages: multiple page allocation information for link descriptors 331 */ 332 struct dp_tx_ext_desc_pool_s { 333 uint16_t elem_count; 334 int elem_size; 335 uint16_t num_free; 336 struct qdf_mem_multi_page_t desc_pages; 337 int link_elem_size; 338 struct qdf_mem_multi_page_t desc_link_pages; 339 struct dp_tx_ext_desc_elem_s *freelist; 340 qdf_spinlock_t lock; 341 qdf_dma_mem_context(memctx); 342 }; 343 344 /** 345 * struct dp_tx_desc_s - Tx Descriptor 346 * @next: Next in the chain of descriptors in freelist or in the completion list 347 * @nbuf: Buffer Address 348 * @msdu_ext_desc: MSDU extension descriptor 349 * @id: Descriptor ID 350 * @vdev: vdev over which the packet was transmitted 351 * @pdev: Handle to pdev 352 * @pool_id: Pool ID - used when releasing the descriptor 353 * @flags: Flags to track the state of descriptor and special frame handling 354 * @comp: Pool ID - used when releasing the descriptor 355 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 356 * This is maintained in descriptor to allow more efficient 357 * processing in completion event processing code. 358 * This field is filled in with the htt_pkt_type enum. 359 * @frm_type: Frame Type - ToDo check if this is redundant 360 * @pkt_offset: Offset from which the actual packet data starts 361 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 362 * Tx completion of ME packet 363 * @pool: handle to flow_pool this descriptor belongs to. 364 */ 365 struct dp_tx_desc_s { 366 struct dp_tx_desc_s *next; 367 qdf_nbuf_t nbuf; 368 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 369 uint32_t id; 370 struct dp_vdev *vdev; 371 struct dp_pdev *pdev; 372 uint8_t pool_id; 373 uint16_t flags; 374 struct hal_tx_desc_comp_s comp; 375 uint16_t tx_encap_type; 376 uint8_t frm_type; 377 uint8_t pkt_offset; 378 void *me_buffer; 379 void *tso_desc; 380 void *tso_num_desc; 381 uint64_t timestamp; 382 }; 383 384 /** 385 * enum flow_pool_status - flow pool status 386 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 387 * and network queues are unpaused 388 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 389 * and network queues are paused 390 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 391 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 392 */ 393 enum flow_pool_status { 394 FLOW_POOL_ACTIVE_UNPAUSED = 0, 395 FLOW_POOL_ACTIVE_PAUSED = 1, 396 FLOW_POOL_BE_BK_PAUSED = 2, 397 FLOW_POOL_VI_PAUSED = 3, 398 FLOW_POOL_VO_PAUSED = 4, 399 FLOW_POOL_INVALID = 5, 400 FLOW_POOL_INACTIVE = 6, 401 }; 402 403 /** 404 * struct dp_tx_tso_seg_pool_s 405 * @pool_size: total number of pool elements 406 * @num_free: free element count 407 * @freelist: first free element pointer 408 * @desc_pages: multiple page allocation information for actual descriptors 409 * @lock: lock for accessing the pool 410 */ 411 struct dp_tx_tso_seg_pool_s { 412 uint16_t pool_size; 413 uint16_t num_free; 414 struct qdf_tso_seg_elem_t *freelist; 415 struct qdf_mem_multi_page_t desc_pages; 416 qdf_spinlock_t lock; 417 }; 418 419 /** 420 * struct dp_tx_tso_num_seg_pool_s { 421 * @num_seg_pool_size: total number of pool elements 422 * @num_free: free element count 423 * @freelist: first free element pointer 424 * @desc_pages: multiple page allocation information for actual descriptors 425 * @lock: lock for accessing the pool 426 */ 427 428 struct dp_tx_tso_num_seg_pool_s { 429 uint16_t num_seg_pool_size; 430 uint16_t num_free; 431 struct qdf_tso_num_seg_elem_t *freelist; 432 struct qdf_mem_multi_page_t desc_pages; 433 /*tso mutex */ 434 qdf_spinlock_t lock; 435 }; 436 437 /** 438 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 439 * @elem_size: Size of each descriptor in the pool 440 * @pool_size: Total number of descriptors in the pool 441 * @num_free: Number of free descriptors 442 * @num_allocated: Number of used descriptors 443 * @freelist: Chain of free descriptors 444 * @desc_pages: multiple page allocation information for actual descriptors 445 * @num_invalid_bin: Deleted pool with pending Tx completions. 446 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 447 * @flow_pool_array: List of allocated flow pools 448 * @lock- Lock for descriptor allocation/free from/to the pool 449 */ 450 struct dp_tx_desc_pool_s { 451 uint16_t elem_size; 452 uint32_t num_allocated; 453 struct dp_tx_desc_s *freelist; 454 struct qdf_mem_multi_page_t desc_pages; 455 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 456 uint16_t pool_size; 457 uint8_t flow_pool_id; 458 uint8_t num_invalid_bin; 459 uint16_t avail_desc; 460 enum flow_pool_status status; 461 enum htt_flow_type flow_type; 462 #ifdef QCA_AC_BASED_FLOW_CONTROL 463 uint16_t stop_th[FL_TH_MAX]; 464 uint16_t start_th[FL_TH_MAX]; 465 qdf_time_t max_pause_time[FL_TH_MAX]; 466 qdf_time_t latest_pause_time[FL_TH_MAX]; 467 #else 468 uint16_t stop_th; 469 uint16_t start_th; 470 #endif 471 uint16_t pkt_drop_no_desc; 472 qdf_spinlock_t flow_pool_lock; 473 uint8_t pool_create_cnt; 474 void *pool_owner_ctx; 475 #else 476 uint16_t elem_count; 477 uint32_t num_free; 478 qdf_spinlock_t lock; 479 #endif 480 }; 481 482 /** 483 * struct dp_txrx_pool_stats - flow pool related statistics 484 * @pool_map_count: flow pool map received 485 * @pool_unmap_count: flow pool unmap received 486 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 487 */ 488 struct dp_txrx_pool_stats { 489 uint16_t pool_map_count; 490 uint16_t pool_unmap_count; 491 uint16_t pkt_drop_no_pool; 492 }; 493 494 struct dp_srng { 495 hal_ring_handle_t hal_srng; 496 void *base_vaddr_unaligned; 497 qdf_dma_addr_t base_paddr_unaligned; 498 uint32_t alloc_size; 499 uint8_t cached; 500 int irq; 501 uint32_t num_entries; 502 }; 503 504 struct dp_rx_reorder_array_elem { 505 qdf_nbuf_t head; 506 qdf_nbuf_t tail; 507 }; 508 509 #define DP_RX_BA_INACTIVE 0 510 #define DP_RX_BA_ACTIVE 1 511 #define DP_RX_BA_IN_PROGRESS 2 512 struct dp_reo_cmd_info { 513 uint16_t cmd; 514 enum hal_reo_cmd_type cmd_type; 515 void *data; 516 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 517 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 518 }; 519 520 /* Rx TID */ 521 struct dp_rx_tid { 522 /* TID */ 523 int tid; 524 525 /* Num of addba requests */ 526 uint32_t num_of_addba_req; 527 528 /* Num of addba responses */ 529 uint32_t num_of_addba_resp; 530 531 /* Num of delba requests */ 532 uint32_t num_of_delba_req; 533 534 /* Num of addba responses successful */ 535 uint32_t num_addba_rsp_success; 536 537 /* Num of addba responses failed */ 538 uint32_t num_addba_rsp_failed; 539 540 /* pn size */ 541 uint8_t pn_size; 542 /* REO TID queue descriptors */ 543 void *hw_qdesc_vaddr_unaligned; 544 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 545 qdf_dma_addr_t hw_qdesc_paddr; 546 uint32_t hw_qdesc_alloc_size; 547 548 /* RX ADDBA session state */ 549 int ba_status; 550 551 /* RX BA window size */ 552 uint16_t ba_win_size; 553 554 /* Starting sequence number in Addba request */ 555 uint16_t startseqnum; 556 557 /* TODO: Check the following while adding defragmentation support */ 558 struct dp_rx_reorder_array_elem *array; 559 /* base - single rx reorder element used for non-aggr cases */ 560 struct dp_rx_reorder_array_elem base; 561 562 /* only used for defrag right now */ 563 TAILQ_ENTRY(dp_rx_tid) defrag_waitlist_elem; 564 565 /* Store dst desc for reinjection */ 566 hal_ring_desc_t dst_ring_desc; 567 struct dp_rx_desc *head_frag_desc; 568 569 /* rx_tid lock */ 570 qdf_spinlock_t tid_lock; 571 572 /* Sequence and fragments that are being processed currently */ 573 uint32_t curr_seq_num; 574 uint32_t curr_frag_num; 575 576 uint32_t defrag_timeout_ms; 577 uint16_t dialogtoken; 578 uint16_t statuscode; 579 /* user defined ADDBA response status code */ 580 uint16_t userstatuscode; 581 582 /* Store ppdu_id when 2k exception is received */ 583 uint32_t ppdu_id_2k; 584 585 /* Delba Tx completion status */ 586 uint8_t delba_tx_status; 587 588 /* Delba Tx retry count */ 589 uint8_t delba_tx_retry; 590 591 /* Delba stats */ 592 uint32_t delba_tx_success_cnt; 593 uint32_t delba_tx_fail_cnt; 594 595 /* Delba reason code for retries */ 596 uint8_t delba_rcode; 597 598 }; 599 600 /** 601 * struct dp_intr_stats - DP Interrupt Stats for an interrupt context 602 * @num_tx_ring_masks: interrupts with tx_ring_mask set 603 * @num_rx_ring_masks: interrupts with rx_ring_mask set 604 * @num_rx_mon_ring_masks: interrupts with rx_mon_ring_mask set 605 * @num_rx_err_ring_masks: interrupts with rx_err_ring_mask set 606 * @num_rx_wbm_rel_ring_masks: interrupts with rx_wbm_rel_ring_mask set 607 * @num_reo_status_ring_masks: interrupts with reo_status_ring_mask set 608 * @num_rxdma2host_ring_masks: interrupts with rxdma2host_ring_mask set 609 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 610 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 611 * @num_masks: total number of times the interrupt was received 612 * 613 * Counter for individual masks are incremented only if there are any packets 614 * on that ring. 615 */ 616 struct dp_intr_stats { 617 uint32_t num_tx_ring_masks[MAX_TCL_DATA_RINGS]; 618 uint32_t num_rx_ring_masks[MAX_REO_DEST_RINGS]; 619 uint32_t num_rx_mon_ring_masks; 620 uint32_t num_rx_err_ring_masks; 621 uint32_t num_rx_wbm_rel_ring_masks; 622 uint32_t num_reo_status_ring_masks; 623 uint32_t num_rxdma2host_ring_masks; 624 uint32_t num_host2rxdma_ring_masks; 625 uint32_t num_masks; 626 }; 627 628 /* per interrupt context */ 629 struct dp_intr { 630 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 631 associated with this napi context */ 632 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 633 with this interrupt context */ 634 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 635 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 636 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 637 uint8_t reo_status_ring_mask; /* REO command response ring */ 638 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 639 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 640 /* Host to RXDMA monitor buffer ring */ 641 uint8_t host2rxdma_mon_ring_mask; 642 struct dp_soc *soc; /* Reference to SoC structure , 643 to get DMA ring handles */ 644 qdf_lro_ctx_t lro_ctx; 645 uint8_t dp_intr_id; 646 647 /* Interrupt Stats for individual masks */ 648 struct dp_intr_stats intr_stats; 649 }; 650 651 #define REO_DESC_FREELIST_SIZE 64 652 #define REO_DESC_FREE_DEFER_MS 1000 653 struct reo_desc_list_node { 654 qdf_list_node_t node; 655 unsigned long free_ts; 656 struct dp_rx_tid rx_tid; 657 bool resend_update_reo_cmd; 658 }; 659 660 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 661 /** 662 * struct reo_cmd_event_record: Elements to record for each reo command 663 * @cmd_type: reo command type 664 * @cmd_return_status: reo command post status 665 * @timestamp: record timestamp for the reo command 666 */ 667 struct reo_cmd_event_record { 668 enum hal_reo_cmd_type cmd_type; 669 uint8_t cmd_return_status; 670 uint32_t timestamp; 671 }; 672 673 /** 674 * struct reo_cmd_event_history: Account for reo cmd events 675 * @index: record number 676 * @cmd_record: list of records 677 */ 678 struct reo_cmd_event_history { 679 qdf_atomic_t index; 680 struct reo_cmd_event_record cmd_record[REO_CMD_EVENT_HIST_MAX]; 681 }; 682 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 683 684 /* SoC level data path statistics */ 685 struct dp_soc_stats { 686 struct { 687 uint32_t added; 688 uint32_t deleted; 689 uint32_t aged_out; 690 uint32_t map_err; 691 } ast; 692 693 /* SOC level TX stats */ 694 struct { 695 /* packets dropped on tx because of no peer */ 696 struct cdp_pkt_info tx_invalid_peer; 697 /* descriptors in each tcl ring */ 698 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 699 /* Descriptors in use at soc */ 700 uint32_t desc_in_use; 701 /* tqm_release_reason == FW removed */ 702 uint32_t dropped_fw_removed; 703 /* tx completion release_src != TQM or FW */ 704 uint32_t invalid_release_source; 705 /* tx completion wbm_internal_error */ 706 uint32_t wbm_internal_error[MAX_WBM_INT_ERROR_REASONS]; 707 /* tx completion non_wbm_internal_error */ 708 uint32_t non_wbm_internal_err; 709 /* TX Comp loop packet limit hit */ 710 uint32_t tx_comp_loop_pkt_limit_hit; 711 /* Head pointer Out of sync at the end of dp_tx_comp_handler */ 712 uint32_t hp_oos2; 713 } tx; 714 715 /* SOC level RX stats */ 716 struct { 717 /* Rx errors */ 718 /* Total Packets in Rx Error ring */ 719 uint32_t err_ring_pkts; 720 /* No of Fragments */ 721 uint32_t rx_frags; 722 /* No of incomplete fragments in waitlist */ 723 uint32_t rx_frag_wait; 724 /* Fragments dropped due to errors */ 725 uint32_t rx_frag_err; 726 /* Fragments dropped due to len errors in skb */ 727 uint32_t rx_frag_err_len_error; 728 /* Fragments dropped due to no peer found */ 729 uint32_t rx_frag_err_no_peer; 730 /* No of reinjected packets */ 731 uint32_t reo_reinject; 732 /* Reap loop packet limit hit */ 733 uint32_t reap_loop_pkt_limit_hit; 734 /* Head pointer Out of sync at the end of dp_rx_process */ 735 uint32_t hp_oos2; 736 /* Rx ring near full */ 737 uint32_t near_full; 738 struct { 739 /* Invalid RBM error count */ 740 uint32_t invalid_rbm; 741 /* Invalid VDEV Error count */ 742 uint32_t invalid_vdev; 743 /* Invalid PDEV error count */ 744 uint32_t invalid_pdev; 745 746 /* Packets delivered to stack that no related peer */ 747 uint32_t pkt_delivered_no_peer; 748 /* Defrag peer uninit error count */ 749 uint32_t defrag_peer_uninit; 750 /* Invalid sa_idx or da_idx*/ 751 uint32_t invalid_sa_da_idx; 752 /* MSDU DONE failures */ 753 uint32_t msdu_done_fail; 754 /* Invalid PEER Error count */ 755 struct cdp_pkt_info rx_invalid_peer; 756 /* Invalid PEER ID count */ 757 struct cdp_pkt_info rx_invalid_peer_id; 758 /* Invalid packet length */ 759 struct cdp_pkt_info rx_invalid_pkt_len; 760 /* HAL ring access Fail error count */ 761 uint32_t hal_ring_access_fail; 762 /* RX DMA error count */ 763 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 764 /* RX REO DEST Desc Invalid Magic count */ 765 uint32_t rx_desc_invalid_magic; 766 /* REO Error count */ 767 uint32_t reo_error[HAL_REO_ERR_MAX]; 768 /* HAL REO ERR Count */ 769 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 770 /* HAL REO DEST Duplicate count */ 771 uint32_t hal_reo_dest_dup; 772 /* HAL WBM RELEASE Duplicate count */ 773 uint32_t hal_wbm_rel_dup; 774 /* HAL RXDMA error Duplicate count */ 775 uint32_t hal_rxdma_err_dup; 776 /* REO cmd send fail/requeue count */ 777 uint32_t reo_cmd_send_fail; 778 } err; 779 780 /* packet count per core - per ring */ 781 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 782 } rx; 783 784 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 785 struct reo_cmd_event_history cmd_event_history; 786 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 787 }; 788 789 union dp_align_mac_addr { 790 uint8_t raw[QDF_MAC_ADDR_SIZE]; 791 struct { 792 uint16_t bytes_ab; 793 uint16_t bytes_cd; 794 uint16_t bytes_ef; 795 } align2; 796 struct { 797 uint32_t bytes_abcd; 798 uint16_t bytes_ef; 799 } align4; 800 struct __attribute__((__packed__)) { 801 uint16_t bytes_ab; 802 uint32_t bytes_cdef; 803 } align4_2; 804 }; 805 806 /** 807 * struct dp_ast_free_cb_params - HMWDS free callback cookie 808 * @mac_addr: ast mac address 809 * @peer_mac_addr: mac address of peer 810 * @type: ast entry type 811 * @vdev_id: vdev_id 812 * @flags: ast flags 813 */ 814 struct dp_ast_free_cb_params { 815 union dp_align_mac_addr mac_addr; 816 union dp_align_mac_addr peer_mac_addr; 817 enum cdp_txrx_ast_entry_type type; 818 uint8_t vdev_id; 819 uint32_t flags; 820 }; 821 822 /* 823 * dp_ast_entry 824 * 825 * @ast_idx: Hardware AST Index 826 * @mac_addr: MAC Address for this AST entry 827 * @peer: Next Hop peer (for non-WDS nodes, this will be point to 828 * associated peer with this MAC address) 829 * @next_hop: Set to 1 if this is for a WDS node 830 * @is_active: flag to indicate active data traffic on this node 831 * (used for aging out/expiry) 832 * @ase_list_elem: node in peer AST list 833 * @is_bss: flag to indicate if entry corresponds to bss peer 834 * @is_mapped: flag to indicate that we have mapped the AST entry 835 * in ast_table 836 * @pdev_id: pdev ID 837 * @vdev_id: vdev ID 838 * @ast_hash_value: hast value in HW 839 * @ref_cnt: reference count 840 * @type: flag to indicate type of the entry(static/WDS/MEC) 841 * @delete_in_progress: Flag to indicate that delete commands send to FW 842 * and host is waiting for response from FW 843 * @callback: ast free/unmap callback 844 * @cookie: argument to callback 845 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 846 */ 847 struct dp_ast_entry { 848 uint16_t ast_idx; 849 union dp_align_mac_addr mac_addr; 850 struct dp_peer *peer; 851 bool next_hop; 852 bool is_active; 853 bool is_mapped; 854 uint8_t pdev_id; 855 uint16_t ast_hash_value; 856 qdf_atomic_t ref_cnt; 857 enum cdp_txrx_ast_entry_type type; 858 bool delete_in_progress; 859 txrx_ast_free_cb callback; 860 void *cookie; 861 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 862 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 863 }; 864 865 /* SOC level htt stats */ 866 struct htt_t2h_stats { 867 /* lock to protect htt_stats_msg update */ 868 qdf_spinlock_t lock; 869 870 /* work queue to process htt stats */ 871 qdf_work_t work; 872 873 /* T2H Ext stats message queue */ 874 qdf_nbuf_queue_t msg; 875 876 /* number of completed stats in htt_stats_msg */ 877 uint32_t num_stats; 878 }; 879 880 /* SOC level structure for data path */ 881 struct dp_soc { 882 /** 883 * re-use memory section starts 884 */ 885 886 /* Common base structure - Should be the first member */ 887 struct cdp_soc_t cdp_soc; 888 889 /* SoC Obj */ 890 struct cdp_ctrl_objmgr_psoc *ctrl_psoc; 891 892 /* OS device abstraction */ 893 qdf_device_t osdev; 894 895 /* WLAN config context */ 896 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 897 898 /* HTT handle for host-fw interaction */ 899 struct htt_soc *htt_handle; 900 901 /* Commint init done */ 902 qdf_atomic_t cmn_init_done; 903 904 /* Opaque hif handle */ 905 struct hif_opaque_softc *hif_handle; 906 907 /* PDEVs on this SOC */ 908 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 909 910 /* Number of PDEVs */ 911 uint8_t pdev_count; 912 913 /*cce disable*/ 914 bool cce_disable; 915 916 /*ast override support in HW*/ 917 bool ast_override_support; 918 919 /*number of hw dscp tid map*/ 920 uint8_t num_hw_dscp_tid_map; 921 922 /* HAL SOC handle */ 923 hal_soc_handle_t hal_soc; 924 925 /* Device ID coming from Bus sub-system */ 926 uint32_t device_id; 927 928 /* Link descriptor memory banks */ 929 struct { 930 void *base_vaddr_unaligned; 931 void *base_vaddr; 932 qdf_dma_addr_t base_paddr_unaligned; 933 qdf_dma_addr_t base_paddr; 934 uint32_t size; 935 } link_desc_banks[MAX_LINK_DESC_BANKS]; 936 937 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 938 struct dp_srng wbm_idle_link_ring; 939 940 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 941 */ 942 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 943 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 944 945 /* Tx SW descriptor pool */ 946 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 947 948 /* Tx MSDU Extension descriptor pool */ 949 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 950 951 /* Tx TSO descriptor pool */ 952 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 953 954 /* Tx TSO Num of segments pool */ 955 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 956 957 /* REO destination rings */ 958 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 959 960 /* REO exception ring - See if should combine this with reo_dest_ring */ 961 struct dp_srng reo_exception_ring; 962 963 /* REO reinjection ring */ 964 struct dp_srng reo_reinject_ring; 965 966 /* REO command ring */ 967 struct dp_srng reo_cmd_ring; 968 969 /* REO command status ring */ 970 struct dp_srng reo_status_ring; 971 972 /* WBM Rx release ring */ 973 struct dp_srng rx_rel_ring; 974 975 /* TCL data ring */ 976 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 977 978 /* Number of TCL data rings */ 979 uint8_t num_tcl_data_rings; 980 981 /* TCL command ring */ 982 struct dp_srng tcl_cmd_ring; 983 984 /* TCL command status ring */ 985 struct dp_srng tcl_status_ring; 986 987 /* WBM Tx completion rings */ 988 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 989 990 /* Common WBM link descriptor release ring (SW to WBM) */ 991 struct dp_srng wbm_desc_rel_ring; 992 993 /* DP Interrupts */ 994 struct dp_intr intr_ctx[WLAN_CFG_INT_NUM_CONTEXTS]; 995 996 /* Rx SW descriptor pool for RXDMA monitor buffer */ 997 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 998 999 /* Rx SW descriptor pool for RXDMA status buffer */ 1000 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 1001 1002 /* Rx SW descriptor pool for RXDMA buffer */ 1003 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 1004 1005 /* Number of REO destination rings */ 1006 uint8_t num_reo_dest_rings; 1007 1008 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1009 /* lock to control access to soc TX descriptors */ 1010 qdf_spinlock_t flow_pool_array_lock; 1011 1012 /* pause callback to pause TX queues as per flow control */ 1013 tx_pause_callback pause_cb; 1014 1015 /* flow pool related statistics */ 1016 struct dp_txrx_pool_stats pool_stats; 1017 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 1018 1019 /* 1020 * Re-use memory section ends. reuse memory indicator. 1021 * Everything above this variable "dp_soc_reinit" is retained across 1022 * WiFi up/down for AP use-cases. 1023 * Everything below this variable "dp_soc_reinit" is reset during 1024 * dp_soc_deinit. 1025 */ 1026 bool dp_soc_reinit; 1027 1028 uint32_t wbm_idle_scatter_buf_size; 1029 1030 /* VDEVs on this SOC */ 1031 struct dp_vdev *vdev_id_map[MAX_VDEV_CNT]; 1032 1033 /* Tx H/W queues lock */ 1034 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 1035 1036 /* Tx ring map for interrupt processing */ 1037 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 1038 1039 /* Rx ring map for interrupt processing */ 1040 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 1041 1042 /* peer ID to peer object map (array of pointers to peer objects) */ 1043 struct dp_peer **peer_id_to_obj_map; 1044 1045 struct { 1046 unsigned mask; 1047 unsigned idx_bits; 1048 TAILQ_HEAD(, dp_peer) * bins; 1049 } peer_hash; 1050 1051 /* rx defrag state – TBD: do we need this per radio? */ 1052 struct { 1053 struct { 1054 TAILQ_HEAD(, dp_rx_tid) waitlist; 1055 uint32_t timeout_ms; 1056 uint32_t next_flush_ms; 1057 qdf_spinlock_t defrag_lock; 1058 } defrag; 1059 struct { 1060 int defrag_timeout_check; 1061 int dup_check; 1062 } flags; 1063 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 1064 qdf_spinlock_t reo_cmd_lock; 1065 } rx; 1066 1067 /* optional rx processing function */ 1068 void (*rx_opt_proc)( 1069 struct dp_vdev *vdev, 1070 struct dp_peer *peer, 1071 unsigned tid, 1072 qdf_nbuf_t msdu_list); 1073 1074 /* pool addr for mcast enhance buff */ 1075 struct { 1076 int size; 1077 uint32_t paddr; 1078 uint32_t *vaddr; 1079 struct dp_tx_me_buf_t *freelist; 1080 int buf_in_use; 1081 qdf_dma_mem_context(memctx); 1082 } me_buf; 1083 1084 /** 1085 * peer ref mutex: 1086 * 1. Protect peer object lookups until the returned peer object's 1087 * reference count is incremented. 1088 * 2. Provide mutex when accessing peer object lookup structures. 1089 */ 1090 DP_MUTEX_TYPE peer_ref_mutex; 1091 1092 /* maximum value for peer_id */ 1093 uint32_t max_peers; 1094 1095 /* SoC level data path statistics */ 1096 struct dp_soc_stats stats; 1097 1098 /* Enable processing of Tx completion status words */ 1099 bool process_tx_status; 1100 bool process_rx_status; 1101 struct dp_ast_entry **ast_table; 1102 struct { 1103 unsigned mask; 1104 unsigned idx_bits; 1105 TAILQ_HEAD(, dp_ast_entry) * bins; 1106 } ast_hash; 1107 1108 qdf_spinlock_t ast_lock; 1109 /*Timer for AST entry ageout maintainance */ 1110 qdf_timer_t ast_aging_timer; 1111 1112 /*Timer counter for WDS AST entry ageout*/ 1113 uint8_t wds_ast_aging_timer_cnt; 1114 1115 /*interrupt timer*/ 1116 qdf_timer_t mon_reap_timer; 1117 uint8_t reap_timer_init; 1118 qdf_timer_t int_timer; 1119 uint8_t intr_mode; 1120 1121 qdf_list_t reo_desc_freelist; 1122 qdf_spinlock_t reo_desc_freelist_lock; 1123 1124 /* htt stats */ 1125 struct htt_t2h_stats htt_stats; 1126 1127 void *external_txrx_handle; /* External data path handle */ 1128 #ifdef IPA_OFFLOAD 1129 /* IPA uC datapath offload Wlan Tx resources */ 1130 struct { 1131 /* Resource info to be passed to IPA */ 1132 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 1133 void *ipa_tcl_ring_base_vaddr; 1134 uint32_t ipa_tcl_ring_size; 1135 qdf_dma_addr_t ipa_tcl_hp_paddr; 1136 uint32_t alloc_tx_buf_cnt; 1137 1138 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 1139 void *ipa_wbm_ring_base_vaddr; 1140 uint32_t ipa_wbm_ring_size; 1141 qdf_dma_addr_t ipa_wbm_tp_paddr; 1142 1143 /* TX buffers populated into the WBM ring */ 1144 void **tx_buf_pool_vaddr_unaligned; 1145 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 1146 } ipa_uc_tx_rsc; 1147 1148 /* IPA uC datapath offload Wlan Rx resources */ 1149 struct { 1150 /* Resource info to be passed to IPA */ 1151 qdf_dma_addr_t ipa_reo_ring_base_paddr; 1152 void *ipa_reo_ring_base_vaddr; 1153 uint32_t ipa_reo_ring_size; 1154 qdf_dma_addr_t ipa_reo_tp_paddr; 1155 1156 /* Resource info to be passed to firmware and IPA */ 1157 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 1158 void *ipa_rx_refill_buf_ring_base_vaddr; 1159 uint32_t ipa_rx_refill_buf_ring_size; 1160 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 1161 } ipa_uc_rx_rsc; 1162 1163 qdf_atomic_t ipa_pipes_enabled; 1164 #endif 1165 1166 #ifdef WLAN_FEATURE_STATS_EXT 1167 struct { 1168 uint32_t rx_mpdu_received; 1169 uint32_t rx_mpdu_missed; 1170 } ext_stats; 1171 qdf_event_t rx_hw_stats_event; 1172 1173 /* Ignore reo command queue status during peer delete */ 1174 bool ignore_reo_status_cb; 1175 #endif 1176 1177 /* Smart monitor capability for HKv2 */ 1178 uint8_t hw_nac_monitor_support; 1179 /* Flag to indicate if HTT v2 is enabled*/ 1180 bool is_peer_map_unmap_v2; 1181 /* Per peer per Tid ba window size support */ 1182 uint8_t per_tid_basize_max_tid; 1183 /* Soc level flag to enable da_war */ 1184 uint8_t da_war_enabled; 1185 /* number of active ast entries */ 1186 uint32_t num_ast_entries; 1187 /* rdk rate statistics context at soc level*/ 1188 struct cdp_soc_rate_stats_ctx *rate_stats_ctx; 1189 /* rdk rate statistics control flag */ 1190 bool wlanstats_enabled; 1191 1192 /* 8021p PCP-TID map values */ 1193 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 1194 /* TID map priority value */ 1195 uint8_t tidmap_prty; 1196 /* Pointer to global per ring type specific configuration table */ 1197 struct wlan_srng_cfg *wlan_srng_cfg; 1198 /* Num Tx outstanding on device */ 1199 qdf_atomic_t num_tx_outstanding; 1200 /* Num Tx allowed */ 1201 uint32_t num_tx_allowed; 1202 1203 /** 1204 * Flag to indicate whether WAR to address single cache entry 1205 * invalidation bug is enabled or not 1206 */ 1207 bool is_rx_fse_full_cache_invalidate_war_enabled; 1208 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 1209 /** 1210 * Pointer to DP RX Flow FST at SOC level if 1211 * is_rx_flow_search_table_per_pdev is false 1212 */ 1213 struct dp_rx_fst *rx_fst; 1214 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 1215 }; 1216 1217 #ifdef IPA_OFFLOAD 1218 /** 1219 * dp_ipa_resources - Resources needed for IPA 1220 */ 1221 struct dp_ipa_resources { 1222 qdf_shared_mem_t tx_ring; 1223 uint32_t tx_num_alloc_buffer; 1224 1225 qdf_shared_mem_t tx_comp_ring; 1226 qdf_shared_mem_t rx_rdy_ring; 1227 qdf_shared_mem_t rx_refill_ring; 1228 1229 /* IPA UC doorbell registers paddr */ 1230 qdf_dma_addr_t tx_comp_doorbell_paddr; 1231 uint32_t *tx_comp_doorbell_vaddr; 1232 qdf_dma_addr_t rx_ready_doorbell_paddr; 1233 }; 1234 #endif 1235 1236 #define MAX_RX_MAC_RINGS 2 1237 /* Same as NAC_MAX_CLENT */ 1238 #define DP_NAC_MAX_CLIENT 24 1239 1240 /* 1241 * Macros to setup link descriptor cookies - for link descriptors, we just 1242 * need first 3 bits to store bank ID. The remaining bytes will be used set a 1243 * unique ID, which will be useful in debugging 1244 */ 1245 #define LINK_DESC_BANK_ID_MASK 0x7 1246 #define LINK_DESC_ID_SHIFT 3 1247 #define LINK_DESC_ID_START 0x8000 1248 1249 #define LINK_DESC_COOKIE(_desc_id, _bank_id) \ 1250 ((((_desc_id) + LINK_DESC_ID_START) << LINK_DESC_ID_SHIFT) | (_bank_id)) 1251 1252 #define LINK_DESC_COOKIE_BANK_ID(_cookie) \ 1253 ((_cookie) & LINK_DESC_BANK_ID_MASK) 1254 1255 /* same as ieee80211_nac_param */ 1256 enum dp_nac_param_cmd { 1257 /* IEEE80211_NAC_PARAM_ADD */ 1258 DP_NAC_PARAM_ADD = 1, 1259 /* IEEE80211_NAC_PARAM_DEL */ 1260 DP_NAC_PARAM_DEL, 1261 /* IEEE80211_NAC_PARAM_LIST */ 1262 DP_NAC_PARAM_LIST, 1263 }; 1264 1265 /** 1266 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 1267 * @neighbour_peers_macaddr: neighbour peer's mac address 1268 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 1269 * @ast_entry: ast_entry for neighbour peer 1270 * @rssi: rssi value 1271 */ 1272 struct dp_neighbour_peer { 1273 /* MAC address of neighbour's peer */ 1274 union dp_align_mac_addr neighbour_peers_macaddr; 1275 struct dp_vdev *vdev; 1276 struct dp_ast_entry *ast_entry; 1277 uint8_t rssi; 1278 /* node in the list of neighbour's peer */ 1279 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 1280 }; 1281 1282 #ifdef WLAN_TX_PKT_CAPTURE_ENH 1283 #define WLAN_TX_PKT_CAPTURE_ENH 1 1284 #define DP_TX_PPDU_PROC_THRESHOLD 8 1285 #define DP_TX_PPDU_PROC_TIMEOUT 10 1286 #endif 1287 1288 /** 1289 * struct ppdu_info - PPDU Status info descriptor 1290 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 1291 * @sched_cmdid - schedule command id, which will be same in a burst 1292 * @max_ppdu_id - wrap around for ppdu id 1293 * @last_tlv_cnt - Keep track for missing ppdu tlvs 1294 * @last_user - last ppdu processed for user 1295 * @is_ampdu - set if Ampdu aggregate 1296 * @nbuf - ppdu descriptor payload 1297 * @ppdu_desc - ppdu descriptor 1298 * @ppdu_info_list_elem - linked list of ppdu tlvs 1299 * @ppdu_info_queue_elem - Singly linked list (queue) of ppdu tlvs 1300 * @mpdu_compltn_common_tlv - Successful MPDU counter from COMPLTN COMMON tlv 1301 * @mpdu_ack_ba_tlv - Successful MPDU from ACK BA tlv 1302 */ 1303 struct ppdu_info { 1304 uint32_t ppdu_id; 1305 uint32_t sched_cmdid; 1306 uint32_t max_ppdu_id; 1307 uint16_t tlv_bitmap; 1308 uint16_t last_tlv_cnt; 1309 uint16_t last_user:8, 1310 is_ampdu:1; 1311 qdf_nbuf_t nbuf; 1312 struct cdp_tx_completion_ppdu *ppdu_desc; 1313 #ifdef WLAN_TX_PKT_CAPTURE_ENH 1314 union { 1315 TAILQ_ENTRY(ppdu_info) ppdu_info_dlist_elem; 1316 STAILQ_ENTRY(ppdu_info) ppdu_info_slist_elem; 1317 } ulist; 1318 #define ppdu_info_list_elem ulist.ppdu_info_dlist_elem 1319 #define ppdu_info_queue_elem ulist.ppdu_info_slist_elem 1320 #else 1321 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 1322 #endif 1323 uint16_t mpdu_compltn_common_tlv; 1324 uint16_t mpdu_ack_ba_tlv; 1325 }; 1326 1327 /** 1328 * struct msdu_completion_info - wbm msdu completion info 1329 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 1330 * @peer_id - peer_id 1331 * @tid - tid which used during transmit 1332 * @first_msdu - first msdu indication 1333 * @last_msdu - last msdu indication 1334 * @msdu_part_of_amsdu - msdu part of amsdu 1335 * @transmit_cnt - retried count 1336 * @status - transmit status 1337 * @tsf - timestamp which it transmitted 1338 */ 1339 struct msdu_completion_info { 1340 uint32_t ppdu_id; 1341 uint16_t peer_id; 1342 uint8_t tid; 1343 uint8_t first_msdu:1, 1344 last_msdu:1, 1345 msdu_part_of_amsdu:1; 1346 uint8_t transmit_cnt; 1347 uint8_t status; 1348 uint32_t tsf; 1349 }; 1350 1351 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 1352 struct rx_protocol_tag_map { 1353 /* This is the user configured tag for the said protocol type */ 1354 uint16_t tag; 1355 }; 1356 1357 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 1358 struct rx_protocol_tag_stats { 1359 uint32_t tag_ctr; 1360 }; 1361 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 1362 1363 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 1364 1365 #ifndef WLAN_TX_PKT_CAPTURE_ENH 1366 struct dp_pdev_tx_capture { 1367 }; 1368 1369 struct dp_peer_tx_capture { 1370 }; 1371 #endif 1372 #ifdef WLAN_RX_PKT_CAPTURE_ENH 1373 /* Template data to be set for Enhanced RX Monitor packets */ 1374 #define RX_MON_CAP_ENH_TRAILER 0xdeadc0dedeadda7a 1375 1376 /** 1377 * struct dp_rx_mon_enh_trailer_data - Data structure to set a known pattern 1378 * at end of each MSDU in monitor-lite mode 1379 * @reserved1: reserved for future use 1380 * @reserved2: reserved for future use 1381 * @flow_tag: flow tag value read from skb->cb 1382 * @protocol_tag: protocol tag value read from skb->cb 1383 */ 1384 struct dp_rx_mon_enh_trailer_data { 1385 uint16_t reserved1; 1386 uint16_t reserved2; 1387 uint16_t flow_tag; 1388 uint16_t protocol_tag; 1389 }; 1390 #endif /* WLAN_RX_PKT_CAPTURE_ENH */ 1391 1392 /* PDEV level structure for data path */ 1393 struct dp_pdev { 1394 /** 1395 * Re-use Memory Section Starts 1396 */ 1397 1398 /* PDEV Id */ 1399 int pdev_id; 1400 1401 /* LMAC Id */ 1402 int lmac_id; 1403 1404 /* TXRX SOC handle */ 1405 struct dp_soc *soc; 1406 1407 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 1408 struct dp_srng rx_refill_buf_ring; 1409 1410 /* RXDMA error destination ring */ 1411 struct dp_srng rxdma_err_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1412 1413 /* Link descriptor memory banks */ 1414 struct { 1415 void *base_vaddr_unaligned; 1416 void *base_vaddr; 1417 qdf_dma_addr_t base_paddr_unaligned; 1418 qdf_dma_addr_t base_paddr; 1419 uint32_t size; 1420 } link_desc_banks[NUM_RXDMA_RINGS_PER_PDEV][MAX_MON_LINK_DESC_BANKS]; 1421 1422 /* RXDMA monitor buffer replenish ring */ 1423 struct dp_srng rxdma_mon_buf_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1424 1425 /* RXDMA monitor destination ring */ 1426 struct dp_srng rxdma_mon_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1427 1428 /* RXDMA monitor status ring. TBD: Check format of this ring */ 1429 struct dp_srng rxdma_mon_status_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1430 1431 struct dp_srng rxdma_mon_desc_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1432 1433 /* Stuck count on monitor destination ring MPDU process */ 1434 uint32_t mon_dest_ring_stuck_cnt; 1435 1436 /* 1437 * re-use memory section ends 1438 * reuse memory/deinit indicator 1439 * 1440 * DO NOT CHANGE NAME OR MOVE THIS VARIABLE 1441 */ 1442 bool pdev_deinit; 1443 1444 /* pdev status down or up required to handle dynamic hw 1445 * mode switch between DBS and DBS_SBS. 1446 * 1 = down 1447 * 0 = up 1448 */ 1449 bool is_pdev_down; 1450 1451 /* Second ring used to replenish rx buffers */ 1452 struct dp_srng rx_refill_buf_ring2; 1453 1454 /* Empty ring used by firmware to post rx buffers to the MAC */ 1455 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 1456 1457 /* wlan_cfg pdev ctxt*/ 1458 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 1459 1460 /** 1461 * TODO: See if we need a ring map here for LMAC rings. 1462 * 1. Monitor rings are currently planning to be processed on receiving 1463 * PPDU end interrupts and hence wont need ring based interrupts. 1464 * 2. Rx buffer rings will be replenished during REO destination 1465 * processing and doesn't require regular interrupt handling - we will 1466 * only handle low water mark interrupts which is not expected 1467 * frequently 1468 */ 1469 1470 /* VDEV list */ 1471 TAILQ_HEAD(, dp_vdev) vdev_list; 1472 1473 /* vdev list lock */ 1474 qdf_spinlock_t vdev_list_lock; 1475 1476 /* Number of vdevs this device have */ 1477 uint16_t vdev_count; 1478 1479 /* PDEV transmit lock */ 1480 qdf_spinlock_t tx_lock; 1481 1482 #ifndef REMOVE_PKT_LOG 1483 bool pkt_log_init; 1484 /* Pktlog pdev */ 1485 struct pktlog_dev_t *pl_dev; 1486 #endif /* #ifndef REMOVE_PKT_LOG */ 1487 1488 /* Monitor mode interface and status storage */ 1489 struct dp_vdev *monitor_vdev; 1490 1491 /* Monitor mode operation channel */ 1492 int mon_chan_num; 1493 1494 /* monitor mode lock */ 1495 qdf_spinlock_t mon_lock; 1496 1497 /*tx_mutex for me*/ 1498 DP_MUTEX_TYPE tx_mutex; 1499 1500 /* monitor */ 1501 bool monitor_configured; 1502 1503 /* Smart Mesh */ 1504 bool filter_neighbour_peers; 1505 1506 /*flag to indicate neighbour_peers_list not empty */ 1507 bool neighbour_peers_added; 1508 /* smart mesh mutex */ 1509 qdf_spinlock_t neighbour_peer_mutex; 1510 /* Neighnour peer list */ 1511 TAILQ_HEAD(, dp_neighbour_peer) neighbour_peers_list; 1512 /* msdu chain head & tail */ 1513 qdf_nbuf_t invalid_peer_head_msdu; 1514 qdf_nbuf_t invalid_peer_tail_msdu; 1515 1516 /* Band steering */ 1517 /* TBD */ 1518 1519 /* PDEV level data path statistics */ 1520 struct cdp_pdev_stats stats; 1521 1522 /* Global RX decap mode for the device */ 1523 enum htt_pkt_type rx_decap_mode; 1524 1525 /* Enhanced Stats is enabled */ 1526 bool enhanced_stats_en; 1527 1528 /* advance filter mode and type*/ 1529 uint8_t mon_filter_mode; 1530 uint16_t fp_mgmt_filter; 1531 uint16_t fp_ctrl_filter; 1532 uint16_t fp_data_filter; 1533 uint16_t mo_mgmt_filter; 1534 uint16_t mo_ctrl_filter; 1535 uint16_t mo_data_filter; 1536 uint16_t md_data_filter; 1537 1538 qdf_atomic_t num_tx_outstanding; 1539 1540 qdf_atomic_t num_tx_exception; 1541 1542 /* MCL specific local peer handle */ 1543 struct { 1544 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 1545 uint8_t freelist; 1546 qdf_spinlock_t lock; 1547 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 1548 } local_peer_ids; 1549 1550 /* dscp_tid_map_*/ 1551 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 1552 1553 struct hal_rx_ppdu_info ppdu_info; 1554 1555 /* operating channel */ 1556 uint8_t operating_channel; 1557 1558 qdf_nbuf_queue_t rx_status_q; 1559 uint32_t mon_ppdu_status; 1560 struct cdp_mon_status rx_mon_recv_status; 1561 /* monitor mode status/destination ring PPDU and MPDU count */ 1562 struct cdp_pdev_mon_stats rx_mon_stats; 1563 /* to track duplicate link descriptor indications by HW for a WAR */ 1564 uint64_t mon_last_linkdesc_paddr; 1565 /* to track duplicate buffer indications by HW for a WAR */ 1566 uint32_t mon_last_buf_cookie; 1567 /* 128 bytes mpdu header queue per user for ppdu */ 1568 qdf_nbuf_queue_t mpdu_q[MAX_MU_USERS]; 1569 /* is this a mpdu header TLV and not msdu header TLV */ 1570 bool is_mpdu_hdr[MAX_MU_USERS]; 1571 /* per user 128 bytes msdu header list for MPDU */ 1572 struct msdu_list msdu_list[MAX_MU_USERS]; 1573 /* RX enhanced capture mode */ 1574 uint8_t rx_enh_capture_mode; 1575 /* Rx per peer enhanced capture mode */ 1576 bool rx_enh_capture_peer; 1577 struct dp_vdev *rx_enh_monitor_vdev; 1578 /* RX enhanced capture trailer enable/disable flag */ 1579 bool is_rx_enh_capture_trailer_enabled; 1580 #ifdef WLAN_RX_PKT_CAPTURE_ENH 1581 /* RX per MPDU/PPDU information */ 1582 struct cdp_rx_indication_mpdu mpdu_ind; 1583 #endif 1584 /* pool addr for mcast enhance buff */ 1585 struct { 1586 int size; 1587 uint32_t paddr; 1588 char *vaddr; 1589 struct dp_tx_me_buf_t *freelist; 1590 int buf_in_use; 1591 qdf_dma_mem_context(memctx); 1592 } me_buf; 1593 1594 bool hmmc_tid_override_en; 1595 uint8_t hmmc_tid; 1596 1597 /* Number of VAPs with mcast enhancement enabled */ 1598 qdf_atomic_t mc_num_vap_attached; 1599 1600 qdf_atomic_t stats_cmd_complete; 1601 1602 #ifdef IPA_OFFLOAD 1603 ipa_uc_op_cb_type ipa_uc_op_cb; 1604 void *usr_ctxt; 1605 struct dp_ipa_resources ipa_resource; 1606 #endif 1607 1608 /* TBD */ 1609 1610 /* map this pdev to a particular Reo Destination ring */ 1611 enum cdp_host_reo_dest_ring reo_dest; 1612 1613 #ifndef REMOVE_PKT_LOG 1614 /* Packet log mode */ 1615 uint8_t rx_pktlog_mode; 1616 #endif 1617 1618 /* WDI event handlers */ 1619 struct wdi_event_subscribe_t **wdi_event_list; 1620 1621 /* ppdu_id of last received HTT TX stats */ 1622 uint32_t last_ppdu_id; 1623 struct { 1624 uint8_t last_user; 1625 qdf_nbuf_t buf; 1626 } tx_ppdu_info; 1627 1628 bool tx_sniffer_enable; 1629 /* mirror copy mode */ 1630 bool mcopy_mode; 1631 bool cfr_rcc_mode; 1632 bool bpr_enable; 1633 1634 /* enable time latency check for tx completion */ 1635 bool latency_capture_enable; 1636 1637 /* enable calculation of delay stats*/ 1638 bool delay_stats_flag; 1639 struct { 1640 uint16_t tx_ppdu_id; 1641 uint16_t tx_peer_id; 1642 uint16_t rx_ppdu_id; 1643 } m_copy_id; 1644 1645 /* To check if PPDU Tx stats are enabled for Pktlog */ 1646 bool pktlog_ppdu_stats; 1647 1648 void *dp_txrx_handle; /* Advanced data path handle */ 1649 1650 #ifdef ATH_SUPPORT_NAC_RSSI 1651 bool nac_rssi_filtering; 1652 #endif 1653 /* list of ppdu tlvs */ 1654 TAILQ_HEAD(, ppdu_info) ppdu_info_list; 1655 uint32_t tlv_count; 1656 uint32_t list_depth; 1657 uint32_t ppdu_id; 1658 bool first_nbuf; 1659 struct { 1660 qdf_nbuf_t last_nbuf; /*Ptr to mgmt last buf */ 1661 uint8_t *mgmt_buf; /* Ptr to mgmt. payload in HTT ppdu stats */ 1662 uint32_t mgmt_buf_len; /* Len of mgmt. payload in ppdu stats */ 1663 uint32_t ppdu_id; 1664 } mgmtctrl_frm_info; 1665 1666 /* Current noise-floor reading for the pdev channel */ 1667 int16_t chan_noise_floor; 1668 1669 /* 1670 * For multiradio device, this flag indicates if 1671 * this radio is primary or secondary. 1672 * 1673 * For HK 1.0, this is used for WAR for the AST issue. 1674 * HK 1.x mandates creation of only 1 AST entry with same MAC address 1675 * across 2 radios. is_primary indicates the radio on which DP should 1676 * install HW AST entry if there is a request to add 2 AST entries 1677 * with same MAC address across 2 radios 1678 */ 1679 uint8_t is_primary; 1680 /* Context of cal client timer */ 1681 struct cdp_cal_client *cal_client_ctx; 1682 struct cdp_tx_sojourn_stats sojourn_stats; 1683 qdf_nbuf_t sojourn_buf; 1684 1685 /* peer pointer for collecting invalid peer stats */ 1686 struct dp_peer *invalid_peer; 1687 1688 union dp_rx_desc_list_elem_t *free_list_head; 1689 union dp_rx_desc_list_elem_t *free_list_tail; 1690 /* Pdev level flag to check peer based pktlog enabled or 1691 * disabled 1692 */ 1693 uint8_t dp_peer_based_pktlog; 1694 1695 /* Cached peer_id from htt_peer_details_tlv */ 1696 uint16_t fw_stats_peer_id; 1697 1698 /* qdf_event for fw_peer_stats */ 1699 qdf_event_t fw_peer_stats_event; 1700 1701 /* User configured max number of tx buffers */ 1702 uint32_t num_tx_allowed; 1703 1704 /* unique cookie required for peer session */ 1705 uint32_t next_peer_cookie; 1706 1707 /* 1708 * Run time enabled when the first protocol tag is added, 1709 * run time disabled when the last protocol tag is deleted 1710 */ 1711 bool is_rx_protocol_tagging_enabled; 1712 1713 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 1714 /* 1715 * The protocol type is used as array index to save 1716 * user provided tag info 1717 */ 1718 struct rx_protocol_tag_map rx_proto_tag_map[RX_PROTOCOL_TAG_MAX]; 1719 1720 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 1721 /* 1722 * Track msdus received from each reo ring separately to avoid 1723 * simultaneous writes from different core 1724 */ 1725 struct rx_protocol_tag_stats 1726 reo_proto_tag_stats[MAX_REO_DEST_RINGS][RX_PROTOCOL_TAG_MAX]; 1727 /* Track msdus received from expection ring separately */ 1728 struct rx_protocol_tag_stats 1729 rx_err_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 1730 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 1731 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 1732 1733 /* tx packet capture enhancement */ 1734 enum cdp_tx_enh_capture_mode tx_capture_enabled; 1735 struct dp_pdev_tx_capture tx_capture; 1736 /* stats counter for tx ppdu processed */ 1737 uint64_t tx_ppdu_proc; 1738 1739 uint32_t *ppdu_tlv_buf; /* Buffer to hold HTT ppdu stats TLVs*/ 1740 1741 /* nbuf queue to maintain rx ppdu status buffer 1742 * belonging to one ppdu 1743 */ 1744 qdf_nbuf_queue_t rx_ppdu_buf_q; 1745 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 1746 /** 1747 * Pointer to DP Flow FST at SOC level if 1748 * is_rx_flow_search_table_per_pdev is true 1749 */ 1750 struct dp_rx_fst *rx_fst; 1751 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 1752 1753 #ifdef FEATURE_TSO_STATS 1754 /* TSO Id to index into TSO packet information */ 1755 qdf_atomic_t tso_idx; 1756 #endif /* FEATURE_TSO_STATS */ 1757 1758 #ifdef WLAN_SUPPORT_DATA_STALL 1759 data_stall_detect_cb data_stall_detect_callback; 1760 #endif /* WLAN_SUPPORT_DATA_STALL */ 1761 }; 1762 1763 struct dp_peer; 1764 1765 /* VDEV structure for data path state */ 1766 struct dp_vdev { 1767 /* OS device abstraction */ 1768 qdf_device_t osdev; 1769 /* physical device that is the parent of this virtual device */ 1770 struct dp_pdev *pdev; 1771 1772 /* Handle to the OS shim SW's virtual device */ 1773 ol_osif_vdev_handle osif_vdev; 1774 1775 /* vdev_id - ID used to specify a particular vdev to the target */ 1776 uint8_t vdev_id; 1777 1778 /* MAC address */ 1779 union dp_align_mac_addr mac_addr; 1780 1781 /* node in the pdev's list of vdevs */ 1782 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 1783 1784 /* dp_peer list */ 1785 TAILQ_HEAD(, dp_peer) peer_list; 1786 1787 /* RX call back function to flush GRO packets*/ 1788 ol_txrx_rx_gro_flush_ind_fp osif_gro_flush; 1789 /* default RX call back function called by dp */ 1790 ol_txrx_rx_fp osif_rx; 1791 /* callback to deliver rx frames to the OS */ 1792 ol_txrx_rx_fp osif_rx_stack; 1793 /* call back function to flush out queued rx packets*/ 1794 ol_txrx_rx_flush_fp osif_rx_flush; 1795 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 1796 ol_txrx_get_key_fp osif_get_key; 1797 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 1798 1799 #ifdef notyet 1800 /* callback to check if the msdu is an WAI (WAPI) frame */ 1801 ol_rx_check_wai_fp osif_check_wai; 1802 #endif 1803 1804 /* proxy arp function */ 1805 ol_txrx_proxy_arp_fp osif_proxy_arp; 1806 1807 /* callback to hand rx monitor 802.11 MPDU to the OS shim */ 1808 ol_txrx_rx_mon_fp osif_rx_mon; 1809 1810 ol_txrx_mcast_me_fp me_convert; 1811 1812 /* completion function used by this vdev*/ 1813 ol_txrx_completion_fp tx_comp; 1814 1815 /* deferred vdev deletion state */ 1816 struct { 1817 /* VDEV delete pending */ 1818 int pending; 1819 /* 1820 * callback and a context argument to provide a 1821 * notification for when the vdev is deleted. 1822 */ 1823 ol_txrx_vdev_delete_cb callback; 1824 void *context; 1825 } delete; 1826 1827 /* tx data delivery notification callback function */ 1828 struct { 1829 ol_txrx_data_tx_cb func; 1830 void *ctxt; 1831 } tx_non_std_data_callback; 1832 1833 1834 /* safe mode control to bypass the encrypt and decipher process*/ 1835 uint32_t safemode; 1836 1837 /* rx filter related */ 1838 uint32_t drop_unenc; 1839 #ifdef notyet 1840 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 1841 uint32_t filters_num; 1842 #endif 1843 /* TDLS Link status */ 1844 bool tdls_link_connected; 1845 bool is_tdls_frame; 1846 1847 1848 /* VDEV operating mode */ 1849 enum wlan_op_mode opmode; 1850 1851 /* VDEV subtype */ 1852 enum wlan_op_subtype subtype; 1853 1854 /* Tx encapsulation type for this VAP */ 1855 enum htt_cmn_pkt_type tx_encap_type; 1856 /* Rx Decapsulation type for this VAP */ 1857 enum htt_cmn_pkt_type rx_decap_type; 1858 1859 /* BSS peer */ 1860 struct dp_peer *vap_bss_peer; 1861 1862 /* WDS enabled */ 1863 bool wds_enabled; 1864 1865 /* MEC enabled */ 1866 bool mec_enabled; 1867 1868 /* WDS Aging timer period */ 1869 uint32_t wds_aging_timer_val; 1870 1871 /* NAWDS enabled */ 1872 bool nawds_enabled; 1873 1874 /* Default HTT meta data for this VDEV */ 1875 /* TBD: check alignment constraints */ 1876 uint16_t htt_tcl_metadata; 1877 1878 /* Mesh mode vdev */ 1879 uint32_t mesh_vdev; 1880 1881 /* Mesh mode rx filter setting */ 1882 uint32_t mesh_rx_filter; 1883 1884 /* DSCP-TID mapping table ID */ 1885 uint8_t dscp_tid_map_id; 1886 1887 /* Multicast enhancement enabled */ 1888 uint8_t mcast_enhancement_en; 1889 1890 /* per vdev rx nbuf queue */ 1891 qdf_nbuf_queue_t rxq; 1892 1893 uint8_t tx_ring_id; 1894 struct dp_tx_desc_pool_s *tx_desc; 1895 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 1896 1897 /* VDEV Stats */ 1898 struct cdp_vdev_stats stats; 1899 1900 /* Is this a proxySTA VAP */ 1901 bool proxysta_vdev; 1902 /* Is isolation mode enabled */ 1903 bool isolation_vdev; 1904 1905 /* Address search flags to be configured in HAL descriptor */ 1906 uint8_t hal_desc_addr_search_flags; 1907 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1908 struct dp_tx_desc_pool_s *pool; 1909 #endif 1910 /* AP BRIDGE enabled */ 1911 uint32_t ap_bridge_enabled; 1912 1913 enum cdp_sec_type sec_type; 1914 1915 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 1916 bool raw_mode_war; 1917 1918 /* Address search type to be set in TX descriptor */ 1919 uint8_t search_type; 1920 1921 /* AST hash value for BSS peer in HW valid for STA VAP*/ 1922 uint16_t bss_ast_hash; 1923 1924 /* AST hash index for BSS peer in HW valid for STA VAP*/ 1925 uint16_t bss_ast_idx; 1926 1927 /* Capture timestamp of previous tx packet enqueued */ 1928 uint64_t prev_tx_enq_tstamp; 1929 1930 /* Capture timestamp of previous rx packet delivered */ 1931 uint64_t prev_rx_deliver_tstamp; 1932 1933 /* 8021p PCP-TID mapping table ID */ 1934 uint8_t tidmap_tbl_id; 1935 1936 /* 8021p PCP-TID map values */ 1937 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 1938 1939 /* TIDmap priority */ 1940 uint8_t tidmap_prty; 1941 /* Self Peer in STA mode */ 1942 struct dp_peer *vap_self_peer; 1943 1944 bool multipass_en; 1945 #ifdef QCA_MULTIPASS_SUPPORT 1946 uint16_t *iv_vlan_map; 1947 1948 /* dp_peer special list */ 1949 TAILQ_HEAD(, dp_peer) mpass_peer_list; 1950 DP_MUTEX_TYPE mpass_peer_mutex; 1951 #endif 1952 }; 1953 1954 1955 enum { 1956 dp_sec_mcast = 0, 1957 dp_sec_ucast 1958 }; 1959 1960 #ifdef WDS_VENDOR_EXTENSION 1961 typedef struct { 1962 uint8_t wds_tx_mcast_4addr:1, 1963 wds_tx_ucast_4addr:1, 1964 wds_rx_filter:1, /* enforce rx filter */ 1965 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 1966 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 1967 1968 } dp_ecm_policy; 1969 #endif 1970 1971 /* 1972 * struct dp_peer_cached_bufq - cached_bufq to enqueue rx packets 1973 * @cached_bufq: nbuff list to enqueue rx packets 1974 * @bufq_lock: spinlock for nbuff list access 1975 * @thres: maximum threshold for number of rx buff to enqueue 1976 * @entries: number of entries 1977 * @dropped: number of packets dropped 1978 */ 1979 struct dp_peer_cached_bufq { 1980 qdf_list_t cached_bufq; 1981 qdf_spinlock_t bufq_lock; 1982 uint32_t thresh; 1983 uint32_t entries; 1984 uint32_t dropped; 1985 }; 1986 1987 /* Peer structure for data path state */ 1988 struct dp_peer { 1989 /* VDEV to which this peer is associated */ 1990 struct dp_vdev *vdev; 1991 1992 struct dp_ast_entry *self_ast_entry; 1993 1994 qdf_atomic_t ref_cnt; 1995 1996 /* TODO: See if multiple peer IDs are required in wifi3.0 */ 1997 /* peer ID(s) for this peer */ 1998 uint16_t peer_ids[MAX_NUM_PEER_ID_PER_PEER]; 1999 2000 union dp_align_mac_addr mac_addr; 2001 2002 /* node in the vdev's list of peers */ 2003 TAILQ_ENTRY(dp_peer) peer_list_elem; 2004 /* node in the hash table bin's list of peers */ 2005 TAILQ_ENTRY(dp_peer) hash_list_elem; 2006 2007 /* TID structures */ 2008 struct dp_rx_tid rx_tid[DP_MAX_TIDS]; 2009 struct dp_peer_tx_capture tx_capture; 2010 2011 2012 /* TBD: No transmit TID state required? */ 2013 2014 struct { 2015 enum cdp_sec_type sec_type; 2016 u_int32_t michael_key[2]; /* relevant for TKIP */ 2017 } security[2]; /* 0 -> multicast, 1 -> unicast */ 2018 2019 /* NAWDS Flag and Bss Peer bit */ 2020 uint8_t nawds_enabled:1, /* NAWDS flag */ 2021 bss_peer:1, /* set for bss peer */ 2022 wds_enabled:1, /* WDS peer */ 2023 authorize:1, /* Set when authorized */ 2024 nac:1, /* NAC Peer*/ 2025 tx_cap_enabled:1, /* Peer's tx-capture is enabled */ 2026 rx_cap_enabled:1, /* Peer's rx-capture is enabled */ 2027 valid:1; /* valid bit */ 2028 2029 /* MCL specific peer local id */ 2030 uint16_t local_id; 2031 enum ol_txrx_peer_state state; 2032 qdf_spinlock_t peer_info_lock; 2033 2034 /* Peer Stats */ 2035 struct cdp_peer_stats stats; 2036 2037 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 2038 /* TBD */ 2039 2040 #ifdef WDS_VENDOR_EXTENSION 2041 dp_ecm_policy wds_ecm; 2042 #endif 2043 bool delete_in_progress; 2044 2045 /* Active Block ack sessions */ 2046 uint16_t active_ba_session_cnt; 2047 2048 /* Current HW buffersize setting */ 2049 uint16_t hw_buffer_size; 2050 2051 /* 2052 * Flag to check if sessions with 256 buffersize 2053 * should be terminated. 2054 */ 2055 uint8_t kill_256_sessions; 2056 qdf_atomic_t is_default_route_set; 2057 /* Peer level flag to check peer based pktlog enabled or 2058 * disabled 2059 */ 2060 uint8_t peer_based_pktlog_filter; 2061 2062 /* rdk statistics context */ 2063 struct cdp_peer_rate_stats_ctx *wlanstats_ctx; 2064 /* average sojourn time */ 2065 qdf_ewma_tx_lag avg_sojourn_msdu[CDP_DATA_TID_MAX]; 2066 2067 #ifdef QCA_MULTIPASS_SUPPORT 2068 /* node in the special peer list element */ 2069 TAILQ_ENTRY(dp_peer) mpass_peer_list_elem; 2070 /* vlan id for key */ 2071 uint16_t vlan_id; 2072 #endif 2073 2074 #ifdef PEER_CACHE_RX_PKTS 2075 qdf_atomic_t flush_in_progress; 2076 struct dp_peer_cached_bufq bufq_info; 2077 #endif 2078 #ifdef FEATURE_PERPKT_INFO 2079 /* delayed ba ppdu stats handling */ 2080 struct cdp_delayed_tx_completion_ppdu_user delayed_ba_ppdu_stats; 2081 /* delayed ba flag */ 2082 bool last_delayed_ba; 2083 /* delayed ba ppdu id */ 2084 uint32_t last_delayed_ba_ppduid; 2085 #endif 2086 }; 2087 2088 /* 2089 * dp_invalid_peer_msg 2090 * @nbuf: data buffer 2091 * @wh: 802.11 header 2092 * @vdev_id: id of vdev 2093 */ 2094 struct dp_invalid_peer_msg { 2095 qdf_nbuf_t nbuf; 2096 struct ieee80211_frame *wh; 2097 uint8_t vdev_id; 2098 }; 2099 2100 /* 2101 * dp_tx_me_buf_t: ME buffer 2102 * next: pointer to next buffer 2103 * data: Destination Mac address 2104 */ 2105 struct dp_tx_me_buf_t { 2106 /* Note: ME buf pool initialization logic expects next pointer to 2107 * be the first element. Dont add anything before next */ 2108 struct dp_tx_me_buf_t *next; 2109 uint8_t data[QDF_MAC_ADDR_SIZE]; 2110 }; 2111 2112 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 2113 struct hal_rx_fst; 2114 2115 struct dp_rx_fse { 2116 /* HAL Rx Flow Search Entry which matches HW definition */ 2117 void *hal_rx_fse; 2118 /* Toeplitz hash value */ 2119 uint32_t flow_hash; 2120 /* Flow index, equivalent to hash value truncated to FST size */ 2121 uint32_t flow_id; 2122 /* Stats tracking for this flow */ 2123 struct cdp_flow_stats stats; 2124 /* Flag indicating whether flow is IPv4 address tuple */ 2125 bool is_ipv4_addr_entry; 2126 /* Flag indicating whether flow is valid */ 2127 bool is_valid; 2128 }; 2129 2130 struct dp_rx_fst { 2131 /* Software (DP) FST */ 2132 uint8_t *base; 2133 /* Pointer to HAL FST */ 2134 struct hal_rx_fst *hal_rx_fst; 2135 /* Base physical address of HAL RX HW FST */ 2136 uint64_t hal_rx_fst_base_paddr; 2137 /* Maximum number of flows FSE supports */ 2138 uint16_t max_entries; 2139 /* Num entries in flow table */ 2140 uint16_t num_entries; 2141 /* SKID Length */ 2142 uint16_t max_skid_length; 2143 /* Hash mask to obtain legitimate hash entry */ 2144 uint32_t hash_mask; 2145 /* Timer for bundling of flows */ 2146 qdf_timer_t cache_invalidate_timer; 2147 /** 2148 * Flag which tracks whether cache update 2149 * is needed on timer expiry 2150 */ 2151 qdf_atomic_t is_cache_update_pending; 2152 /* Flag to indicate completion of FSE setup in HW/FW */ 2153 bool fse_setup_done; 2154 }; 2155 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 2156 2157 #endif /* _DP_TYPES_H_ */ 2158