1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DP_TYPES_H_ 20 #define _DP_TYPES_H_ 21 22 #include <qdf_types.h> 23 #include <qdf_nbuf.h> 24 #include <qdf_lock.h> 25 #include <qdf_atomic.h> 26 #include <qdf_util.h> 27 #include <qdf_list.h> 28 #include <qdf_lro.h> 29 #include <queue.h> 30 #include <htt_common.h> 31 32 #include <cdp_txrx_cmn.h> 33 #ifdef CONFIG_MCL 34 #include <cds_ieee80211_common.h> 35 #else 36 #include <linux/ieee80211.h> 37 #endif 38 39 #ifndef CONFIG_WIN 40 #include <wdi_event_api.h> /* WDI subscriber event list */ 41 #endif 42 43 #include "hal_hw_headers.h" 44 #include <hal_tx.h> 45 #include <hal_reo.h> 46 #include "wlan_cfg.h" 47 #include "hal_rx.h" 48 #include <hal_api.h> 49 #include <hal_api_mon.h> 50 #include "hal_rx.h" 51 52 #define MAX_BW 7 53 #define MAX_RETRIES 4 54 #define MAX_RECEPTION_TYPES 4 55 56 #ifndef REMOVE_PKT_LOG 57 #include <pktlog.h> 58 #endif 59 60 #define REPT_MU_MIMO 1 61 #define REPT_MU_OFDMA_MIMO 3 62 #define DP_VO_TID 6 63 64 #define DP_MAX_INTERRUPT_CONTEXTS 8 65 #define DP_MAX_TID_MAPS 16 /* MAX TID MAPS AVAILABLE PER PDEV*/ 66 #define DSCP_TID_MAP_MAX (64) 67 #define DP_IP_DSCP_SHIFT 2 68 #define DP_IP_DSCP_MASK 0x3f 69 #define DP_FC0_SUBTYPE_QOS 0x80 70 #define DP_QOS_TID 0x0f 71 #define DP_IPV6_PRIORITY_SHIFT 20 72 #define MAX_MON_LINK_DESC_BANKS 2 73 #define DP_VDEV_ALL 0xff 74 75 #if defined(CONFIG_MCL) 76 #define MAX_PDEV_CNT 1 77 #else 78 #define MAX_PDEV_CNT 3 79 #endif 80 81 #define MAX_LINK_DESC_BANKS 8 82 #define MAX_TXDESC_POOLS 4 83 #define MAX_RXDESC_POOLS 4 84 #define MAX_REO_DEST_RINGS 4 85 #define MAX_TCL_DATA_RINGS 4 86 #define MAX_IDLE_SCATTER_BUFS 16 87 #define DP_MAX_IRQ_PER_CONTEXT 12 88 #define DP_MAX_INTERRUPT_CONTEXTS 8 89 #define DEFAULT_HW_PEER_ID 0xffff 90 91 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 92 93 #define DP_MAX_INTERRUPT_CONTEXTS 8 94 95 /* Maximum retries for Delba per tid per peer */ 96 #define DP_MAX_DELBA_RETRY 3 97 98 #ifndef REMOVE_PKT_LOG 99 enum rx_pktlog_mode { 100 DP_RX_PKTLOG_DISABLED = 0, 101 DP_RX_PKTLOG_FULL, 102 DP_RX_PKTLOG_LITE, 103 }; 104 #endif 105 106 struct dp_soc_cmn; 107 struct dp_pdev; 108 struct dp_vdev; 109 struct dp_tx_desc_s; 110 struct dp_soc; 111 union dp_rx_desc_list_elem_t; 112 113 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 114 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 115 116 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 117 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 118 119 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 120 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 121 122 #define DP_MUTEX_TYPE qdf_spinlock_t 123 124 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 125 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 126 127 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 128 ((_a)[0] == 0x33 && \ 129 (_a)[1] == 0x33) 130 131 #define DP_FRAME_IS_BROADCAST(_a) \ 132 ((_a)[0] == 0xff && \ 133 (_a)[1] == 0xff && \ 134 (_a)[2] == 0xff && \ 135 (_a)[3] == 0xff && \ 136 (_a)[4] == 0xff && \ 137 (_a)[5] == 0xff) 138 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 139 (_llc)->llc_ssap == 0xaa && \ 140 (_llc)->llc_un.type_snap.control == 0x3) 141 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 142 #define DP_FRAME_FC0_TYPE_MASK 0x0c 143 #define DP_FRAME_FC0_TYPE_DATA 0x08 144 #define DP_FRAME_IS_DATA(_frame) \ 145 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 146 147 /** 148 * macros to convert hw mac id to sw mac id: 149 * mac ids used by hardware start from a value of 1 while 150 * those in host software start from a value of 0. Use the 151 * macros below to convert between mac ids used by software and 152 * hardware 153 */ 154 #define DP_SW2HW_MACID(id) ((id) + 1) 155 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 156 #define DP_MAC_ADDR_LEN 6 157 158 /** 159 * enum dp_intr_mode 160 * @DP_INTR_LEGACY: Legacy/Line interrupts, for WIN 161 * @DP_INTR_MSI: MSI interrupts, for MCL 162 * @DP_INTR_POLL: Polling 163 */ 164 enum dp_intr_mode { 165 DP_INTR_LEGACY = 0, 166 DP_INTR_MSI, 167 DP_INTR_POLL, 168 }; 169 170 /** 171 * enum dp_tx_frm_type 172 * @dp_tx_frm_std: Regular frame, no added header fragments 173 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 174 * @dp_tx_frm_sg: SG segment 175 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 176 * @dp_tx_frm_me: Multicast to Unicast Converted frame 177 * @dp_tx_frm_raw: Raw Frame 178 */ 179 enum dp_tx_frm_type { 180 dp_tx_frm_std = 0, 181 dp_tx_frm_tso, 182 dp_tx_frm_sg, 183 dp_tx_frm_audio, 184 dp_tx_frm_me, 185 dp_tx_frm_raw, 186 }; 187 188 /** 189 * enum dp_ast_type 190 * @dp_ast_type_wds: WDS peer AST type 191 * @dp_ast_type_static: static ast entry type 192 * @dp_ast_type_mec: Multicast echo ast entry type 193 */ 194 enum dp_ast_type { 195 dp_ast_type_wds = 0, 196 dp_ast_type_static, 197 dp_ast_type_mec, 198 }; 199 200 /** 201 * enum dp_nss_cfg 202 * @dp_nss_cfg_default: No radios are offloaded 203 * @dp_nss_cfg_first_radio: First radio offloaded 204 * @dp_nss_cfg_second_radio: Second radio offloaded 205 * @dp_nss_cfg_dbdc: Dual radios offloaded 206 */ 207 enum dp_nss_cfg { 208 dp_nss_cfg_default, 209 dp_nss_cfg_first_radio, 210 dp_nss_cfg_second_radio, 211 dp_nss_cfg_dbdc, 212 }; 213 214 /** 215 * struct rx_desc_pool 216 * @pool_size: number of RX descriptor in the pool 217 * @array: pointer to array of RX descriptor 218 * @freelist: pointer to free RX descriptor link list 219 * @lock: Protection for the RX descriptor pool 220 * @owner: owner for nbuf 221 */ 222 struct rx_desc_pool { 223 uint32_t pool_size; 224 union dp_rx_desc_list_elem_t *array; 225 union dp_rx_desc_list_elem_t *freelist; 226 qdf_spinlock_t lock; 227 uint8_t owner; 228 }; 229 230 /** 231 * struct dp_tx_ext_desc_elem_s 232 * @next: next extension descriptor pointer 233 * @vaddr: hlos virtual address pointer 234 * @paddr: physical address pointer for descriptor 235 */ 236 struct dp_tx_ext_desc_elem_s { 237 struct dp_tx_ext_desc_elem_s *next; 238 void *vaddr; 239 qdf_dma_addr_t paddr; 240 }; 241 242 /** 243 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 244 * @elem_count: Number of descriptors in the pool 245 * @elem_size: Size of each descriptor 246 * @num_free: Number of free descriptors 247 * @msdu_ext_desc: MSDU extension descriptor 248 * @desc_pages: multiple page allocation information for actual descriptors 249 * @link_elem_size: size of the link descriptor in cacheable memory used for 250 * chaining the extension descriptors 251 * @desc_link_pages: multiple page allocation information for link descriptors 252 */ 253 struct dp_tx_ext_desc_pool_s { 254 uint16_t elem_count; 255 int elem_size; 256 uint16_t num_free; 257 struct qdf_mem_multi_page_t desc_pages; 258 int link_elem_size; 259 struct qdf_mem_multi_page_t desc_link_pages; 260 struct dp_tx_ext_desc_elem_s *freelist; 261 qdf_spinlock_t lock; 262 qdf_dma_mem_context(memctx); 263 }; 264 265 /** 266 * struct dp_tx_desc_s - Tx Descriptor 267 * @next: Next in the chain of descriptors in freelist or in the completion list 268 * @nbuf: Buffer Address 269 * @msdu_ext_desc: MSDU extension descriptor 270 * @id: Descriptor ID 271 * @vdev: vdev over which the packet was transmitted 272 * @pdev: Handle to pdev 273 * @pool_id: Pool ID - used when releasing the descriptor 274 * @flags: Flags to track the state of descriptor and special frame handling 275 * @comp: Pool ID - used when releasing the descriptor 276 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 277 * This is maintained in descriptor to allow more efficient 278 * processing in completion event processing code. 279 * This field is filled in with the htt_pkt_type enum. 280 * @frm_type: Frame Type - ToDo check if this is redundant 281 * @pkt_offset: Offset from which the actual packet data starts 282 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 283 * Tx completion of ME packet 284 * @pool: handle to flow_pool this descriptor belongs to. 285 */ 286 struct dp_tx_desc_s { 287 struct dp_tx_desc_s *next; 288 qdf_nbuf_t nbuf; 289 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 290 uint32_t id; 291 struct dp_vdev *vdev; 292 struct dp_pdev *pdev; 293 uint8_t pool_id; 294 uint16_t flags; 295 struct hal_tx_desc_comp_s comp; 296 uint16_t tx_encap_type; 297 uint8_t frm_type; 298 uint8_t pkt_offset; 299 void *me_buffer; 300 void *tso_desc; 301 void *tso_num_desc; 302 }; 303 304 /** 305 * enum flow_pool_status - flow pool status 306 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 307 * and network queues are unpaused 308 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 309 * and network queues are paused 310 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 311 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 312 */ 313 enum flow_pool_status { 314 FLOW_POOL_ACTIVE_UNPAUSED = 0, 315 FLOW_POOL_ACTIVE_PAUSED = 1, 316 FLOW_POOL_INVALID = 2, 317 FLOW_POOL_INACTIVE = 3, 318 }; 319 320 /** 321 * struct dp_tx_tso_seg_pool_s 322 * @pool_size: total number of pool elements 323 * @num_free: free element count 324 * @freelist: first free element pointer 325 * @lock: lock for accessing the pool 326 */ 327 struct dp_tx_tso_seg_pool_s { 328 uint16_t pool_size; 329 uint16_t num_free; 330 struct qdf_tso_seg_elem_t *freelist; 331 qdf_spinlock_t lock; 332 }; 333 334 /** 335 * struct dp_tx_tso_num_seg_pool_s { 336 * @num_seg_pool_size: total number of pool elements 337 * @num_free: free element count 338 * @freelist: first free element pointer 339 * @lock: lock for accessing the pool 340 */ 341 342 struct dp_tx_tso_num_seg_pool_s { 343 uint16_t num_seg_pool_size; 344 uint16_t num_free; 345 struct qdf_tso_num_seg_elem_t *freelist; 346 /*tso mutex */ 347 qdf_spinlock_t lock; 348 }; 349 350 /** 351 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 352 * @elem_size: Size of each descriptor in the pool 353 * @pool_size: Total number of descriptors in the pool 354 * @num_free: Number of free descriptors 355 * @num_allocated: Number of used descriptors 356 * @freelist: Chain of free descriptors 357 * @desc_pages: multiple page allocation information for actual descriptors 358 * @num_invalid_bin: Deleted pool with pending Tx completions. 359 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 360 * @flow_pool_array: List of allocated flow pools 361 * @lock- Lock for descriptor allocation/free from/to the pool 362 */ 363 struct dp_tx_desc_pool_s { 364 uint16_t elem_size; 365 uint32_t num_allocated; 366 struct dp_tx_desc_s *freelist; 367 struct qdf_mem_multi_page_t desc_pages; 368 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 369 uint16_t pool_size; 370 uint8_t flow_pool_id; 371 uint8_t num_invalid_bin; 372 uint16_t avail_desc; 373 enum flow_pool_status status; 374 enum htt_flow_type flow_type; 375 uint16_t stop_th; 376 uint16_t start_th; 377 uint16_t pkt_drop_no_desc; 378 qdf_spinlock_t flow_pool_lock; 379 uint8_t pool_create_cnt; 380 void *pool_owner_ctx; 381 #else 382 uint16_t elem_count; 383 uint32_t num_free; 384 qdf_spinlock_t lock; 385 #endif 386 }; 387 388 /** 389 * struct dp_txrx_pool_stats - flow pool related statistics 390 * @pool_map_count: flow pool map received 391 * @pool_unmap_count: flow pool unmap received 392 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 393 */ 394 struct dp_txrx_pool_stats { 395 uint16_t pool_map_count; 396 uint16_t pool_unmap_count; 397 uint16_t pkt_drop_no_pool; 398 }; 399 400 struct dp_srng { 401 void *hal_srng; 402 void *base_vaddr_unaligned; 403 qdf_dma_addr_t base_paddr_unaligned; 404 uint32_t alloc_size; 405 int irq; 406 uint32_t num_entries; 407 }; 408 409 struct dp_rx_reorder_array_elem { 410 qdf_nbuf_t head; 411 qdf_nbuf_t tail; 412 }; 413 414 #define DP_RX_BA_INACTIVE 0 415 #define DP_RX_BA_ACTIVE 1 416 #define DP_RX_BA_IN_PROGRESS 2 417 struct dp_reo_cmd_info { 418 uint16_t cmd; 419 enum hal_reo_cmd_type cmd_type; 420 void *data; 421 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 422 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 423 }; 424 425 /* Rx TID */ 426 struct dp_rx_tid { 427 /* TID */ 428 int tid; 429 430 /* Num of addba requests */ 431 uint32_t num_of_addba_req; 432 433 /* Num of addba responses */ 434 uint32_t num_of_addba_resp; 435 436 /* Num of delba requests */ 437 uint32_t num_of_delba_req; 438 439 /* Num of addba responses successful */ 440 uint32_t num_addba_rsp_success; 441 442 /* Num of addba responses failed */ 443 uint32_t num_addba_rsp_failed; 444 445 /* pn size */ 446 uint8_t pn_size; 447 /* REO TID queue descriptors */ 448 void *hw_qdesc_vaddr_unaligned; 449 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 450 qdf_dma_addr_t hw_qdesc_paddr; 451 uint32_t hw_qdesc_alloc_size; 452 453 /* RX ADDBA session state */ 454 int ba_status; 455 456 /* RX BA window size */ 457 uint16_t ba_win_size; 458 459 /* Starting sequence number in Addba request */ 460 uint16_t startseqnum; 461 462 /* TODO: Check the following while adding defragmentation support */ 463 struct dp_rx_reorder_array_elem *array; 464 /* base - single rx reorder element used for non-aggr cases */ 465 struct dp_rx_reorder_array_elem base; 466 467 /* only used for defrag right now */ 468 TAILQ_ENTRY(dp_rx_tid) defrag_waitlist_elem; 469 470 /* Store dst desc for reinjection */ 471 void *dst_ring_desc; 472 struct dp_rx_desc *head_frag_desc; 473 474 /* rx_tid lock */ 475 qdf_spinlock_t tid_lock; 476 477 /* Sequence and fragments that are being processed currently */ 478 uint32_t curr_seq_num; 479 uint32_t curr_frag_num; 480 481 uint32_t defrag_timeout_ms; 482 uint16_t dialogtoken; 483 uint16_t statuscode; 484 /* user defined ADDBA response status code */ 485 uint16_t userstatuscode; 486 487 /* Store ppdu_id when 2k exception is received */ 488 uint32_t ppdu_id_2k; 489 490 /* Delba Tx completion status */ 491 uint8_t delba_tx_status; 492 493 /* Delba Tx retry count */ 494 uint8_t delba_tx_retry; 495 496 /* Delba stats */ 497 uint32_t delba_tx_success_cnt; 498 uint32_t delba_tx_fail_cnt; 499 500 }; 501 502 /* per interrupt context */ 503 struct dp_intr { 504 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 505 associated with this napi context */ 506 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 507 with this interrupt context */ 508 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 509 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 510 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 511 uint8_t reo_status_ring_mask; /* REO command response ring */ 512 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 513 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 514 struct dp_soc *soc; /* Reference to SoC structure , 515 to get DMA ring handles */ 516 qdf_lro_ctx_t lro_ctx; 517 uint8_t dp_intr_id; 518 }; 519 520 #define REO_DESC_FREELIST_SIZE 64 521 #define REO_DESC_FREE_DEFER_MS 1000 522 struct reo_desc_list_node { 523 qdf_list_node_t node; 524 unsigned long free_ts; 525 struct dp_rx_tid rx_tid; 526 }; 527 528 /* SoC level data path statistics */ 529 struct dp_soc_stats { 530 struct { 531 uint32_t added; 532 uint32_t deleted; 533 uint32_t aged_out; 534 } ast; 535 536 /* SOC level TX stats */ 537 struct { 538 /* packets dropped on tx because of no peer */ 539 struct cdp_pkt_info tx_invalid_peer; 540 /* descriptors in each tcl ring */ 541 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 542 /* Descriptors in use at soc */ 543 uint32_t desc_in_use; 544 /* tqm_release_reason == FW removed */ 545 uint32_t dropped_fw_removed; 546 547 } tx; 548 549 /* SOC level RX stats */ 550 struct { 551 /* Rx errors */ 552 /* Total Packets in Rx Error ring */ 553 uint32_t err_ring_pkts; 554 /* No of Fragments */ 555 uint32_t rx_frags; 556 struct { 557 /* Invalid RBM error count */ 558 uint32_t invalid_rbm; 559 /* Invalid VDEV Error count */ 560 uint32_t invalid_vdev; 561 /* Invalid PDEV error count */ 562 uint32_t invalid_pdev; 563 /* Invalid PEER Error count */ 564 struct cdp_pkt_info rx_invalid_peer; 565 /* HAL ring access Fail error count */ 566 uint32_t hal_ring_access_fail; 567 /* RX DMA error count */ 568 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 569 /* REO Error count */ 570 uint32_t reo_error[HAL_REO_ERR_MAX]; 571 /* HAL REO ERR Count */ 572 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 573 } err; 574 575 /* packet count per core - per ring */ 576 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 577 } rx; 578 }; 579 580 #define DP_MAC_ADDR_LEN 6 581 union dp_align_mac_addr { 582 uint8_t raw[DP_MAC_ADDR_LEN]; 583 struct { 584 uint16_t bytes_ab; 585 uint16_t bytes_cd; 586 uint16_t bytes_ef; 587 } align2; 588 struct { 589 uint32_t bytes_abcd; 590 uint16_t bytes_ef; 591 } align4; 592 struct { 593 uint16_t bytes_ab; 594 uint32_t bytes_cdef; 595 } align4_2; 596 }; 597 598 /* 599 * dp_ast_entry 600 * 601 * @ast_idx: Hardware AST Index 602 * @mac_addr: MAC Address for this AST entry 603 * @peer: Next Hop peer (for non-WDS nodes, this will be point to 604 * associated peer with this MAC address) 605 * @next_hop: Set to 1 if this is for a WDS node 606 * @is_active: flag to indicate active data traffic on this node 607 * (used for aging out/expiry) 608 * @ase_list_elem: node in peer AST list 609 * @is_bss: flag to indicate if entry corresponds to bss peer 610 * @pdev_id: pdev ID 611 * @vdev_id: vdev ID 612 * @type: flag to indicate type of the entry(static/WDS/MEC) 613 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 614 */ 615 struct dp_ast_entry { 616 uint16_t ast_idx; 617 /* MAC address */ 618 union dp_align_mac_addr mac_addr; 619 struct dp_peer *peer; 620 bool next_hop; 621 bool is_active; 622 bool is_bss; 623 uint8_t pdev_id; 624 uint8_t vdev_id; 625 enum cdp_txrx_ast_entry_type type; 626 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 627 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 628 }; 629 630 /* SOC level htt stats */ 631 struct htt_t2h_stats { 632 /* lock to protect htt_stats_msg update */ 633 qdf_spinlock_t lock; 634 635 /* work queue to process htt stats */ 636 qdf_work_t work; 637 638 /* T2H Ext stats message queue */ 639 qdf_nbuf_queue_t msg; 640 641 /* number of completed stats in htt_stats_msg */ 642 uint32_t num_stats; 643 }; 644 645 /* SOC level structure for data path */ 646 struct dp_soc { 647 /* Common base structure - Should be the first member */ 648 struct cdp_soc_t cdp_soc; 649 650 /* SoC Obj */ 651 void *ctrl_psoc; 652 653 /* OS device abstraction */ 654 qdf_device_t osdev; 655 656 /* WLAN config context */ 657 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 658 659 /* HTT handle for host-fw interaction */ 660 void *htt_handle; 661 662 /* Commint init done */ 663 qdf_atomic_t cmn_init_done; 664 665 /* Opaque hif handle */ 666 struct hif_opaque_softc *hif_handle; 667 668 /* PDEVs on this SOC */ 669 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 670 671 /* Number of PDEVs */ 672 uint8_t pdev_count; 673 674 /*cce disable*/ 675 bool cce_disable; 676 677 /* Link descriptor memory banks */ 678 struct { 679 void *base_vaddr_unaligned; 680 void *base_vaddr; 681 qdf_dma_addr_t base_paddr_unaligned; 682 qdf_dma_addr_t base_paddr; 683 uint32_t size; 684 } link_desc_banks[MAX_LINK_DESC_BANKS]; 685 686 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 687 struct dp_srng wbm_idle_link_ring; 688 689 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 690 */ 691 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 692 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 693 uint32_t wbm_idle_scatter_buf_size; 694 695 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 696 qdf_spinlock_t flow_pool_array_lock; 697 tx_pause_callback pause_cb; 698 struct dp_txrx_pool_stats pool_stats; 699 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 700 /* Tx SW descriptor pool */ 701 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 702 703 /* Tx MSDU Extension descriptor pool */ 704 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 705 706 /* Tx TSO descriptor pool */ 707 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 708 709 /* Tx TSO Num of segments pool */ 710 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 711 712 /* Tx H/W queues lock */ 713 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 714 715 /* Rx SW descriptor pool for RXDMA buffer */ 716 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 717 718 /* Rx SW descriptor pool for RXDMA monitor buffer */ 719 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 720 721 /* Rx SW descriptor pool for RXDMA status buffer */ 722 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 723 724 /* HAL SOC handle */ 725 void *hal_soc; 726 727 /* DP Interrupts */ 728 struct dp_intr intr_ctx[DP_MAX_INTERRUPT_CONTEXTS]; 729 730 /* REO destination rings */ 731 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 732 733 /* Number of REO destination rings */ 734 uint8_t num_reo_dest_rings; 735 736 /* REO exception ring - See if should combine this with reo_dest_ring */ 737 struct dp_srng reo_exception_ring; 738 739 /* REO reinjection ring */ 740 struct dp_srng reo_reinject_ring; 741 742 /* REO command ring */ 743 struct dp_srng reo_cmd_ring; 744 745 /* REO command status ring */ 746 struct dp_srng reo_status_ring; 747 748 /* WBM Rx release ring */ 749 struct dp_srng rx_rel_ring; 750 751 /* Number of TCL data rings */ 752 uint8_t num_tcl_data_rings; 753 754 /* TCL data ring */ 755 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 756 757 /* TCL command ring */ 758 struct dp_srng tcl_cmd_ring; 759 760 /* TCL command status ring */ 761 struct dp_srng tcl_status_ring; 762 763 /* WBM Tx completion rings */ 764 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 765 766 /* Common WBM link descriptor release ring (SW to WBM) */ 767 struct dp_srng wbm_desc_rel_ring; 768 769 /* Tx ring map for interrupt processing */ 770 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 771 772 /* Rx ring map for interrupt processing */ 773 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 774 775 /* peer ID to peer object map (array of pointers to peer objects) */ 776 struct dp_peer **peer_id_to_obj_map; 777 778 struct { 779 unsigned mask; 780 unsigned idx_bits; 781 TAILQ_HEAD(, dp_peer) * bins; 782 } peer_hash; 783 784 /* rx defrag state – TBD: do we need this per radio? */ 785 struct { 786 struct { 787 TAILQ_HEAD(, dp_rx_tid) waitlist; 788 uint32_t timeout_ms; 789 qdf_spinlock_t defrag_lock; 790 } defrag; 791 struct { 792 int defrag_timeout_check; 793 int dup_check; 794 } flags; 795 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 796 qdf_spinlock_t reo_cmd_lock; 797 } rx; 798 799 /* optional rx processing function */ 800 void (*rx_opt_proc)( 801 struct dp_vdev *vdev, 802 struct dp_peer *peer, 803 unsigned tid, 804 qdf_nbuf_t msdu_list); 805 806 /* pool addr for mcast enhance buff */ 807 struct { 808 int size; 809 uint32_t paddr; 810 uint32_t *vaddr; 811 struct dp_tx_me_buf_t *freelist; 812 int buf_in_use; 813 qdf_dma_mem_context(memctx); 814 } me_buf; 815 816 /** 817 * peer ref mutex: 818 * 1. Protect peer object lookups until the returned peer object's 819 * reference count is incremented. 820 * 2. Provide mutex when accessing peer object lookup structures. 821 */ 822 DP_MUTEX_TYPE peer_ref_mutex; 823 824 /* maximum value for peer_id */ 825 uint32_t max_peers; 826 827 /* SoC level data path statistics */ 828 struct dp_soc_stats stats; 829 830 /* Enable processing of Tx completion status words */ 831 bool process_tx_status; 832 bool process_rx_status; 833 struct dp_ast_entry *ast_table[WLAN_UMAC_PSOC_MAX_PEERS * 2]; 834 struct { 835 unsigned mask; 836 unsigned idx_bits; 837 TAILQ_HEAD(, dp_ast_entry) * bins; 838 } ast_hash; 839 840 qdf_spinlock_t ast_lock; 841 qdf_timer_t wds_aging_timer; 842 843 /*interrupt timer*/ 844 qdf_timer_t mon_reap_timer; 845 uint8_t reap_timer_init; 846 qdf_timer_t int_timer; 847 uint8_t intr_mode; 848 849 qdf_list_t reo_desc_freelist; 850 qdf_spinlock_t reo_desc_freelist_lock; 851 852 #ifdef QCA_SUPPORT_SON 853 /* The timer to check station's inactivity status */ 854 os_timer_t pdev_bs_inact_timer; 855 /* The current inactivity count reload value 856 based on overload condition */ 857 u_int16_t pdev_bs_inact_reload; 858 859 /* The inactivity timer value when not overloaded */ 860 u_int16_t pdev_bs_inact_normal; 861 862 /* The inactivity timer value when overloaded */ 863 u_int16_t pdev_bs_inact_overload; 864 865 /* The inactivity timer check interval */ 866 u_int16_t pdev_bs_inact_interval; 867 /* Inactivity timer */ 868 #endif /* QCA_SUPPORT_SON */ 869 870 /* htt stats */ 871 struct htt_t2h_stats htt_stats; 872 873 void *external_txrx_handle; /* External data path handle */ 874 #ifdef IPA_OFFLOAD 875 /* IPA uC datapath offload Wlan Tx resources */ 876 struct { 877 /* Resource info to be passed to IPA */ 878 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 879 void *ipa_tcl_ring_base_vaddr; 880 uint32_t ipa_tcl_ring_size; 881 qdf_dma_addr_t ipa_tcl_hp_paddr; 882 uint32_t alloc_tx_buf_cnt; 883 884 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 885 void *ipa_wbm_ring_base_vaddr; 886 uint32_t ipa_wbm_ring_size; 887 qdf_dma_addr_t ipa_wbm_tp_paddr; 888 889 /* TX buffers populated into the WBM ring */ 890 void **tx_buf_pool_vaddr_unaligned; 891 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 892 } ipa_uc_tx_rsc; 893 894 /* IPA uC datapath offload Wlan Rx resources */ 895 struct { 896 /* Resource info to be passed to IPA */ 897 qdf_dma_addr_t ipa_reo_ring_base_paddr; 898 void *ipa_reo_ring_base_vaddr; 899 uint32_t ipa_reo_ring_size; 900 qdf_dma_addr_t ipa_reo_tp_paddr; 901 902 /* Resource info to be passed to firmware and IPA */ 903 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 904 void *ipa_rx_refill_buf_ring_base_vaddr; 905 uint32_t ipa_rx_refill_buf_ring_size; 906 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 907 } ipa_uc_rx_rsc; 908 #endif 909 /* Device ID coming from Bus sub-system */ 910 uint32_t device_id; 911 }; 912 913 #ifdef IPA_OFFLOAD 914 /** 915 * dp_ipa_resources - Resources needed for IPA 916 */ 917 struct dp_ipa_resources { 918 qdf_dma_addr_t tx_ring_base_paddr; 919 uint32_t tx_ring_size; 920 uint32_t tx_num_alloc_buffer; 921 922 qdf_dma_addr_t tx_comp_ring_base_paddr; 923 uint32_t tx_comp_ring_size; 924 925 qdf_dma_addr_t rx_rdy_ring_base_paddr; 926 uint32_t rx_rdy_ring_size; 927 928 qdf_dma_addr_t rx_refill_ring_base_paddr; 929 uint32_t rx_refill_ring_size; 930 931 /* IPA UC doorbell registers paddr */ 932 qdf_dma_addr_t tx_comp_doorbell_paddr; 933 uint32_t *tx_comp_doorbell_vaddr; 934 qdf_dma_addr_t rx_ready_doorbell_paddr; 935 }; 936 #endif 937 938 #define MAX_RX_MAC_RINGS 2 939 /* Same as NAC_MAX_CLENT */ 940 #define DP_NAC_MAX_CLIENT 24 941 942 /* 943 * Macros to setup link descriptor cookies - for link descriptors, we just 944 * need first 3 bits to store bank ID. The remaining bytes will be used set a 945 * unique ID, which will be useful in debugging 946 */ 947 #define LINK_DESC_BANK_ID_MASK 0x7 948 #define LINK_DESC_ID_SHIFT 3 949 #define LINK_DESC_ID_START 0x8000 950 951 #define LINK_DESC_COOKIE(_desc_id, _bank_id) \ 952 ((((_desc_id) + LINK_DESC_ID_START) << LINK_DESC_ID_SHIFT) | (_bank_id)) 953 954 #define LINK_DESC_COOKIE_BANK_ID(_cookie) \ 955 ((_cookie) & LINK_DESC_BANK_ID_MASK) 956 957 /* same as ieee80211_nac_param */ 958 enum dp_nac_param_cmd { 959 /* IEEE80211_NAC_PARAM_ADD */ 960 DP_NAC_PARAM_ADD = 1, 961 /* IEEE80211_NAC_PARAM_DEL */ 962 DP_NAC_PARAM_DEL, 963 /* IEEE80211_NAC_PARAM_LIST */ 964 DP_NAC_PARAM_LIST, 965 }; 966 967 /** 968 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 969 * @neighbour_peers_macaddr: neighbour peer's mac address 970 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 971 * @ast_entry: ast_entry for neighbour peer 972 * @rssi: rssi value 973 */ 974 struct dp_neighbour_peer { 975 /* MAC address of neighbour's peer */ 976 union dp_align_mac_addr neighbour_peers_macaddr; 977 struct dp_vdev *vdev; 978 struct dp_ast_entry *ast_entry; 979 uint8_t rssi; 980 /* node in the list of neighbour's peer */ 981 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 982 }; 983 984 /** 985 * struct ppdu_info - PPDU Status info descriptor 986 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 987 * @max_ppdu_id - wrap around for ppdu id 988 * @last_tlv_cnt - Keep track for missing ppdu tlvs 989 * @last_user - last ppdu processed for user 990 * @is_ampdu - set if Ampdu aggregate 991 * @nbuf - ppdu descriptor payload 992 * @ppdu_desc - ppdu descriptor 993 * @ppdu_info_list_elem - linked list of ppdu tlvs 994 */ 995 struct ppdu_info { 996 uint32_t ppdu_id; 997 uint32_t max_ppdu_id; 998 uint16_t tlv_bitmap; 999 uint16_t last_tlv_cnt; 1000 uint16_t last_user:8, 1001 is_ampdu:1; 1002 qdf_nbuf_t nbuf; 1003 struct cdp_tx_completion_ppdu *ppdu_desc; 1004 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 1005 }; 1006 1007 /* PDEV level structure for data path */ 1008 struct dp_pdev { 1009 /* PDEV handle from OSIF layer TBD: see if we really need osif_pdev */ 1010 struct cdp_ctrl_objmgr_pdev *ctrl_pdev; 1011 1012 /* PDEV Id */ 1013 int pdev_id; 1014 1015 /* TXRX SOC handle */ 1016 struct dp_soc *soc; 1017 1018 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 1019 struct dp_srng rx_refill_buf_ring; 1020 1021 /* Second ring used to replenish rx buffers */ 1022 struct dp_srng rx_refill_buf_ring2; 1023 1024 /* Empty ring used by firmware to post rx buffers to the MAC */ 1025 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 1026 1027 /* wlan_cfg pdev ctxt*/ 1028 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 1029 1030 /* RXDMA monitor buffer replenish ring */ 1031 struct dp_srng rxdma_mon_buf_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1032 1033 /* RXDMA monitor destination ring */ 1034 struct dp_srng rxdma_mon_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1035 1036 /* RXDMA monitor status ring. TBD: Check format of this ring */ 1037 struct dp_srng rxdma_mon_status_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1038 1039 struct dp_srng rxdma_mon_desc_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1040 1041 /* RXDMA error destination ring */ 1042 struct dp_srng rxdma_err_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1043 1044 /* Link descriptor memory banks */ 1045 struct { 1046 void *base_vaddr_unaligned; 1047 void *base_vaddr; 1048 qdf_dma_addr_t base_paddr_unaligned; 1049 qdf_dma_addr_t base_paddr; 1050 uint32_t size; 1051 } link_desc_banks[NUM_RXDMA_RINGS_PER_PDEV][MAX_MON_LINK_DESC_BANKS]; 1052 1053 1054 /** 1055 * TODO: See if we need a ring map here for LMAC rings. 1056 * 1. Monitor rings are currently planning to be processed on receiving 1057 * PPDU end interrupts and hence wont need ring based interrupts. 1058 * 2. Rx buffer rings will be replenished during REO destination 1059 * processing and doesn't require regular interrupt handling - we will 1060 * only handle low water mark interrupts which is not expected 1061 * frequently 1062 */ 1063 1064 /* VDEV list */ 1065 TAILQ_HEAD(, dp_vdev) vdev_list; 1066 1067 /* vdev list lock */ 1068 qdf_spinlock_t vdev_list_lock; 1069 1070 /* Number of vdevs this device have */ 1071 uint16_t vdev_count; 1072 1073 /* PDEV transmit lock */ 1074 qdf_spinlock_t tx_lock; 1075 1076 #ifndef REMOVE_PKT_LOG 1077 bool pkt_log_init; 1078 /* Pktlog pdev */ 1079 struct pktlog_dev_t *pl_dev; 1080 #endif /* #ifndef REMOVE_PKT_LOG */ 1081 1082 /* Monitor mode interface and status storage */ 1083 struct dp_vdev *monitor_vdev; 1084 1085 /* monitor mode lock */ 1086 qdf_spinlock_t mon_lock; 1087 1088 /*tx_mutex for me*/ 1089 DP_MUTEX_TYPE tx_mutex; 1090 1091 /* Smart Mesh */ 1092 bool filter_neighbour_peers; 1093 1094 /*flag to indicate neighbour_peers_list not empty */ 1095 bool neighbour_peers_added; 1096 /* smart mesh mutex */ 1097 qdf_spinlock_t neighbour_peer_mutex; 1098 /* Neighnour peer list */ 1099 TAILQ_HEAD(, dp_neighbour_peer) neighbour_peers_list; 1100 /* msdu chain head & tail */ 1101 qdf_nbuf_t invalid_peer_head_msdu; 1102 qdf_nbuf_t invalid_peer_tail_msdu; 1103 1104 /* Band steering */ 1105 /* TBD */ 1106 1107 /* PDEV level data path statistics */ 1108 struct cdp_pdev_stats stats; 1109 1110 /* Global RX decap mode for the device */ 1111 enum htt_pkt_type rx_decap_mode; 1112 1113 /* Enhanced Stats is enabled */ 1114 bool enhanced_stats_en; 1115 1116 /* advance filter mode and type*/ 1117 uint8_t mon_filter_mode; 1118 uint16_t fp_mgmt_filter; 1119 uint16_t fp_ctrl_filter; 1120 uint16_t fp_data_filter; 1121 uint16_t mo_mgmt_filter; 1122 uint16_t mo_ctrl_filter; 1123 uint16_t mo_data_filter; 1124 1125 qdf_atomic_t num_tx_outstanding; 1126 1127 qdf_atomic_t num_tx_exception; 1128 1129 /* MCL specific local peer handle */ 1130 struct { 1131 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 1132 uint8_t freelist; 1133 qdf_spinlock_t lock; 1134 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 1135 } local_peer_ids; 1136 1137 /* dscp_tid_map_*/ 1138 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 1139 1140 struct hal_rx_ppdu_info ppdu_info; 1141 1142 /* operating channel */ 1143 uint8_t operating_channel; 1144 1145 qdf_nbuf_queue_t rx_status_q; 1146 uint32_t mon_ppdu_status; 1147 struct cdp_mon_status rx_mon_recv_status; 1148 /* monitor mode status/destination ring PPDU and MPDU count */ 1149 struct cdp_pdev_mon_stats rx_mon_stats; 1150 1151 /* pool addr for mcast enhance buff */ 1152 struct { 1153 int size; 1154 uint32_t paddr; 1155 char *vaddr; 1156 struct dp_tx_me_buf_t *freelist; 1157 int buf_in_use; 1158 qdf_dma_mem_context(memctx); 1159 } me_buf; 1160 1161 /* Number of VAPs with mcast enhancement enabled */ 1162 qdf_atomic_t mc_num_vap_attached; 1163 1164 qdf_atomic_t stats_cmd_complete; 1165 1166 #ifdef IPA_OFFLOAD 1167 ipa_uc_op_cb_type ipa_uc_op_cb; 1168 void *usr_ctxt; 1169 struct dp_ipa_resources ipa_resource; 1170 #endif 1171 1172 /* TBD */ 1173 1174 /* map this pdev to a particular Reo Destination ring */ 1175 enum cdp_host_reo_dest_ring reo_dest; 1176 1177 #ifndef REMOVE_PKT_LOG 1178 /* Packet log mode */ 1179 uint8_t rx_pktlog_mode; 1180 #endif 1181 1182 /* WDI event handlers */ 1183 struct wdi_event_subscribe_t **wdi_event_list; 1184 1185 /* ppdu_id of last received HTT TX stats */ 1186 uint32_t last_ppdu_id; 1187 struct { 1188 uint8_t last_user; 1189 qdf_nbuf_t buf; 1190 } tx_ppdu_info; 1191 1192 bool tx_sniffer_enable; 1193 /* mirror copy mode */ 1194 bool mcopy_mode; 1195 bool bpr_enable; 1196 struct { 1197 uint16_t tx_ppdu_id; 1198 uint16_t tx_peer_id; 1199 uint16_t rx_ppdu_id; 1200 } m_copy_id; 1201 1202 /* To check if PPDU Tx stats are enabled for Pktlog */ 1203 bool pktlog_ppdu_stats; 1204 1205 void *dp_txrx_handle; /* Advanced data path handle */ 1206 1207 #ifdef ATH_SUPPORT_NAC_RSSI 1208 bool nac_rssi_filtering; 1209 #endif 1210 /* list of ppdu tlvs */ 1211 TAILQ_HEAD(, ppdu_info) ppdu_info_list; 1212 uint32_t tlv_count; 1213 uint32_t list_depth; 1214 uint32_t ppdu_id; 1215 bool first_nbuf; 1216 struct { 1217 uint8_t *mgmt_buf; /* Ptr to mgmt. payload in HTT ppdu stats */ 1218 uint32_t mgmt_buf_len; /* Len of mgmt. payload in ppdu stats */ 1219 uint32_t ppdu_id; 1220 } mgmtctrl_frm_info; 1221 1222 /* Current noise-floor reading for the pdev channel */ 1223 int16_t chan_noise_floor; 1224 1225 /* 1226 * For multiradio device, this flag indicates if 1227 * this radio is primary or secondary. 1228 * 1229 * For HK 1.0, this is used for WAR for the AST issue. 1230 * HK 1.x mandates creation of only 1 AST entry with same MAC address 1231 * across 2 radios. is_primary indicates the radio on which DP should 1232 * install HW AST entry if there is a request to add 2 AST entries 1233 * with same MAC address across 2 radios 1234 */ 1235 uint8_t is_primary; 1236 }; 1237 1238 struct dp_peer; 1239 1240 /* VDEV structure for data path state */ 1241 struct dp_vdev { 1242 /* OS device abstraction */ 1243 qdf_device_t osdev; 1244 /* physical device that is the parent of this virtual device */ 1245 struct dp_pdev *pdev; 1246 1247 /* Handle to the OS shim SW's virtual device */ 1248 ol_osif_vdev_handle osif_vdev; 1249 1250 /* Handle to the UMAC handle */ 1251 struct cdp_ctrl_objmgr_vdev *ctrl_vdev; 1252 /* vdev_id - ID used to specify a particular vdev to the target */ 1253 uint8_t vdev_id; 1254 1255 /* MAC address */ 1256 union dp_align_mac_addr mac_addr; 1257 1258 /* node in the pdev's list of vdevs */ 1259 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 1260 1261 /* dp_peer list */ 1262 TAILQ_HEAD(, dp_peer) peer_list; 1263 1264 /* callback to hand rx frames to the OS shim */ 1265 ol_txrx_rx_fp osif_rx; 1266 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 1267 ol_txrx_get_key_fp osif_get_key; 1268 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 1269 1270 #ifdef notyet 1271 /* callback to check if the msdu is an WAI (WAPI) frame */ 1272 ol_rx_check_wai_fp osif_check_wai; 1273 #endif 1274 1275 /* proxy arp function */ 1276 ol_txrx_proxy_arp_fp osif_proxy_arp; 1277 1278 /* callback to hand rx monitor 802.11 MPDU to the OS shim */ 1279 ol_txrx_rx_mon_fp osif_rx_mon; 1280 1281 ol_txrx_mcast_me_fp me_convert; 1282 1283 /* completion function used by this vdev*/ 1284 ol_txrx_completion_fp tx_comp; 1285 1286 /* deferred vdev deletion state */ 1287 struct { 1288 /* VDEV delete pending */ 1289 int pending; 1290 /* 1291 * callback and a context argument to provide a 1292 * notification for when the vdev is deleted. 1293 */ 1294 ol_txrx_vdev_delete_cb callback; 1295 void *context; 1296 } delete; 1297 1298 /* tx data delivery notification callback function */ 1299 struct { 1300 ol_txrx_data_tx_cb func; 1301 void *ctxt; 1302 } tx_non_std_data_callback; 1303 1304 1305 /* safe mode control to bypass the encrypt and decipher process*/ 1306 uint32_t safemode; 1307 1308 /* rx filter related */ 1309 uint32_t drop_unenc; 1310 #ifdef notyet 1311 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 1312 uint32_t filters_num; 1313 #endif 1314 /* TDLS Link status */ 1315 bool tdls_link_connected; 1316 bool is_tdls_frame; 1317 1318 1319 /* VDEV operating mode */ 1320 enum wlan_op_mode opmode; 1321 1322 /* Tx encapsulation type for this VAP */ 1323 enum htt_cmn_pkt_type tx_encap_type; 1324 /* Rx Decapsulation type for this VAP */ 1325 enum htt_cmn_pkt_type rx_decap_type; 1326 1327 /* BSS peer */ 1328 struct dp_peer *vap_bss_peer; 1329 1330 /* WDS enabled */ 1331 bool wds_enabled; 1332 1333 /* WDS Aging timer period */ 1334 uint32_t wds_aging_timer_val; 1335 1336 /* NAWDS enabled */ 1337 bool nawds_enabled; 1338 1339 /* Default HTT meta data for this VDEV */ 1340 /* TBD: check alignment constraints */ 1341 uint16_t htt_tcl_metadata; 1342 1343 /* Mesh mode vdev */ 1344 uint32_t mesh_vdev; 1345 1346 /* Mesh mode rx filter setting */ 1347 uint32_t mesh_rx_filter; 1348 1349 /* DSCP-TID mapping table ID */ 1350 uint8_t dscp_tid_map_id; 1351 1352 /* Multicast enhancement enabled */ 1353 uint8_t mcast_enhancement_en; 1354 1355 /* per vdev rx nbuf queue */ 1356 qdf_nbuf_queue_t rxq; 1357 1358 uint8_t tx_ring_id; 1359 struct dp_tx_desc_pool_s *tx_desc; 1360 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 1361 1362 /* VDEV Stats */ 1363 struct cdp_vdev_stats stats; 1364 bool lro_enable; 1365 1366 /* Is this a proxySTA VAP */ 1367 bool proxysta_vdev; 1368 /* Is isolation mode enabled */ 1369 bool isolation_vdev; 1370 1371 /* Address search flags to be configured in HAL descriptor */ 1372 uint8_t hal_desc_addr_search_flags; 1373 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1374 struct dp_tx_desc_pool_s *pool; 1375 #endif 1376 /* AP BRIDGE enabled */ 1377 uint32_t ap_bridge_enabled; 1378 1379 enum cdp_sec_type sec_type; 1380 }; 1381 1382 1383 enum { 1384 dp_sec_mcast = 0, 1385 dp_sec_ucast 1386 }; 1387 1388 #ifdef WDS_VENDOR_EXTENSION 1389 typedef struct { 1390 uint8_t wds_tx_mcast_4addr:1, 1391 wds_tx_ucast_4addr:1, 1392 wds_rx_filter:1, /* enforce rx filter */ 1393 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 1394 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 1395 1396 } dp_ecm_policy; 1397 #endif 1398 1399 /* Peer structure for data path state */ 1400 struct dp_peer { 1401 /* VDEV to which this peer is associated */ 1402 struct dp_vdev *vdev; 1403 1404 struct cdp_ctrl_objmgr_peer *ctrl_peer; 1405 1406 struct dp_ast_entry *self_ast_entry; 1407 1408 qdf_atomic_t ref_cnt; 1409 1410 /* TODO: See if multiple peer IDs are required in wifi3.0 */ 1411 /* peer ID(s) for this peer */ 1412 uint16_t peer_ids[MAX_NUM_PEER_ID_PER_PEER]; 1413 1414 union dp_align_mac_addr mac_addr; 1415 1416 /* node in the vdev's list of peers */ 1417 TAILQ_ENTRY(dp_peer) peer_list_elem; 1418 /* node in the hash table bin's list of peers */ 1419 TAILQ_ENTRY(dp_peer) hash_list_elem; 1420 1421 /* TID structures */ 1422 struct dp_rx_tid rx_tid[DP_MAX_TIDS]; 1423 1424 /* TBD: No transmit TID state required? */ 1425 1426 struct { 1427 enum htt_sec_type sec_type; 1428 u_int32_t michael_key[2]; /* relevant for TKIP */ 1429 } security[2]; /* 0 -> multicast, 1 -> unicast */ 1430 1431 /* 1432 * rx proc function: this either is a copy of pdev's rx_opt_proc for 1433 * regular rx processing, or has been redirected to a /dev/null discard 1434 * function when peer deletion is in progress. 1435 */ 1436 void (*rx_opt_proc)(struct dp_vdev *vdev, struct dp_peer *peer, 1437 unsigned tid, qdf_nbuf_t msdu_list); 1438 1439 /* set when node is authorized */ 1440 uint8_t authorize:1; 1441 1442 u_int8_t nac; 1443 1444 /* Band steering: Set when node is inactive */ 1445 uint8_t peer_bs_inact_flag:1; 1446 u_int16_t peer_bs_inact; /* inactivity mark count */ 1447 1448 /* NAWDS Flag and Bss Peer bit */ 1449 uint8_t nawds_enabled:1, 1450 bss_peer:1, 1451 wapi:1, 1452 wds_enabled:1; 1453 1454 /* MCL specific peer local id */ 1455 uint16_t local_id; 1456 enum ol_txrx_peer_state state; 1457 qdf_spinlock_t peer_info_lock; 1458 1459 qdf_time_t last_assoc_rcvd; 1460 qdf_time_t last_disassoc_rcvd; 1461 qdf_time_t last_deauth_rcvd; 1462 /* Peer Stats */ 1463 struct cdp_peer_stats stats; 1464 1465 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 1466 /* TBD */ 1467 1468 #ifdef WDS_VENDOR_EXTENSION 1469 dp_ecm_policy wds_ecm; 1470 #endif 1471 bool delete_in_progress; 1472 }; 1473 1474 #ifdef CONFIG_WIN 1475 /* 1476 * dp_invalid_peer_msg 1477 * @nbuf: data buffer 1478 * @wh: 802.11 header 1479 * @vdev_id: id of vdev 1480 */ 1481 struct dp_invalid_peer_msg { 1482 qdf_nbuf_t nbuf; 1483 struct ieee80211_frame *wh; 1484 uint8_t vdev_id; 1485 }; 1486 #endif 1487 1488 /* 1489 * dp_tx_me_buf_t: ME buffer 1490 * next: pointer to next buffer 1491 * data: Destination Mac address 1492 */ 1493 struct dp_tx_me_buf_t { 1494 /* Note: ME buf pool initialization logic expects next pointer to 1495 * be the first element. Dont add anything before next */ 1496 struct dp_tx_me_buf_t *next; 1497 uint8_t data[DP_MAC_ADDR_LEN]; 1498 }; 1499 1500 #endif /* _DP_TYPES_H_ */ 1501