1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _DP_TYPES_H_ 21 #define _DP_TYPES_H_ 22 23 #include <qdf_types.h> 24 #include <qdf_nbuf.h> 25 #include <qdf_lock.h> 26 #include <qdf_atomic.h> 27 #include <qdf_util.h> 28 #include <qdf_list.h> 29 #include <qdf_lro.h> 30 #include <queue.h> 31 #include <htt_common.h> 32 #include <htt.h> 33 #include <htt_stats.h> 34 #include <cdp_txrx_cmn.h> 35 #ifdef DP_MOB_DEFS 36 #include <cds_ieee80211_common.h> 37 #endif 38 #include <wdi_event_api.h> /* WDI subscriber event list */ 39 40 #include "hal_hw_headers.h" 41 #include <hal_tx.h> 42 #include <hal_reo.h> 43 #include "wlan_cfg.h" 44 #include "hal_rx.h" 45 #include <hal_api.h> 46 #include <hal_api_mon.h> 47 #include "hal_rx.h" 48 49 #define dp_init_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_INIT, params) 50 #define dp_init_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_INIT, params) 51 #define dp_init_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_INIT, params) 52 #define dp_init_info(params...) \ 53 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_INIT, ## params) 54 #define dp_init_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_INIT, params) 55 56 #define dp_vdev_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_VDEV, params) 57 #define dp_vdev_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_VDEV, params) 58 #define dp_vdev_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_VDEV, params) 59 #define dp_vdev_info(params...) \ 60 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_VDEV, ## params) 61 #define dp_vdev_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_VDEV, params) 62 63 #define MAX_BW 8 64 #define MAX_RETRIES 4 65 #define MAX_RECEPTION_TYPES 4 66 67 #define MINIDUMP_STR_SIZE 25 68 #include <dp_umac_reset.h> 69 70 #define REPT_MU_MIMO 1 71 #define REPT_MU_OFDMA_MIMO 3 72 #define DP_VO_TID 6 73 /** MAX TID MAPS AVAILABLE PER PDEV */ 74 #define DP_MAX_TID_MAPS 16 75 /** pad DSCP_TID_MAP_MAX with 6 to fix oob issue */ 76 #define DSCP_TID_MAP_MAX (64 + 6) 77 #define DP_IP_DSCP_SHIFT 2 78 #define DP_IP_DSCP_MASK 0x3f 79 #define DP_FC0_SUBTYPE_QOS 0x80 80 #define DP_QOS_TID 0x0f 81 #define DP_IPV6_PRIORITY_SHIFT 20 82 #define MAX_MON_LINK_DESC_BANKS 2 83 #define DP_VDEV_ALL CDP_VDEV_ALL 84 85 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 86 #define WLAN_DP_RESET_MON_BUF_RING_FILTER 87 #define MAX_TXDESC_POOLS 6 88 #else 89 #define MAX_TXDESC_POOLS 4 90 #endif 91 92 /* Max no of descriptors to handle special frames like EAPOL */ 93 #define MAX_TX_SPL_DESC 1024 94 95 #define MAX_RXDESC_POOLS 4 96 #define MAX_PPE_TXDESC_POOLS 1 97 98 /* Max no. of VDEV per PSOC */ 99 #ifdef WLAN_PSOC_MAX_VDEVS 100 #define MAX_VDEV_CNT WLAN_PSOC_MAX_VDEVS 101 #else 102 #define MAX_VDEV_CNT 51 103 #endif 104 105 /* Max no. of VDEVs, a PDEV can support */ 106 #ifdef WLAN_PDEV_MAX_VDEVS 107 #define DP_PDEV_MAX_VDEVS WLAN_PDEV_MAX_VDEVS 108 #else 109 #define DP_PDEV_MAX_VDEVS 17 110 #endif 111 112 #define EXCEPTION_DEST_RING_ID 0 113 #define MAX_IDLE_SCATTER_BUFS 16 114 #define DP_MAX_IRQ_PER_CONTEXT 12 115 #define DEFAULT_HW_PEER_ID 0xffff 116 117 #define MAX_AST_AGEOUT_COUNT 128 118 119 #ifdef TX_ADDR_INDEX_SEARCH 120 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_INDEX_SEARCH 121 #else 122 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_SEARCH_DEFAULT 123 #endif 124 125 #define WBM_INT_ERROR_ALL 0 126 #define WBM_INT_ERROR_REO_NULL_BUFFER 1 127 #define WBM_INT_ERROR_REO_NULL_LINK_DESC 2 128 #define WBM_INT_ERROR_REO_NULL_MSDU_BUFF 3 129 #define WBM_INT_ERROR_REO_BUFF_REAPED 4 130 #define MAX_WBM_INT_ERROR_REASONS 5 131 132 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 133 /* Maximum retries for Delba per tid per peer */ 134 #define DP_MAX_DELBA_RETRY 3 135 136 #ifdef AST_OFFLOAD_ENABLE 137 #define AST_OFFLOAD_ENABLE_STATUS 1 138 #else 139 #define AST_OFFLOAD_ENABLE_STATUS 0 140 #endif 141 142 #ifdef FEATURE_MEC_OFFLOAD 143 #define FW_MEC_FW_OFFLOAD_ENABLED 1 144 #else 145 #define FW_MEC_FW_OFFLOAD_ENABLED 0 146 #endif 147 148 #define PCP_TID_MAP_MAX 8 149 #define MAX_MU_USERS 37 150 151 #define REO_CMD_EVENT_HIST_MAX 64 152 153 #define DP_MAX_SRNGS 64 154 155 /* 2G PHYB */ 156 #define PHYB_2G_LMAC_ID 2 157 #define PHYB_2G_TARGET_PDEV_ID 2 158 159 /* Flags for skippig s/w tid classification */ 160 #define DP_TX_HW_DSCP_TID_MAP_VALID 0x1 161 #define DP_TXRX_HLOS_TID_OVERRIDE_ENABLED 0x2 162 #define DP_TX_MESH_ENABLED 0x4 163 #define DP_TX_INVALID_QOS_TAG 0xf 164 165 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 166 #define DP_RX_REFILL_BUFF_POOL_BURST 64 167 #endif 168 169 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 170 #define DP_RX_FSE_FLOW_MATCH_SFE 0xAAAA 171 #endif 172 173 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 174 #define DP_SKIP_BAR_UPDATE_TIMEOUT 5000 175 #endif 176 177 #define DP_TX_MAGIC_PATTERN_INUSE 0xABCD1234 178 #define DP_TX_MAGIC_PATTERN_FREE 0xDEADBEEF 179 180 #define DP_INTR_POLL_TIMER_MS 5 181 182 #ifdef IPA_OFFLOAD 183 #define DP_PEER_REO_STATS_TID_SHIFT 16 184 #define DP_PEER_REO_STATS_TID_MASK 0xFFFF0000 185 #define DP_PEER_REO_STATS_PEER_ID_MASK 0x0000FFFF 186 #define DP_PEER_GET_REO_STATS_TID(comb_peer_id_tid) \ 187 ((comb_peer_id_tid & DP_PEER_REO_STATS_TID_MASK) >> \ 188 DP_PEER_REO_STATS_TID_SHIFT) 189 #define DP_PEER_GET_REO_STATS_PEER_ID(comb_peer_id_tid) \ 190 (comb_peer_id_tid & DP_PEER_REO_STATS_PEER_ID_MASK) 191 #endif 192 193 typedef void dp_ptnr_soc_iter_func(struct dp_soc *ptnr_soc, void *arg, 194 int chip_id); 195 196 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 197 #define DP_MLD_MODE_UNIFIED_NONBOND 0 198 #define DP_MLD_MODE_UNIFIED_BOND 1 199 #define DP_MLD_MODE_HYBRID_NONBOND 2 200 #define DP_MLD_MODE_MAX DP_MLD_MODE_HYBRID_NONBOND 201 202 #define DP_LINK_VDEV_ITER 1 203 #define DP_BRIDGE_VDEV_ITER 2 204 #define DP_ALL_VDEV_ITER 3 205 #define IS_LINK_VDEV_ITER_REQUIRED(type) (type & DP_LINK_VDEV_ITER) 206 #define IS_BRIDGE_VDEV_ITER_REQUIRED(type) (type & DP_BRIDGE_VDEV_ITER) 207 #define DP_VDEV_ITERATE_ALL 1 208 #define DP_VDEV_ITERATE_SKIP_SELF 0 209 #endif 210 211 /** 212 * enum dp_pkt_xmit_type - The type of ingress stats are being referred 213 * 214 * @DP_XMIT_LINK: Packet ingress-ed on Link 215 * @DP_XMIT_MLD: Packet ingress-ed on MLD 216 * @DP_XMIT_TOTAL: Packets ingress-ed on MLD and LINK 217 */ 218 enum dp_pkt_xmit_type { 219 DP_XMIT_LINK, 220 DP_XMIT_MLD, 221 DP_XMIT_TOTAL, 222 }; 223 224 enum rx_pktlog_mode { 225 DP_RX_PKTLOG_DISABLED = 0, 226 DP_RX_PKTLOG_FULL, 227 DP_RX_PKTLOG_LITE, 228 }; 229 230 /* enum m_copy_mode - Available mcopy mode 231 * 232 */ 233 enum m_copy_mode { 234 M_COPY_DISABLED = 0, 235 M_COPY = 2, 236 M_COPY_EXTENDED = 4, 237 }; 238 239 struct msdu_list { 240 qdf_nbuf_t head; 241 qdf_nbuf_t tail; 242 uint32_t sum_len; 243 }; 244 245 struct dp_soc_cmn; 246 struct dp_pdev; 247 struct dp_vdev; 248 struct dp_tx_desc_s; 249 struct dp_soc; 250 union dp_rx_desc_list_elem_t; 251 struct cdp_peer_rate_stats_ctx; 252 struct cdp_soc_rate_stats_ctx; 253 struct dp_rx_fst; 254 struct dp_mon_filter; 255 struct dp_mon_mpdu; 256 #ifdef BE_PKTLOG_SUPPORT 257 struct dp_mon_filter_be; 258 #endif 259 struct dp_peer; 260 struct dp_txrx_peer; 261 262 /** 263 * enum dp_peer_state - DP peer states 264 * @DP_PEER_STATE_NONE: 265 * @DP_PEER_STATE_INIT: 266 * @DP_PEER_STATE_ACTIVE: 267 * @DP_PEER_STATE_LOGICAL_DELETE: 268 * @DP_PEER_STATE_INACTIVE: 269 * @DP_PEER_STATE_FREED: 270 * @DP_PEER_STATE_INVALID: 271 */ 272 enum dp_peer_state { 273 DP_PEER_STATE_NONE, 274 DP_PEER_STATE_INIT, 275 DP_PEER_STATE_ACTIVE, 276 DP_PEER_STATE_LOGICAL_DELETE, 277 DP_PEER_STATE_INACTIVE, 278 DP_PEER_STATE_FREED, 279 DP_PEER_STATE_INVALID, 280 }; 281 282 /** 283 * enum dp_mod_id - DP module IDs 284 * @DP_MOD_ID_TX_RX: 285 * @DP_MOD_ID_TX_COMP: 286 * @DP_MOD_ID_RX: 287 * @DP_MOD_ID_HTT_COMP: 288 * @DP_MOD_ID_RX_ERR: 289 * @DP_MOD_ID_TX_PPDU_STATS: 290 * @DP_MOD_ID_RX_PPDU_STATS: 291 * @DP_MOD_ID_CDP: 292 * @DP_MOD_ID_GENERIC_STATS: 293 * @DP_MOD_ID_TX_MULTIPASS: 294 * @DP_MOD_ID_TX_CAPTURE: 295 * @DP_MOD_ID_NSS_OFFLOAD: 296 * @DP_MOD_ID_CONFIG: 297 * @DP_MOD_ID_HTT: 298 * @DP_MOD_ID_IPA: 299 * @DP_MOD_ID_AST: 300 * @DP_MOD_ID_MCAST2UCAST: 301 * @DP_MOD_ID_CHILD: 302 * @DP_MOD_ID_MESH: 303 * @DP_MOD_ID_TX_EXCEPTION: 304 * @DP_MOD_ID_TDLS: 305 * @DP_MOD_ID_MISC: 306 * @DP_MOD_ID_MSCS: 307 * @DP_MOD_ID_TX: 308 * @DP_MOD_ID_SAWF: 309 * @DP_MOD_ID_REINJECT: 310 * @DP_MOD_ID_SCS: 311 * @DP_MOD_ID_UMAC_RESET: 312 * @DP_MOD_ID_TX_MCAST: 313 * @DP_MOD_ID_DS: 314 * @DP_MOD_ID_MLO_DEV: 315 * @DP_MOD_ID_MAX: 316 */ 317 enum dp_mod_id { 318 DP_MOD_ID_TX_RX, 319 DP_MOD_ID_TX_COMP, 320 DP_MOD_ID_RX, 321 DP_MOD_ID_HTT_COMP, 322 DP_MOD_ID_RX_ERR, 323 DP_MOD_ID_TX_PPDU_STATS, 324 DP_MOD_ID_RX_PPDU_STATS, 325 DP_MOD_ID_CDP, 326 DP_MOD_ID_GENERIC_STATS, 327 DP_MOD_ID_TX_MULTIPASS, 328 DP_MOD_ID_TX_CAPTURE, 329 DP_MOD_ID_NSS_OFFLOAD, 330 DP_MOD_ID_CONFIG, 331 DP_MOD_ID_HTT, 332 DP_MOD_ID_IPA, 333 DP_MOD_ID_AST, 334 DP_MOD_ID_MCAST2UCAST, 335 DP_MOD_ID_CHILD, 336 DP_MOD_ID_MESH, 337 DP_MOD_ID_TX_EXCEPTION, 338 DP_MOD_ID_TDLS, 339 DP_MOD_ID_MISC, 340 DP_MOD_ID_MSCS, 341 DP_MOD_ID_TX, 342 DP_MOD_ID_SAWF, 343 DP_MOD_ID_REINJECT, 344 DP_MOD_ID_SCS, 345 DP_MOD_ID_UMAC_RESET, 346 DP_MOD_ID_TX_MCAST, 347 DP_MOD_ID_DS, 348 DP_MOD_ID_MLO_DEV, 349 DP_MOD_ID_MAX, 350 }; 351 352 /** 353 * enum dp_peer_type - DP peer type 354 * @DP_PEER_TYPE_LEGACY: 355 * @DP_PEER_TYPE_MLO_LINK: 356 * @DP_PEER_TYPE_MLO: 357 */ 358 enum dp_peer_type { 359 DP_PEER_TYPE_LEGACY, 360 DP_PEER_TYPE_MLO_LINK, 361 DP_PEER_TYPE_MLO, 362 }; 363 364 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 365 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 366 367 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 368 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 369 370 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 371 TAILQ_FOREACH_SAFE((_ase), &_peer->ast_entry_list, ase_list_elem, (_temp_ase)) 372 373 #define DP_MUTEX_TYPE qdf_spinlock_t 374 375 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 376 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 377 378 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 379 ((_a)[0] == 0x33 && \ 380 (_a)[1] == 0x33) 381 382 #define DP_FRAME_IS_BROADCAST(_a) \ 383 ((_a)[0] == 0xff && \ 384 (_a)[1] == 0xff && \ 385 (_a)[2] == 0xff && \ 386 (_a)[3] == 0xff && \ 387 (_a)[4] == 0xff && \ 388 (_a)[5] == 0xff) 389 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 390 (_llc)->llc_ssap == 0xaa && \ 391 (_llc)->llc_un.type_snap.control == 0x3) 392 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 393 #define DP_FRAME_FC0_TYPE_MASK 0x0c 394 #define DP_FRAME_FC0_TYPE_DATA 0x08 395 #define DP_FRAME_IS_DATA(_frame) \ 396 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 397 398 /* 399 * macros to convert hw mac id to sw mac id: 400 * mac ids used by hardware start from a value of 1 while 401 * those in host software start from a value of 0. Use the 402 * macros below to convert between mac ids used by software and 403 * hardware 404 */ 405 #define DP_SW2HW_MACID(id) ((id) + 1) 406 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 407 408 /* 409 * Number of Tx Queues 410 * enum and macro to define how many threshold levels is used 411 * for the AC based flow control 412 */ 413 #ifdef QCA_AC_BASED_FLOW_CONTROL 414 enum dp_fl_ctrl_threshold { 415 DP_TH_BE_BK = 0, 416 DP_TH_VI, 417 DP_TH_VO, 418 DP_TH_HI, 419 }; 420 421 #define FL_TH_MAX (4) 422 #define FL_TH_VI_PERCENTAGE (80) 423 #define FL_TH_VO_PERCENTAGE (60) 424 #define FL_TH_HI_PERCENTAGE (40) 425 #endif 426 427 /** 428 * enum dp_intr_mode 429 * @DP_INTR_INTEGRATED: Line interrupts 430 * @DP_INTR_MSI: MSI interrupts 431 * @DP_INTR_POLL: Polling 432 * @DP_INTR_LEGACY_VIRTUAL_IRQ: 433 */ 434 enum dp_intr_mode { 435 DP_INTR_INTEGRATED = 0, 436 DP_INTR_MSI, 437 DP_INTR_POLL, 438 DP_INTR_LEGACY_VIRTUAL_IRQ, 439 }; 440 441 /** 442 * enum dp_tx_frm_type 443 * @dp_tx_frm_std: Regular frame, no added header fragments 444 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 445 * @dp_tx_frm_sg: SG segment 446 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 447 * @dp_tx_frm_me: Multicast to Unicast Converted frame 448 * @dp_tx_frm_raw: Raw Frame 449 * @dp_tx_frm_rmnet: 450 */ 451 enum dp_tx_frm_type { 452 dp_tx_frm_std = 0, 453 dp_tx_frm_tso, 454 dp_tx_frm_sg, 455 dp_tx_frm_audio, 456 dp_tx_frm_me, 457 dp_tx_frm_raw, 458 dp_tx_frm_rmnet, 459 }; 460 461 /** 462 * enum dp_ast_type 463 * @dp_ast_type_wds: WDS peer AST type 464 * @dp_ast_type_static: static ast entry type 465 * @dp_ast_type_mec: Multicast echo ast entry type 466 */ 467 enum dp_ast_type { 468 dp_ast_type_wds = 0, 469 dp_ast_type_static, 470 dp_ast_type_mec, 471 }; 472 473 /** 474 * enum dp_nss_cfg 475 * @dp_nss_cfg_default: No radios are offloaded 476 * @dp_nss_cfg_first_radio: First radio offloaded 477 * @dp_nss_cfg_second_radio: Second radio offloaded 478 * @dp_nss_cfg_dbdc: Dual radios offloaded 479 * @dp_nss_cfg_dbtc: Three radios offloaded 480 * @dp_nss_cfg_max: max value 481 */ 482 enum dp_nss_cfg { 483 dp_nss_cfg_default = 0x0, 484 dp_nss_cfg_first_radio = 0x1, 485 dp_nss_cfg_second_radio = 0x2, 486 dp_nss_cfg_dbdc = 0x3, 487 dp_nss_cfg_dbtc = 0x7, 488 dp_nss_cfg_max 489 }; 490 491 #ifdef WLAN_TX_PKT_CAPTURE_ENH 492 #define DP_CPU_RING_MAP_1 1 493 #endif 494 495 /** 496 * enum dp_cpu_ring_map_types - dp tx cpu ring map 497 * @DP_NSS_DEFAULT_MAP: Default mode with no NSS offloaded 498 * @DP_NSS_FIRST_RADIO_OFFLOADED_MAP: Only First Radio is offloaded 499 * @DP_NSS_SECOND_RADIO_OFFLOADED_MAP: Only second radio is offloaded 500 * @DP_NSS_DBDC_OFFLOADED_MAP: Both radios are offloaded 501 * @DP_NSS_DBTC_OFFLOADED_MAP: All three radios are offloaded 502 * @DP_SINGLE_TX_RING_MAP: to avoid out of order all cpu mapped to single ring 503 * @DP_NSS_CPU_RING_MAP_MAX: Max cpu ring map val 504 */ 505 enum dp_cpu_ring_map_types { 506 DP_NSS_DEFAULT_MAP, 507 DP_NSS_FIRST_RADIO_OFFLOADED_MAP, 508 DP_NSS_SECOND_RADIO_OFFLOADED_MAP, 509 DP_NSS_DBDC_OFFLOADED_MAP, 510 DP_NSS_DBTC_OFFLOADED_MAP, 511 #ifdef WLAN_TX_PKT_CAPTURE_ENH 512 DP_SINGLE_TX_RING_MAP, 513 #endif 514 DP_NSS_CPU_RING_MAP_MAX 515 }; 516 517 /** 518 * struct dp_rx_nbuf_frag_info - Hold vaddr and paddr for a buffer 519 * 520 * @paddr: Physical address of buffer allocated. 521 * @virt_addr: union of virtual address representations 522 * @nbuf: Allocated nbuf in case of nbuf approach. 523 * @vaddr: Virtual address of frag allocated in case of frag approach. 524 */ 525 struct dp_rx_nbuf_frag_info { 526 qdf_dma_addr_t paddr; 527 union { 528 qdf_nbuf_t nbuf; 529 qdf_frag_t vaddr; 530 } virt_addr; 531 }; 532 533 /** 534 * enum dp_ctxt_type - context type 535 * @DP_PDEV_TYPE: PDEV context 536 * @DP_RX_RING_HIST_TYPE: Datapath rx ring history 537 * @DP_RX_ERR_RING_HIST_TYPE: Datapath rx error ring history 538 * @DP_RX_REINJECT_RING_HIST_TYPE: Datapath reinject ring history 539 * @DP_TX_TCL_HIST_TYPE: 540 * @DP_TX_COMP_HIST_TYPE: 541 * @DP_FISA_RX_FT_TYPE: 542 * @DP_RX_REFILL_RING_HIST_TYPE: Datapath rx refill ring history 543 * @DP_TX_HW_DESC_HIST_TYPE: Datapath TX HW descriptor history 544 * @DP_MON_SOC_TYPE: Datapath monitor soc context 545 * @DP_MON_PDEV_TYPE: Datapath monitor pdev context 546 * @DP_MON_STATUS_BUF_HIST_TYPE: DP monitor status buffer history 547 * @DP_CFG_EVENT_HIST_TYPE: DP config events history 548 * @DP_MON_TX_DESC_POOL_TYPE: DP TX desc pool buffer 549 * @DP_MON_RX_DESC_POOL_TYPE: DP RX desc pool buffer 550 */ 551 enum dp_ctxt_type { 552 DP_PDEV_TYPE, 553 DP_RX_RING_HIST_TYPE, 554 DP_RX_ERR_RING_HIST_TYPE, 555 DP_RX_REINJECT_RING_HIST_TYPE, 556 DP_TX_TCL_HIST_TYPE, 557 DP_TX_COMP_HIST_TYPE, 558 DP_FISA_RX_FT_TYPE, 559 DP_RX_REFILL_RING_HIST_TYPE, 560 DP_TX_HW_DESC_HIST_TYPE, 561 DP_MON_SOC_TYPE, 562 DP_MON_PDEV_TYPE, 563 DP_MON_STATUS_BUF_HIST_TYPE, 564 DP_CFG_EVENT_HIST_TYPE, 565 DP_MON_TX_DESC_POOL_TYPE, 566 DP_MON_RX_DESC_POOL_TYPE, 567 }; 568 569 /** 570 * struct rx_desc_pool 571 * @pool_size: number of RX descriptor in the pool 572 * @elem_size: Element size 573 * @desc_pages: Multi page descriptors 574 * @array: pointer to array of RX descriptor 575 * @freelist: pointer to free RX descriptor link list 576 * @lock: Protection for the RX descriptor pool 577 * @owner: owner for nbuf 578 * @buf_size: Buffer size 579 * @buf_alignment: Buffer alignment 580 * @rx_mon_dest_frag_enable: Enable frag processing for mon dest buffer 581 * @pf_cache: page frag cache 582 * @desc_type: type of desc this pool serves 583 */ 584 struct rx_desc_pool { 585 uint32_t pool_size; 586 #ifdef RX_DESC_MULTI_PAGE_ALLOC 587 uint16_t elem_size; 588 struct qdf_mem_multi_page_t desc_pages; 589 #else 590 union dp_rx_desc_list_elem_t *array; 591 #endif 592 union dp_rx_desc_list_elem_t *freelist; 593 qdf_spinlock_t lock; 594 uint8_t owner; 595 uint16_t buf_size; 596 uint8_t buf_alignment; 597 bool rx_mon_dest_frag_enable; 598 qdf_frag_cache_t pf_cache; 599 enum qdf_dp_desc_type desc_type; 600 }; 601 602 /** 603 * struct dp_tx_ext_desc_elem_s 604 * @next: next extension descriptor pointer 605 * @vaddr: hlos virtual address pointer 606 * @paddr: physical address pointer for descriptor 607 * @flags: mark features for extension descriptor 608 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 609 * Tx completion of ME packet 610 * @tso_desc: Pointer to Tso desc 611 * @tso_num_desc: Pointer to tso_num_desc 612 */ 613 struct dp_tx_ext_desc_elem_s { 614 struct dp_tx_ext_desc_elem_s *next; 615 void *vaddr; 616 qdf_dma_addr_t paddr; 617 uint16_t flags; 618 struct dp_tx_me_buf_t *me_buffer; 619 struct qdf_tso_seg_elem_t *tso_desc; 620 struct qdf_tso_num_seg_elem_t *tso_num_desc; 621 }; 622 623 /* 624 * NB: intentionally not using kernel-doc comment because the kernel-doc 625 * script does not handle the qdf_dma_mem_context macro 626 * struct dp_tx_ext_desc_pool_s - Tx Extension Descriptor Pool 627 * @elem_count: Number of descriptors in the pool 628 * @elem_size: Size of each descriptor 629 * @num_free: Number of free descriptors 630 * @desc_pages: multiple page allocation information for actual descriptors 631 * @link_elem_size: size of the link descriptor in cacheable memory used for 632 * chaining the extension descriptors 633 * @desc_link_pages: multiple page allocation information for link descriptors 634 * @freelist: 635 * @lock: 636 * @memctx: 637 */ 638 struct dp_tx_ext_desc_pool_s { 639 uint16_t elem_count; 640 int elem_size; 641 uint16_t num_free; 642 struct qdf_mem_multi_page_t desc_pages; 643 int link_elem_size; 644 struct qdf_mem_multi_page_t desc_link_pages; 645 struct dp_tx_ext_desc_elem_s *freelist; 646 qdf_spinlock_t lock; 647 qdf_dma_mem_context(memctx); 648 }; 649 650 /** 651 * struct dp_tx_desc_s - Tx Descriptor 652 * @next: Next in the chain of descriptors in freelist or in the completion list 653 * @nbuf: Buffer Address 654 * @length: 655 * @magic: 656 * @timestamp_tick: 657 * @flags: Flags to track the state of descriptor and special frame handling 658 * @id: Descriptor ID 659 * @dma_addr: 660 * @vdev_id: vdev_id of vdev over which the packet was transmitted 661 * @tx_status: 662 * @peer_id: 663 * @pdev: Handle to pdev 664 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 665 * This is maintained in descriptor to allow more efficient 666 * processing in completion event processing code. 667 * This field is filled in with the htt_pkt_type enum. 668 * @buffer_src: buffer source TQM, REO, FW etc. 669 * @reserved: 670 * @frm_type: Frame Type - ToDo check if this is redundant 671 * @pkt_offset: Offset from which the actual packet data starts 672 * @pool_id: Pool ID - used when releasing the descriptor 673 * @msdu_ext_desc: MSDU extension descriptor 674 * @timestamp: 675 * @driver_egress_ts: driver egress timestamp 676 * @driver_ingress_ts: driver ingress timestamp 677 * @comp: 678 * @tcl_cmd_vaddr: VADDR of the TCL descriptor, valid for soft-umac arch 679 * @tcl_cmd_paddr: PADDR of the TCL descriptor, valid for soft-umac arch 680 */ 681 struct dp_tx_desc_s { 682 struct dp_tx_desc_s *next; 683 qdf_nbuf_t nbuf; 684 uint16_t length; 685 #ifdef DP_TX_TRACKING 686 uint32_t magic; 687 uint64_t timestamp_tick; 688 #endif 689 uint32_t flags; 690 uint32_t id; 691 qdf_dma_addr_t dma_addr; 692 uint8_t vdev_id; 693 uint8_t tx_status; 694 uint16_t peer_id; 695 struct dp_pdev *pdev; 696 uint8_t tx_encap_type:2, 697 buffer_src:3, 698 reserved:3; 699 uint8_t frm_type; 700 uint8_t pkt_offset; 701 uint8_t pool_id; 702 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 703 qdf_ktime_t timestamp; 704 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 705 qdf_ktime_t driver_egress_ts; 706 qdf_ktime_t driver_ingress_ts; 707 #endif 708 struct hal_tx_desc_comp_s comp; 709 #ifdef WLAN_SOFTUMAC_SUPPORT 710 void *tcl_cmd_vaddr; 711 qdf_dma_addr_t tcl_cmd_paddr; 712 #endif 713 }; 714 715 #ifdef QCA_AC_BASED_FLOW_CONTROL 716 /** 717 * enum flow_pool_status - flow pool status 718 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 719 * and network queues are unpaused 720 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 721 * and network queues are paused 722 * @FLOW_POOL_BE_BK_PAUSED: 723 * @FLOW_POOL_VI_PAUSED: 724 * @FLOW_POOL_VO_PAUSED: 725 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 726 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 727 * @FLOW_POOL_ACTIVE_UNPAUSED_REATTACH: pool is reattached but network 728 * queues are not paused 729 */ 730 enum flow_pool_status { 731 FLOW_POOL_ACTIVE_UNPAUSED = 0, 732 FLOW_POOL_ACTIVE_PAUSED = 1, 733 FLOW_POOL_BE_BK_PAUSED = 2, 734 FLOW_POOL_VI_PAUSED = 3, 735 FLOW_POOL_VO_PAUSED = 4, 736 FLOW_POOL_INVALID = 5, 737 FLOW_POOL_INACTIVE = 6, 738 FLOW_POOL_ACTIVE_UNPAUSED_REATTACH = 7, 739 }; 740 741 #else 742 /** 743 * enum flow_pool_status - flow pool status 744 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 745 * and network queues are unpaused 746 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 747 * and network queues are paused 748 * @FLOW_POOL_BE_BK_PAUSED: 749 * @FLOW_POOL_VI_PAUSED: 750 * @FLOW_POOL_VO_PAUSED: 751 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 752 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 753 */ 754 enum flow_pool_status { 755 FLOW_POOL_ACTIVE_UNPAUSED = 0, 756 FLOW_POOL_ACTIVE_PAUSED = 1, 757 FLOW_POOL_BE_BK_PAUSED = 2, 758 FLOW_POOL_VI_PAUSED = 3, 759 FLOW_POOL_VO_PAUSED = 4, 760 FLOW_POOL_INVALID = 5, 761 FLOW_POOL_INACTIVE = 6, 762 }; 763 764 #endif 765 766 /** 767 * struct dp_tx_tso_seg_pool_s 768 * @pool_size: total number of pool elements 769 * @num_free: free element count 770 * @freelist: first free element pointer 771 * @desc_pages: multiple page allocation information for actual descriptors 772 * @lock: lock for accessing the pool 773 */ 774 struct dp_tx_tso_seg_pool_s { 775 uint16_t pool_size; 776 uint16_t num_free; 777 struct qdf_tso_seg_elem_t *freelist; 778 struct qdf_mem_multi_page_t desc_pages; 779 qdf_spinlock_t lock; 780 }; 781 782 /** 783 * struct dp_tx_tso_num_seg_pool_s - TSO Num seg pool 784 * @num_seg_pool_size: total number of pool elements 785 * @num_free: free element count 786 * @freelist: first free element pointer 787 * @desc_pages: multiple page allocation information for actual descriptors 788 * @lock: lock for accessing the pool 789 */ 790 791 struct dp_tx_tso_num_seg_pool_s { 792 uint16_t num_seg_pool_size; 793 uint16_t num_free; 794 struct qdf_tso_num_seg_elem_t *freelist; 795 struct qdf_mem_multi_page_t desc_pages; 796 /*tso mutex */ 797 qdf_spinlock_t lock; 798 }; 799 800 /** 801 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 802 * @elem_size: Size of each descriptor in the pool 803 * @num_allocated: Number of used descriptors 804 * @freelist: Chain of free descriptors 805 * @desc_pages: multiple page allocation information for actual descriptors 806 * @pool_size: Total number of descriptors in the pool 807 * @flow_pool_id: 808 * @num_invalid_bin: Deleted pool with pending Tx completions. 809 * @avail_desc: 810 * @status: 811 * @flow_type: 812 * @stop_th: 813 * @start_th: 814 * @max_pause_time: 815 * @latest_pause_time: 816 * @pkt_drop_no_desc: 817 * @flow_pool_lock: 818 * @pool_create_cnt: 819 * @pool_owner_ctx: 820 * @elem_count: 821 * @num_free: Number of free descriptors 822 * @lock: Lock for descriptor allocation/free from/to the pool 823 */ 824 struct dp_tx_desc_pool_s { 825 uint16_t elem_size; 826 uint32_t num_allocated; 827 struct dp_tx_desc_s *freelist; 828 struct qdf_mem_multi_page_t desc_pages; 829 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 830 uint16_t pool_size; 831 uint8_t flow_pool_id; 832 uint8_t num_invalid_bin; 833 uint16_t avail_desc; 834 enum flow_pool_status status; 835 enum htt_flow_type flow_type; 836 #ifdef QCA_AC_BASED_FLOW_CONTROL 837 uint16_t stop_th[FL_TH_MAX]; 838 uint16_t start_th[FL_TH_MAX]; 839 qdf_time_t max_pause_time[FL_TH_MAX]; 840 qdf_time_t latest_pause_time[FL_TH_MAX]; 841 #else 842 uint16_t stop_th; 843 uint16_t start_th; 844 #endif 845 uint16_t pkt_drop_no_desc; 846 qdf_spinlock_t flow_pool_lock; 847 uint8_t pool_create_cnt; 848 void *pool_owner_ctx; 849 #else 850 uint16_t elem_count; 851 uint32_t num_free; 852 qdf_spinlock_t lock; 853 #endif 854 }; 855 856 /** 857 * struct dp_txrx_pool_stats - flow pool related statistics 858 * @pool_map_count: flow pool map received 859 * @pool_unmap_count: flow pool unmap received 860 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 861 */ 862 struct dp_txrx_pool_stats { 863 uint16_t pool_map_count; 864 uint16_t pool_unmap_count; 865 uint16_t pkt_drop_no_pool; 866 }; 867 868 /** 869 * struct dp_srng - DP srng structure 870 * @hal_srng: hal_srng handle 871 * @base_vaddr_unaligned: un-aligned virtual base address of the srng ring 872 * @base_vaddr_aligned: aligned virtual base address of the srng ring 873 * @base_paddr_unaligned: un-aligned physical base address of the srng ring 874 * @base_paddr_aligned: aligned physical base address of the srng ring 875 * @alloc_size: size of the srng ring 876 * @cached: is the srng ring memory cached or un-cached memory 877 * @irq: irq number of the srng ring 878 * @num_entries: number of entries in the srng ring 879 * @stats: Structure to track the ring utilization stats 880 * @is_mem_prealloc: Is this srng memory pre-allocated 881 * @crit_thresh: Critical threshold for near-full processing of this srng 882 * @safe_thresh: Safe threshold for near-full processing of this srng 883 * @near_full: Flag to indicate srng is near-full 884 */ 885 struct dp_srng { 886 hal_ring_handle_t hal_srng; 887 void *base_vaddr_unaligned; 888 void *base_vaddr_aligned; 889 qdf_dma_addr_t base_paddr_unaligned; 890 qdf_dma_addr_t base_paddr_aligned; 891 uint32_t alloc_size; 892 uint8_t cached; 893 int irq; 894 uint32_t num_entries; 895 struct ring_util_stats stats; 896 #ifdef DP_MEM_PRE_ALLOC 897 uint8_t is_mem_prealloc; 898 #endif 899 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 900 uint16_t crit_thresh; 901 uint16_t safe_thresh; 902 qdf_atomic_t near_full; 903 #endif 904 }; 905 906 struct dp_rx_reorder_array_elem { 907 qdf_nbuf_t head; 908 qdf_nbuf_t tail; 909 }; 910 911 #define DP_RX_BA_INACTIVE 0 912 #define DP_RX_BA_ACTIVE 1 913 #define DP_RX_BA_IN_PROGRESS 2 914 struct dp_reo_cmd_info { 915 uint16_t cmd; 916 enum hal_reo_cmd_type cmd_type; 917 void *data; 918 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 919 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 920 }; 921 922 struct dp_peer_delay_stats { 923 struct cdp_delay_tid_stats delay_tid_stats[CDP_MAX_DATA_TIDS] 924 [CDP_MAX_TXRX_CTX]; 925 }; 926 927 /* Rx TID defrag*/ 928 struct dp_rx_tid_defrag { 929 /* TID */ 930 int tid; 931 932 /* only used for defrag right now */ 933 TAILQ_ENTRY(dp_rx_tid_defrag) defrag_waitlist_elem; 934 935 /* Store dst desc for reinjection */ 936 hal_ring_desc_t dst_ring_desc; 937 struct dp_rx_desc *head_frag_desc; 938 939 /* Sequence and fragments that are being processed currently */ 940 uint32_t curr_seq_num; 941 uint32_t curr_frag_num; 942 943 /* TODO: Check the following while adding defragmentation support */ 944 struct dp_rx_reorder_array_elem *array; 945 /* base - single rx reorder element used for non-aggr cases */ 946 struct dp_rx_reorder_array_elem base; 947 /* rx_tid lock */ 948 qdf_spinlock_t defrag_tid_lock; 949 950 /* head PN number */ 951 uint64_t pn128[2]; 952 953 uint32_t defrag_timeout_ms; 954 955 /* defrag usage only, dp_peer pointer related with this tid */ 956 struct dp_txrx_peer *defrag_peer; 957 }; 958 959 /* Rx TID */ 960 struct dp_rx_tid { 961 /* TID */ 962 int tid; 963 964 /* Num of addba requests */ 965 uint32_t num_of_addba_req; 966 967 /* Num of addba responses */ 968 uint32_t num_of_addba_resp; 969 970 /* Num of delba requests */ 971 uint32_t num_of_delba_req; 972 973 /* Num of addba responses successful */ 974 uint32_t num_addba_rsp_success; 975 976 /* Num of addba responses failed */ 977 uint32_t num_addba_rsp_failed; 978 979 /* pn size */ 980 uint8_t pn_size; 981 /* REO TID queue descriptors */ 982 void *hw_qdesc_vaddr_unaligned; 983 void *hw_qdesc_vaddr_aligned; 984 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 985 qdf_dma_addr_t hw_qdesc_paddr; 986 uint32_t hw_qdesc_alloc_size; 987 988 /* RX ADDBA session state */ 989 int ba_status; 990 991 /* RX BA window size */ 992 uint16_t ba_win_size; 993 994 /* Starting sequence number in Addba request */ 995 uint16_t startseqnum; 996 uint16_t dialogtoken; 997 uint16_t statuscode; 998 /* user defined ADDBA response status code */ 999 uint16_t userstatuscode; 1000 1001 /* rx_tid lock */ 1002 qdf_spinlock_t tid_lock; 1003 1004 /* Store ppdu_id when 2k exception is received */ 1005 uint32_t ppdu_id_2k; 1006 1007 /* Delba Tx completion status */ 1008 uint8_t delba_tx_status; 1009 1010 /* Delba Tx retry count */ 1011 uint8_t delba_tx_retry; 1012 1013 /* Delba stats */ 1014 uint32_t delba_tx_success_cnt; 1015 uint32_t delba_tx_fail_cnt; 1016 1017 /* Delba reason code for retries */ 1018 uint8_t delba_rcode; 1019 1020 /* Coex Override preserved windows size 1 based */ 1021 uint16_t rx_ba_win_size_override; 1022 #ifdef IPA_OFFLOAD 1023 /* rx msdu count per tid */ 1024 struct cdp_pkt_info rx_msdu_cnt; 1025 #endif 1026 1027 }; 1028 1029 /** 1030 * struct dp_intr_stats - DP Interrupt Stats for an interrupt context 1031 * @num_tx_ring_masks: interrupts with tx_ring_mask set 1032 * @num_rx_ring_masks: interrupts with rx_ring_mask set 1033 * @num_rx_mon_ring_masks: interrupts with rx_mon_ring_mask set 1034 * @num_rx_err_ring_masks: interrupts with rx_err_ring_mask set 1035 * @num_rx_wbm_rel_ring_masks: interrupts with rx_wbm_rel_ring_mask set 1036 * @num_reo_status_ring_masks: interrupts with reo_status_ring_mask set 1037 * @num_rxdma2host_ring_masks: interrupts with rxdma2host_ring_mask set 1038 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 1039 * @num_host2rxdma_mon_ring_masks: interrupts with host2rxdma_ring_mask set 1040 * @num_rx_ring_near_full_masks: Near-full interrupts for REO DST ring 1041 * @num_tx_comp_ring_near_full_masks: Near-full interrupts for TX completion 1042 * @num_rx_wbm_rel_ring_near_full_masks: total number of times the wbm rel ring 1043 * near full interrupt was received 1044 * @num_reo_status_ring_near_full_masks: total number of times the reo status 1045 * near full interrupt was received 1046 * @num_near_full_masks: total number of times the near full interrupt 1047 * was received 1048 * @num_masks: total number of times the interrupt was received 1049 * @num_host2txmon_ring__masks: interrupts with host2txmon_ring_mask set 1050 * @num_near_full_masks: total number of times the interrupt was received 1051 * @num_masks: total number of times the near full interrupt was received 1052 * @num_tx_mon_ring_masks: interrupts with num_tx_mon_ring_masks set 1053 * 1054 * Counter for individual masks are incremented only if there are any packets 1055 * on that ring. 1056 */ 1057 struct dp_intr_stats { 1058 uint32_t num_tx_ring_masks[MAX_TCL_DATA_RINGS]; 1059 uint32_t num_rx_ring_masks[MAX_REO_DEST_RINGS]; 1060 uint32_t num_rx_mon_ring_masks; 1061 uint32_t num_rx_err_ring_masks; 1062 uint32_t num_rx_wbm_rel_ring_masks; 1063 uint32_t num_reo_status_ring_masks; 1064 uint32_t num_rxdma2host_ring_masks; 1065 uint32_t num_host2rxdma_ring_masks; 1066 uint32_t num_host2rxdma_mon_ring_masks; 1067 uint32_t num_rx_ring_near_full_masks[MAX_REO_DEST_RINGS]; 1068 uint32_t num_tx_comp_ring_near_full_masks[MAX_TCL_DATA_RINGS]; 1069 uint32_t num_rx_wbm_rel_ring_near_full_masks; 1070 uint32_t num_reo_status_ring_near_full_masks; 1071 uint32_t num_host2txmon_ring__masks; 1072 uint32_t num_near_full_masks; 1073 uint32_t num_masks; 1074 uint32_t num_tx_mon_ring_masks; 1075 }; 1076 1077 #ifdef DP_UMAC_HW_RESET_SUPPORT 1078 /** 1079 * struct dp_intr_bkp - DP per interrupt context ring masks old state 1080 * @tx_ring_mask: WBM Tx completion rings (0-2) associated with this napi ctxt 1081 * @rx_ring_mask: Rx REO rings (0-3) associated with this interrupt context 1082 * @rx_mon_ring_mask: Rx monitor ring mask (0-2) 1083 * @rx_err_ring_mask: REO Exception Ring 1084 * @rx_wbm_rel_ring_mask: WBM2SW Rx Release Ring 1085 * @reo_status_ring_mask: REO command response ring 1086 * @rxdma2host_ring_mask: RXDMA to host destination ring 1087 * @host2rxdma_ring_mask: Host to RXDMA buffer ring 1088 * @host2rxdma_mon_ring_mask: Host to RXDMA monitor buffer ring 1089 * @host2txmon_ring_mask: Tx monitor buffer ring 1090 * @tx_mon_ring_mask: Tx monitor ring mask (0-2) 1091 * 1092 */ 1093 struct dp_intr_bkp { 1094 uint8_t tx_ring_mask; 1095 uint8_t rx_ring_mask; 1096 uint8_t rx_mon_ring_mask; 1097 uint8_t rx_err_ring_mask; 1098 uint8_t rx_wbm_rel_ring_mask; 1099 uint8_t reo_status_ring_mask; 1100 uint8_t rxdma2host_ring_mask; 1101 uint8_t host2rxdma_ring_mask; 1102 uint8_t host2rxdma_mon_ring_mask; 1103 uint8_t host2txmon_ring_mask; 1104 uint8_t tx_mon_ring_mask; 1105 }; 1106 #endif 1107 1108 /* per interrupt context */ 1109 struct dp_intr { 1110 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 1111 associated with this napi context */ 1112 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 1113 with this interrupt context */ 1114 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 1115 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 1116 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 1117 uint8_t reo_status_ring_mask; /* REO command response ring */ 1118 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 1119 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 1120 /* Host to RXDMA monitor buffer ring */ 1121 uint8_t host2rxdma_mon_ring_mask; 1122 /* RX REO rings near full interrupt mask */ 1123 uint8_t rx_near_full_grp_1_mask; 1124 /* RX REO rings near full interrupt mask */ 1125 uint8_t rx_near_full_grp_2_mask; 1126 /* WBM TX completion rings near full interrupt mask */ 1127 uint8_t tx_ring_near_full_mask; 1128 uint8_t host2txmon_ring_mask; /* Tx monitor buffer ring */ 1129 uint8_t tx_mon_ring_mask; /* Tx monitor ring mask (0-2) */ 1130 struct dp_soc *soc; /* Reference to SoC structure , 1131 to get DMA ring handles */ 1132 qdf_lro_ctx_t lro_ctx; 1133 uint8_t dp_intr_id; 1134 1135 /* Interrupt Stats for individual masks */ 1136 struct dp_intr_stats intr_stats; 1137 uint8_t umac_reset_intr_mask; /* UMAC reset interrupt mask */ 1138 }; 1139 1140 #define REO_DESC_FREELIST_SIZE 64 1141 #define REO_DESC_FREE_DEFER_MS 1000 1142 struct reo_desc_list_node { 1143 qdf_list_node_t node; 1144 unsigned long free_ts; 1145 struct dp_rx_tid rx_tid; 1146 bool resend_update_reo_cmd; 1147 uint32_t pending_ext_desc_size; 1148 #ifdef REO_QDESC_HISTORY 1149 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1150 #endif 1151 }; 1152 1153 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 1154 #define REO_DESC_DEFERRED_FREELIST_SIZE 256 1155 #define REO_DESC_DEFERRED_FREE_MS 30000 1156 1157 struct reo_desc_deferred_freelist_node { 1158 qdf_list_node_t node; 1159 unsigned long free_ts; 1160 void *hw_qdesc_vaddr_unaligned; 1161 qdf_dma_addr_t hw_qdesc_paddr; 1162 uint32_t hw_qdesc_alloc_size; 1163 #ifdef REO_QDESC_HISTORY 1164 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1165 #endif /* REO_QDESC_HISTORY */ 1166 }; 1167 #endif /* WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY */ 1168 1169 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1170 /** 1171 * struct reo_cmd_event_record: Elements to record for each reo command 1172 * @cmd_type: reo command type 1173 * @cmd_return_status: reo command post status 1174 * @timestamp: record timestamp for the reo command 1175 */ 1176 struct reo_cmd_event_record { 1177 enum hal_reo_cmd_type cmd_type; 1178 uint8_t cmd_return_status; 1179 uint64_t timestamp; 1180 }; 1181 1182 /** 1183 * struct reo_cmd_event_history: Account for reo cmd events 1184 * @index: record number 1185 * @cmd_record: list of records 1186 */ 1187 struct reo_cmd_event_history { 1188 qdf_atomic_t index; 1189 struct reo_cmd_event_record cmd_record[REO_CMD_EVENT_HIST_MAX]; 1190 }; 1191 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1192 1193 /** 1194 * struct htt_t2h_msg_stats: HTT T2H message stats 1195 * @peer_map: Peer map event count 1196 * @peer_unmap: Peer unmap event count (peer_unmap -= ml_peer_unmap) 1197 * @invalid_peer_unmap: Peer unmap with invalid peer id 1198 * @ml_peer_map: MLD peer map count 1199 * @ml_peer_unmap: MLD peer unmap count 1200 */ 1201 struct htt_t2h_msg_stats { 1202 uint32_t peer_map; 1203 uint32_t peer_unmap; 1204 uint32_t invalid_peer_unmap; 1205 uint32_t ml_peer_map; 1206 uint32_t ml_peer_unmap; 1207 }; 1208 1209 /* SoC level data path statistics */ 1210 struct dp_soc_stats { 1211 struct { 1212 uint32_t added; 1213 uint32_t deleted; 1214 uint32_t aged_out; 1215 uint32_t map_err; 1216 uint32_t ast_mismatch; 1217 } ast; 1218 1219 struct { 1220 uint32_t added; 1221 uint32_t deleted; 1222 } mec; 1223 1224 /* SOC level TX stats */ 1225 struct { 1226 /* Total packets transmitted */ 1227 struct cdp_pkt_info egress[MAX_TCL_DATA_RINGS]; 1228 /* Enqueues per tcl ring */ 1229 uint32_t tcl_enq[MAX_TCL_DATA_RINGS]; 1230 /* packets dropped on tx because of no peer */ 1231 struct cdp_pkt_info tx_invalid_peer; 1232 /* descriptors in each tcl ring */ 1233 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 1234 /* Descriptors in use at soc */ 1235 uint32_t desc_in_use; 1236 /* tqm_release_reason == FW removed */ 1237 uint32_t dropped_fw_removed; 1238 /* tx completion release_src != TQM or FW */ 1239 uint32_t invalid_release_source; 1240 /* TX descriptor from completion ring Desc is not valid */ 1241 uint32_t invalid_tx_comp_desc; 1242 /* tx completion wbm_internal_error */ 1243 uint32_t wbm_internal_error[MAX_WBM_INT_ERROR_REASONS]; 1244 /* tx completion non_wbm_internal_error */ 1245 uint32_t non_wbm_internal_err; 1246 /* TX Comp loop packet limit hit */ 1247 uint32_t tx_comp_loop_pkt_limit_hit; 1248 /* Head pointer Out of sync at the end of dp_tx_comp_handler */ 1249 uint32_t hp_oos2; 1250 /* tx desc freed as part of vdev detach */ 1251 uint32_t tx_comp_exception; 1252 /* TQM drops after/during peer delete */ 1253 uint64_t tqm_drop_no_peer; 1254 /* Number of tx completions reaped per WBM2SW release ring */ 1255 uint32_t tx_comp[MAX_TCL_DATA_RINGS]; 1256 /* Number of tx completions force freed */ 1257 uint32_t tx_comp_force_freed; 1258 /* Tx completion ring near full */ 1259 uint32_t near_full; 1260 /* Tx drops with buffer src as HAL_TX_COMP_RELEASE_SOURCE_FW */ 1261 uint32_t fw2wbm_tx_drop; 1262 } tx; 1263 1264 /* SOC level RX stats */ 1265 struct { 1266 /* Total rx packets count */ 1267 struct cdp_pkt_info ingress; 1268 /* Rx errors */ 1269 /* Total Packets in Rx Error ring */ 1270 uint32_t err_ring_pkts; 1271 /* No of Fragments */ 1272 uint32_t rx_frags; 1273 /* No of incomplete fragments in waitlist */ 1274 uint32_t rx_frag_wait; 1275 /* Fragments dropped due to errors */ 1276 uint32_t rx_frag_err; 1277 /* Fragments received OOR causing sequence num mismatch */ 1278 uint32_t rx_frag_oor; 1279 /* Fragments dropped due to len errors in skb */ 1280 uint32_t rx_frag_err_len_error; 1281 /* Fragments dropped due to no peer found */ 1282 uint32_t rx_frag_err_no_peer; 1283 /* No of reinjected packets */ 1284 uint32_t reo_reinject; 1285 /* Reap loop packet limit hit */ 1286 uint32_t reap_loop_pkt_limit_hit; 1287 /* Head pointer Out of sync at the end of dp_rx_process */ 1288 uint32_t hp_oos2; 1289 /* Rx ring near full */ 1290 uint32_t near_full; 1291 /* Break ring reaping as not all scattered msdu received */ 1292 uint32_t msdu_scatter_wait_break; 1293 /* Number of bar frames received */ 1294 uint32_t bar_frame; 1295 /* Number of frames routed from rxdma */ 1296 uint32_t rxdma2rel_route_drop; 1297 /* Number of frames routed from reo*/ 1298 uint32_t reo2rel_route_drop; 1299 uint64_t fast_recycled; 1300 /* Number of hw stats requested */ 1301 uint32_t rx_hw_stats_requested; 1302 /* Number of hw stats request timeout */ 1303 uint32_t rx_hw_stats_timeout; 1304 1305 struct { 1306 /* Invalid RBM error count */ 1307 uint32_t invalid_rbm; 1308 /* Invalid VDEV Error count */ 1309 uint32_t invalid_vdev; 1310 /* Invalid PDEV error count */ 1311 uint32_t invalid_pdev; 1312 1313 /* Packets delivered to stack that no related peer */ 1314 uint32_t pkt_delivered_no_peer; 1315 /* Defrag peer uninit error count */ 1316 uint32_t defrag_peer_uninit; 1317 /* Invalid sa_idx or da_idx*/ 1318 uint32_t invalid_sa_da_idx; 1319 /* MSDU DONE failures */ 1320 uint32_t msdu_done_fail; 1321 /* Invalid PEER Error count */ 1322 struct cdp_pkt_info rx_invalid_peer; 1323 /* Invalid PEER ID count */ 1324 struct cdp_pkt_info rx_invalid_peer_id; 1325 /* Invalid packet length */ 1326 struct cdp_pkt_info rx_invalid_pkt_len; 1327 /* HAL ring access Fail error count */ 1328 uint32_t hal_ring_access_fail; 1329 /* HAL ring access full Fail error count */ 1330 uint32_t hal_ring_access_full_fail; 1331 /* RX DMA error count */ 1332 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 1333 /* RX REO DEST Desc Invalid Magic count */ 1334 uint32_t rx_desc_invalid_magic; 1335 /* REO Error count */ 1336 uint32_t reo_error[HAL_REO_ERR_MAX]; 1337 /* HAL REO ERR Count */ 1338 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 1339 /* HAL REO DEST Duplicate count */ 1340 uint32_t hal_reo_dest_dup; 1341 /* HAL WBM RELEASE Duplicate count */ 1342 uint32_t hal_wbm_rel_dup; 1343 /* HAL RXDMA error Duplicate count */ 1344 uint32_t hal_rxdma_err_dup; 1345 /* ipa smmu map duplicate count */ 1346 uint32_t ipa_smmu_map_dup; 1347 /* ipa smmu unmap duplicate count */ 1348 uint32_t ipa_smmu_unmap_dup; 1349 /* ipa smmu unmap while ipa pipes is disabled */ 1350 uint32_t ipa_unmap_no_pipe; 1351 /* REO cmd send fail/requeue count */ 1352 uint32_t reo_cmd_send_fail; 1353 /* REO cmd send drain count */ 1354 uint32_t reo_cmd_send_drain; 1355 /* RX msdu drop count due to scatter */ 1356 uint32_t scatter_msdu; 1357 /* RX msdu drop count due to invalid cookie */ 1358 uint32_t invalid_cookie; 1359 /* Count of stale cookie read in RX path */ 1360 uint32_t stale_cookie; 1361 /* Delba sent count due to RX 2k jump */ 1362 uint32_t rx_2k_jump_delba_sent; 1363 /* RX 2k jump msdu indicated to stack count */ 1364 uint32_t rx_2k_jump_to_stack; 1365 /* RX 2k jump msdu dropped count */ 1366 uint32_t rx_2k_jump_drop; 1367 /* REO ERR msdu buffer received */ 1368 uint32_t reo_err_msdu_buf_rcved; 1369 /* REO ERR msdu buffer with invalid coookie received */ 1370 uint32_t reo_err_msdu_buf_invalid_cookie; 1371 /* REO OOR msdu drop count */ 1372 uint32_t reo_err_oor_drop; 1373 /* REO OOR msdu indicated to stack count */ 1374 uint32_t reo_err_oor_to_stack; 1375 /* REO OOR scattered msdu count */ 1376 uint32_t reo_err_oor_sg_count; 1377 /* RX msdu rejected count on delivery to vdev stack_fn*/ 1378 uint32_t rejected; 1379 /* Incorrect msdu count in MPDU desc info */ 1380 uint32_t msdu_count_mismatch; 1381 /* RX raw frame dropped count */ 1382 uint32_t raw_frm_drop; 1383 /* Stale link desc cookie count*/ 1384 uint32_t invalid_link_cookie; 1385 /* Nbuf sanity failure */ 1386 uint32_t nbuf_sanity_fail; 1387 /* Duplicate link desc refilled */ 1388 uint32_t dup_refill_link_desc; 1389 /* Incorrect msdu continuation bit in MSDU desc */ 1390 uint32_t msdu_continuation_err; 1391 /* count of start sequence (ssn) updates */ 1392 uint32_t ssn_update_count; 1393 /* count of bar handling fail */ 1394 uint32_t bar_handle_fail_count; 1395 /* EAPOL drop count in intrabss scenario */ 1396 uint32_t intrabss_eapol_drop; 1397 /* PN check failed for 2K-jump or OOR error */ 1398 uint32_t pn_in_dest_check_fail; 1399 /* MSDU len err count */ 1400 uint32_t msdu_len_err; 1401 /* Rx flush count */ 1402 uint32_t rx_flush_count; 1403 /* Rx invalid tid count */ 1404 uint32_t rx_invalid_tid_err; 1405 /* Invalid address1 in defrag path*/ 1406 uint32_t defrag_ad1_invalid; 1407 /* decrypt error drop */ 1408 uint32_t decrypt_err_drop; 1409 #ifdef GLOBAL_ASSERT_AVOIDANCE 1410 /* rx_desc NULL war count*/ 1411 uint32_t rx_desc_null; 1412 /* wbm err invalid release buffer type */ 1413 uint32_t wbm_err_buf_rel_type; 1414 /* Reo entry rx desc null */ 1415 uint32_t reo_err_rx_desc_null; 1416 /* Invalid chip id received in intrabss path */ 1417 uint64_t intra_bss_bad_chipid; 1418 #endif 1419 } err; 1420 1421 /* packet count per core - per ring */ 1422 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 1423 } rx; 1424 1425 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1426 struct reo_cmd_event_history cmd_event_history; 1427 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1428 struct htt_t2h_msg_stats t2h_msg_stats; 1429 }; 1430 1431 union dp_align_mac_addr { 1432 uint8_t raw[QDF_MAC_ADDR_SIZE]; 1433 struct { 1434 uint16_t bytes_ab; 1435 uint16_t bytes_cd; 1436 uint16_t bytes_ef; 1437 } align2; 1438 struct { 1439 uint32_t bytes_abcd; 1440 uint16_t bytes_ef; 1441 } align4; 1442 struct __attribute__((__packed__)) { 1443 uint16_t bytes_ab; 1444 uint32_t bytes_cdef; 1445 } align4_2; 1446 }; 1447 1448 /** 1449 * struct dp_ast_free_cb_params - HMWDS free callback cookie 1450 * @mac_addr: ast mac address 1451 * @peer_mac_addr: mac address of peer 1452 * @type: ast entry type 1453 * @vdev_id: vdev_id 1454 * @flags: ast flags 1455 */ 1456 struct dp_ast_free_cb_params { 1457 union dp_align_mac_addr mac_addr; 1458 union dp_align_mac_addr peer_mac_addr; 1459 enum cdp_txrx_ast_entry_type type; 1460 uint8_t vdev_id; 1461 uint32_t flags; 1462 }; 1463 1464 /** 1465 * struct dp_ast_entry - AST entry 1466 * 1467 * @ast_idx: Hardware AST Index 1468 * @peer_id: Next Hop peer_id (for non-WDS nodes, this will be point to 1469 * associated peer with this MAC address) 1470 * @mac_addr: MAC Address for this AST entry 1471 * @next_hop: Set to 1 if this is for a WDS node 1472 * @is_active: flag to indicate active data traffic on this node 1473 * (used for aging out/expiry) 1474 * @ase_list_elem: node in peer AST list 1475 * @is_bss: flag to indicate if entry corresponds to bss peer 1476 * @is_mapped: flag to indicate that we have mapped the AST entry 1477 * in ast_table 1478 * @pdev_id: pdev ID 1479 * @vdev_id: vdev ID 1480 * @ast_hash_value: hast value in HW 1481 * @ref_cnt: reference count 1482 * @type: flag to indicate type of the entry(static/WDS/MEC) 1483 * @delete_in_progress: Flag to indicate that delete commands send to FW 1484 * and host is waiting for response from FW 1485 * @callback: ast free/unmap callback 1486 * @cookie: argument to callback 1487 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 1488 */ 1489 struct dp_ast_entry { 1490 uint16_t ast_idx; 1491 uint16_t peer_id; 1492 union dp_align_mac_addr mac_addr; 1493 bool next_hop; 1494 bool is_active; 1495 bool is_mapped; 1496 uint8_t pdev_id; 1497 uint8_t vdev_id; 1498 uint16_t ast_hash_value; 1499 qdf_atomic_t ref_cnt; 1500 enum cdp_txrx_ast_entry_type type; 1501 bool delete_in_progress; 1502 txrx_ast_free_cb callback; 1503 void *cookie; 1504 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 1505 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 1506 }; 1507 1508 /** 1509 * struct dp_mec_entry - MEC entry 1510 * 1511 * @mac_addr: MAC Address for this MEC entry 1512 * @is_active: flag to indicate active data traffic on this node 1513 * (used for aging out/expiry) 1514 * @pdev_id: pdev ID 1515 * @vdev_id: vdev ID 1516 * @hash_list_elem: node in soc MEC hash list (mac address used as hash) 1517 */ 1518 struct dp_mec_entry { 1519 union dp_align_mac_addr mac_addr; 1520 bool is_active; 1521 uint8_t pdev_id; 1522 uint8_t vdev_id; 1523 1524 TAILQ_ENTRY(dp_mec_entry) hash_list_elem; 1525 }; 1526 1527 /* SOC level htt stats */ 1528 struct htt_t2h_stats { 1529 /* lock to protect htt_stats_msg update */ 1530 qdf_spinlock_t lock; 1531 1532 /* work queue to process htt stats */ 1533 qdf_work_t work; 1534 1535 /* T2H Ext stats message queue */ 1536 qdf_nbuf_queue_t msg; 1537 1538 /* number of completed stats in htt_stats_msg */ 1539 uint32_t num_stats; 1540 }; 1541 1542 struct link_desc_bank { 1543 void *base_vaddr_unaligned; 1544 void *base_vaddr; 1545 qdf_dma_addr_t base_paddr_unaligned; 1546 qdf_dma_addr_t base_paddr; 1547 uint32_t size; 1548 }; 1549 1550 struct rx_buff_pool { 1551 qdf_nbuf_queue_head_t emerg_nbuf_q; 1552 uint32_t nbuf_fail_cnt; 1553 bool is_initialized; 1554 }; 1555 1556 struct rx_refill_buff_pool { 1557 bool is_initialized; 1558 uint16_t head; 1559 uint16_t tail; 1560 struct dp_pdev *dp_pdev; 1561 uint16_t max_bufq_len; 1562 qdf_nbuf_t *buf_elem; 1563 }; 1564 1565 #ifdef DP_TX_HW_DESC_HISTORY 1566 #define DP_TX_HW_DESC_HIST_MAX 6144 1567 #define DP_TX_HW_DESC_HIST_PER_SLOT_MAX 2048 1568 #define DP_TX_HW_DESC_HIST_MAX_SLOTS 3 1569 #define DP_TX_HW_DESC_HIST_SLOT_SHIFT 11 1570 1571 struct dp_tx_hw_desc_evt { 1572 uint8_t tcl_desc[HAL_TX_DESC_LEN_BYTES]; 1573 uint8_t tcl_ring_id; 1574 uint64_t posted; 1575 uint32_t hp; 1576 uint32_t tp; 1577 }; 1578 1579 /* struct dp_tx_hw_desc_history - TX HW desc hisotry 1580 * @index: Index where the last entry is written 1581 * @entry: history entries 1582 */ 1583 struct dp_tx_hw_desc_history { 1584 qdf_atomic_t index; 1585 uint16_t num_entries_per_slot; 1586 uint16_t allocated; 1587 struct dp_tx_hw_desc_evt *entry[DP_TX_HW_DESC_HIST_MAX_SLOTS]; 1588 }; 1589 #endif 1590 1591 /** 1592 * enum dp_mon_status_process_event - Events for monitor status buffer record 1593 * @DP_MON_STATUS_BUF_REAP: Monitor status buffer is reaped from ring 1594 * @DP_MON_STATUS_BUF_ENQUEUE: Status buffer is enqueued to local queue 1595 * @DP_MON_STATUS_BUF_DEQUEUE: Status buffer is dequeued from local queue 1596 */ 1597 enum dp_mon_status_process_event { 1598 DP_MON_STATUS_BUF_REAP, 1599 DP_MON_STATUS_BUF_ENQUEUE, 1600 DP_MON_STATUS_BUF_DEQUEUE, 1601 }; 1602 1603 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 1604 #define DP_MON_STATUS_HIST_MAX 2048 1605 1606 /** 1607 * struct dp_mon_stat_info_record - monitor stat ring buffer info 1608 * @hbi: HW ring buffer info 1609 * @timestamp: timestamp when this entry was recorded 1610 * @event: event 1611 * @rx_desc: RX descriptor corresponding to the received buffer 1612 * @nbuf: buffer attached to rx_desc, if event is REAP, else the buffer 1613 * which was enqueued or dequeued. 1614 * @rx_desc_nbuf_data: nbuf data pointer. 1615 */ 1616 struct dp_mon_stat_info_record { 1617 struct hal_buf_info hbi; 1618 uint64_t timestamp; 1619 enum dp_mon_status_process_event event; 1620 void *rx_desc; 1621 qdf_nbuf_t nbuf; 1622 uint8_t *rx_desc_nbuf_data; 1623 }; 1624 1625 /* struct dp_rx_history - rx ring hisotry 1626 * @index: Index where the last entry is written 1627 * @entry: history entries 1628 */ 1629 struct dp_mon_status_ring_history { 1630 qdf_atomic_t index; 1631 struct dp_mon_stat_info_record entry[DP_MON_STATUS_HIST_MAX]; 1632 }; 1633 #endif 1634 1635 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 1636 /* 1637 * The logic for get current index of these history is dependent on this 1638 * value being power of 2. 1639 */ 1640 #define DP_RX_HIST_MAX 2048 1641 #define DP_RX_ERR_HIST_MAX 2048 1642 #define DP_RX_REINJECT_HIST_MAX 1024 1643 #define DP_RX_REFILL_HIST_MAX 2048 1644 1645 QDF_COMPILE_TIME_ASSERT(rx_history_size, 1646 (DP_RX_HIST_MAX & 1647 (DP_RX_HIST_MAX - 1)) == 0); 1648 QDF_COMPILE_TIME_ASSERT(rx_err_history_size, 1649 (DP_RX_ERR_HIST_MAX & 1650 (DP_RX_ERR_HIST_MAX - 1)) == 0); 1651 QDF_COMPILE_TIME_ASSERT(rx_reinject_history_size, 1652 (DP_RX_REINJECT_HIST_MAX & 1653 (DP_RX_REINJECT_HIST_MAX - 1)) == 0); 1654 QDF_COMPILE_TIME_ASSERT(rx_refill_history_size, 1655 (DP_RX_REFILL_HIST_MAX & 1656 (DP_RX_REFILL_HIST_MAX - 1)) == 0); 1657 1658 1659 /** 1660 * struct dp_buf_info_record - ring buffer info 1661 * @hbi: HW ring buffer info 1662 * @timestamp: timestamp when this entry was recorded 1663 */ 1664 struct dp_buf_info_record { 1665 struct hal_buf_info hbi; 1666 uint64_t timestamp; 1667 }; 1668 1669 /** 1670 * struct dp_refill_info_record - ring refill buffer info 1671 * @hp: HP value after refill 1672 * @tp: cached tail value during refill 1673 * @num_req: number of buffers requested to refill 1674 * @num_refill: number of buffers refilled to ring 1675 * @timestamp: timestamp when this entry was recorded 1676 */ 1677 struct dp_refill_info_record { 1678 uint32_t hp; 1679 uint32_t tp; 1680 uint32_t num_req; 1681 uint32_t num_refill; 1682 uint64_t timestamp; 1683 }; 1684 1685 /** 1686 * struct dp_rx_history - rx ring hisotry 1687 * @index: Index where the last entry is written 1688 * @entry: history entries 1689 */ 1690 struct dp_rx_history { 1691 qdf_atomic_t index; 1692 struct dp_buf_info_record entry[DP_RX_HIST_MAX]; 1693 }; 1694 1695 /** 1696 * struct dp_rx_err_history - rx err ring hisotry 1697 * @index: Index where the last entry is written 1698 * @entry: history entries 1699 */ 1700 struct dp_rx_err_history { 1701 qdf_atomic_t index; 1702 struct dp_buf_info_record entry[DP_RX_ERR_HIST_MAX]; 1703 }; 1704 1705 /** 1706 * struct dp_rx_reinject_history - rx reinject ring hisotry 1707 * @index: Index where the last entry is written 1708 * @entry: history entries 1709 */ 1710 struct dp_rx_reinject_history { 1711 qdf_atomic_t index; 1712 struct dp_buf_info_record entry[DP_RX_REINJECT_HIST_MAX]; 1713 }; 1714 1715 /** 1716 * struct dp_rx_refill_history - rx buf refill hisotry 1717 * @index: Index where the last entry is written 1718 * @entry: history entries 1719 */ 1720 struct dp_rx_refill_history { 1721 qdf_atomic_t index; 1722 struct dp_refill_info_record entry[DP_RX_REFILL_HIST_MAX]; 1723 }; 1724 1725 #endif 1726 1727 /** 1728 * enum dp_cfg_event_type - Datapath config events type 1729 * @DP_CFG_EVENT_VDEV_ATTACH: vdev attach 1730 * @DP_CFG_EVENT_VDEV_DETACH: vdev detach 1731 * @DP_CFG_EVENT_VDEV_UNREF_DEL: vdev memory free after last ref is released 1732 * @DP_CFG_EVENT_PEER_CREATE: peer create 1733 * @DP_CFG_EVENT_PEER_DELETE: peer delete 1734 * @DP_CFG_EVENT_PEER_UNREF_DEL: peer memory free after last ref is released 1735 * @DP_CFG_EVENT_PEER_SETUP: peer setup 1736 * @DP_CFG_EVENT_MLO_ADD_LINK: add link peer to mld peer 1737 * @DP_CFG_EVENT_MLO_DEL_LINK: delete link peer from mld peer 1738 * @DP_CFG_EVENT_MLO_SETUP: MLO peer setup 1739 * @DP_CFG_EVENT_MLO_SETUP_VDEV_UPDATE: MLD peer vdev update 1740 * @DP_CFG_EVENT_PEER_MAP: peer map 1741 * @DP_CFG_EVENT_PEER_UNMAP: peer unmap 1742 * @DP_CFG_EVENT_MLO_PEER_MAP: MLD peer map 1743 * @DP_CFG_EVENT_MLO_PEER_UNMAP: MLD peer unmap 1744 */ 1745 enum dp_cfg_event_type { 1746 DP_CFG_EVENT_VDEV_ATTACH, 1747 DP_CFG_EVENT_VDEV_DETACH, 1748 DP_CFG_EVENT_VDEV_UNREF_DEL, 1749 DP_CFG_EVENT_PEER_CREATE, 1750 DP_CFG_EVENT_PEER_DELETE, 1751 DP_CFG_EVENT_PEER_UNREF_DEL, 1752 DP_CFG_EVENT_PEER_SETUP, 1753 DP_CFG_EVENT_MLO_ADD_LINK, 1754 DP_CFG_EVENT_MLO_DEL_LINK, 1755 DP_CFG_EVENT_MLO_SETUP, 1756 DP_CFG_EVENT_MLO_SETUP_VDEV_UPDATE, 1757 DP_CFG_EVENT_PEER_MAP, 1758 DP_CFG_EVENT_PEER_UNMAP, 1759 DP_CFG_EVENT_MLO_PEER_MAP, 1760 DP_CFG_EVENT_MLO_PEER_UNMAP, 1761 }; 1762 1763 #ifdef WLAN_FEATURE_DP_CFG_EVENT_HISTORY 1764 /* Size must be in 2 power, for bitwise index rotation */ 1765 #define DP_CFG_EVT_HISTORY_SIZE 0x800 1766 #define DP_CFG_EVT_HIST_PER_SLOT_MAX 256 1767 #define DP_CFG_EVT_HIST_MAX_SLOTS 8 1768 #define DP_CFG_EVT_HIST_SLOT_SHIFT 8 1769 1770 /** 1771 * struct dp_vdev_attach_detach_desc - vdev ops descriptor 1772 * @vdev: DP vdev handle 1773 * @mac_addr: vdev mac address 1774 * @vdev_id: vdev id 1775 * @ref_count: vdev ref count 1776 */ 1777 struct dp_vdev_attach_detach_desc { 1778 struct dp_vdev *vdev; 1779 union dp_align_mac_addr mac_addr; 1780 uint8_t vdev_id; 1781 int32_t ref_count; 1782 }; 1783 1784 /** 1785 * struct dp_peer_cmn_ops_desc - peer events descriptor 1786 * @vdev_id: vdev_id of the vdev on which peer exists 1787 * @is_reuse: indicates if its a peer reuse case, during peer create 1788 * @peer: DP peer handle 1789 * @vdev: DP vdev handle on which peer exists 1790 * @mac_addr: peer mac address 1791 * @vdev_mac_addr: vdev mac address 1792 * @vdev_ref_count: vdev ref count 1793 * @peer_ref_count: peer ref count 1794 */ 1795 struct dp_peer_cmn_ops_desc { 1796 uint8_t vdev_id : 5, 1797 is_reuse : 1; 1798 struct dp_peer *peer; 1799 struct dp_vdev *vdev; 1800 union dp_align_mac_addr mac_addr; 1801 union dp_align_mac_addr vdev_mac_addr; 1802 int32_t vdev_ref_count; 1803 int32_t peer_ref_count; 1804 }; 1805 1806 /** 1807 * struct dp_mlo_add_del_link_desc - MLO add/del link event descriptor 1808 * @idx: index at which link peer got added in MLD peer's list 1809 * @num_links: num links added in the MLD peer's list 1810 * @action_result: add/del was success or not 1811 * @reserved: reserved bit 1812 * @link_peer: link peer handle 1813 * @mld_peer: MLD peer handle 1814 * @link_mac_addr: link peer mac address 1815 * @mld_mac_addr: MLD peer mac address 1816 */ 1817 struct dp_mlo_add_del_link_desc { 1818 uint8_t idx : 3, 1819 num_links : 3, 1820 action_result : 1, 1821 reserved : 1; 1822 struct dp_peer *link_peer; 1823 struct dp_peer *mld_peer; 1824 union dp_align_mac_addr link_mac_addr; 1825 union dp_align_mac_addr mld_mac_addr; 1826 }; 1827 1828 /** 1829 * struct dp_mlo_setup_vdev_update_desc - MLD peer vdev update event desc 1830 * @mld_peer: MLD peer handle 1831 * @prev_vdev: previous vdev handle 1832 * @new_vdev: new vdev handle 1833 */ 1834 struct dp_mlo_setup_vdev_update_desc { 1835 struct dp_peer *mld_peer; 1836 struct dp_vdev *prev_vdev; 1837 struct dp_vdev *new_vdev; 1838 }; 1839 1840 /** 1841 * struct dp_rx_peer_map_unmap_desc - peer map/unmap event descriptor 1842 * @peer_id: peer id 1843 * @ml_peer_id: ML peer id, if its an MLD peer 1844 * @hw_peer_id: hw peer id 1845 * @vdev_id: vdev id of the peer 1846 * @is_ml_peer: is this MLD peer 1847 * @mac_addr: mac address of the peer 1848 * @peer: peer handle 1849 */ 1850 struct dp_rx_peer_map_unmap_desc { 1851 uint16_t peer_id; 1852 uint16_t ml_peer_id; 1853 uint16_t hw_peer_id; 1854 uint8_t vdev_id; 1855 uint8_t is_ml_peer; 1856 union dp_align_mac_addr mac_addr; 1857 struct dp_peer *peer; 1858 }; 1859 1860 /** 1861 * struct dp_peer_setup_desc - peer setup event descriptor 1862 * @peer: DP peer handle 1863 * @vdev: vdev handle on which peer exists 1864 * @vdev_ref_count: vdev ref count 1865 * @mac_addr: peer mac address 1866 * @mld_mac_addr: MLD mac address 1867 * @is_first_link: is the current link the first link created 1868 * @is_primary_link: is the current link primary link 1869 * @vdev_id: vdev id of the vdev on which the current link peer exists 1870 * @reserved: reserved bit 1871 */ 1872 struct dp_peer_setup_desc { 1873 struct dp_peer *peer; 1874 struct dp_vdev *vdev; 1875 int32_t vdev_ref_count; 1876 union dp_align_mac_addr mac_addr; 1877 union dp_align_mac_addr mld_mac_addr; 1878 uint8_t is_first_link : 1, 1879 is_primary_link : 1, 1880 vdev_id : 5, 1881 reserved : 1; 1882 }; 1883 1884 /** 1885 * union dp_cfg_event_desc - DP config event descriptor 1886 * @vdev_evt: vdev events desc 1887 * @peer_cmn_evt: common peer events desc 1888 * @peer_setup_evt: peer setup event desc 1889 * @mlo_link_delink_evt: MLO link/delink event desc 1890 * @mlo_setup_vdev_update: MLD peer vdev update event desc 1891 * @peer_map_unmap_evt: peer map/unmap event desc 1892 */ 1893 union dp_cfg_event_desc { 1894 struct dp_vdev_attach_detach_desc vdev_evt; 1895 struct dp_peer_cmn_ops_desc peer_cmn_evt; 1896 struct dp_peer_setup_desc peer_setup_evt; 1897 struct dp_mlo_add_del_link_desc mlo_link_delink_evt; 1898 struct dp_mlo_setup_vdev_update_desc mlo_setup_vdev_update; 1899 struct dp_rx_peer_map_unmap_desc peer_map_unmap_evt; 1900 }; 1901 1902 /** 1903 * struct dp_cfg_event - DP config event descriptor 1904 * @timestamp: timestamp at which event was recorded 1905 * @type: event type 1906 * @event_desc: event descriptor 1907 */ 1908 struct dp_cfg_event { 1909 uint64_t timestamp; 1910 enum dp_cfg_event_type type; 1911 union dp_cfg_event_desc event_desc; 1912 }; 1913 1914 /** 1915 * struct dp_cfg_event_history - DP config event history 1916 * @index: current index 1917 * @num_entries_per_slot: number of entries per slot 1918 * @allocated: Is the history allocated or not 1919 * @entry: event history descriptors 1920 */ 1921 struct dp_cfg_event_history { 1922 qdf_atomic_t index; 1923 uint16_t num_entries_per_slot; 1924 uint16_t allocated; 1925 struct dp_cfg_event *entry[DP_CFG_EVT_HIST_MAX_SLOTS]; 1926 }; 1927 #endif 1928 1929 enum dp_tx_event_type { 1930 DP_TX_DESC_INVAL_EVT = 0, 1931 DP_TX_DESC_MAP, 1932 DP_TX_DESC_COOKIE, 1933 DP_TX_DESC_FLUSH, 1934 DP_TX_DESC_UNMAP, 1935 DP_TX_COMP_UNMAP, 1936 DP_TX_COMP_UNMAP_ERR, 1937 DP_TX_COMP_MSDU_EXT, 1938 }; 1939 1940 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 1941 /* Size must be in 2 power, for bitwise index rotation */ 1942 #define DP_TX_TCL_HISTORY_SIZE 0x4000 1943 #define DP_TX_TCL_HIST_PER_SLOT_MAX 2048 1944 #define DP_TX_TCL_HIST_MAX_SLOTS 8 1945 #define DP_TX_TCL_HIST_SLOT_SHIFT 11 1946 1947 /* Size must be in 2 power, for bitwise index rotation */ 1948 #define DP_TX_COMP_HISTORY_SIZE 0x4000 1949 #define DP_TX_COMP_HIST_PER_SLOT_MAX 2048 1950 #define DP_TX_COMP_HIST_MAX_SLOTS 8 1951 #define DP_TX_COMP_HIST_SLOT_SHIFT 11 1952 1953 struct dp_tx_desc_event { 1954 qdf_nbuf_t skb; 1955 dma_addr_t paddr; 1956 uint32_t sw_cookie; 1957 enum dp_tx_event_type type; 1958 uint64_t ts; 1959 }; 1960 1961 struct dp_tx_tcl_history { 1962 qdf_atomic_t index; 1963 uint16_t num_entries_per_slot; 1964 uint16_t allocated; 1965 struct dp_tx_desc_event *entry[DP_TX_TCL_HIST_MAX_SLOTS]; 1966 }; 1967 1968 struct dp_tx_comp_history { 1969 qdf_atomic_t index; 1970 uint16_t num_entries_per_slot; 1971 uint16_t allocated; 1972 struct dp_tx_desc_event *entry[DP_TX_COMP_HIST_MAX_SLOTS]; 1973 }; 1974 #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */ 1975 1976 /* structure to record recent operation related variable */ 1977 struct dp_last_op_info { 1978 /* last link desc buf info through WBM release ring */ 1979 struct hal_buf_info wbm_rel_link_desc; 1980 /* last link desc buf info through REO reinject ring */ 1981 struct hal_buf_info reo_reinject_link_desc; 1982 }; 1983 1984 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 1985 1986 /** 1987 * struct dp_swlm_tcl_data - params for tcl register write coalescing 1988 * decision making 1989 * @nbuf: TX packet 1990 * @tid: tid for transmitting the current packet 1991 * @num_ll_connections: Number of low latency connections on this vdev 1992 * @ring_id: TCL ring id 1993 * @pkt_len: Packet length 1994 * 1995 * This structure contains the information required by the software 1996 * latency manager to decide on whether to coalesce the current TCL 1997 * register write or not. 1998 */ 1999 struct dp_swlm_tcl_data { 2000 qdf_nbuf_t nbuf; 2001 uint8_t tid; 2002 uint8_t num_ll_connections; 2003 uint8_t ring_id; 2004 uint32_t pkt_len; 2005 }; 2006 2007 /** 2008 * union swlm_data - SWLM query data 2009 * @tcl_data: data for TCL query in SWLM 2010 */ 2011 union swlm_data { 2012 struct dp_swlm_tcl_data *tcl_data; 2013 }; 2014 2015 /** 2016 * struct dp_swlm_ops - SWLM ops 2017 * @tcl_wr_coalesce_check: handler to check if the current TCL register 2018 * write can be coalesced or not 2019 */ 2020 struct dp_swlm_ops { 2021 int (*tcl_wr_coalesce_check)(struct dp_soc *soc, 2022 struct dp_swlm_tcl_data *tcl_data); 2023 }; 2024 2025 /** 2026 * struct dp_swlm_stats - Stats for Software Latency manager. 2027 * @tcl: TCL stats 2028 * @tcl.timer_flush_success: Num TCL HP writes success from timer context 2029 * @tcl.timer_flush_fail: Num TCL HP writes failure from timer context 2030 * @tcl.tid_fail: Num TCL register write coalescing skips, since the pkt 2031 * was being transmitted on a TID above coalescing threshold 2032 * @tcl.sp_frames: Num TCL register write coalescing skips, since the pkt 2033 * being transmitted was a special frame 2034 * @tcl.ll_connection: Num TCL register write coalescing skips, since the 2035 * vdev has low latency connections 2036 * @tcl.bytes_thresh_reached: Num TCL HP writes flush after the coalescing 2037 * bytes threshold was reached 2038 * @tcl.time_thresh_reached: Num TCL HP writes flush after the coalescing 2039 * session time expired 2040 * @tcl.tput_criteria_fail: Num TCL HP writes coalescing fails, since the 2041 * throughput did not meet session threshold 2042 * @tcl.coalesce_success: Num of TCL HP writes coalesced successfully. 2043 * @tcl.coalesce_fail: Num of TCL HP writes coalesces failed 2044 */ 2045 struct dp_swlm_stats { 2046 struct { 2047 uint32_t timer_flush_success; 2048 uint32_t timer_flush_fail; 2049 uint32_t tid_fail; 2050 uint32_t sp_frames; 2051 uint32_t ll_connection; 2052 uint32_t bytes_thresh_reached; 2053 uint32_t time_thresh_reached; 2054 uint32_t tput_criteria_fail; 2055 uint32_t coalesce_success; 2056 uint32_t coalesce_fail; 2057 } tcl[MAX_TCL_DATA_RINGS]; 2058 }; 2059 2060 /** 2061 * struct dp_swlm_tcl_params: Parameters based on TCL for different modules 2062 * in the Software latency manager. 2063 * @soc: DP soc reference 2064 * @ring_id: TCL ring id 2065 * @flush_timer: Timer for flushing the coalesced TCL HP writes 2066 * @sampling_session_tx_bytes: Num bytes transmitted in the sampling time 2067 * @bytes_flush_thresh: Bytes threshold to flush the TCL HP register write 2068 * @coalesce_end_time: End timestamp for current coalescing session 2069 * @bytes_coalesced: Num bytes coalesced in the current session 2070 * @prev_tx_packets: Previous TX packets accounted 2071 * @prev_tx_bytes: Previous TX bytes accounted 2072 * @prev_rx_bytes: Previous RX bytes accounted 2073 * @expire_time: expiry time for sample 2074 * @tput_pass_cnt: threshold throughput pass counter 2075 */ 2076 struct dp_swlm_tcl_params { 2077 struct dp_soc *soc; 2078 uint32_t ring_id; 2079 qdf_timer_t flush_timer; 2080 uint32_t sampling_session_tx_bytes; 2081 uint32_t bytes_flush_thresh; 2082 uint64_t coalesce_end_time; 2083 uint32_t bytes_coalesced; 2084 uint32_t prev_tx_packets; 2085 uint32_t prev_tx_bytes; 2086 uint32_t prev_rx_bytes; 2087 uint64_t expire_time; 2088 uint32_t tput_pass_cnt; 2089 }; 2090 2091 /** 2092 * struct dp_swlm_params: Parameters for different modules in the 2093 * Software latency manager. 2094 * @rx_traffic_thresh: Threshold for RX traffic, to begin TCL register 2095 * write coalescing 2096 * @tx_traffic_thresh: Threshold for TX traffic, to begin TCL register 2097 * write coalescing 2098 * @sampling_time: Sampling time to test the throughput threshold 2099 * @time_flush_thresh: Time threshold to flush the TCL HP register write 2100 * @tx_thresh_multiplier: Multiplier to deduce the bytes threshold after 2101 * which the TCL HP register is written, thereby 2102 * ending the coalescing. 2103 * @tx_pkt_thresh: Threshold for TX packet count, to begin TCL register 2104 * write coalescing 2105 * @tcl: TCL ring specific params 2106 */ 2107 2108 struct dp_swlm_params { 2109 uint32_t rx_traffic_thresh; 2110 uint32_t tx_traffic_thresh; 2111 uint32_t sampling_time; 2112 uint32_t time_flush_thresh; 2113 uint32_t tx_thresh_multiplier; 2114 uint32_t tx_pkt_thresh; 2115 struct dp_swlm_tcl_params tcl[MAX_TCL_DATA_RINGS]; 2116 }; 2117 2118 /** 2119 * struct dp_swlm - Software latency manager context 2120 * @ops: SWLM ops pointers 2121 * @is_enabled: SWLM enabled/disabled 2122 * @is_init: SWLM module initialized 2123 * @stats: SWLM stats 2124 * @params: SWLM SRNG params 2125 * @tcl_flush_timer: flush timer for TCL register writes 2126 */ 2127 struct dp_swlm { 2128 struct dp_swlm_ops *ops; 2129 uint8_t is_enabled:1, 2130 is_init:1; 2131 struct dp_swlm_stats stats; 2132 struct dp_swlm_params params; 2133 }; 2134 #endif 2135 2136 #ifdef IPA_OFFLOAD 2137 /* IPA uC datapath offload Wlan Tx resources */ 2138 struct ipa_dp_tx_rsc { 2139 /* Resource info to be passed to IPA */ 2140 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 2141 void *ipa_tcl_ring_base_vaddr; 2142 uint32_t ipa_tcl_ring_size; 2143 qdf_dma_addr_t ipa_tcl_hp_paddr; 2144 uint32_t alloc_tx_buf_cnt; 2145 2146 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 2147 void *ipa_wbm_ring_base_vaddr; 2148 uint32_t ipa_wbm_ring_size; 2149 qdf_dma_addr_t ipa_wbm_tp_paddr; 2150 /* WBM2SW HP shadow paddr */ 2151 qdf_dma_addr_t ipa_wbm_hp_shadow_paddr; 2152 2153 /* TX buffers populated into the WBM ring */ 2154 void **tx_buf_pool_vaddr_unaligned; 2155 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 2156 }; 2157 2158 /* IPA uC datapath offload Wlan Rx resources */ 2159 struct ipa_dp_rx_rsc { 2160 /* Resource info to be passed to IPA */ 2161 qdf_dma_addr_t ipa_reo_ring_base_paddr; 2162 void *ipa_reo_ring_base_vaddr; 2163 uint32_t ipa_reo_ring_size; 2164 qdf_dma_addr_t ipa_reo_tp_paddr; 2165 2166 /* Resource info to be passed to firmware and IPA */ 2167 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 2168 void *ipa_rx_refill_buf_ring_base_vaddr; 2169 uint32_t ipa_rx_refill_buf_ring_size; 2170 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 2171 }; 2172 #endif 2173 2174 struct dp_tx_msdu_info_s; 2175 /** 2176 * enum dp_context_type- DP Context Type 2177 * @DP_CONTEXT_TYPE_SOC: Context type DP SOC 2178 * @DP_CONTEXT_TYPE_PDEV: Context type DP PDEV 2179 * @DP_CONTEXT_TYPE_VDEV: Context type DP VDEV 2180 * @DP_CONTEXT_TYPE_PEER: Context type DP PEER 2181 * @DP_CONTEXT_TYPE_MON_SOC: Context type DP MON SOC 2182 * @DP_CONTEXT_TYPE_MON_PDEV: Context type DP MON PDEV 2183 * 2184 * Helper enums to be used to retrieve the size of the corresponding 2185 * data structure by passing the type. 2186 */ 2187 enum dp_context_type { 2188 DP_CONTEXT_TYPE_SOC, 2189 DP_CONTEXT_TYPE_PDEV, 2190 DP_CONTEXT_TYPE_VDEV, 2191 DP_CONTEXT_TYPE_PEER, 2192 DP_CONTEXT_TYPE_MON_SOC, 2193 DP_CONTEXT_TYPE_MON_PDEV 2194 }; 2195 2196 /** 2197 * struct dp_arch_ops - DP target specific arch ops 2198 * @txrx_soc_attach: 2199 * @txrx_soc_detach: 2200 * @txrx_soc_init: 2201 * @txrx_soc_deinit: 2202 * @txrx_soc_srng_alloc: 2203 * @txrx_soc_srng_init: 2204 * @txrx_soc_srng_deinit: 2205 * @txrx_soc_srng_free: 2206 * @txrx_pdev_attach: 2207 * @txrx_pdev_detach: 2208 * @txrx_vdev_attach: 2209 * @txrx_vdev_detach: 2210 * @txrx_peer_map_attach: 2211 * @txrx_peer_map_detach: 2212 * @dp_rxdma_ring_sel_cfg: 2213 * @soc_cfg_attach: 2214 * @txrx_peer_setup: 2215 * @peer_get_reo_hash: 2216 * @reo_remap_config: 2217 * @tx_hw_enqueue: enqueue TX data to HW 2218 * @tx_comp_get_params_from_hal_desc: get software tx descriptor and release 2219 * source from HAL desc for wbm release ring 2220 * @dp_tx_mlo_mcast_send: Tx send handler for MLO multicast enhance 2221 * @dp_tx_process_htt_completion: 2222 * @dp_rx_process: 2223 * @dp_tx_send_fast: 2224 * @dp_tx_desc_pool_init: 2225 * @dp_tx_desc_pool_deinit: 2226 * @dp_rx_desc_pool_init: 2227 * @dp_rx_desc_pool_deinit: 2228 * @dp_wbm_get_rx_desc_from_hal_desc: 2229 * @dp_rx_intrabss_mcast_handler: 2230 * @dp_rx_word_mask_subscribe: 2231 * @dp_rx_desc_cookie_2_va: 2232 * @dp_service_near_full_srngs: Handler for servicing the near full IRQ 2233 * @tx_implicit_rbm_set: 2234 * @dp_rx_peer_metadata_peer_id_get: 2235 * @dp_rx_chain_msdus: 2236 * @txrx_set_vdev_param: target specific ops while setting vdev params 2237 * @txrx_get_vdev_mcast_param: target specific ops for getting vdev 2238 * params related to multicast 2239 * @txrx_get_context_size: 2240 * @txrx_get_mon_context_size: 2241 * @dp_srng_test_and_update_nf_params: Check if the srng is in near full state 2242 * and set the near-full params. 2243 * @dp_tx_mcast_handler: 2244 * @dp_rx_mcast_handler: 2245 * @dp_tx_is_mcast_primary: 2246 * @dp_soc_get_by_idle_bm_id: 2247 * @mlo_peer_find_hash_detach: 2248 * @mlo_peer_find_hash_attach: 2249 * @mlo_peer_find_hash_add: 2250 * @mlo_peer_find_hash_remove: 2251 * @mlo_peer_find_hash_find: 2252 * @mlo_get_chip_id: get the MLO chip id 2253 * @mlo_link_peer_find_hash_find_by_chip_id: return the link peer on the chip 2254 * @get_hw_link_id: 2255 * @dp_rx_peer_set_link_id: set link id in nbuf cb 2256 * @get_reo_qdesc_addr: 2257 * @get_rx_hash_key: 2258 * @dp_set_rx_fst: 2259 * @dp_get_rx_fst: 2260 * @dp_rx_fst_deref: 2261 * @dp_rx_fst_ref: 2262 * @txrx_print_peer_stats: 2263 * @dp_peer_rx_reorder_queue_setup: Dp peer reorder queue setup 2264 * @dp_bank_reconfig: 2265 * @dp_get_soc_by_chip_id: Get soc by chip id 2266 * @dp_soc_get_num_soc: 2267 * @dp_reconfig_tx_vdev_mcast_ctrl: 2268 * @dp_cc_reg_cfg_init: 2269 * @dp_tx_compute_hw_delay: 2270 * @print_mlo_ast_stats: 2271 * @dp_partner_chips_map: 2272 * @dp_partner_chips_unmap: 2273 * @ipa_get_bank_id: Get TCL bank id used by IPA 2274 * @ipa_get_wdi_ver: Get WDI version 2275 * @dp_txrx_ppeds_rings_status: 2276 * @dp_tx_ppeds_inuse_desc: 2277 * @dp_ppeds_clear_stats: Clear ppeds related stats 2278 * @dp_tx_ppeds_cfg_astidx_cache_mapping: 2279 * @dp_txrx_ppeds_rings_stats: Printing the util stats of ring 2280 * @dp_txrx_ppeds_clear_rings_stats: Clearing the ring util stats 2281 * @txrx_soc_ppeds_start: 2282 * @txrx_soc_ppeds_stop: 2283 * @dp_register_ppeds_interrupts: 2284 * @dp_free_ppeds_interrupts: 2285 * @dp_rx_wbm_err_reap_desc: Reap WBM Error Ring Descriptor 2286 * @dp_rx_null_q_desc_handle: Handle Null Queue Exception Error 2287 * @dp_tx_desc_pool_alloc: Allocate arch specific TX descriptor pool 2288 * @dp_tx_desc_pool_free: Free arch specific TX descriptor pool 2289 * @txrx_srng_init: Init txrx srng 2290 * @dp_get_vdev_stats_for_unmap_peer: Get vdev stats pointer for unmap peer 2291 * @dp_get_interface_stats: Get interface stats 2292 * @ppeds_handle_attached: 2293 * @txrx_soc_ppeds_interrupt_stop: 2294 * @txrx_soc_ppeds_interrupt_start: 2295 * @txrx_soc_ppeds_service_status_update: 2296 * @txrx_soc_ppeds_enabled_check: 2297 * @txrx_soc_ppeds_txdesc_pool_reset: 2298 * @dp_update_ring_hptp: Update rings hptp during suspend/resume 2299 * @dp_get_fst_cmem_base: Get CMEM base address for FISA 2300 * @dp_flush_tx_ring: Flush TCL ring HP 2301 * @dp_mlo_print_ptnr_info: print partner vdev info 2302 * @dp_soc_interrupt_attach: DP interrupt attach 2303 * @dp_soc_attach_poll: DP poll attach 2304 * @dp_soc_interrupt_detach: DP interrupt detach 2305 * @dp_service_srngs: Service DP interrupts 2306 */ 2307 struct dp_arch_ops { 2308 /* INIT/DEINIT Arch Ops */ 2309 QDF_STATUS (*txrx_soc_attach)(struct dp_soc *soc, 2310 struct cdp_soc_attach_params *params); 2311 QDF_STATUS (*txrx_soc_detach)(struct dp_soc *soc); 2312 void* (*txrx_soc_init)(struct dp_soc *soc, HTC_HANDLE htc_handle, 2313 struct hif_opaque_softc *hif_handle); 2314 QDF_STATUS (*txrx_soc_deinit)(struct dp_soc *soc); 2315 QDF_STATUS (*txrx_soc_srng_alloc)(struct dp_soc *soc); 2316 QDF_STATUS (*txrx_soc_srng_init)(struct dp_soc *soc); 2317 void (*txrx_soc_srng_deinit)(struct dp_soc *soc); 2318 void (*txrx_soc_srng_free)(struct dp_soc *soc); 2319 QDF_STATUS (*txrx_pdev_attach)(struct dp_pdev *pdev, 2320 struct cdp_pdev_attach_params *params); 2321 QDF_STATUS (*txrx_pdev_detach)(struct dp_pdev *pdev); 2322 QDF_STATUS (*txrx_vdev_attach)(struct dp_soc *soc, 2323 struct dp_vdev *vdev); 2324 QDF_STATUS (*txrx_vdev_detach)(struct dp_soc *soc, 2325 struct dp_vdev *vdev); 2326 QDF_STATUS (*txrx_peer_map_attach)(struct dp_soc *soc); 2327 void (*txrx_peer_map_detach)(struct dp_soc *soc); 2328 QDF_STATUS (*dp_rxdma_ring_sel_cfg)(struct dp_soc *soc); 2329 void (*soc_cfg_attach)(struct dp_soc *soc); 2330 QDF_STATUS (*txrx_peer_setup)(struct cdp_soc_t *soc_hdl, 2331 uint8_t vdev_id, uint8_t *peer_mac, 2332 struct cdp_peer_setup_info *setup_info); 2333 void (*peer_get_reo_hash)(struct dp_vdev *vdev, 2334 struct cdp_peer_setup_info *setup_info, 2335 enum cdp_host_reo_dest_ring *reo_dest, 2336 bool *hash_based, 2337 uint8_t *lmac_peer_id_msb); 2338 bool (*reo_remap_config)(struct dp_soc *soc, uint32_t *remap0, 2339 uint32_t *remap1, uint32_t *remap2); 2340 2341 /* TX RX Arch Ops */ 2342 QDF_STATUS (*tx_hw_enqueue)(struct dp_soc *soc, struct dp_vdev *vdev, 2343 struct dp_tx_desc_s *tx_desc, 2344 uint16_t fw_metadata, 2345 struct cdp_tx_exception_metadata *metadata, 2346 struct dp_tx_msdu_info_s *msdu_info); 2347 2348 QDF_STATUS (*tx_comp_get_params_from_hal_desc)( 2349 struct dp_soc *soc, void *tx_comp_hal_desc, 2350 struct dp_tx_desc_s **desc); 2351 2352 qdf_nbuf_t (*dp_tx_mlo_mcast_send)(struct dp_soc *soc, 2353 struct dp_vdev *vdev, 2354 qdf_nbuf_t nbuf, 2355 struct cdp_tx_exception_metadata 2356 *tx_exc_metadata); 2357 2358 void (*dp_tx_process_htt_completion)(struct dp_soc *soc, 2359 struct dp_tx_desc_s *tx_desc, 2360 uint8_t *status, 2361 uint8_t ring_id); 2362 2363 uint32_t (*dp_rx_process)(struct dp_intr *int_ctx, 2364 hal_ring_handle_t hal_ring_hdl, 2365 uint8_t reo_ring_num, uint32_t quota); 2366 2367 qdf_nbuf_t (*dp_tx_send_fast)(struct cdp_soc_t *soc_hdl, 2368 uint8_t vdev_id, 2369 qdf_nbuf_t nbuf); 2370 2371 QDF_STATUS (*dp_tx_desc_pool_init)(struct dp_soc *soc, 2372 uint32_t num_elem, 2373 uint8_t pool_id, 2374 bool spcl_tx_desc); 2375 void (*dp_tx_desc_pool_deinit)( 2376 struct dp_soc *soc, 2377 struct dp_tx_desc_pool_s *tx_desc_pool, 2378 uint8_t pool_id, 2379 bool spcl_tx_desc); 2380 2381 QDF_STATUS (*dp_rx_desc_pool_init)(struct dp_soc *soc, 2382 struct rx_desc_pool *rx_desc_pool, 2383 uint32_t pool_id); 2384 void (*dp_rx_desc_pool_deinit)(struct dp_soc *soc, 2385 struct rx_desc_pool *rx_desc_pool, 2386 uint32_t pool_id); 2387 2388 QDF_STATUS (*dp_wbm_get_rx_desc_from_hal_desc)( 2389 struct dp_soc *soc, 2390 void *ring_desc, 2391 struct dp_rx_desc **r_rx_desc); 2392 2393 bool 2394 (*dp_rx_intrabss_mcast_handler)(struct dp_soc *soc, 2395 struct dp_txrx_peer *ta_txrx_peer, 2396 qdf_nbuf_t nbuf_copy, 2397 struct cdp_tid_rx_stats *tid_stats, 2398 uint8_t link_id); 2399 2400 void (*dp_rx_word_mask_subscribe)( 2401 struct dp_soc *soc, 2402 uint32_t *msg_word, 2403 void *rx_filter); 2404 2405 struct dp_rx_desc *(*dp_rx_desc_cookie_2_va)(struct dp_soc *soc, 2406 uint32_t cookie); 2407 uint32_t (*dp_service_near_full_srngs)(struct dp_soc *soc, 2408 struct dp_intr *int_ctx, 2409 uint32_t dp_budget); 2410 void (*tx_implicit_rbm_set)(struct dp_soc *soc, uint8_t tx_ring_id, 2411 uint8_t bm_id); 2412 uint16_t (*dp_rx_peer_metadata_peer_id_get)(struct dp_soc *soc, 2413 uint32_t peer_metadata); 2414 bool (*dp_rx_chain_msdus)(struct dp_soc *soc, qdf_nbuf_t nbuf, 2415 uint8_t *rx_tlv_hdr, uint8_t mac_id); 2416 /* Control Arch Ops */ 2417 QDF_STATUS (*txrx_set_vdev_param)(struct dp_soc *soc, 2418 struct dp_vdev *vdev, 2419 enum cdp_vdev_param_type param, 2420 cdp_config_param_type val); 2421 2422 QDF_STATUS (*txrx_get_vdev_mcast_param)(struct dp_soc *soc, 2423 struct dp_vdev *vdev, 2424 cdp_config_param_type *val); 2425 2426 /* Misc Arch Ops */ 2427 qdf_size_t (*txrx_get_context_size)(enum dp_context_type); 2428 #ifdef WIFI_MONITOR_SUPPORT 2429 qdf_size_t (*txrx_get_mon_context_size)(enum dp_context_type); 2430 #endif 2431 int (*dp_srng_test_and_update_nf_params)(struct dp_soc *soc, 2432 struct dp_srng *dp_srng, 2433 int *max_reap_limit); 2434 2435 /* MLO ops */ 2436 #ifdef WLAN_FEATURE_11BE_MLO 2437 #ifdef WLAN_MCAST_MLO 2438 void (*dp_tx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 2439 qdf_nbuf_t nbuf); 2440 bool (*dp_rx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 2441 struct dp_txrx_peer *peer, qdf_nbuf_t nbuf, 2442 uint8_t link_id); 2443 bool (*dp_tx_is_mcast_primary)(struct dp_soc *soc, 2444 struct dp_vdev *vdev); 2445 #endif 2446 struct dp_soc * (*dp_soc_get_by_idle_bm_id)(struct dp_soc *soc, 2447 uint8_t bm_id); 2448 2449 void (*mlo_peer_find_hash_detach)(struct dp_soc *soc); 2450 QDF_STATUS (*mlo_peer_find_hash_attach)(struct dp_soc *soc); 2451 void (*mlo_peer_find_hash_add)(struct dp_soc *soc, 2452 struct dp_peer *peer); 2453 void (*mlo_peer_find_hash_remove)(struct dp_soc *soc, 2454 struct dp_peer *peer); 2455 2456 struct dp_peer *(*mlo_peer_find_hash_find)(struct dp_soc *soc, 2457 uint8_t *peer_mac_addr, 2458 int mac_addr_is_aligned, 2459 enum dp_mod_id mod_id, 2460 uint8_t vdev_id); 2461 #ifdef WLAN_MLO_MULTI_CHIP 2462 uint8_t (*mlo_get_chip_id)(struct dp_soc *soc); 2463 struct dp_peer *(*mlo_link_peer_find_hash_find_by_chip_id) 2464 (struct dp_soc *soc, 2465 uint8_t *peer_mac_addr, 2466 int mac_addr_is_aligned, 2467 uint8_t vdev_id, 2468 uint8_t chip_id, 2469 enum dp_mod_id mod_id); 2470 #endif 2471 #endif 2472 uint8_t (*get_hw_link_id)(struct dp_pdev *pdev); 2473 void (*dp_rx_peer_set_link_id)(qdf_nbuf_t nbuf, uint32_t peer_mdata); 2474 uint64_t (*get_reo_qdesc_addr)(hal_soc_handle_t hal_soc_hdl, 2475 uint8_t *dst_ring_desc, 2476 uint8_t *buf, 2477 struct dp_txrx_peer *peer, 2478 unsigned int tid); 2479 void (*get_rx_hash_key)(struct dp_soc *soc, 2480 struct cdp_lro_hash_config *lro_hash); 2481 void (*dp_set_rx_fst)(struct dp_rx_fst *fst); 2482 struct dp_rx_fst *(*dp_get_rx_fst)(void); 2483 uint32_t (*dp_rx_fst_deref)(void); 2484 void (*dp_rx_fst_ref)(void); 2485 void (*txrx_print_peer_stats)(struct cdp_peer_stats *peer_stats, 2486 enum peer_stats_type stats_type); 2487 QDF_STATUS (*dp_peer_rx_reorder_queue_setup)(struct dp_soc *soc, 2488 struct dp_peer *peer, 2489 uint32_t tid_bitmap, 2490 uint32_t ba_window_size); 2491 void (*dp_bank_reconfig)(struct dp_soc *soc, struct dp_vdev *vdev); 2492 2493 struct dp_soc * (*dp_get_soc_by_chip_id)(struct dp_soc *soc, 2494 uint8_t chip_id); 2495 2496 uint8_t (*dp_soc_get_num_soc)(struct dp_soc *soc); 2497 void (*dp_reconfig_tx_vdev_mcast_ctrl)(struct dp_soc *soc, 2498 struct dp_vdev *vdev); 2499 2500 void (*dp_cc_reg_cfg_init)(struct dp_soc *soc, bool is_4k_align); 2501 2502 QDF_STATUS 2503 (*dp_tx_compute_hw_delay)(struct dp_soc *soc, 2504 struct dp_vdev *vdev, 2505 struct hal_tx_completion_status *ts, 2506 uint32_t *delay_us); 2507 void (*print_mlo_ast_stats)(struct dp_soc *soc); 2508 void (*dp_partner_chips_map)(struct dp_soc *soc, 2509 struct dp_peer *peer, 2510 uint16_t peer_id); 2511 void (*dp_partner_chips_unmap)(struct dp_soc *soc, 2512 uint16_t peer_id); 2513 2514 #ifdef IPA_OFFLOAD 2515 int8_t (*ipa_get_bank_id)(struct dp_soc *soc); 2516 void (*ipa_get_wdi_ver)(uint8_t *wdi_ver); 2517 #endif 2518 #ifdef WLAN_SUPPORT_PPEDS 2519 void (*dp_txrx_ppeds_rings_status)(struct dp_soc *soc); 2520 void (*dp_tx_ppeds_inuse_desc)(struct dp_soc *soc); 2521 void (*dp_ppeds_clear_stats)(struct dp_soc *soc); 2522 void (*dp_tx_ppeds_cfg_astidx_cache_mapping)(struct dp_soc *soc, 2523 struct dp_vdev *vdev, 2524 bool peer_map); 2525 void (*dp_txrx_ppeds_rings_stats)(struct dp_soc *soc); 2526 void (*dp_txrx_ppeds_clear_rings_stats)(struct dp_soc *soc); 2527 #endif 2528 bool (*ppeds_handle_attached)(struct dp_soc *soc); 2529 QDF_STATUS (*txrx_soc_ppeds_start)(struct dp_soc *soc); 2530 void (*txrx_soc_ppeds_stop)(struct dp_soc *soc); 2531 int (*dp_register_ppeds_interrupts)(struct dp_soc *soc, 2532 struct dp_srng *srng, int vector, 2533 int ring_type, int ring_num); 2534 void (*dp_free_ppeds_interrupts)(struct dp_soc *soc, 2535 struct dp_srng *srng, int ring_type, 2536 int ring_num); 2537 qdf_nbuf_t (*dp_rx_wbm_err_reap_desc)(struct dp_intr *int_ctx, 2538 struct dp_soc *soc, 2539 hal_ring_handle_t hal_ring_hdl, 2540 uint32_t quota, 2541 uint32_t *rx_bufs_used); 2542 QDF_STATUS (*dp_rx_null_q_desc_handle)(struct dp_soc *soc, 2543 qdf_nbuf_t nbuf, 2544 uint8_t *rx_tlv_hdr, 2545 uint8_t pool_id, 2546 struct dp_txrx_peer *txrx_peer, 2547 bool is_reo_exception, 2548 uint8_t link_id); 2549 2550 QDF_STATUS (*dp_tx_desc_pool_alloc)(struct dp_soc *soc, 2551 uint32_t num_elem, 2552 uint8_t pool_id); 2553 void (*dp_tx_desc_pool_free)(struct dp_soc *soc, uint8_t pool_id); 2554 2555 QDF_STATUS (*txrx_srng_init)(struct dp_soc *soc, struct dp_srng *srng, 2556 int ring_type, int ring_num, int mac_id); 2557 2558 void (*dp_get_vdev_stats_for_unmap_peer)( 2559 struct dp_vdev *vdev, 2560 struct dp_peer *peer); 2561 QDF_STATUS (*dp_get_interface_stats)(struct cdp_soc_t *soc_hdl, 2562 uint8_t vdev_id, 2563 void *buf, 2564 bool is_aggregate); 2565 #ifdef WLAN_SUPPORT_PPEDS 2566 void (*txrx_soc_ppeds_interrupt_stop)(struct dp_soc *soc); 2567 void (*txrx_soc_ppeds_interrupt_start)(struct dp_soc *soc); 2568 void (*txrx_soc_ppeds_service_status_update)(struct dp_soc *soc, 2569 bool enable); 2570 bool (*txrx_soc_ppeds_enabled_check)(struct dp_soc *soc); 2571 void (*txrx_soc_ppeds_txdesc_pool_reset)(struct dp_soc *soc, 2572 qdf_nbuf_t *nbuf_list); 2573 #endif 2574 void (*dp_update_ring_hptp)(struct dp_soc *soc, bool force_flush_tx); 2575 uint64_t (*dp_get_fst_cmem_base)(struct dp_soc *soc, uint64_t size); 2576 int (*dp_flush_tx_ring)(struct dp_pdev *pdev, int ring_id); 2577 void (*dp_mlo_print_ptnr_info)(struct dp_vdev *vdev); 2578 QDF_STATUS (*dp_soc_interrupt_attach)(struct cdp_soc_t *txrx_soc); 2579 QDF_STATUS (*dp_soc_attach_poll)(struct cdp_soc_t *txrx_soc); 2580 void (*dp_soc_interrupt_detach)(struct cdp_soc_t *txrx_soc); 2581 uint32_t (*dp_service_srngs)(void *dp_ctx, uint32_t dp_budget, int cpu); 2582 }; 2583 2584 /** 2585 * struct dp_soc_features: Data structure holding the SOC level feature flags. 2586 * @pn_in_reo_dest: PN provided by hardware in the REO destination ring. 2587 * @dmac_cmn_src_rxbuf_ring_enabled: Flag to indicate DMAC mode common Rx 2588 * buffer source rings 2589 * @rssi_dbm_conv_support: Rssi dbm conversion support param. 2590 * @umac_hw_reset_support: UMAC HW reset support 2591 * @wds_ext_ast_override_enable: 2592 * @multi_rx_reorder_q_setup_support: multi rx reorder q setup at a time support 2593 */ 2594 struct dp_soc_features { 2595 uint8_t pn_in_reo_dest:1, 2596 dmac_cmn_src_rxbuf_ring_enabled:1; 2597 bool rssi_dbm_conv_support; 2598 bool umac_hw_reset_support; 2599 bool wds_ext_ast_override_enable; 2600 bool multi_rx_reorder_q_setup_support; 2601 }; 2602 2603 enum sysfs_printing_mode { 2604 PRINTING_MODE_DISABLED = 0, 2605 PRINTING_MODE_ENABLED 2606 }; 2607 2608 /** 2609 * typedef notify_pre_reset_fw_callback() - pre-reset callback 2610 * @soc: DP SoC 2611 */ 2612 typedef void (*notify_pre_reset_fw_callback)(struct dp_soc *soc); 2613 2614 #ifdef WLAN_SYSFS_DP_STATS 2615 /** 2616 * struct sysfs_stats_config: Data structure holding stats sysfs config. 2617 * @rw_stats_lock: Lock to read and write to stat_type and pdev_id. 2618 * @sysfs_read_lock: Lock held while another stat req is being executed. 2619 * @sysfs_write_user_buffer: Lock to change buff len, max buf len 2620 * and *buf. 2621 * @sysfs_txrx_fw_request_done: Event to wait for firmware response. 2622 * @stat_type_requested: stat type requested. 2623 * @mac_id: mac id for which stat type are requested. 2624 * @printing_mode: Should a print go through. 2625 * @process_id: Process allowed to write to buffer. 2626 * @curr_buffer_length: Curr length of buffer written 2627 * @max_buffer_length: Max buffer length. 2628 * @buf: Sysfs buffer. 2629 */ 2630 struct sysfs_stats_config { 2631 /* lock held to read stats */ 2632 qdf_spinlock_t rw_stats_lock; 2633 qdf_mutex_t sysfs_read_lock; 2634 qdf_spinlock_t sysfs_write_user_buffer; 2635 qdf_event_t sysfs_txrx_fw_request_done; 2636 uint32_t stat_type_requested; 2637 uint32_t mac_id; 2638 enum sysfs_printing_mode printing_mode; 2639 int process_id; 2640 uint16_t curr_buffer_length; 2641 uint16_t max_buffer_length; 2642 char *buf; 2643 }; 2644 #endif 2645 2646 struct test_mem_free { 2647 unsigned long ts_qdesc_mem_hdl; 2648 qdf_dma_addr_t hw_qdesc_paddr; 2649 void *hw_qdesc_vaddr_align; 2650 void *hw_qdesc_vaddr_unalign; 2651 uint32_t peer_id; 2652 uint32_t tid; 2653 uint8_t chip_id; 2654 unsigned long ts_hw_flush_back; 2655 }; 2656 2657 struct test_qaddr_del { 2658 unsigned long ts_qaddr_del; 2659 uint32_t peer_id; 2660 uint32_t paddr; 2661 uint32_t tid; 2662 uint8_t chip_id; 2663 }; 2664 2665 #ifdef DP_RX_MSDU_DONE_FAIL_HISTORY 2666 2667 #define DP_MSDU_DONE_FAIL_HIST_MAX 128 2668 2669 struct dp_msdu_done_fail_entry { 2670 qdf_dma_addr_t paddr; 2671 uint32_t sw_cookie; 2672 }; 2673 2674 struct dp_msdu_done_fail_history { 2675 qdf_atomic_t index; 2676 struct dp_msdu_done_fail_entry entry[DP_MSDU_DONE_FAIL_HIST_MAX]; 2677 }; 2678 #endif 2679 2680 #ifdef DP_RX_PEEK_MSDU_DONE_WAR 2681 #define DP_MSDU_DONE_FAIL_DESCS_MAX 64 2682 2683 struct dp_rx_msdu_done_fail_desc_list { 2684 qdf_atomic_t index; 2685 struct dp_rx_desc *msdu_done_fail_descs[DP_MSDU_DONE_FAIL_DESCS_MAX]; 2686 }; 2687 #endif 2688 2689 /* SOC level structure for data path */ 2690 struct dp_soc { 2691 /** 2692 * re-use memory section starts 2693 */ 2694 2695 /* Common base structure - Should be the first member */ 2696 struct cdp_soc_t cdp_soc; 2697 2698 /* SoC Obj */ 2699 struct cdp_ctrl_objmgr_psoc *ctrl_psoc; 2700 2701 /* OS device abstraction */ 2702 qdf_device_t osdev; 2703 2704 /*cce disable*/ 2705 bool cce_disable; 2706 2707 /* WLAN config context */ 2708 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 2709 2710 /* HTT handle for host-fw interaction */ 2711 struct htt_soc *htt_handle; 2712 2713 /* Commint init done */ 2714 qdf_atomic_t cmn_init_done; 2715 2716 /* Opaque hif handle */ 2717 struct hif_opaque_softc *hif_handle; 2718 2719 /* PDEVs on this SOC */ 2720 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 2721 2722 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 2723 struct dp_srng rx_refill_buf_ring[MAX_PDEV_CNT]; 2724 2725 struct dp_srng rxdma_mon_desc_ring[MAX_NUM_LMAC_HW]; 2726 2727 /* RXDMA error destination ring */ 2728 struct dp_srng rxdma_err_dst_ring[MAX_NUM_LMAC_HW]; 2729 2730 /* RXDMA monitor buffer replenish ring */ 2731 struct dp_srng rxdma_mon_buf_ring[MAX_NUM_LMAC_HW]; 2732 2733 /* RXDMA monitor destination ring */ 2734 struct dp_srng rxdma_mon_dst_ring[MAX_NUM_LMAC_HW]; 2735 2736 /* RXDMA monitor status ring. TBD: Check format of this ring */ 2737 struct dp_srng rxdma_mon_status_ring[MAX_NUM_LMAC_HW]; 2738 2739 /* Ring to handover links to hw in monitor mode for SOFTUMAC arch */ 2740 struct dp_srng sw2rxdma_link_ring[MAX_NUM_LMAC_HW]; 2741 2742 /* Number of PDEVs */ 2743 uint8_t pdev_count; 2744 2745 /*ast override support in HW*/ 2746 bool ast_override_support; 2747 2748 /*number of hw dscp tid map*/ 2749 uint8_t num_hw_dscp_tid_map; 2750 2751 /* HAL SOC handle */ 2752 hal_soc_handle_t hal_soc; 2753 2754 /* rx monitor pkt tlv size */ 2755 uint16_t rx_mon_pkt_tlv_size; 2756 /* rx pkt tlv size */ 2757 uint16_t rx_pkt_tlv_size; 2758 /* rx pkt tlv size in current operation mode */ 2759 uint16_t curr_rx_pkt_tlv_size; 2760 2761 /* enable/disable dp debug logs */ 2762 bool dp_debug_log_en; 2763 2764 struct dp_arch_ops arch_ops; 2765 2766 /* Device ID coming from Bus sub-system */ 2767 uint32_t device_id; 2768 2769 /* Link descriptor pages */ 2770 struct qdf_mem_multi_page_t link_desc_pages; 2771 2772 /* total link descriptors for regular RX and TX */ 2773 uint32_t total_link_descs; 2774 2775 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 2776 struct dp_srng wbm_idle_link_ring; 2777 2778 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 2779 */ 2780 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 2781 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 2782 uint32_t num_scatter_bufs; 2783 2784 /* Tx SW descriptor pool */ 2785 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 2786 2787 /* Tx MSDU Extension descriptor pool */ 2788 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 2789 2790 /* Tx TSO descriptor pool */ 2791 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 2792 2793 /* Tx TSO Num of segments pool */ 2794 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 2795 2796 /* REO destination rings */ 2797 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 2798 2799 /* REO exception ring - See if should combine this with reo_dest_ring */ 2800 struct dp_srng reo_exception_ring; 2801 2802 /* REO reinjection ring */ 2803 struct dp_srng reo_reinject_ring; 2804 2805 /* REO command ring */ 2806 struct dp_srng reo_cmd_ring; 2807 2808 /* REO command status ring */ 2809 struct dp_srng reo_status_ring; 2810 2811 /* WBM Rx release ring */ 2812 struct dp_srng rx_rel_ring; 2813 2814 /* TCL data ring */ 2815 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 2816 2817 /* Number of Tx comp rings */ 2818 uint8_t num_tx_comp_rings; 2819 2820 /* Number of TCL data rings */ 2821 uint8_t num_tcl_data_rings; 2822 2823 /* TCL CMD_CREDIT ring */ 2824 bool init_tcl_cmd_cred_ring; 2825 2826 /* It is used as credit based ring on QCN9000 else command ring */ 2827 struct dp_srng tcl_cmd_credit_ring; 2828 2829 /* TCL command status ring */ 2830 struct dp_srng tcl_status_ring; 2831 2832 /* WBM Tx completion rings */ 2833 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 2834 2835 /* Common WBM link descriptor release ring (SW to WBM) */ 2836 struct dp_srng wbm_desc_rel_ring; 2837 2838 /* DP Interrupts */ 2839 struct dp_intr intr_ctx[WLAN_CFG_INT_NUM_CONTEXTS]; 2840 2841 /* Monitor mode mac id to dp_intr_id map */ 2842 int mon_intr_id_lmac_map[MAX_NUM_LMAC_HW]; 2843 /* Rx SW descriptor pool for RXDMA monitor buffer */ 2844 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 2845 2846 /* Rx SW descriptor pool for RXDMA status buffer */ 2847 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 2848 2849 /* Rx SW descriptor pool for RXDMA buffer */ 2850 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 2851 2852 /* Number of REO destination rings */ 2853 uint8_t num_reo_dest_rings; 2854 2855 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 2856 /* lock to control access to soc TX descriptors */ 2857 qdf_spinlock_t flow_pool_array_lock; 2858 2859 /* pause callback to pause TX queues as per flow control */ 2860 tx_pause_callback pause_cb; 2861 2862 /* flow pool related statistics */ 2863 struct dp_txrx_pool_stats pool_stats; 2864 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 2865 2866 notify_pre_reset_fw_callback notify_fw_callback; 2867 2868 unsigned long service_rings_running; 2869 2870 uint32_t wbm_idle_scatter_buf_size; 2871 2872 /* VDEVs on this SOC */ 2873 struct dp_vdev *vdev_id_map[MAX_VDEV_CNT]; 2874 2875 uint8_t hw_txrx_stats_en:1; 2876 2877 /* Tx H/W queues lock */ 2878 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 2879 2880 /* Tx ring map for interrupt processing */ 2881 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2882 2883 /* Rx ring map for interrupt processing */ 2884 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2885 2886 /* peer ID to peer object map (array of pointers to peer objects) */ 2887 struct dp_peer **peer_id_to_obj_map; 2888 2889 struct { 2890 unsigned mask; 2891 unsigned idx_bits; 2892 TAILQ_HEAD(, dp_peer) * bins; 2893 } peer_hash; 2894 2895 /* rx defrag state – TBD: do we need this per radio? */ 2896 struct { 2897 struct { 2898 TAILQ_HEAD(, dp_rx_tid_defrag) waitlist; 2899 uint32_t timeout_ms; 2900 uint32_t next_flush_ms; 2901 qdf_spinlock_t defrag_lock; 2902 } defrag; 2903 struct { 2904 int defrag_timeout_check; 2905 int dup_check; 2906 } flags; 2907 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 2908 qdf_spinlock_t reo_cmd_lock; 2909 } rx; 2910 2911 /* optional rx processing function */ 2912 void (*rx_opt_proc)( 2913 struct dp_vdev *vdev, 2914 struct dp_peer *peer, 2915 unsigned tid, 2916 qdf_nbuf_t msdu_list); 2917 2918 /* pool addr for mcast enhance buff */ 2919 struct { 2920 int size; 2921 uint32_t paddr; 2922 uint32_t *vaddr; 2923 struct dp_tx_me_buf_t *freelist; 2924 int buf_in_use; 2925 qdf_dma_mem_context(memctx); 2926 } me_buf; 2927 2928 /* Protect peer hash table */ 2929 DP_MUTEX_TYPE peer_hash_lock; 2930 /* Protect peer_id_to_objmap */ 2931 DP_MUTEX_TYPE peer_map_lock; 2932 2933 /* maximum number of suppoerted peers */ 2934 uint32_t max_peers; 2935 /* maximum value for peer_id */ 2936 uint32_t max_peer_id; 2937 2938 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH 2939 uint32_t peer_id_shift; 2940 uint32_t peer_id_mask; 2941 #endif 2942 2943 /* rx peer metadata field shift and mask configuration */ 2944 uint8_t htt_peer_id_s; 2945 uint32_t htt_peer_id_m; 2946 uint8_t htt_vdev_id_s; 2947 uint32_t htt_vdev_id_m; 2948 uint8_t htt_mld_peer_valid_s; 2949 uint32_t htt_mld_peer_valid_m; 2950 /* rx peer metadata version */ 2951 uint8_t rx_peer_metadata_ver; 2952 2953 /* SoC level data path statistics */ 2954 struct dp_soc_stats stats; 2955 #ifdef WLAN_SYSFS_DP_STATS 2956 /* sysfs config for DP stats */ 2957 struct sysfs_stats_config *sysfs_config; 2958 #endif 2959 /* timestamp to keep track of msdu buffers received on reo err ring */ 2960 uint64_t rx_route_err_start_pkt_ts; 2961 2962 /* Num RX Route err in a given window to keep track of rate of errors */ 2963 uint32_t rx_route_err_in_window; 2964 2965 /* Enable processing of Tx completion status words */ 2966 bool process_tx_status; 2967 bool process_rx_status; 2968 struct dp_ast_entry **ast_table; 2969 struct { 2970 unsigned mask; 2971 unsigned idx_bits; 2972 TAILQ_HEAD(, dp_ast_entry) * bins; 2973 } ast_hash; 2974 2975 #ifdef DP_TX_HW_DESC_HISTORY 2976 struct dp_tx_hw_desc_history tx_hw_desc_history; 2977 #endif 2978 2979 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 2980 struct dp_rx_history *rx_ring_history[MAX_REO_DEST_RINGS]; 2981 struct dp_rx_refill_history *rx_refill_ring_history[MAX_PDEV_CNT]; 2982 struct dp_rx_err_history *rx_err_ring_history; 2983 struct dp_rx_reinject_history *rx_reinject_ring_history; 2984 #endif 2985 2986 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 2987 struct dp_mon_status_ring_history *mon_status_ring_history; 2988 #endif 2989 2990 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 2991 struct dp_tx_tcl_history tx_tcl_history; 2992 struct dp_tx_comp_history tx_comp_history; 2993 #endif 2994 2995 #ifdef WLAN_FEATURE_DP_CFG_EVENT_HISTORY 2996 struct dp_cfg_event_history cfg_event_history; 2997 #endif 2998 2999 qdf_spinlock_t ast_lock; 3000 /*Timer for AST entry ageout maintenance */ 3001 qdf_timer_t ast_aging_timer; 3002 3003 /*Timer counter for WDS AST entry ageout*/ 3004 uint8_t wds_ast_aging_timer_cnt; 3005 bool pending_ageout; 3006 bool ast_offload_support; 3007 bool host_ast_db_enable; 3008 uint32_t max_ast_ageout_count; 3009 uint8_t eapol_over_control_port; 3010 3011 uint8_t sta_mode_search_policy; 3012 qdf_timer_t lmac_reap_timer; 3013 uint8_t lmac_timer_init; 3014 qdf_timer_t int_timer; 3015 uint8_t intr_mode; 3016 uint8_t lmac_polled_mode; 3017 3018 qdf_list_t reo_desc_freelist; 3019 qdf_spinlock_t reo_desc_freelist_lock; 3020 3021 /* htt stats */ 3022 struct htt_t2h_stats htt_stats; 3023 3024 void *external_txrx_handle; /* External data path handle */ 3025 qdf_atomic_t ipa_map_allowed; 3026 #ifdef IPA_OFFLOAD 3027 struct ipa_dp_tx_rsc ipa_uc_tx_rsc; 3028 #ifdef IPA_WDI3_TX_TWO_PIPES 3029 /* Resources for the alternative IPA TX pipe */ 3030 struct ipa_dp_tx_rsc ipa_uc_tx_rsc_alt; 3031 #endif 3032 3033 struct ipa_dp_rx_rsc ipa_uc_rx_rsc; 3034 #ifdef IPA_WDI3_VLAN_SUPPORT 3035 struct ipa_dp_rx_rsc ipa_uc_rx_rsc_alt; 3036 #endif 3037 qdf_atomic_t ipa_pipes_enabled; 3038 bool ipa_first_tx_db_access; 3039 qdf_spinlock_t ipa_rx_buf_map_lock; 3040 bool ipa_rx_buf_map_lock_initialized; 3041 uint8_t ipa_reo_ctx_lock_required[MAX_REO_DEST_RINGS]; 3042 #endif 3043 3044 #ifdef WLAN_FEATURE_STATS_EXT 3045 struct { 3046 uint32_t rx_mpdu_received; 3047 uint32_t rx_mpdu_missed; 3048 } ext_stats; 3049 qdf_event_t rx_hw_stats_event; 3050 qdf_spinlock_t rx_hw_stats_lock; 3051 bool is_last_stats_ctx_init; 3052 struct dp_req_rx_hw_stats_t *rx_hw_stats; 3053 #endif /* WLAN_FEATURE_STATS_EXT */ 3054 3055 /* Indicates HTT map/unmap versions*/ 3056 uint8_t peer_map_unmap_versions; 3057 /* Per peer per Tid ba window size support */ 3058 uint8_t per_tid_basize_max_tid; 3059 /* Soc level flag to enable da_war */ 3060 uint8_t da_war_enabled; 3061 /* number of active ast entries */ 3062 uint32_t num_ast_entries; 3063 /* peer extended rate statistics context at soc level*/ 3064 struct cdp_soc_rate_stats_ctx *rate_stats_ctx; 3065 /* peer extended rate statistics control flag */ 3066 bool peerstats_enabled; 3067 3068 /* 8021p PCP-TID map values */ 3069 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 3070 /* TID map priority value */ 3071 uint8_t tidmap_prty; 3072 /* Pointer to global per ring type specific configuration table */ 3073 struct wlan_srng_cfg *wlan_srng_cfg; 3074 /* Num Tx outstanding on device */ 3075 qdf_atomic_t num_tx_outstanding; 3076 /* Num Tx exception on device */ 3077 qdf_atomic_t num_tx_exception; 3078 /* Num Tx allowed */ 3079 uint32_t num_tx_allowed; 3080 /* Num Regular Tx allowed */ 3081 uint32_t num_reg_tx_allowed; 3082 /* Num Tx allowed for special frames*/ 3083 uint32_t num_tx_spl_allowed; 3084 /* Preferred HW mode */ 3085 uint8_t preferred_hw_mode; 3086 3087 /** 3088 * Flag to indicate whether WAR to address single cache entry 3089 * invalidation bug is enabled or not 3090 */ 3091 bool is_rx_fse_full_cache_invalidate_war_enabled; 3092 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) 3093 /** 3094 * Pointer to DP RX Flow FST at SOC level if 3095 * is_rx_flow_search_table_per_pdev is false 3096 * TBD: rx_fst[num_macs] if we decide to have per mac FST 3097 */ 3098 struct dp_rx_fst *rx_fst; 3099 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 3100 /* SG supported for msdu continued packets from wbm release ring */ 3101 bool wbm_release_desc_rx_sg_support; 3102 bool peer_map_attach_success; 3103 /* Flag to disable mac1 ring interrupts */ 3104 bool disable_mac1_intr; 3105 /* Flag to disable mac2 ring interrupts */ 3106 bool disable_mac2_intr; 3107 3108 struct { 3109 /* 1st msdu in sg for msdu continued packets in wbm rel ring */ 3110 bool wbm_is_first_msdu_in_sg; 3111 /* Wbm sg list head */ 3112 qdf_nbuf_t wbm_sg_nbuf_head; 3113 /* Wbm sg list tail */ 3114 qdf_nbuf_t wbm_sg_nbuf_tail; 3115 uint32_t wbm_sg_desc_msdu_len; 3116 } wbm_sg_param; 3117 /* Number of msdu exception descriptors */ 3118 uint32_t num_msdu_exception_desc; 3119 3120 /* RX buffer params */ 3121 struct rx_buff_pool rx_buff_pool[MAX_PDEV_CNT]; 3122 struct rx_refill_buff_pool rx_refill_buff_pool; 3123 /* Save recent operation related variable */ 3124 struct dp_last_op_info last_op_info; 3125 TAILQ_HEAD(, dp_peer) inactive_peer_list; 3126 qdf_spinlock_t inactive_peer_list_lock; 3127 TAILQ_HEAD(, dp_vdev) inactive_vdev_list; 3128 qdf_spinlock_t inactive_vdev_list_lock; 3129 /* lock to protect vdev_id_map table*/ 3130 qdf_spinlock_t vdev_map_lock; 3131 3132 /* Flow Search Table is in CMEM */ 3133 bool fst_in_cmem; 3134 3135 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 3136 struct dp_swlm swlm; 3137 #endif 3138 3139 #ifdef FEATURE_RUNTIME_PM 3140 /* DP Rx timestamp */ 3141 qdf_time_t rx_last_busy; 3142 /* Dp runtime refcount */ 3143 qdf_atomic_t dp_runtime_refcount; 3144 /* Dp tx pending count in RTPM */ 3145 qdf_atomic_t tx_pending_rtpm; 3146 #endif 3147 /* Invalid buffer that allocated for RX buffer */ 3148 qdf_nbuf_queue_t invalid_buf_queue; 3149 3150 #ifdef FEATURE_MEC 3151 /** @mec_lock: spinlock for MEC table */ 3152 qdf_spinlock_t mec_lock; 3153 /** @mec_cnt: number of active mec entries */ 3154 qdf_atomic_t mec_cnt; 3155 struct { 3156 /** @mask: mask bits */ 3157 uint32_t mask; 3158 /** @idx_bits: index to shift bits */ 3159 uint32_t idx_bits; 3160 /** @bins: MEC table */ 3161 TAILQ_HEAD(, dp_mec_entry) * bins; 3162 } mec_hash; 3163 #endif 3164 3165 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 3166 qdf_list_t reo_desc_deferred_freelist; 3167 qdf_spinlock_t reo_desc_deferred_freelist_lock; 3168 bool reo_desc_deferred_freelist_init; 3169 #endif 3170 /* BM id for first WBM2SW ring */ 3171 uint32_t wbm_sw0_bm_id; 3172 3173 /* Store arch_id from device_id */ 3174 uint16_t arch_id; 3175 3176 /* link desc ID start per device type */ 3177 uint32_t link_desc_id_start; 3178 3179 /* CMEM buffer target reserved for host usage */ 3180 uint64_t cmem_base; 3181 /* CMEM size in bytes */ 3182 uint64_t cmem_total_size; 3183 /* CMEM free size in bytes */ 3184 uint64_t cmem_avail_size; 3185 3186 /* SOC level feature flags */ 3187 struct dp_soc_features features; 3188 3189 #ifdef WIFI_MONITOR_SUPPORT 3190 struct dp_mon_soc *monitor_soc; 3191 #endif 3192 uint8_t rxdma2sw_rings_not_supported:1, 3193 wbm_sg_last_msdu_war:1, 3194 mec_fw_offload:1, 3195 multi_peer_grp_cmd_supported:1, 3196 umac_reset_supported:1; 3197 3198 /* Number of Rx refill rings */ 3199 uint8_t num_rx_refill_buf_rings; 3200 #ifdef FEATURE_RUNTIME_PM 3201 /* flag to indicate vote for runtime_pm for high tput castt*/ 3202 qdf_atomic_t rtpm_high_tput_flag; 3203 #endif 3204 /* Buffer manager ID for idle link descs */ 3205 uint8_t idle_link_bm_id; 3206 qdf_atomic_t ref_count; 3207 3208 unsigned long vdev_stats_id_map; 3209 bool txmon_hw_support; 3210 3211 #ifdef DP_UMAC_HW_RESET_SUPPORT 3212 struct dp_soc_umac_reset_ctx umac_reset_ctx; 3213 #endif 3214 /* PPDU to link_id mapping parameters */ 3215 uint8_t link_id_offset; 3216 uint8_t link_id_bits; 3217 #ifdef FEATURE_RX_LINKSPEED_ROAM_TRIGGER 3218 /* A flag using to decide the switch of rx link speed */ 3219 bool high_throughput; 3220 #endif 3221 bool is_tx_pause; 3222 3223 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 3224 /* number of IPv4 flows inserted */ 3225 qdf_atomic_t ipv4_fse_cnt; 3226 /* number of IPv6 flows inserted */ 3227 qdf_atomic_t ipv6_fse_cnt; 3228 #endif 3229 /* Reo queue ref table items */ 3230 struct reo_queue_ref_table reo_qref; 3231 #ifdef DP_TX_PACKET_INSPECT_FOR_ILP 3232 /* Flag to show if TX ILP is enabled */ 3233 bool tx_ilp_enable; 3234 #endif 3235 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 3236 uint8_t mld_mode_ap; 3237 #endif 3238 struct test_qaddr_del *list_shared_qaddr_del; 3239 struct test_qaddr_del *reo_write_list; 3240 struct test_mem_free *list_qdesc_addr_free; 3241 struct test_mem_free *list_qdesc_addr_alloc; 3242 uint64_t free_addr_list_idx; 3243 uint64_t alloc_addr_list_idx; 3244 uint64_t shared_qaddr_del_idx; 3245 uint64_t write_paddr_list_idx; 3246 3247 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 3248 /* callback function for tx latency stats */ 3249 cdp_tx_latency_cb tx_latency_cb; 3250 #endif 3251 3252 #ifdef DP_TX_COMP_RING_DESC_SANITY_CHECK 3253 struct { 3254 uint32_t detected; 3255 uint64_t start_time; 3256 } stale_entry[MAX_TCL_DATA_RINGS]; 3257 #endif 3258 #ifdef DP_RX_MSDU_DONE_FAIL_HISTORY 3259 struct dp_msdu_done_fail_history *msdu_done_fail_hist; 3260 #endif 3261 #ifdef DP_RX_PEEK_MSDU_DONE_WAR 3262 struct dp_rx_msdu_done_fail_desc_list msdu_done_fail_desc_list; 3263 #endif 3264 /* monitor interface flags */ 3265 uint32_t mon_flags; 3266 }; 3267 3268 #ifdef IPA_OFFLOAD 3269 /** 3270 * struct dp_ipa_resources - Resources needed for IPA 3271 * @tx_ring: 3272 * @tx_num_alloc_buffer: 3273 * @tx_comp_ring: 3274 * @rx_rdy_ring: 3275 * @rx_refill_ring: 3276 * @tx_comp_doorbell_paddr: IPA UC doorbell registers paddr 3277 * @tx_comp_doorbell_vaddr: 3278 * @rx_ready_doorbell_paddr: 3279 * @is_db_ddr_mapped: 3280 * @tx_alt_ring: 3281 * @tx_alt_ring_num_alloc_buffer: 3282 * @tx_alt_comp_ring: 3283 * @tx_alt_comp_doorbell_paddr: IPA UC doorbell registers paddr 3284 * @tx_alt_comp_doorbell_vaddr: 3285 * @rx_alt_rdy_ring: 3286 * @rx_alt_refill_ring: 3287 * @rx_alt_ready_doorbell_paddr: 3288 */ 3289 struct dp_ipa_resources { 3290 qdf_shared_mem_t tx_ring; 3291 uint32_t tx_num_alloc_buffer; 3292 3293 qdf_shared_mem_t tx_comp_ring; 3294 qdf_shared_mem_t rx_rdy_ring; 3295 qdf_shared_mem_t rx_refill_ring; 3296 3297 /* IPA UC doorbell registers paddr */ 3298 qdf_dma_addr_t tx_comp_doorbell_paddr; 3299 uint32_t *tx_comp_doorbell_vaddr; 3300 qdf_dma_addr_t rx_ready_doorbell_paddr; 3301 3302 bool is_db_ddr_mapped; 3303 3304 #ifdef IPA_WDI3_TX_TWO_PIPES 3305 qdf_shared_mem_t tx_alt_ring; 3306 uint32_t tx_alt_ring_num_alloc_buffer; 3307 qdf_shared_mem_t tx_alt_comp_ring; 3308 3309 /* IPA UC doorbell registers paddr */ 3310 qdf_dma_addr_t tx_alt_comp_doorbell_paddr; 3311 uint32_t *tx_alt_comp_doorbell_vaddr; 3312 #endif 3313 #ifdef IPA_WDI3_VLAN_SUPPORT 3314 qdf_shared_mem_t rx_alt_rdy_ring; 3315 qdf_shared_mem_t rx_alt_refill_ring; 3316 qdf_dma_addr_t rx_alt_ready_doorbell_paddr; 3317 #endif 3318 }; 3319 #endif 3320 3321 #define MAX_RX_MAC_RINGS 2 3322 /* Same as NAC_MAX_CLENT */ 3323 #define DP_NAC_MAX_CLIENT 24 3324 3325 /* 3326 * 24 bits cookie size 3327 * 10 bits page id 0 ~ 1023 for MCL 3328 * 3 bits page id 0 ~ 7 for WIN 3329 * WBM Idle List Desc size = 128, 3330 * Num descs per page = 4096/128 = 32 for MCL 3331 * Num descs per page = 2MB/128 = 16384 for WIN 3332 */ 3333 /* 3334 * Macros to setup link descriptor cookies - for link descriptors, we just 3335 * need first 3 bits to store bank/page ID for WIN. The 3336 * remaining bytes will be used to set a unique ID, which will 3337 * be useful in debugging 3338 */ 3339 #ifdef MAX_ALLOC_PAGE_SIZE 3340 #if PAGE_SIZE == 4096 3341 #define LINK_DESC_PAGE_ID_MASK 0x007FE0 3342 #define LINK_DESC_ID_SHIFT 5 3343 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 3344 #elif PAGE_SIZE == 65536 3345 #define LINK_DESC_PAGE_ID_MASK 0x007E00 3346 #define LINK_DESC_ID_SHIFT 9 3347 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x800 3348 #else 3349 #error "Unsupported kernel PAGE_SIZE" 3350 #endif 3351 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 3352 ((((_page_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_desc_id)) 3353 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 3354 (((_cookie) & LINK_DESC_PAGE_ID_MASK) >> LINK_DESC_ID_SHIFT) 3355 #else 3356 #define LINK_DESC_PAGE_ID_MASK 0x7 3357 #define LINK_DESC_ID_SHIFT 3 3358 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 3359 ((((_desc_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_page_id)) 3360 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 3361 ((_cookie) & LINK_DESC_PAGE_ID_MASK) 3362 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 3363 #endif 3364 #define LINK_DESC_ID_START_20_BITS_COOKIE 0x4000 3365 3366 /* same as ieee80211_nac_param */ 3367 enum dp_nac_param_cmd { 3368 /* IEEE80211_NAC_PARAM_ADD */ 3369 DP_NAC_PARAM_ADD = 1, 3370 /* IEEE80211_NAC_PARAM_DEL */ 3371 DP_NAC_PARAM_DEL, 3372 /* IEEE80211_NAC_PARAM_LIST */ 3373 DP_NAC_PARAM_LIST, 3374 }; 3375 3376 /** 3377 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 3378 * @neighbour_peers_macaddr: neighbour peer's mac address 3379 * @vdev: associated vdev 3380 * @ast_entry: ast_entry for neighbour peer 3381 * @rssi: rssi value 3382 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 3383 */ 3384 struct dp_neighbour_peer { 3385 union dp_align_mac_addr neighbour_peers_macaddr; 3386 struct dp_vdev *vdev; 3387 struct dp_ast_entry *ast_entry; 3388 uint8_t rssi; 3389 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 3390 }; 3391 3392 #ifdef WLAN_TX_PKT_CAPTURE_ENH 3393 #define WLAN_TX_PKT_CAPTURE_ENH 1 3394 #define DP_TX_PPDU_PROC_THRESHOLD 8 3395 #define DP_TX_PPDU_PROC_TIMEOUT 10 3396 #endif 3397 3398 /** 3399 * struct ppdu_info - PPDU Status info descriptor 3400 * @ppdu_id: Unique ppduid assigned by firmware for every tx packet 3401 * @sched_cmdid: schedule command id, which will be same in a burst 3402 * @max_ppdu_id: wrap around for ppdu id 3403 * @tsf_l32: 3404 * @tlv_bitmap: 3405 * @last_tlv_cnt: Keep track for missing ppdu tlvs 3406 * @last_user: last ppdu processed for user 3407 * @is_ampdu: set if Ampdu aggregate 3408 * @nbuf: ppdu descriptor payload 3409 * @ppdu_desc: ppdu descriptor 3410 * @ulist: Union of lists 3411 * @ppdu_info_dlist_elem: linked list of ppdu tlvs 3412 * @ppdu_info_slist_elem: Singly linked list (queue) of ppdu tlvs 3413 * @ppdu_info_list_elem: linked list of ppdu tlvs 3414 * @ppdu_info_queue_elem: Singly linked list (queue) of ppdu tlvs 3415 * @compltn_common_tlv: Successful tlv counter from COMPLTN COMMON tlv 3416 * @ack_ba_tlv: Successful tlv counter from ACK BA tlv 3417 * @done: 3418 */ 3419 struct ppdu_info { 3420 uint32_t ppdu_id; 3421 uint32_t sched_cmdid; 3422 uint32_t max_ppdu_id; 3423 uint32_t tsf_l32; 3424 uint16_t tlv_bitmap; 3425 uint16_t last_tlv_cnt; 3426 uint16_t last_user:8, 3427 is_ampdu:1; 3428 qdf_nbuf_t nbuf; 3429 struct cdp_tx_completion_ppdu *ppdu_desc; 3430 #ifdef WLAN_TX_PKT_CAPTURE_ENH 3431 union { 3432 TAILQ_ENTRY(ppdu_info) ppdu_info_dlist_elem; 3433 STAILQ_ENTRY(ppdu_info) ppdu_info_slist_elem; 3434 } ulist; 3435 #define ppdu_info_list_elem ulist.ppdu_info_dlist_elem 3436 #define ppdu_info_queue_elem ulist.ppdu_info_slist_elem 3437 #else 3438 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 3439 #endif 3440 uint8_t compltn_common_tlv; 3441 uint8_t ack_ba_tlv; 3442 bool done; 3443 }; 3444 3445 /** 3446 * struct msdu_completion_info - wbm msdu completion info 3447 * @ppdu_id: Unique ppduid assigned by firmware for every tx packet 3448 * @peer_id: peer_id 3449 * @tid: tid which used during transmit 3450 * @first_msdu: first msdu indication 3451 * @last_msdu: last msdu indication 3452 * @msdu_part_of_amsdu: msdu part of amsdu 3453 * @transmit_cnt: retried count 3454 * @status: transmit status 3455 * @tsf: timestamp which it transmitted 3456 */ 3457 struct msdu_completion_info { 3458 uint32_t ppdu_id; 3459 uint16_t peer_id; 3460 uint8_t tid; 3461 uint8_t first_msdu:1, 3462 last_msdu:1, 3463 msdu_part_of_amsdu:1; 3464 uint8_t transmit_cnt; 3465 uint8_t status; 3466 uint32_t tsf; 3467 }; 3468 3469 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 3470 struct rx_protocol_tag_map { 3471 /* This is the user configured tag for the said protocol type */ 3472 uint16_t tag; 3473 }; 3474 3475 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 3476 /** 3477 * struct rx_protocol_tag_stats - protocol statistics 3478 * @tag_ctr: number of rx msdus matching this tag 3479 */ 3480 struct rx_protocol_tag_stats { 3481 uint32_t tag_ctr; 3482 }; 3483 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 3484 3485 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 3486 3487 #ifdef WLAN_RX_PKT_CAPTURE_ENH 3488 /* Template data to be set for Enhanced RX Monitor packets */ 3489 #define RX_MON_CAP_ENH_TRAILER 0xdeadc0dedeadda7a 3490 3491 /** 3492 * struct dp_rx_mon_enh_trailer_data - Data structure to set a known pattern 3493 * at end of each MSDU in monitor-lite mode 3494 * @reserved1: reserved for future use 3495 * @reserved2: reserved for future use 3496 * @flow_tag: flow tag value read from skb->cb 3497 * @protocol_tag: protocol tag value read from skb->cb 3498 */ 3499 struct dp_rx_mon_enh_trailer_data { 3500 uint16_t reserved1; 3501 uint16_t reserved2; 3502 uint16_t flow_tag; 3503 uint16_t protocol_tag; 3504 }; 3505 #endif /* WLAN_RX_PKT_CAPTURE_ENH */ 3506 3507 #ifdef HTT_STATS_DEBUGFS_SUPPORT 3508 /* Number of debugfs entries created for HTT stats */ 3509 #define PDEV_HTT_STATS_DBGFS_SIZE HTT_DBG_NUM_EXT_STATS 3510 3511 /** 3512 * struct pdev_htt_stats_dbgfs_priv - Structure to maintain debugfs information 3513 * of HTT stats 3514 * @pdev: dp pdev of debugfs entry 3515 * @stats_id: stats id of debugfs entry 3516 */ 3517 struct pdev_htt_stats_dbgfs_priv { 3518 struct dp_pdev *pdev; 3519 uint16_t stats_id; 3520 }; 3521 3522 /** 3523 * struct pdev_htt_stats_dbgfs_cfg - PDEV level data structure for debugfs 3524 * support for HTT stats 3525 * @debugfs_entry: qdf_debugfs directory entry 3526 * @m: qdf debugfs file handler 3527 * @pdev_htt_stats_dbgfs_ops: File operations of entry created 3528 * @priv: HTT stats debugfs private object 3529 * @htt_stats_dbgfs_event: HTT stats event for debugfs support 3530 * @lock: HTT stats debugfs lock 3531 * @htt_stats_dbgfs_msg_process: Function callback to print HTT stats 3532 */ 3533 struct pdev_htt_stats_dbgfs_cfg { 3534 qdf_dentry_t debugfs_entry[PDEV_HTT_STATS_DBGFS_SIZE]; 3535 qdf_debugfs_file_t m; 3536 struct qdf_debugfs_fops 3537 pdev_htt_stats_dbgfs_ops[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 3538 struct pdev_htt_stats_dbgfs_priv priv[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 3539 qdf_event_t htt_stats_dbgfs_event; 3540 qdf_mutex_t lock; 3541 void (*htt_stats_dbgfs_msg_process)(void *data, A_INT32 len); 3542 }; 3543 #endif /* HTT_STATS_DEBUGFS_SUPPORT */ 3544 3545 struct dp_srng_ring_state { 3546 enum hal_ring_type ring_type; 3547 uint32_t sw_head; 3548 uint32_t sw_tail; 3549 uint32_t hw_head; 3550 uint32_t hw_tail; 3551 3552 }; 3553 3554 struct dp_soc_srngs_state { 3555 uint32_t seq_num; 3556 uint32_t max_ring_id; 3557 struct dp_srng_ring_state ring_state[DP_MAX_SRNGS]; 3558 TAILQ_ENTRY(dp_soc_srngs_state) list_elem; 3559 }; 3560 3561 #ifdef WLAN_FEATURE_11BE_MLO 3562 /* struct dp_mlo_sync_timestamp - PDEV level data structure for storing 3563 * MLO timestamp received via HTT msg. 3564 * msg_type: This would be set to HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 3565 * pdev_id: pdev_id 3566 * chip_id: chip_id 3567 * mac_clk_freq: mac clock frequency of the mac HW block in MHz 3568 * sync_tstmp_lo_us: lower 32 bits of the WLAN global time stamp (in us) at 3569 * which last sync interrupt was received 3570 * sync_tstmp_hi_us: upper 32 bits of the WLAN global time stamp (in us) at 3571 * which last sync interrupt was received 3572 * mlo_offset_lo_us: lower 32 bits of the MLO time stamp offset in us 3573 * mlo_offset_hi_us: upper 32 bits of the MLO time stamp offset in us 3574 * mlo_offset_clks: MLO time stamp offset in clock ticks for sub us 3575 * mlo_comp_us: MLO time stamp compensation applied in us 3576 * mlo_comp_clks: MLO time stamp compensation applied in clock ticks 3577 * for sub us resolution 3578 * mlo_comp_timer: period of MLO compensation timer at which compensation 3579 * is applied, in us 3580 */ 3581 struct dp_mlo_sync_timestamp { 3582 uint32_t msg_type:8, 3583 pdev_id:2, 3584 chip_id:2, 3585 rsvd1:4, 3586 mac_clk_freq:16; 3587 uint32_t sync_tstmp_lo_us; 3588 uint32_t sync_tstmp_hi_us; 3589 uint32_t mlo_offset_lo_us; 3590 uint32_t mlo_offset_hi_us; 3591 uint32_t mlo_offset_clks; 3592 uint32_t mlo_comp_us:16, 3593 mlo_comp_clks:10, 3594 rsvd2:6; 3595 uint32_t mlo_comp_timer:22, 3596 rsvd3:10; 3597 }; 3598 #endif 3599 3600 /* PDEV level structure for data path */ 3601 struct dp_pdev { 3602 /** 3603 * Re-use Memory Section Starts 3604 */ 3605 3606 /* PDEV Id */ 3607 uint8_t pdev_id; 3608 3609 /* LMAC Id */ 3610 uint8_t lmac_id; 3611 3612 /* Target pdev Id */ 3613 uint8_t target_pdev_id; 3614 3615 bool pdev_deinit; 3616 3617 /* TXRX SOC handle */ 3618 struct dp_soc *soc; 3619 3620 /* pdev status down or up required to handle dynamic hw 3621 * mode switch between DBS and DBS_SBS. 3622 * 1 = down 3623 * 0 = up 3624 */ 3625 bool is_pdev_down; 3626 3627 /* Enhanced Stats is enabled */ 3628 uint8_t enhanced_stats_en:1, 3629 link_peer_stats:1; 3630 3631 /* Flag to indicate fast path Tx flags */ 3632 uint32_t tx_fast_flag; 3633 3634 /* Flag to indicate fast RX */ 3635 bool rx_fast_flag; 3636 3637 /* Second ring used to replenish rx buffers */ 3638 struct dp_srng rx_refill_buf_ring2; 3639 #ifdef IPA_WDI3_VLAN_SUPPORT 3640 /* Third ring used to replenish rx buffers */ 3641 struct dp_srng rx_refill_buf_ring3; 3642 #endif 3643 3644 #ifdef FEATURE_DIRECT_LINK 3645 /* Fourth ring used to replenish rx buffers */ 3646 struct dp_srng rx_refill_buf_ring4; 3647 #endif 3648 3649 /* Empty ring used by firmware to post rx buffers to the MAC */ 3650 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 3651 3652 int ch_band_lmac_id_mapping[REG_BAND_UNKNOWN]; 3653 3654 /* wlan_cfg pdev ctxt*/ 3655 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 3656 3657 /** 3658 * TODO: See if we need a ring map here for LMAC rings. 3659 * 1. Monitor rings are currently planning to be processed on receiving 3660 * PPDU end interrupts and hence won't need ring based interrupts. 3661 * 2. Rx buffer rings will be replenished during REO destination 3662 * processing and doesn't require regular interrupt handling - we will 3663 * only handle low water mark interrupts which is not expected 3664 * frequently 3665 */ 3666 3667 /* VDEV list */ 3668 TAILQ_HEAD(, dp_vdev) vdev_list; 3669 3670 /* vdev list lock */ 3671 qdf_spinlock_t vdev_list_lock; 3672 3673 /* Number of vdevs this device have */ 3674 uint16_t vdev_count; 3675 3676 /* PDEV transmit lock */ 3677 qdf_spinlock_t tx_lock; 3678 3679 /*tx_mutex for me*/ 3680 DP_MUTEX_TYPE tx_mutex; 3681 3682 /* msdu chain head & tail */ 3683 qdf_nbuf_t invalid_peer_head_msdu; 3684 qdf_nbuf_t invalid_peer_tail_msdu; 3685 3686 /* Band steering */ 3687 /* TBD */ 3688 3689 /* PDEV level data path statistics */ 3690 struct cdp_pdev_stats stats; 3691 3692 /* Global RX decap mode for the device */ 3693 enum htt_pkt_type rx_decap_mode; 3694 3695 qdf_atomic_t num_tx_outstanding; 3696 int32_t tx_descs_max; 3697 3698 qdf_atomic_t num_tx_exception; 3699 3700 /* MCL specific local peer handle */ 3701 struct { 3702 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 3703 uint8_t freelist; 3704 qdf_spinlock_t lock; 3705 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 3706 } local_peer_ids; 3707 3708 /* dscp_tid_map_*/ 3709 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 3710 3711 /* operating channel */ 3712 struct { 3713 uint8_t num; 3714 uint8_t band; 3715 uint16_t freq; 3716 } operating_channel; 3717 3718 /* pool addr for mcast enhance buff */ 3719 struct { 3720 int size; 3721 uint32_t paddr; 3722 char *vaddr; 3723 struct dp_tx_me_buf_t *freelist; 3724 int buf_in_use; 3725 qdf_dma_mem_context(memctx); 3726 } me_buf; 3727 3728 bool hmmc_tid_override_en; 3729 uint8_t hmmc_tid; 3730 3731 /* Number of VAPs with mcast enhancement enabled */ 3732 qdf_atomic_t mc_num_vap_attached; 3733 3734 qdf_atomic_t stats_cmd_complete; 3735 3736 #ifdef IPA_OFFLOAD 3737 ipa_uc_op_cb_type ipa_uc_op_cb; 3738 void *usr_ctxt; 3739 struct dp_ipa_resources ipa_resource; 3740 #endif 3741 3742 /* TBD */ 3743 3744 /* map this pdev to a particular Reo Destination ring */ 3745 enum cdp_host_reo_dest_ring reo_dest; 3746 3747 /* WDI event handlers */ 3748 struct wdi_event_subscribe_t **wdi_event_list; 3749 3750 bool cfr_rcc_mode; 3751 3752 /* enable time latency check for tx completion */ 3753 bool latency_capture_enable; 3754 3755 /* enable calculation of delay stats*/ 3756 bool delay_stats_flag; 3757 /* vow stats */ 3758 bool vow_stats; 3759 void *dp_txrx_handle; /* Advanced data path handle */ 3760 uint32_t ppdu_id; 3761 bool first_nbuf; 3762 /* Current noise-floor reading for the pdev channel */ 3763 int16_t chan_noise_floor; 3764 3765 /* 3766 * For multiradio device, this flag indicates if 3767 * this radio is primary or secondary. 3768 * 3769 * For HK 1.0, this is used for WAR for the AST issue. 3770 * HK 1.x mandates creation of only 1 AST entry with same MAC address 3771 * across 2 radios. is_primary indicates the radio on which DP should 3772 * install HW AST entry if there is a request to add 2 AST entries 3773 * with same MAC address across 2 radios 3774 */ 3775 uint8_t is_primary; 3776 struct cdp_tx_sojourn_stats sojourn_stats; 3777 qdf_nbuf_t sojourn_buf; 3778 3779 union dp_rx_desc_list_elem_t *free_list_head; 3780 union dp_rx_desc_list_elem_t *free_list_tail; 3781 /* Cached peer_id from htt_peer_details_tlv */ 3782 uint16_t fw_stats_peer_id; 3783 3784 /* qdf_event for fw_peer_stats */ 3785 qdf_event_t fw_peer_stats_event; 3786 3787 /* qdf_event for fw_stats */ 3788 qdf_event_t fw_stats_event; 3789 3790 /* qdf_event for fw__obss_stats */ 3791 qdf_event_t fw_obss_stats_event; 3792 3793 /* To check if request is already sent for obss stats */ 3794 bool pending_fw_obss_stats_response; 3795 3796 /* User configured max number of tx buffers */ 3797 uint32_t num_tx_allowed; 3798 3799 /* 3800 * User configured max num of tx buffers excluding the 3801 * number of buffers reserved for handling special frames 3802 */ 3803 uint32_t num_reg_tx_allowed; 3804 3805 /* User configured max number of tx buffers for the special frames*/ 3806 uint32_t num_tx_spl_allowed; 3807 3808 /* unique cookie required for peer session */ 3809 uint32_t next_peer_cookie; 3810 3811 /* 3812 * Run time enabled when the first protocol tag is added, 3813 * run time disabled when the last protocol tag is deleted 3814 */ 3815 bool is_rx_protocol_tagging_enabled; 3816 3817 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 3818 /* 3819 * The protocol type is used as array index to save 3820 * user provided tag info 3821 */ 3822 struct rx_protocol_tag_map rx_proto_tag_map[RX_PROTOCOL_TAG_MAX]; 3823 3824 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 3825 /* 3826 * Track msdus received from each reo ring separately to avoid 3827 * simultaneous writes from different core 3828 */ 3829 struct rx_protocol_tag_stats 3830 reo_proto_tag_stats[MAX_REO_DEST_RINGS][RX_PROTOCOL_TAG_MAX]; 3831 /* Track msdus received from exception ring separately */ 3832 struct rx_protocol_tag_stats 3833 rx_err_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 3834 struct rx_protocol_tag_stats 3835 mon_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 3836 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 3837 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 3838 3839 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 3840 /** 3841 * Pointer to DP Flow FST at SOC level if 3842 * is_rx_flow_search_table_per_pdev is true 3843 */ 3844 struct dp_rx_fst *rx_fst; 3845 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 3846 3847 #ifdef FEATURE_TSO_STATS 3848 /* TSO Id to index into TSO packet information */ 3849 qdf_atomic_t tso_idx; 3850 #endif /* FEATURE_TSO_STATS */ 3851 3852 #ifdef WLAN_SUPPORT_DATA_STALL 3853 data_stall_detect_cb data_stall_detect_callback; 3854 #endif /* WLAN_SUPPORT_DATA_STALL */ 3855 3856 /* flag to indicate whether LRO hash command has been sent to FW */ 3857 uint8_t is_lro_hash_configured; 3858 3859 #ifdef HTT_STATS_DEBUGFS_SUPPORT 3860 /* HTT stats debugfs params */ 3861 struct pdev_htt_stats_dbgfs_cfg *dbgfs_cfg; 3862 #endif 3863 struct { 3864 qdf_work_t work; 3865 qdf_workqueue_t *work_queue; 3866 uint32_t seq_num; 3867 uint8_t queue_depth; 3868 qdf_spinlock_t list_lock; 3869 3870 TAILQ_HEAD(, dp_soc_srngs_state) list; 3871 } bkp_stats; 3872 #ifdef WIFI_MONITOR_SUPPORT 3873 struct dp_mon_pdev *monitor_pdev; 3874 #endif 3875 #ifdef WLAN_FEATURE_11BE_MLO 3876 struct dp_mlo_sync_timestamp timestamp; 3877 #endif 3878 /* Is isolation mode enabled */ 3879 bool isolation; 3880 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 3881 uint8_t is_first_wakeup_packet; 3882 #endif 3883 #ifdef CONNECTIVITY_PKTLOG 3884 /* packetdump callback functions */ 3885 ol_txrx_pktdump_cb dp_tx_packetdump_cb; 3886 ol_txrx_pktdump_cb dp_rx_packetdump_cb; 3887 #endif 3888 3889 /* Firmware Stats for TLV received from Firmware */ 3890 uint64_t fw_stats_tlv_bitmap_rcvd; 3891 3892 /* For Checking Pending Firmware Response */ 3893 bool pending_fw_stats_response; 3894 }; 3895 3896 struct dp_peer; 3897 3898 #ifdef DP_RX_UDP_OVER_PEER_ROAM 3899 #define WLAN_ROAM_PEER_AUTH_STATUS_NONE 0x0 3900 /* 3901 * This macro is equivalent to macro ROAM_AUTH_STATUS_AUTHENTICATED used 3902 * in connection mgr 3903 */ 3904 #define WLAN_ROAM_PEER_AUTH_STATUS_AUTHENTICATED 0x2 3905 #endif 3906 3907 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 3908 /** 3909 * struct dp_tx_latency_config - configuration for per-link transmit latency 3910 * statistics 3911 * @enabled: the feature is enabled or not 3912 * @report: async report is enabled or not 3913 * @granularity: granularity(in microseconds) of the distribution for the types 3914 */ 3915 struct dp_tx_latency_config { 3916 qdf_atomic_t enabled; 3917 qdf_atomic_t report; 3918 qdf_atomic_t granularity[CDP_TX_LATENCY_TYPE_MAX]; 3919 }; 3920 3921 /** 3922 * struct dp_tx_latency_stats - transmit latency distribution for a type 3923 * @latency_accum: accumulated latencies 3924 * @msdus_accum: accumulated number of msdus 3925 * @distribution: distribution of latencies 3926 */ 3927 struct dp_tx_latency_stats { 3928 qdf_atomic_t latency_accum; 3929 qdf_atomic_t msdus_accum; 3930 qdf_atomic_t distribution[CDP_TX_LATENCY_DISTR_LV_MAX]; 3931 }; 3932 3933 /** 3934 * struct dp_tx_latency - transmit latency statistics for remote link peer 3935 * @cur_idx: current row index of the 2D stats array 3936 * @stats: two-dimensional array, to store the transmit latency statistics. 3937 * one row is used to store the stats of the current cycle, it's indicated 3938 * by cur_idx, the other is for the last cycle. 3939 */ 3940 struct dp_tx_latency { 3941 uint8_t cur_idx; 3942 struct dp_tx_latency_stats stats[2][CDP_TX_LATENCY_TYPE_MAX]; 3943 }; 3944 #endif 3945 3946 /** 3947 * struct dp_vdev_stats - vdev stats structure for dp vdev 3948 * @tx_i: ingress tx stats, contains legacy and MLO ingress tx stats 3949 * @rx_i: ingress rx stats 3950 * @tx: cdp tx stats 3951 * @rx: cdp rx stats 3952 * @tso_stats: tso stats 3953 * @tid_tx_stats: tid tx stats 3954 */ 3955 struct dp_vdev_stats { 3956 struct cdp_tx_ingress_stats tx_i[DP_INGRESS_STATS_MAX_SIZE]; 3957 struct cdp_rx_ingress_stats rx_i; 3958 struct cdp_tx_stats tx; 3959 struct cdp_rx_stats rx; 3960 struct cdp_tso_stats tso_stats; 3961 #ifdef HW_TX_DELAY_STATS_ENABLE 3962 struct cdp_tid_tx_stats tid_tx_stats[CDP_MAX_TX_COMP_RINGS] 3963 [CDP_MAX_DATA_TIDS]; 3964 #endif 3965 }; 3966 3967 /* VDEV structure for data path state */ 3968 struct dp_vdev { 3969 /* OS device abstraction */ 3970 qdf_device_t osdev; 3971 3972 /* physical device that is the parent of this virtual device */ 3973 struct dp_pdev *pdev; 3974 3975 /* VDEV operating mode */ 3976 enum wlan_op_mode opmode; 3977 3978 /* VDEV subtype */ 3979 enum wlan_op_subtype subtype; 3980 3981 /* Tx encapsulation type for this VAP */ 3982 enum htt_cmn_pkt_type tx_encap_type; 3983 3984 /* Rx Decapsulation type for this VAP */ 3985 enum htt_cmn_pkt_type rx_decap_type; 3986 3987 /* WDS enabled */ 3988 bool wds_enabled; 3989 3990 /* MEC enabled */ 3991 bool mec_enabled; 3992 3993 #ifdef QCA_SUPPORT_WDS_EXTENDED 3994 bool wds_ext_enabled; 3995 bool drop_tx_mcast; 3996 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 3997 bool drop_3addr_mcast; 3998 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 3999 bool skip_bar_update; 4000 unsigned long skip_bar_update_last_ts; 4001 #endif 4002 /* WDS Aging timer period */ 4003 uint32_t wds_aging_timer_val; 4004 4005 /* NAWDS enabled */ 4006 bool nawds_enabled; 4007 4008 /* Multicast enhancement enabled */ 4009 uint8_t mcast_enhancement_en; 4010 4011 /* IGMP multicast enhancement enabled */ 4012 uint8_t igmp_mcast_enhanc_en; 4013 4014 /* vdev_id - ID used to specify a particular vdev to the target */ 4015 uint8_t vdev_id; 4016 4017 /* Default HTT meta data for this VDEV */ 4018 /* TBD: check alignment constraints */ 4019 uint16_t htt_tcl_metadata; 4020 4021 /* vdev lmac_id */ 4022 uint8_t lmac_id; 4023 4024 /* vdev bank_id */ 4025 uint8_t bank_id; 4026 4027 /* Mesh mode vdev */ 4028 uint32_t mesh_vdev; 4029 4030 /* Mesh mode rx filter setting */ 4031 uint32_t mesh_rx_filter; 4032 4033 /* DSCP-TID mapping table ID */ 4034 uint8_t dscp_tid_map_id; 4035 4036 /* Address search type to be set in TX descriptor */ 4037 uint8_t search_type; 4038 4039 /* 4040 * Flag to indicate if s/w tid classification should be 4041 * skipped 4042 */ 4043 uint8_t skip_sw_tid_classification; 4044 4045 /* Flag to enable peer authorization */ 4046 uint8_t peer_authorize; 4047 4048 /* AST hash value for BSS peer in HW valid for STA VAP*/ 4049 uint16_t bss_ast_hash; 4050 4051 /* AST hash index for BSS peer in HW valid for STA VAP*/ 4052 uint16_t bss_ast_idx; 4053 4054 bool multipass_en; 4055 4056 /* Address search flags to be configured in HAL descriptor */ 4057 uint8_t hal_desc_addr_search_flags; 4058 4059 /* Handle to the OS shim SW's virtual device */ 4060 ol_osif_vdev_handle osif_vdev; 4061 4062 /* MAC address */ 4063 union dp_align_mac_addr mac_addr; 4064 4065 #ifdef WLAN_FEATURE_11BE_MLO 4066 /* MLO MAC address corresponding to vdev */ 4067 union dp_align_mac_addr mld_mac_addr; 4068 #if defined(WLAN_MLO_MULTI_CHIP) && defined(WLAN_MCAST_MLO) 4069 uint8_t mlo_vdev:1, 4070 is_bridge_vdev:1, 4071 reserved_1:6; 4072 #endif 4073 #endif 4074 4075 /* node in the pdev's list of vdevs */ 4076 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 4077 4078 /* dp_peer list */ 4079 TAILQ_HEAD(, dp_peer) peer_list; 4080 /* to protect peer_list */ 4081 DP_MUTEX_TYPE peer_list_lock; 4082 4083 /* RX call back function to flush GRO packets*/ 4084 ol_txrx_rx_gro_flush_ind_fp osif_gro_flush; 4085 /* default RX call back function called by dp */ 4086 ol_txrx_rx_fp osif_rx; 4087 #ifdef QCA_SUPPORT_EAPOL_OVER_CONTROL_PORT 4088 /* callback to receive eapol frames */ 4089 ol_txrx_rx_fp osif_rx_eapol; 4090 #endif 4091 /* callback to deliver rx frames to the OS */ 4092 ol_txrx_rx_fp osif_rx_stack; 4093 /* Callback to handle rx fisa frames */ 4094 ol_txrx_fisa_rx_fp osif_fisa_rx; 4095 ol_txrx_fisa_flush_fp osif_fisa_flush; 4096 4097 /* call back function to flush out queued rx packets*/ 4098 ol_txrx_rx_flush_fp osif_rx_flush; 4099 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 4100 ol_txrx_get_key_fp osif_get_key; 4101 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 4102 4103 #ifdef notyet 4104 /* callback to check if the msdu is an WAI (WAPI) frame */ 4105 ol_rx_check_wai_fp osif_check_wai; 4106 #endif 4107 4108 /* proxy arp function */ 4109 ol_txrx_proxy_arp_fp osif_proxy_arp; 4110 4111 ol_txrx_mcast_me_fp me_convert; 4112 4113 /* completion function used by this vdev*/ 4114 ol_txrx_completion_fp tx_comp; 4115 4116 ol_txrx_get_tsf_time get_tsf_time; 4117 4118 /* callback to classify critical packets */ 4119 ol_txrx_classify_critical_pkt_fp tx_classify_critical_pkt_cb; 4120 4121 /* delete notifier to DP component */ 4122 ol_txrx_vdev_delete_cb vdev_del_notify; 4123 4124 /* deferred vdev deletion state */ 4125 struct { 4126 /* VDEV delete pending */ 4127 int pending; 4128 /* 4129 * callback and a context argument to provide a 4130 * notification for when the vdev is deleted. 4131 */ 4132 ol_txrx_vdev_delete_cb callback; 4133 void *context; 4134 } delete; 4135 4136 /* tx data delivery notification callback function */ 4137 struct { 4138 ol_txrx_data_tx_cb func; 4139 void *ctxt; 4140 } tx_non_std_data_callback; 4141 4142 4143 /* safe mode control to bypass the encrypt and decipher process*/ 4144 uint32_t safemode; 4145 4146 /* rx filter related */ 4147 uint32_t drop_unenc; 4148 #ifdef notyet 4149 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 4150 uint32_t filters_num; 4151 #endif 4152 /* TDLS Link status */ 4153 bool tdls_link_connected; 4154 bool is_tdls_frame; 4155 4156 /* per vdev rx nbuf queue */ 4157 qdf_nbuf_queue_t rxq; 4158 4159 uint8_t tx_ring_id; 4160 struct dp_tx_desc_pool_s *tx_desc; 4161 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 4162 4163 /* Capture timestamp of previous tx packet enqueued */ 4164 uint64_t prev_tx_enq_tstamp; 4165 4166 /* Capture timestamp of previous rx packet delivered */ 4167 uint64_t prev_rx_deliver_tstamp; 4168 4169 /* VDEV Stats */ 4170 struct dp_vdev_stats stats; 4171 4172 /* Is this a proxySTA VAP */ 4173 uint8_t proxysta_vdev : 1, /* Is this a proxySTA VAP */ 4174 wrap_vdev : 1, /* Is this a QWRAP AP VAP */ 4175 isolation_vdev : 1, /* Is this a QWRAP AP VAP */ 4176 reserved : 5; /* Reserved */ 4177 4178 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 4179 struct dp_tx_desc_pool_s *pool; 4180 #endif 4181 /* AP BRIDGE enabled */ 4182 bool ap_bridge_enabled; 4183 4184 enum cdp_sec_type sec_type; 4185 4186 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 4187 bool raw_mode_war; 4188 4189 4190 /* 8021p PCP-TID mapping table ID */ 4191 uint8_t tidmap_tbl_id; 4192 4193 /* 8021p PCP-TID map values */ 4194 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 4195 4196 /* TIDmap priority */ 4197 uint8_t tidmap_prty; 4198 4199 #ifdef QCA_MULTIPASS_SUPPORT 4200 uint16_t *iv_vlan_map; 4201 4202 /* dp_peer special list */ 4203 TAILQ_HEAD(, dp_txrx_peer) mpass_peer_list; 4204 DP_MUTEX_TYPE mpass_peer_mutex; 4205 #endif 4206 /* Extended data path handle */ 4207 struct cdp_ext_vdev *vdev_dp_ext_handle; 4208 #ifdef VDEV_PEER_PROTOCOL_COUNT 4209 /* 4210 * Rx-Ingress and Tx-Egress are in the lower level DP layer 4211 * Rx-Egress and Tx-ingress are handled in osif layer for DP 4212 * So 4213 * Rx-Egress and Tx-ingress mask definitions are in OSIF layer 4214 * Rx-Ingress and Tx-Egress definitions are here below 4215 */ 4216 #define VDEV_PEER_PROTOCOL_RX_INGRESS_MASK 1 4217 #define VDEV_PEER_PROTOCOL_TX_INGRESS_MASK 2 4218 #define VDEV_PEER_PROTOCOL_RX_EGRESS_MASK 4 4219 #define VDEV_PEER_PROTOCOL_TX_EGRESS_MASK 8 4220 bool peer_protocol_count_track; 4221 int peer_protocol_count_dropmask; 4222 #endif 4223 /* callback to collect connectivity stats */ 4224 ol_txrx_stats_rx_fp stats_cb; 4225 uint32_t num_peers; 4226 /* entry to inactive_list*/ 4227 TAILQ_ENTRY(dp_vdev) inactive_list_elem; 4228 4229 #ifdef WLAN_SUPPORT_RX_FISA 4230 /** 4231 * Params used for controlling the fisa aggregation dynamically 4232 */ 4233 uint8_t fisa_disallowed[MAX_REO_DEST_RINGS]; 4234 uint8_t fisa_force_flushed[MAX_REO_DEST_RINGS]; 4235 #endif 4236 /* 4237 * Refcount for VDEV currently incremented when 4238 * peer is created for VDEV 4239 */ 4240 qdf_atomic_t ref_cnt; 4241 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 4242 uint8_t num_latency_critical_conn; 4243 #ifdef WLAN_SUPPORT_MESH_LATENCY 4244 uint8_t peer_tid_latency_enabled; 4245 /* tid latency configuration parameters */ 4246 struct { 4247 uint32_t service_interval; 4248 uint32_t burst_size; 4249 uint8_t latency_tid; 4250 } mesh_tid_latency_config; 4251 #endif 4252 #ifdef WIFI_MONITOR_SUPPORT 4253 struct dp_mon_vdev *monitor_vdev; 4254 #endif 4255 #if defined(WLAN_FEATURE_TSF_AUTO_REPORT) || defined(WLAN_CONFIG_TX_DELAY) 4256 /* Delta between TQM clock and TSF clock */ 4257 uint32_t delta_tsf; 4258 #endif 4259 #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY 4260 /* Indicate if uplink delay report is enabled or not */ 4261 qdf_atomic_t ul_delay_report; 4262 /* accumulative delay for every TX completion */ 4263 qdf_atomic_t ul_delay_accum; 4264 /* accumulative number of packets delay has accumulated */ 4265 qdf_atomic_t ul_pkts_accum; 4266 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */ 4267 4268 /* vdev_stats_id - ID used for stats collection by FW from HW*/ 4269 uint8_t vdev_stats_id; 4270 #ifdef HW_TX_DELAY_STATS_ENABLE 4271 /* hw tx delay stats enable */ 4272 uint8_t hw_tx_delay_stats_enabled; 4273 #endif 4274 #ifdef DP_RX_UDP_OVER_PEER_ROAM 4275 uint32_t roaming_peer_status; 4276 union dp_align_mac_addr roaming_peer_mac; 4277 #endif 4278 #ifdef DP_TRAFFIC_END_INDICATION 4279 /* per vdev feature enable/disable status */ 4280 bool traffic_end_ind_en; 4281 /* per vdev nbuf queue for traffic end indication packets */ 4282 qdf_nbuf_queue_t end_ind_pkt_q; 4283 #endif 4284 #ifdef FEATURE_DIRECT_LINK 4285 /* Flag to indicate if to_fw should be set for tx pkts on this vdev */ 4286 bool to_fw; 4287 #endif 4288 /* QDF VDEV operating mode */ 4289 enum QDF_OPMODE qdf_opmode; 4290 4291 #ifdef WLAN_TX_PKT_CAPTURE_ENH 4292 /* TX capture feature to over ride return buffer manager */ 4293 bool is_override_rbm_id; 4294 /* Return buffer manager ID */ 4295 uint8_t rbm_id; 4296 #endif 4297 4298 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 4299 /* configuration for tx latency stats */ 4300 struct dp_tx_latency_config tx_latency_cfg; 4301 #endif 4302 }; 4303 4304 enum { 4305 dp_sec_mcast = 0, 4306 dp_sec_ucast 4307 }; 4308 4309 #ifdef WDS_VENDOR_EXTENSION 4310 typedef struct { 4311 uint8_t wds_tx_mcast_4addr:1, 4312 wds_tx_ucast_4addr:1, 4313 wds_rx_filter:1, /* enforce rx filter */ 4314 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 4315 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 4316 4317 } dp_ecm_policy; 4318 #endif 4319 4320 /** 4321 * struct dp_peer_cached_bufq - cached_bufq to enqueue rx packets 4322 * @cached_bufq: nbuff list to enqueue rx packets 4323 * @bufq_lock: spinlock for nbuff list access 4324 * @thresh: maximum threshold for number of rx buff to enqueue 4325 * @entries: number of entries 4326 * @dropped: number of packets dropped 4327 */ 4328 struct dp_peer_cached_bufq { 4329 qdf_list_t cached_bufq; 4330 qdf_spinlock_t bufq_lock; 4331 uint32_t thresh; 4332 uint32_t entries; 4333 uint32_t dropped; 4334 }; 4335 4336 /** 4337 * enum dp_peer_ast_flowq 4338 * @DP_PEER_AST_FLOWQ_HI_PRIO: Hi Priority flow queue 4339 * @DP_PEER_AST_FLOWQ_LOW_PRIO: Low priority flow queue 4340 * @DP_PEER_AST_FLOWQ_UDP: flow queue type is UDP 4341 * @DP_PEER_AST_FLOWQ_NON_UDP: flow queue type is Non UDP 4342 * @DP_PEER_AST_FLOWQ_MAX: max value 4343 */ 4344 enum dp_peer_ast_flowq { 4345 DP_PEER_AST_FLOWQ_HI_PRIO, 4346 DP_PEER_AST_FLOWQ_LOW_PRIO, 4347 DP_PEER_AST_FLOWQ_UDP, 4348 DP_PEER_AST_FLOWQ_NON_UDP, 4349 DP_PEER_AST_FLOWQ_MAX, 4350 }; 4351 4352 /** 4353 * struct dp_ast_flow_override_info - ast override info 4354 * @ast_idx: ast indexes in peer map message 4355 * @ast_valid_mask: ast valid mask for each ast index 4356 * @ast_flow_mask: ast flow mask for each ast index 4357 * @tid_valid_low_pri_mask: per tid mask for low priority flow 4358 * @tid_valid_hi_pri_mask: per tid mask for hi priority flow 4359 */ 4360 struct dp_ast_flow_override_info { 4361 uint16_t ast_idx[DP_PEER_AST_FLOWQ_MAX]; 4362 uint8_t ast_valid_mask; 4363 uint8_t ast_flow_mask[DP_PEER_AST_FLOWQ_MAX]; 4364 uint8_t tid_valid_low_pri_mask; 4365 uint8_t tid_valid_hi_pri_mask; 4366 }; 4367 4368 #if defined(WLAN_FEATURE_11BE_MLO) && defined(DP_MLO_LINK_STATS_SUPPORT) 4369 /** 4370 * struct dp_peer_ext_evt_info - peer extended event info 4371 * @peer_id: peer_id from firmware 4372 * @vdev_id: vdev ID 4373 * @link_id: Link ID 4374 * @link_id_valid: link_id_valid 4375 * @peer_mac_addr: mac address of the peer 4376 */ 4377 struct dp_peer_ext_evt_info { 4378 uint16_t peer_id; 4379 uint8_t vdev_id; 4380 uint8_t link_id; 4381 bool link_id_valid; 4382 uint8_t *peer_mac_addr; 4383 }; 4384 #endif 4385 4386 /** 4387 * struct dp_peer_ast_params - ast parameters for a msdu flow-queue 4388 * @ast_idx: ast index populated by FW 4389 * @is_valid: ast flow valid mask 4390 * @valid_tid_mask: per tid mask for this ast index 4391 * @flowQ: flow queue id associated with this ast index 4392 */ 4393 struct dp_peer_ast_params { 4394 uint16_t ast_idx; 4395 uint8_t is_valid; 4396 uint8_t valid_tid_mask; 4397 uint8_t flowQ; 4398 }; 4399 4400 #define DP_MLO_FLOW_INFO_MAX 3 4401 4402 /** 4403 * struct dp_mlo_flow_override_info - Flow override info 4404 * @ast_idx: Primary TCL AST Index 4405 * @ast_idx_valid: Is AST index valid 4406 * @chip_id: CHIP ID 4407 * @tidmask: tidmask 4408 * @cache_set_num: Cache set number 4409 */ 4410 struct dp_mlo_flow_override_info { 4411 uint16_t ast_idx; 4412 uint8_t ast_idx_valid; 4413 uint8_t chip_id; 4414 uint8_t tidmask; 4415 uint8_t cache_set_num; 4416 }; 4417 4418 /** 4419 * struct dp_mlo_link_info - Link info 4420 * @peer_chip_id: Peer Chip ID 4421 * @vdev_id: Vdev ID 4422 */ 4423 struct dp_mlo_link_info { 4424 uint8_t peer_chip_id; 4425 uint8_t vdev_id; 4426 }; 4427 4428 #ifdef WLAN_SUPPORT_MSCS 4429 /*MSCS Procedure based macros */ 4430 #define IEEE80211_MSCS_MAX_ELEM_SIZE 5 4431 #define IEEE80211_TCLAS_MASK_CLA_TYPE_4 4 4432 /** 4433 * struct dp_peer_mscs_parameter - MSCS database obtained from 4434 * MSCS Request and Response in the control path. This data is used 4435 * by the AP to find out what priority to set based on the tuple 4436 * classification during packet processing. 4437 * @user_priority_bitmap: User priority bitmap obtained during 4438 * handshake 4439 * @user_priority_limit: User priority limit obtained during 4440 * handshake 4441 * @classifier_mask: params to be compared during processing 4442 */ 4443 struct dp_peer_mscs_parameter { 4444 uint8_t user_priority_bitmap; 4445 uint8_t user_priority_limit; 4446 uint8_t classifier_mask; 4447 }; 4448 #endif 4449 4450 #ifdef QCA_SUPPORT_WDS_EXTENDED 4451 #define WDS_EXT_PEER_INIT_BIT 0 4452 4453 /** 4454 * struct dp_wds_ext_peer - wds ext peer structure 4455 * This is used when wds extended feature is enabled 4456 * both compile time and run time. It is created 4457 * when 1st 4 address frame is received from 4458 * wds backhaul. 4459 * @osif_peer: Handle to the OS shim SW's virtual device 4460 * @init: wds ext netdev state 4461 */ 4462 struct dp_wds_ext_peer { 4463 ol_osif_peer_handle osif_peer; 4464 unsigned long init; 4465 }; 4466 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 4467 4468 #ifdef WLAN_SUPPORT_MESH_LATENCY 4469 /*Advanced Mesh latency feature based macros */ 4470 4471 /** 4472 * struct dp_peer_mesh_latency_parameter - Mesh latency related 4473 * parameters. This data is updated per peer per TID based on 4474 * the flow tuple classification in external rule database 4475 * during packet processing. 4476 * @service_interval_dl: Service interval associated with TID in DL 4477 * @burst_size_dl: Burst size additive over multiple flows in DL 4478 * @service_interval_ul: Service interval associated with TID in UL 4479 * @burst_size_ul: Burst size additive over multiple flows in UL 4480 * @ac: custom ac derived from service interval 4481 * @msduq: MSDU queue number within TID 4482 */ 4483 struct dp_peer_mesh_latency_parameter { 4484 uint32_t service_interval_dl; 4485 uint32_t burst_size_dl; 4486 uint32_t service_interval_ul; 4487 uint32_t burst_size_ul; 4488 uint8_t ac; 4489 uint8_t msduq; 4490 }; 4491 #endif 4492 4493 #ifdef WLAN_FEATURE_11BE_MLO 4494 /* Max number of links for MLO connection */ 4495 #define DP_MAX_MLO_LINKS 4 4496 4497 /** 4498 * struct dp_peer_link_info - link peer information for MLO 4499 * @mac_addr: Mac address 4500 * @vdev_id: Vdev ID for current link peer 4501 * @is_valid: flag for link peer info valid or not 4502 * @chip_id: chip id 4503 * @is_bridge_peer: flag to indicate if peer is bridge peer 4504 */ 4505 struct dp_peer_link_info { 4506 union dp_align_mac_addr mac_addr; 4507 uint8_t vdev_id; 4508 uint8_t is_valid; 4509 uint8_t chip_id; 4510 uint8_t is_bridge_peer; 4511 }; 4512 4513 /** 4514 * struct dp_mld_link_peers - this structure is used to get link peers 4515 * pointer from mld peer 4516 * @link_peers: link peers pointer array 4517 * @num_links: number of link peers fetched 4518 */ 4519 struct dp_mld_link_peers { 4520 struct dp_peer *link_peers[DP_MAX_MLO_LINKS]; 4521 uint8_t num_links; 4522 }; 4523 #else 4524 #define DP_MAX_MLO_LINKS 0 4525 #endif 4526 4527 typedef void *dp_txrx_ref_handle; 4528 4529 /** 4530 * struct dp_peer_per_pkt_tx_stats- Peer Tx stats updated in per pkt 4531 * Tx completion path 4532 * @ucast: Unicast Packet Count 4533 * @mcast: Multicast Packet Count 4534 * @bcast: Broadcast Packet Count 4535 * @nawds_mcast: NAWDS Multicast Packet Count 4536 * @tx_success: Successful Tx Packets 4537 * @nawds_mcast_drop: NAWDS Multicast Drop Count 4538 * @ofdma: Total Packets as ofdma 4539 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 4540 * @amsdu_cnt: Number of MSDUs part of AMSDU 4541 * @dropped: Dropped packet statistics 4542 * @dropped.fw_rem: Discarded by firmware 4543 * @dropped.fw_rem_notx: firmware_discard_untransmitted 4544 * @dropped.fw_rem_tx: firmware_discard_transmitted 4545 * @dropped.age_out: aged out in mpdu/msdu queues 4546 * @dropped.fw_reason1: discarded by firmware reason 1 4547 * @dropped.fw_reason2: discarded by firmware reason 2 4548 * @dropped.fw_reason3: discarded by firmware reason 3 4549 * @dropped.fw_rem_no_match: dropped due to fw no match command 4550 * @dropped.drop_threshold: dropped due to HW threshold 4551 * @dropped.drop_link_desc_na: dropped due resource not available in HW 4552 * @dropped.invalid_drop: Invalid msdu drop 4553 * @dropped.mcast_vdev_drop: MCAST drop configured for VDEV in HW 4554 * @dropped.invalid_rr: Invalid TQM release reason 4555 * @failed_retry_count: packets failed due to retry above 802.11 retry limit 4556 * @retry_count: packets successfully send after one or more retry 4557 * @multiple_retry_count: packets successfully sent after more than one retry 4558 * @no_ack_count: no ack pkt count for different protocols 4559 * @tx_success_twt: Successful Tx Packets in TWT session 4560 * @last_tx_ts: last timestamp in jiffies when tx comp occurred 4561 * @avg_sojourn_msdu: Avg sojourn msdu stat 4562 * @protocol_trace_cnt: per-peer protocol counter 4563 * @release_src_not_tqm: Counter to keep track of release source is not TQM 4564 * in TX completion status processing 4565 * @inval_link_id_pkt_cnt: Counter to capture Invalid Link Id 4566 */ 4567 struct dp_peer_per_pkt_tx_stats { 4568 struct cdp_pkt_info ucast; 4569 struct cdp_pkt_info mcast; 4570 struct cdp_pkt_info bcast; 4571 struct cdp_pkt_info nawds_mcast; 4572 struct cdp_pkt_info tx_success; 4573 uint32_t nawds_mcast_drop; 4574 uint32_t ofdma; 4575 uint32_t non_amsdu_cnt; 4576 uint32_t amsdu_cnt; 4577 struct { 4578 struct cdp_pkt_info fw_rem; 4579 uint32_t fw_rem_notx; 4580 uint32_t fw_rem_tx; 4581 uint32_t age_out; 4582 uint32_t fw_reason1; 4583 uint32_t fw_reason2; 4584 uint32_t fw_reason3; 4585 uint32_t fw_rem_queue_disable; 4586 uint32_t fw_rem_no_match; 4587 uint32_t drop_threshold; 4588 uint32_t drop_link_desc_na; 4589 uint32_t invalid_drop; 4590 uint32_t mcast_vdev_drop; 4591 uint32_t invalid_rr; 4592 } dropped; 4593 uint32_t failed_retry_count; 4594 uint32_t retry_count; 4595 uint32_t multiple_retry_count; 4596 uint32_t no_ack_count[QDF_PROTO_SUBTYPE_MAX]; 4597 struct cdp_pkt_info tx_success_twt; 4598 unsigned long last_tx_ts; 4599 qdf_ewma_tx_lag avg_sojourn_msdu[CDP_DATA_TID_MAX]; 4600 #ifdef VDEV_PEER_PROTOCOL_COUNT 4601 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 4602 #endif 4603 uint32_t release_src_not_tqm; 4604 uint32_t inval_link_id_pkt_cnt; 4605 }; 4606 4607 /** 4608 * struct dp_peer_extd_tx_stats - Peer Tx stats updated in either 4609 * per pkt Tx completion path when macro QCA_ENHANCED_STATS_SUPPORT is 4610 * disabled or in HTT Tx PPDU completion path when macro is enabled 4611 * @stbc: Packets in STBC 4612 * @ldpc: Packets in LDPC 4613 * @retries: Packet retries 4614 * @pkt_type: pkt count for different .11 modes 4615 * @wme_ac_type: Wireless Multimedia type Count 4616 * @excess_retries_per_ac: Wireless Multimedia type Count 4617 * @ampdu_cnt: completion of aggregation 4618 * @non_ampdu_cnt: tx completion not aggregated 4619 * @num_ppdu_cookie_valid: no. of valid ppdu cookies rcvd from FW 4620 * @tx_ppdus: ppdus in tx 4621 * @tx_mpdus_success: mpdus successful in tx 4622 * @tx_mpdus_tried: mpdus tried in tx 4623 * @tx_rate: Tx Rate in kbps 4624 * @last_tx_rate: Last tx rate for unicast packets 4625 * @last_tx_rate_mcs: Tx rate mcs for unicast packets 4626 * @mcast_last_tx_rate: Last tx rate for multicast packets 4627 * @mcast_last_tx_rate_mcs: Last tx rate mcs for multicast 4628 * @rnd_avg_tx_rate: Rounded average tx rate 4629 * @avg_tx_rate: Average TX rate 4630 * @tx_ratecode: Tx rate code of last frame 4631 * @pream_punct_cnt: Preamble Punctured count 4632 * @sgi_count: SGI count 4633 * @nss: Packet count for different num_spatial_stream values 4634 * @bw: Packet Count for different bandwidths 4635 * @ru_start: RU start index 4636 * @ru_tones: RU tones size 4637 * @ru_loc: pkt info for RU location 26/ 52/ 106/ 242/ 484 counter 4638 * @transmit_type: pkt info for tx transmit type 4639 * @mu_group_id: mumimo mu group id 4640 * @last_ack_rssi: RSSI of last acked packet 4641 * @nss_info: NSS 1,2, ...8 4642 * @mcs_info: MCS index 4643 * @bw_info: Bandwidth 4644 * <enum 0 bw_20_MHz> 4645 * <enum 1 bw_40_MHz> 4646 * <enum 2 bw_80_MHz> 4647 * <enum 3 bw_160_MHz> 4648 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 4649 * <enum 1 0_4_us_sgi > Legacy short GI 4650 * <enum 2 1_6_us_sgi > HE related GI 4651 * <enum 3 3_2_us_sgi > HE 4652 * @preamble_info: preamble 4653 * @tx_ucast_total: total ucast count 4654 * @tx_ucast_success: total ucast success count 4655 * @retries_mpdu: mpdu number of successfully transmitted after retries 4656 * @mpdu_success_with_retries: mpdu retry count in case of successful tx 4657 * @su_be_ppdu_cnt: SU Tx packet count for 11BE 4658 * @mu_be_ppdu_cnt: MU Tx packet count for 11BE 4659 * @punc_bw: MSDU count for punctured bw 4660 * @rts_success: RTS success count 4661 * @rts_failure: RTS failure count 4662 * @bar_cnt: Block ACK Request frame count 4663 * @ndpa_cnt: NDP announcement frame count 4664 * @rssi_chain: rssi chain 4665 * @wme_ac_type_bytes: Wireless Multimedia bytes Count 4666 */ 4667 struct dp_peer_extd_tx_stats { 4668 uint32_t stbc; 4669 uint32_t ldpc; 4670 uint32_t retries; 4671 struct cdp_pkt_type pkt_type[DOT11_MAX]; 4672 uint32_t wme_ac_type[WME_AC_MAX]; 4673 uint32_t excess_retries_per_ac[WME_AC_MAX]; 4674 uint32_t ampdu_cnt; 4675 uint32_t non_ampdu_cnt; 4676 uint32_t num_ppdu_cookie_valid; 4677 uint32_t tx_ppdus; 4678 uint32_t tx_mpdus_success; 4679 uint32_t tx_mpdus_tried; 4680 4681 uint32_t tx_rate; 4682 uint32_t last_tx_rate; 4683 uint32_t last_tx_rate_mcs; 4684 uint32_t mcast_last_tx_rate; 4685 uint32_t mcast_last_tx_rate_mcs; 4686 uint64_t rnd_avg_tx_rate; 4687 uint64_t avg_tx_rate; 4688 uint16_t tx_ratecode; 4689 4690 uint32_t sgi_count[MAX_GI]; 4691 uint32_t pream_punct_cnt; 4692 uint32_t nss[SS_COUNT]; 4693 uint32_t bw[MAX_BW]; 4694 uint32_t ru_start; 4695 uint32_t ru_tones; 4696 struct cdp_tx_pkt_info ru_loc[MAX_RU_LOCATIONS]; 4697 4698 struct cdp_tx_pkt_info transmit_type[MAX_TRANSMIT_TYPES]; 4699 uint32_t mu_group_id[MAX_MU_GROUP_ID]; 4700 4701 uint32_t last_ack_rssi; 4702 4703 uint32_t nss_info:4, 4704 mcs_info:4, 4705 bw_info:4, 4706 gi_info:4, 4707 preamble_info:4; 4708 4709 uint32_t retries_mpdu; 4710 uint32_t mpdu_success_with_retries; 4711 struct cdp_pkt_info tx_ucast_total; 4712 struct cdp_pkt_info tx_ucast_success; 4713 #ifdef WLAN_FEATURE_11BE 4714 struct cdp_pkt_type su_be_ppdu_cnt; 4715 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 4716 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 4717 #endif 4718 uint32_t rts_success; 4719 uint32_t rts_failure; 4720 uint32_t bar_cnt; 4721 uint32_t ndpa_cnt; 4722 int32_t rssi_chain[CDP_RSSI_CHAIN_LEN]; 4723 uint64_t wme_ac_type_bytes[WME_AC_MAX]; 4724 }; 4725 4726 /** 4727 * struct dp_peer_per_pkt_rx_stats - Peer Rx stats updated in per pkt Rx path 4728 * @rcvd_reo: Packets received on the reo ring 4729 * @rx_lmac: Packets received on each lmac 4730 * @unicast: Total unicast packets 4731 * @multicast: Total multicast packets 4732 * @bcast: Broadcast Packet Count 4733 * @raw: Raw Pakets received 4734 * @nawds_mcast_drop: Total NAWDS multicast packets dropped 4735 * @mec_drop: Total MEC packets dropped 4736 * @ppeds_drop: Total DS packets dropped 4737 * @last_rx_ts: last timestamp in jiffies when RX happened 4738 * @intra_bss: Intra BSS statistics 4739 * @intra_bss.pkts: Intra BSS packets received 4740 * @intra_bss.fail: Intra BSS packets failed 4741 * @intra_bss.mdns_no_fws: Intra BSS MDNS packets not forwarded 4742 * @err: error counters 4743 * @err.mic_err: Rx MIC errors CCMP 4744 * @err.decrypt_err: Rx Decryption Errors CRC 4745 * @err.fcserr: rx MIC check failed (CCMP) 4746 * @err.pn_err: pn check failed 4747 * @err.oor_err: Rx OOR errors 4748 * @err.jump_2k_err: 2k jump errors 4749 * @err.rxdma_wifi_parse_err: rxdma wifi parse errors 4750 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 4751 * @amsdu_cnt: Number of MSDUs part of AMSDU 4752 * @rx_retries: retries of packet in rx 4753 * @multipass_rx_pkt_drop: Dropped multipass rx pkt 4754 * @peer_unauth_rx_pkt_drop: Unauth rx packet drops 4755 * @policy_check_drop: policy check drops 4756 * @to_stack_twt: Total packets sent up the stack in TWT session 4757 * @rx_success: Total RX success count 4758 * @protocol_trace_cnt: per-peer protocol counters 4759 * @mcast_3addr_drop: 4760 * @rx_total: total rx count 4761 * @inval_link_id_pkt_cnt: Counter to capture Invalid Link Id 4762 */ 4763 struct dp_peer_per_pkt_rx_stats { 4764 struct cdp_pkt_info rcvd_reo[CDP_MAX_RX_RINGS]; 4765 struct cdp_pkt_info rx_lmac[CDP_MAX_LMACS]; 4766 struct cdp_pkt_info unicast; 4767 struct cdp_pkt_info multicast; 4768 struct cdp_pkt_info bcast; 4769 struct cdp_pkt_info raw; 4770 uint32_t nawds_mcast_drop; 4771 struct cdp_pkt_info mec_drop; 4772 struct cdp_pkt_info ppeds_drop; 4773 unsigned long last_rx_ts; 4774 struct { 4775 struct cdp_pkt_info pkts; 4776 struct cdp_pkt_info fail; 4777 uint32_t mdns_no_fwd; 4778 } intra_bss; 4779 struct { 4780 uint32_t mic_err; 4781 uint32_t decrypt_err; 4782 uint32_t fcserr; 4783 uint32_t pn_err; 4784 uint32_t oor_err; 4785 uint32_t jump_2k_err; 4786 uint32_t rxdma_wifi_parse_err; 4787 } err; 4788 uint32_t non_amsdu_cnt; 4789 uint32_t amsdu_cnt; 4790 uint32_t rx_retries; 4791 uint32_t multipass_rx_pkt_drop; 4792 uint32_t peer_unauth_rx_pkt_drop; 4793 uint32_t policy_check_drop; 4794 struct cdp_pkt_info to_stack_twt; 4795 struct cdp_pkt_info rx_success; 4796 #ifdef VDEV_PEER_PROTOCOL_COUNT 4797 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 4798 #endif 4799 uint32_t mcast_3addr_drop; 4800 #ifdef IPA_OFFLOAD 4801 struct cdp_pkt_info rx_total; 4802 #endif 4803 uint32_t inval_link_id_pkt_cnt; 4804 }; 4805 4806 /** 4807 * struct dp_peer_extd_rx_stats - Peer Rx stats updated in either 4808 * per pkt Rx path when macro QCA_ENHANCED_STATS_SUPPORT is disabled or in 4809 * Rx monitor patch when macro is enabled 4810 * @pkt_type: pkt counter for different .11 modes 4811 * @wme_ac_type: Wireless Multimedia type Count 4812 * @mpdu_cnt_fcs_ok: SU Rx success mpdu count 4813 * @mpdu_cnt_fcs_err: SU Rx fail mpdu count 4814 * @non_ampdu_cnt: Number of MSDUs with no MPDU level aggregation 4815 * @ampdu_cnt: Number of MSDUs part of AMSPU 4816 * @rx_mpdus: mpdu in rx 4817 * @rx_ppdus: ppdu in rx 4818 * @su_ax_ppdu_cnt: SU Rx packet count for .11ax 4819 * @rx_mu: Rx MU stats 4820 * @reception_type: Reception type of packets 4821 * @ppdu_cnt: PPDU packet count in reception type 4822 * @sgi_count: sgi count 4823 * @nss: packet count in spatiel Streams 4824 * @ppdu_nss: PPDU packet count in spatial streams 4825 * @bw: Packet Count in different bandwidths 4826 * @rx_mpdu_cnt: rx mpdu count per MCS rate 4827 * @rx_rate: Rx rate 4828 * @last_rx_rate: Previous rx rate 4829 * @rnd_avg_rx_rate: Rounded average rx rate 4830 * @avg_rx_rate: Average Rx rate 4831 * @rx_ratecode: Rx rate code of last frame 4832 * @avg_snr: Average snr 4833 * @rx_snr_measured_time: Time at which snr is measured 4834 * @snr: SNR of received signal 4835 * @last_snr: Previous snr 4836 * @nss_info: NSS 1,2, ...8 4837 * @mcs_info: MCS index 4838 * @bw_info: Bandwidth 4839 * <enum 0 bw_20_MHz> 4840 * <enum 1 bw_40_MHz> 4841 * <enum 2 bw_80_MHz> 4842 * <enum 3 bw_160_MHz> 4843 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 4844 * <enum 1 0_4_us_sgi > Legacy short GI 4845 * <enum 2 1_6_us_sgi > HE related GI 4846 * <enum 3 3_2_us_sgi > HE 4847 * @preamble_info: preamble 4848 * @mpdu_retry_cnt: retries of mpdu in rx 4849 * @su_be_ppdu_cnt: SU Rx packet count for BE 4850 * @mu_be_ppdu_cnt: MU rx packet count for BE 4851 * @punc_bw: MSDU count for punctured bw 4852 * @bar_cnt: Block ACK Request frame count 4853 * @ndpa_cnt: NDP announcement frame count 4854 * @wme_ac_type_bytes: Wireless Multimedia type Bytes Count 4855 */ 4856 struct dp_peer_extd_rx_stats { 4857 struct cdp_pkt_type pkt_type[DOT11_MAX]; 4858 uint32_t wme_ac_type[WME_AC_MAX]; 4859 uint32_t mpdu_cnt_fcs_ok; 4860 uint32_t mpdu_cnt_fcs_err; 4861 uint32_t non_ampdu_cnt; 4862 uint32_t ampdu_cnt; 4863 uint32_t rx_mpdus; 4864 uint32_t rx_ppdus; 4865 4866 struct cdp_pkt_type su_ax_ppdu_cnt; 4867 struct cdp_rx_mu rx_mu[TXRX_TYPE_MU_MAX]; 4868 uint32_t reception_type[MAX_RECEPTION_TYPES]; 4869 uint32_t ppdu_cnt[MAX_RECEPTION_TYPES]; 4870 4871 uint32_t sgi_count[MAX_GI]; 4872 uint32_t nss[SS_COUNT]; 4873 uint32_t ppdu_nss[SS_COUNT]; 4874 uint32_t bw[MAX_BW]; 4875 uint32_t rx_mpdu_cnt[MAX_MCS]; 4876 4877 uint32_t rx_rate; 4878 uint32_t last_rx_rate; 4879 uint32_t rnd_avg_rx_rate; 4880 uint32_t avg_rx_rate; 4881 uint32_t rx_ratecode; 4882 4883 uint32_t avg_snr; 4884 unsigned long rx_snr_measured_time; 4885 uint8_t snr; 4886 uint8_t last_snr; 4887 4888 uint32_t nss_info:4, 4889 mcs_info:4, 4890 bw_info:4, 4891 gi_info:4, 4892 preamble_info:4; 4893 4894 uint32_t mpdu_retry_cnt; 4895 #ifdef WLAN_FEATURE_11BE 4896 struct cdp_pkt_type su_be_ppdu_cnt; 4897 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 4898 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 4899 #endif 4900 uint32_t bar_cnt; 4901 uint32_t ndpa_cnt; 4902 uint64_t wme_ac_type_bytes[WME_AC_MAX]; 4903 }; 4904 4905 /** 4906 * struct dp_peer_per_pkt_stats - Per pkt stats for peer 4907 * @tx: Per pkt Tx stats 4908 * @rx: Per pkt Rx stats 4909 */ 4910 struct dp_peer_per_pkt_stats { 4911 struct dp_peer_per_pkt_tx_stats tx; 4912 struct dp_peer_per_pkt_rx_stats rx; 4913 }; 4914 4915 /** 4916 * struct dp_peer_extd_stats - Stats from extended path for peer 4917 * @tx: Extended path tx stats 4918 * @rx: Extended path rx stats 4919 */ 4920 struct dp_peer_extd_stats { 4921 struct dp_peer_extd_tx_stats tx; 4922 struct dp_peer_extd_rx_stats rx; 4923 }; 4924 4925 /** 4926 * struct dp_peer_stats - Peer stats 4927 * @per_pkt_stats: Per packet path stats 4928 * @extd_stats: Extended path stats 4929 * @tx_latency: transmit latency stats 4930 */ 4931 struct dp_peer_stats { 4932 struct dp_peer_per_pkt_stats per_pkt_stats; 4933 #ifndef QCA_ENHANCED_STATS_SUPPORT 4934 struct dp_peer_extd_stats extd_stats; 4935 #endif 4936 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 4937 struct dp_tx_latency tx_latency; 4938 #endif 4939 }; 4940 4941 /** 4942 * struct dp_local_link_id_peer_map - Mapping table entry for link peer mac 4943 * address to local_link_id 4944 * @in_use: set if this entry is having valid mapping between local_link_id 4945 * and the link peer mac address. 4946 * @local_link_id: local_link_id assigned to the link peer 4947 * @mac_addr: link peer mac address 4948 */ 4949 struct dp_local_link_id_peer_map { 4950 uint8_t in_use; 4951 uint8_t local_link_id; 4952 union dp_align_mac_addr mac_addr; 4953 }; 4954 4955 /** 4956 * struct dp_txrx_peer: DP txrx_peer structure used in per pkt path 4957 * @vdev: VDEV to which this peer is associated 4958 * @peer_id: peer ID for this peer 4959 * @authorize: Set when authorized 4960 * @in_twt: in TWT session 4961 * @hw_txrx_stats_en: Indicate HW offload vdev stats 4962 * @is_mld_peer:1: MLD peer 4963 * @tx_failed: Total Tx failure 4964 * @comp_pkt: Pkt Info for which completions were received 4965 * @to_stack: Total packets sent up the stack 4966 * @delay_stats: Peer delay stats 4967 * @jitter_stats: Peer jitter stats 4968 * @security: Security credentials 4969 * @nawds_enabled: NAWDS flag 4970 * @bss_peer: set for bss peer 4971 * @isolation: enable peer isolation for this peer 4972 * @wds_enabled: WDS peer 4973 * @wds_ecm: 4974 * @flush_in_progress: 4975 * @bufq_info: 4976 * @mpass_peer_list_elem: node in the special peer list element 4977 * @vlan_id: vlan id for key 4978 * @wds_ext: 4979 * @osif_rx: 4980 * @rx_tid: 4981 * @sawf_stats: 4982 * @bw: bandwidth of peer connection 4983 * @mpdu_retry_threshold: MPDU retry threshold to increment tx bad count 4984 * @band: Link ID to band mapping 4985 * @ll_id_peer_map: Mapping table for link peer mac address to local_link_id 4986 * @ll_band: Local link id band mapping 4987 * @stats_arr_size: peer stats array size 4988 * @stats: Peer link and mld statistics 4989 */ 4990 struct dp_txrx_peer { 4991 struct dp_vdev *vdev; 4992 uint16_t peer_id; 4993 uint8_t authorize:1, 4994 in_twt:1, 4995 hw_txrx_stats_en:1, 4996 is_mld_peer:1; 4997 uint32_t tx_failed; 4998 struct cdp_pkt_info comp_pkt; 4999 struct cdp_pkt_info to_stack; 5000 5001 struct dp_peer_delay_stats *delay_stats; 5002 5003 struct cdp_peer_tid_stats *jitter_stats; 5004 5005 struct { 5006 enum cdp_sec_type sec_type; 5007 u_int32_t michael_key[2]; /* relevant for TKIP */ 5008 } security[2]; /* 0 -> multicast, 1 -> unicast */ 5009 5010 uint16_t nawds_enabled:1, 5011 bss_peer:1, 5012 isolation:1, 5013 wds_enabled:1; 5014 #ifdef WDS_VENDOR_EXTENSION 5015 dp_ecm_policy wds_ecm; 5016 #endif 5017 #ifdef PEER_CACHE_RX_PKTS 5018 qdf_atomic_t flush_in_progress; 5019 struct dp_peer_cached_bufq bufq_info; 5020 #endif 5021 #ifdef QCA_MULTIPASS_SUPPORT 5022 TAILQ_ENTRY(dp_txrx_peer) mpass_peer_list_elem; 5023 uint16_t vlan_id; 5024 #endif 5025 #ifdef QCA_SUPPORT_WDS_EXTENDED 5026 struct dp_wds_ext_peer wds_ext; 5027 ol_txrx_rx_fp osif_rx; 5028 #endif 5029 struct dp_rx_tid_defrag rx_tid[DP_MAX_TIDS]; 5030 #ifdef CONFIG_SAWF 5031 struct dp_peer_sawf_stats *sawf_stats; 5032 #endif 5033 #ifdef DP_PEER_EXTENDED_API 5034 enum cdp_peer_bw bw; 5035 uint8_t mpdu_retry_threshold; 5036 #endif 5037 #if defined WLAN_FEATURE_11BE_MLO && defined DP_MLO_LINK_STATS_SUPPORT 5038 /* Link ID to band mapping, (1 MLD + DP_MAX_MLO_LINKS) */ 5039 uint8_t band[DP_MAX_MLO_LINKS + 1]; 5040 5041 struct dp_local_link_id_peer_map ll_id_peer_map[DP_MAX_MLO_LINKS]; 5042 uint8_t ll_band[DP_MAX_MLO_LINKS + 1]; 5043 #endif 5044 uint8_t stats_arr_size; 5045 5046 /* dp_peer_stats should be the last member in the structure */ 5047 struct dp_peer_stats stats[]; 5048 }; 5049 5050 /* Peer structure for data path state */ 5051 struct dp_peer { 5052 struct dp_txrx_peer *txrx_peer; 5053 #ifdef WIFI_MONITOR_SUPPORT 5054 struct dp_mon_peer *monitor_peer; 5055 #endif 5056 /* peer ID for this peer */ 5057 uint16_t peer_id; 5058 5059 /* VDEV to which this peer is associated */ 5060 struct dp_vdev *vdev; 5061 5062 struct dp_ast_entry *self_ast_entry; 5063 5064 qdf_atomic_t ref_cnt; 5065 5066 union dp_align_mac_addr mac_addr; 5067 5068 /* node in the vdev's list of peers */ 5069 TAILQ_ENTRY(dp_peer) peer_list_elem; 5070 /* node in the hash table bin's list of peers */ 5071 TAILQ_ENTRY(dp_peer) hash_list_elem; 5072 5073 /* TID structures pointer */ 5074 struct dp_rx_tid *rx_tid; 5075 5076 /* TBD: No transmit TID state required? */ 5077 5078 struct { 5079 enum cdp_sec_type sec_type; 5080 u_int32_t michael_key[2]; /* relevant for TKIP */ 5081 } security[2]; /* 0 -> multicast, 1 -> unicast */ 5082 5083 /* NAWDS Flag and Bss Peer bit */ 5084 uint16_t bss_peer:1, /* set for bss peer */ 5085 authorize:1, /* Set when authorized */ 5086 valid:1, /* valid bit */ 5087 delete_in_progress:1, /* Indicate kickout sent */ 5088 sta_self_peer:1, /* Indicate STA self peer */ 5089 is_tdls_peer:1; /* Indicate TDLS peer */ 5090 5091 /* MCL specific peer local id */ 5092 uint16_t local_id; 5093 enum ol_txrx_peer_state state; 5094 5095 #ifdef WLAN_FEATURE_11BE_MLO 5096 uint8_t first_link:1, /* first link peer for MLO */ 5097 primary_link:1; /* primary link for MLO */ 5098 #endif 5099 5100 qdf_spinlock_t peer_info_lock; 5101 5102 /* Peer calibrated stats */ 5103 struct cdp_calibr_stats stats; 5104 5105 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 5106 /* TBD */ 5107 5108 /* Active Block ack sessions */ 5109 uint16_t active_ba_session_cnt; 5110 5111 /* Current HW buffersize setting */ 5112 uint16_t hw_buffer_size; 5113 5114 /* 5115 * Flag to check if sessions with 256 buffersize 5116 * should be terminated. 5117 */ 5118 uint8_t kill_256_sessions; 5119 qdf_atomic_t is_default_route_set; 5120 5121 #ifdef QCA_PEER_MULTIQ_SUPPORT 5122 struct dp_peer_ast_params peer_ast_flowq_idx[DP_PEER_AST_FLOWQ_MAX]; 5123 #endif 5124 /* entry to inactive_list*/ 5125 TAILQ_ENTRY(dp_peer) inactive_list_elem; 5126 5127 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 5128 5129 uint8_t peer_state; 5130 qdf_spinlock_t peer_state_lock; 5131 #ifdef WLAN_SUPPORT_MSCS 5132 struct dp_peer_mscs_parameter mscs_ipv4_parameter, mscs_ipv6_parameter; 5133 bool mscs_active; 5134 #endif 5135 #ifdef WLAN_SUPPORT_MESH_LATENCY 5136 struct dp_peer_mesh_latency_parameter mesh_latency_params[DP_MAX_TIDS]; 5137 #endif 5138 #ifdef WLAN_FEATURE_11BE_MLO 5139 /* peer type */ 5140 enum cdp_peer_type peer_type; 5141 /*---------for link peer---------*/ 5142 struct dp_peer *mld_peer; 5143 5144 /*Link ID of link peer*/ 5145 uint8_t link_id; 5146 bool link_id_valid; 5147 uint8_t local_link_id; 5148 5149 /*---------for mld peer----------*/ 5150 struct dp_peer_link_info link_peers[DP_MAX_MLO_LINKS]; 5151 uint8_t num_links; 5152 DP_MUTEX_TYPE link_peers_info_lock; 5153 #ifdef WLAN_FEATURE_11BE_MLO_3_LINK_TX 5154 uint32_t flow_cnt[CDP_DATA_TID_MAX]; 5155 #endif 5156 #endif 5157 #ifdef CONFIG_SAWF_DEF_QUEUES 5158 struct dp_peer_sawf *sawf; 5159 #endif 5160 /* AST hash index for peer in HW */ 5161 uint16_t ast_idx; 5162 5163 /* AST hash value for peer in HW */ 5164 uint16_t ast_hash; 5165 5166 /* Peer Frequency */ 5167 uint32_t freq; 5168 }; 5169 5170 /** 5171 * struct dp_invalid_peer_msg - Invalid peer message 5172 * @nbuf: data buffer 5173 * @wh: 802.11 header 5174 * @vdev_id: id of vdev 5175 */ 5176 struct dp_invalid_peer_msg { 5177 qdf_nbuf_t nbuf; 5178 struct ieee80211_frame *wh; 5179 uint8_t vdev_id; 5180 }; 5181 5182 /** 5183 * struct dp_tx_me_buf_t - ME buffer 5184 * @next: pointer to next buffer 5185 * @data: Destination Mac address 5186 * @paddr_macbuf: physical address for dest_mac 5187 */ 5188 struct dp_tx_me_buf_t { 5189 /* Note: ME buf pool initialization logic expects next pointer to 5190 * be the first element. Dont add anything before next */ 5191 struct dp_tx_me_buf_t *next; 5192 uint8_t data[QDF_MAC_ADDR_SIZE]; 5193 qdf_dma_addr_t paddr_macbuf; 5194 }; 5195 5196 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) || defined(WLAN_SUPPORT_RX_FISA) 5197 struct hal_rx_fst; 5198 #endif /* WLAN_SUPPORT_RX_FLOW_TAG || WLAN_SUPPORT_RX_FISA */ 5199 5200 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 5201 struct dp_rx_fse { 5202 /* HAL Rx Flow Search Entry which matches HW definition */ 5203 void *hal_rx_fse; 5204 /* Toeplitz hash value */ 5205 uint32_t flow_hash; 5206 /* Flow index, equivalent to hash value truncated to FST size */ 5207 uint32_t flow_id; 5208 /* Stats tracking for this flow */ 5209 struct cdp_flow_stats stats; 5210 /* Flag indicating whether flow is IPv4 address tuple */ 5211 uint8_t is_ipv4_addr_entry; 5212 /* Flag indicating whether flow is valid */ 5213 uint8_t is_valid; 5214 }; 5215 5216 struct dp_rx_fst { 5217 /* Software (DP) FST */ 5218 uint8_t *base; 5219 /* Pointer to HAL FST */ 5220 struct hal_rx_fst *hal_rx_fst; 5221 /* Base physical address of HAL RX HW FST */ 5222 uint64_t hal_rx_fst_base_paddr; 5223 /* Maximum number of flows FSE supports */ 5224 uint16_t max_entries; 5225 /* Num entries in flow table */ 5226 uint16_t num_entries; 5227 /* SKID Length */ 5228 uint16_t max_skid_length; 5229 /* Hash mask to obtain legitimate hash entry */ 5230 uint32_t hash_mask; 5231 /* Timer for bundling of flows */ 5232 qdf_timer_t cache_invalidate_timer; 5233 /** 5234 * Flag which tracks whether cache update 5235 * is needed on timer expiry 5236 */ 5237 qdf_atomic_t is_cache_update_pending; 5238 /* Flag to indicate completion of FSE setup in HW/FW */ 5239 bool fse_setup_done; 5240 /* Last ring id used to add a flow */ 5241 uint8_t ring_id; 5242 }; 5243 5244 #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_rx_fse) 5245 5246 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 5247 5248 #ifdef WLAN_FEATURE_STATS_EXT 5249 /** 5250 * struct dp_req_rx_hw_stats_t - RX peer HW stats query structure 5251 * @pending_tid_stats_cnt: pending tid stats count which waits for REO status 5252 * @is_query_timeout: flag to show is stats query timeout 5253 */ 5254 struct dp_req_rx_hw_stats_t { 5255 qdf_atomic_t pending_tid_stats_cnt; 5256 bool is_query_timeout; 5257 }; 5258 #endif 5259 /* soc level structure to declare arch specific ops for DP */ 5260 5261 #ifndef WLAN_SOFTUMAC_SUPPORT 5262 /** 5263 * dp_hw_link_desc_pool_banks_free() - Free h/w link desc pool banks 5264 * @soc: DP SOC handle 5265 * @mac_id: mac id 5266 * 5267 * Return: none 5268 */ 5269 void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, uint32_t mac_id); 5270 5271 /** 5272 * dp_hw_link_desc_pool_banks_alloc() - Allocate h/w link desc pool banks 5273 * @soc: DP SOC handle 5274 * @mac_id: mac id 5275 * 5276 * Allocates memory pages for link descriptors, the page size is 4K for 5277 * MCL and 2MB for WIN. if the mac_id is invalid link descriptor pages are 5278 * allocated for regular RX/TX and if the there is a proper mac_id link 5279 * descriptors are allocated for RX monitor mode. 5280 * 5281 * Return: QDF_STATUS_SUCCESS: Success 5282 * QDF_STATUS_E_FAILURE: Failure 5283 */ 5284 QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, 5285 uint32_t mac_id); 5286 #else 5287 static inline void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, 5288 uint32_t mac_id) 5289 { 5290 } 5291 5292 static inline QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, 5293 uint32_t mac_id) 5294 { 5295 return QDF_STATUS_SUCCESS; 5296 } 5297 #endif 5298 5299 /** 5300 * dp_link_desc_ring_replenish() - Replenish hw link desc rings 5301 * @soc: DP SOC handle 5302 * @mac_id: mac id 5303 * 5304 * Return: None 5305 */ 5306 void dp_link_desc_ring_replenish(struct dp_soc *soc, uint32_t mac_id); 5307 5308 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 5309 void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc); 5310 #else 5311 static inline void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc) {} 5312 #endif 5313 5314 /** 5315 * dp_srng_alloc() - Allocate memory for SRNG 5316 * @soc : Data path soc handle 5317 * @srng : SRNG pointer 5318 * @ring_type : Ring Type 5319 * @num_entries: Number of entries 5320 * @cached: cached flag variable 5321 * 5322 * Return: QDF_STATUS 5323 */ 5324 QDF_STATUS dp_srng_alloc(struct dp_soc *soc, struct dp_srng *srng, 5325 int ring_type, uint32_t num_entries, 5326 bool cached); 5327 5328 /** 5329 * dp_srng_free() - Free SRNG memory 5330 * @soc: Data path soc handle 5331 * @srng: SRNG pointer 5332 * 5333 * Return: None 5334 */ 5335 void dp_srng_free(struct dp_soc *soc, struct dp_srng *srng); 5336 5337 /** 5338 * dp_srng_init() - Initialize SRNG 5339 * @soc : Data path soc handle 5340 * @srng : SRNG pointer 5341 * @ring_type : Ring Type 5342 * @ring_num: Ring number 5343 * @mac_id: mac_id 5344 * 5345 * Return: QDF_STATUS 5346 */ 5347 QDF_STATUS dp_srng_init(struct dp_soc *soc, struct dp_srng *srng, 5348 int ring_type, int ring_num, int mac_id); 5349 5350 /** 5351 * dp_srng_init_idx() - Initialize SRNG 5352 * @soc : Data path soc handle 5353 * @srng : SRNG pointer 5354 * @ring_type : Ring Type 5355 * @ring_num: Ring number 5356 * @mac_id: mac_id 5357 * @idx: ring index 5358 * 5359 * Return: QDF_STATUS 5360 */ 5361 QDF_STATUS dp_srng_init_idx(struct dp_soc *soc, struct dp_srng *srng, 5362 int ring_type, int ring_num, int mac_id, 5363 uint32_t idx); 5364 5365 /** 5366 * dp_srng_deinit() - Internal function to deinit SRNG rings used by data path 5367 * @soc: DP SOC handle 5368 * @srng: source ring structure 5369 * @ring_type: type of ring 5370 * @ring_num: ring number 5371 * 5372 * Return: None 5373 */ 5374 void dp_srng_deinit(struct dp_soc *soc, struct dp_srng *srng, 5375 int ring_type, int ring_num); 5376 5377 void dp_print_peer_txrx_stats_be(struct cdp_peer_stats *peer_stats, 5378 enum peer_stats_type stats_type); 5379 void dp_print_peer_txrx_stats_li(struct cdp_peer_stats *peer_stats, 5380 enum peer_stats_type stats_type); 5381 5382 void dp_print_peer_txrx_stats_rh(struct cdp_peer_stats *peer_stats, 5383 enum peer_stats_type stats_type); 5384 5385 /** 5386 * dp_should_timer_irq_yield() - Decide if the bottom half should yield 5387 * @soc: DP soc handle 5388 * @work_done: work done in softirq context 5389 * @start_time: start time for the softirq 5390 * 5391 * Return: enum with yield code 5392 */ 5393 enum timer_yield_status 5394 dp_should_timer_irq_yield(struct dp_soc *soc, uint32_t work_done, 5395 uint64_t start_time); 5396 5397 /** 5398 * dp_vdev_get_default_reo_hash() - get reo dest ring and hash values for a vdev 5399 * @vdev: Datapath VDEV handle 5400 * @reo_dest: pointer to default reo_dest ring for vdev to be populated 5401 * @hash_based: pointer to hash value (enabled/disabled) to be populated 5402 * 5403 * Return: None 5404 */ 5405 void dp_vdev_get_default_reo_hash(struct dp_vdev *vdev, 5406 enum cdp_host_reo_dest_ring *reo_dest, 5407 bool *hash_based); 5408 5409 /** 5410 * dp_reo_remap_config() - configure reo remap register value based 5411 * nss configuration. 5412 * @soc: DP soc handle 5413 * @remap0: output parameter indicates reo remap 0 register value 5414 * @remap1: output parameter indicates reo remap 1 register value 5415 * @remap2: output parameter indicates reo remap 2 register value 5416 * 5417 * based on offload_radio value below remap configuration 5418 * get applied. 5419 * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4) 5420 * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4) 5421 * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4) 5422 * 3 - both Radios handled by NSS (remap not required) 5423 * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3) 5424 * 5425 * Return: bool type, true if remap is configured else false. 5426 */ 5427 5428 bool dp_reo_remap_config(struct dp_soc *soc, uint32_t *remap0, 5429 uint32_t *remap1, uint32_t *remap2); 5430 5431 #ifdef QCA_DP_TX_HW_SW_NBUF_DESC_PREFETCH 5432 /** 5433 * dp_tx_comp_get_prefetched_params_from_hal_desc() - Get prefetched TX desc 5434 * @soc: DP soc handle 5435 * @tx_comp_hal_desc: HAL TX Comp Descriptor 5436 * @r_tx_desc: SW Tx Descriptor retrieved from HAL desc. 5437 * 5438 * Return: None 5439 */ 5440 void dp_tx_comp_get_prefetched_params_from_hal_desc( 5441 struct dp_soc *soc, 5442 void *tx_comp_hal_desc, 5443 struct dp_tx_desc_s **r_tx_desc); 5444 #endif 5445 #endif /* _DP_TYPES_H_ */ 5446