1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DP_TYPES_H_ 20 #define _DP_TYPES_H_ 21 22 #include <qdf_types.h> 23 #include <qdf_nbuf.h> 24 #include <qdf_lock.h> 25 #include <qdf_atomic.h> 26 #include <qdf_util.h> 27 #include <qdf_list.h> 28 #include <qdf_lro.h> 29 #include <queue.h> 30 #include <htt_common.h> 31 32 #include <cdp_txrx_cmn.h> 33 #ifdef CONFIG_MCL 34 #include <cds_ieee80211_common.h> 35 #else 36 #include <linux/ieee80211.h> 37 #endif 38 39 #ifndef CONFIG_WIN 40 #include <wdi_event_api.h> /* WDI subscriber event list */ 41 #endif 42 43 #include <hal_tx.h> 44 #include <hal_reo.h> 45 #include "wlan_cfg.h" 46 #include "hal_rx.h" 47 #include <hal_api.h> 48 #include <hal_api_mon.h> 49 #include "hal_rx.h" 50 51 #define MAX_BW 7 52 #define MAX_RETRIES 4 53 #define MAX_RECEPTION_TYPES 4 54 55 #ifndef REMOVE_PKT_LOG 56 #include <pktlog.h> 57 #endif 58 59 #define REPT_MU_MIMO 1 60 #define REPT_MU_OFDMA_MIMO 3 61 #define DP_VO_TID 6 62 63 #define DP_MAX_INTERRUPT_CONTEXTS 8 64 #define DP_MAX_TID_MAPS 16 /* MAX TID MAPS AVAILABLE PER PDEV*/ 65 #define DSCP_TID_MAP_MAX (64) 66 #define DP_IP_DSCP_SHIFT 2 67 #define DP_IP_DSCP_MASK 0x3f 68 #define DP_FC0_SUBTYPE_QOS 0x80 69 #define DP_QOS_TID 0x0f 70 #define DP_IPV6_PRIORITY_SHIFT 20 71 #define MAX_MON_LINK_DESC_BANKS 2 72 73 #if defined(CONFIG_MCL) 74 #define MAX_PDEV_CNT 1 75 #else 76 #define MAX_PDEV_CNT 3 77 #endif 78 79 #define MAX_LINK_DESC_BANKS 8 80 #define MAX_TXDESC_POOLS 4 81 #define MAX_RXDESC_POOLS 4 82 #define MAX_REO_DEST_RINGS 4 83 #define MAX_TCL_DATA_RINGS 4 84 #define MAX_IDLE_SCATTER_BUFS 16 85 #define DP_MAX_IRQ_PER_CONTEXT 12 86 #define DP_MAX_INTERRUPT_CONTEXTS 8 87 #define DEFAULT_HW_PEER_ID 0xffff 88 89 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 90 91 #define DP_MAX_INTERRUPT_CONTEXTS 8 92 93 #ifndef REMOVE_PKT_LOG 94 enum rx_pktlog_mode { 95 DP_RX_PKTLOG_DISABLED = 0, 96 DP_RX_PKTLOG_FULL, 97 DP_RX_PKTLOG_LITE, 98 }; 99 #endif 100 101 struct dp_soc_cmn; 102 struct dp_pdev; 103 struct dp_vdev; 104 struct dp_tx_desc_s; 105 struct dp_soc; 106 union dp_rx_desc_list_elem_t; 107 108 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 109 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 110 111 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 112 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 113 114 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 115 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 116 117 #define DP_MUTEX_TYPE qdf_spinlock_t 118 119 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 120 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 121 122 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 123 ((_a)[0] == 0x33 && \ 124 (_a)[1] == 0x33) 125 126 #define DP_FRAME_IS_BROADCAST(_a) \ 127 ((_a)[0] == 0xff && \ 128 (_a)[1] == 0xff && \ 129 (_a)[2] == 0xff && \ 130 (_a)[3] == 0xff && \ 131 (_a)[4] == 0xff && \ 132 (_a)[5] == 0xff) 133 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 134 (_llc)->llc_ssap == 0xaa && \ 135 (_llc)->llc_un.type_snap.control == 0x3) 136 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 137 #define DP_FRAME_FC0_TYPE_MASK 0x0c 138 #define DP_FRAME_FC0_TYPE_DATA 0x08 139 #define DP_FRAME_IS_DATA(_frame) \ 140 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 141 142 /** 143 * macros to convert hw mac id to sw mac id: 144 * mac ids used by hardware start from a value of 1 while 145 * those in host software start from a value of 0. Use the 146 * macros below to convert between mac ids used by software and 147 * hardware 148 */ 149 #define DP_SW2HW_MACID(id) ((id) + 1) 150 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 151 #define DP_MAC_ADDR_LEN 6 152 153 /** 154 * enum dp_intr_mode 155 * @DP_INTR_LEGACY: Legacy/Line interrupts, for WIN 156 * @DP_INTR_MSI: MSI interrupts, for MCL 157 * @DP_INTR_POLL: Polling 158 */ 159 enum dp_intr_mode { 160 DP_INTR_LEGACY = 0, 161 DP_INTR_MSI, 162 DP_INTR_POLL, 163 }; 164 165 /** 166 * enum dp_tx_frm_type 167 * @dp_tx_frm_std: Regular frame, no added header fragments 168 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 169 * @dp_tx_frm_sg: SG segment 170 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 171 * @dp_tx_frm_me: Multicast to Unicast Converted frame 172 * @dp_tx_frm_raw: Raw Frame 173 */ 174 enum dp_tx_frm_type { 175 dp_tx_frm_std = 0, 176 dp_tx_frm_tso, 177 dp_tx_frm_sg, 178 dp_tx_frm_audio, 179 dp_tx_frm_me, 180 dp_tx_frm_raw, 181 }; 182 183 /** 184 * enum dp_ast_type 185 * @dp_ast_type_wds: WDS peer AST type 186 * @dp_ast_type_static: static ast entry type 187 * @dp_ast_type_mec: Multicast echo ast entry type 188 */ 189 enum dp_ast_type { 190 dp_ast_type_wds = 0, 191 dp_ast_type_static, 192 dp_ast_type_mec, 193 }; 194 195 /** 196 * enum dp_nss_cfg 197 * @dp_nss_cfg_default: No radios are offloaded 198 * @dp_nss_cfg_first_radio: First radio offloaded 199 * @dp_nss_cfg_second_radio: Second radio offloaded 200 * @dp_nss_cfg_dbdc: Dual radios offloaded 201 */ 202 enum dp_nss_cfg { 203 dp_nss_cfg_default, 204 dp_nss_cfg_first_radio, 205 dp_nss_cfg_second_radio, 206 dp_nss_cfg_dbdc, 207 }; 208 209 /** 210 * struct rx_desc_pool 211 * @pool_size: number of RX descriptor in the pool 212 * @array: pointer to array of RX descriptor 213 * @freelist: pointer to free RX descriptor link list 214 * @lock: Protection for the RX descriptor pool 215 * @owner: owner for nbuf 216 */ 217 struct rx_desc_pool { 218 uint32_t pool_size; 219 union dp_rx_desc_list_elem_t *array; 220 union dp_rx_desc_list_elem_t *freelist; 221 qdf_spinlock_t lock; 222 uint8_t owner; 223 }; 224 225 /** 226 * struct dp_tx_ext_desc_elem_s 227 * @next: next extension descriptor pointer 228 * @vaddr: hlos virtual address pointer 229 * @paddr: physical address pointer for descriptor 230 */ 231 struct dp_tx_ext_desc_elem_s { 232 struct dp_tx_ext_desc_elem_s *next; 233 void *vaddr; 234 qdf_dma_addr_t paddr; 235 }; 236 237 /** 238 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 239 * @elem_count: Number of descriptors in the pool 240 * @elem_size: Size of each descriptor 241 * @num_free: Number of free descriptors 242 * @msdu_ext_desc: MSDU extension descriptor 243 * @desc_pages: multiple page allocation information for actual descriptors 244 * @link_elem_size: size of the link descriptor in cacheable memory used for 245 * chaining the extension descriptors 246 * @desc_link_pages: multiple page allocation information for link descriptors 247 */ 248 struct dp_tx_ext_desc_pool_s { 249 uint16_t elem_count; 250 int elem_size; 251 uint16_t num_free; 252 struct qdf_mem_multi_page_t desc_pages; 253 int link_elem_size; 254 struct qdf_mem_multi_page_t desc_link_pages; 255 struct dp_tx_ext_desc_elem_s *freelist; 256 qdf_spinlock_t lock; 257 qdf_dma_mem_context(memctx); 258 }; 259 260 /** 261 * struct dp_tx_desc_s - Tx Descriptor 262 * @next: Next in the chain of descriptors in freelist or in the completion list 263 * @nbuf: Buffer Address 264 * @msdu_ext_desc: MSDU extension descriptor 265 * @id: Descriptor ID 266 * @vdev: vdev over which the packet was transmitted 267 * @pdev: Handle to pdev 268 * @pool_id: Pool ID - used when releasing the descriptor 269 * @flags: Flags to track the state of descriptor and special frame handling 270 * @comp: Pool ID - used when releasing the descriptor 271 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 272 * This is maintained in descriptor to allow more efficient 273 * processing in completion event processing code. 274 * This field is filled in with the htt_pkt_type enum. 275 * @frm_type: Frame Type - ToDo check if this is redundant 276 * @pkt_offset: Offset from which the actual packet data starts 277 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 278 * Tx completion of ME packet 279 * @pool: handle to flow_pool this descriptor belongs to. 280 */ 281 struct dp_tx_desc_s { 282 struct dp_tx_desc_s *next; 283 qdf_nbuf_t nbuf; 284 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 285 uint32_t id; 286 struct dp_vdev *vdev; 287 struct dp_pdev *pdev; 288 uint8_t pool_id; 289 uint16_t flags; 290 struct hal_tx_desc_comp_s comp; 291 uint16_t tx_encap_type; 292 uint8_t frm_type; 293 uint8_t pkt_offset; 294 void *me_buffer; 295 void *tso_desc; 296 void *tso_num_desc; 297 }; 298 299 /** 300 * enum flow_pool_status - flow pool status 301 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 302 * and network queues are unpaused 303 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 304 * and network queues are paused 305 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 306 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 307 */ 308 enum flow_pool_status { 309 FLOW_POOL_ACTIVE_UNPAUSED = 0, 310 FLOW_POOL_ACTIVE_PAUSED = 1, 311 FLOW_POOL_INVALID = 2, 312 FLOW_POOL_INACTIVE = 3, 313 }; 314 315 /** 316 * struct dp_tx_tso_seg_pool_s 317 * @pool_size: total number of pool elements 318 * @num_free: free element count 319 * @freelist: first free element pointer 320 * @lock: lock for accessing the pool 321 */ 322 struct dp_tx_tso_seg_pool_s { 323 uint16_t pool_size; 324 uint16_t num_free; 325 struct qdf_tso_seg_elem_t *freelist; 326 qdf_spinlock_t lock; 327 }; 328 329 /** 330 * struct dp_tx_tso_num_seg_pool_s { 331 * @num_seg_pool_size: total number of pool elements 332 * @num_free: free element count 333 * @freelist: first free element pointer 334 * @lock: lock for accessing the pool 335 */ 336 337 struct dp_tx_tso_num_seg_pool_s { 338 uint16_t num_seg_pool_size; 339 uint16_t num_free; 340 struct qdf_tso_num_seg_elem_t *freelist; 341 /*tso mutex */ 342 qdf_spinlock_t lock; 343 }; 344 345 /** 346 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 347 * @elem_size: Size of each descriptor in the pool 348 * @pool_size: Total number of descriptors in the pool 349 * @num_free: Number of free descriptors 350 * @num_allocated: Number of used descriptors 351 * @freelist: Chain of free descriptors 352 * @desc_pages: multiple page allocation information for actual descriptors 353 * @num_invalid_bin: Deleted pool with pending Tx completions. 354 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 355 * @flow_pool_array: List of allocated flow pools 356 * @lock- Lock for descriptor allocation/free from/to the pool 357 */ 358 struct dp_tx_desc_pool_s { 359 uint16_t elem_size; 360 uint32_t num_allocated; 361 struct dp_tx_desc_s *freelist; 362 struct qdf_mem_multi_page_t desc_pages; 363 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 364 uint16_t pool_size; 365 uint8_t flow_pool_id; 366 uint8_t num_invalid_bin; 367 uint16_t avail_desc; 368 enum flow_pool_status status; 369 enum htt_flow_type flow_type; 370 uint16_t stop_th; 371 uint16_t start_th; 372 uint16_t pkt_drop_no_desc; 373 qdf_spinlock_t flow_pool_lock; 374 void *pool_owner_ctx; 375 #else 376 uint16_t elem_count; 377 uint32_t num_free; 378 qdf_spinlock_t lock; 379 #endif 380 }; 381 382 /** 383 * struct dp_txrx_pool_stats - flow pool related statistics 384 * @pool_map_count: flow pool map received 385 * @pool_unmap_count: flow pool unmap received 386 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 387 */ 388 struct dp_txrx_pool_stats { 389 uint16_t pool_map_count; 390 uint16_t pool_unmap_count; 391 uint16_t pkt_drop_no_pool; 392 }; 393 394 struct dp_srng { 395 void *hal_srng; 396 void *base_vaddr_unaligned; 397 qdf_dma_addr_t base_paddr_unaligned; 398 uint32_t alloc_size; 399 int irq; 400 uint32_t num_entries; 401 }; 402 403 struct dp_rx_reorder_array_elem { 404 qdf_nbuf_t head; 405 qdf_nbuf_t tail; 406 }; 407 408 #define DP_RX_BA_INACTIVE 0 409 #define DP_RX_BA_ACTIVE 1 410 struct dp_reo_cmd_info { 411 uint16_t cmd; 412 enum hal_reo_cmd_type cmd_type; 413 void *data; 414 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 415 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 416 }; 417 418 /* Rx TID */ 419 struct dp_rx_tid { 420 /* TID */ 421 int tid; 422 423 /* Num of addba requests */ 424 uint32_t num_of_addba_req; 425 426 /* Num of addba responses */ 427 uint32_t num_of_addba_resp; 428 429 /* Num of delba requests */ 430 uint32_t num_of_delba_req; 431 432 /* pn size */ 433 uint8_t pn_size; 434 /* REO TID queue descriptors */ 435 void *hw_qdesc_vaddr_unaligned; 436 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 437 qdf_dma_addr_t hw_qdesc_paddr; 438 uint32_t hw_qdesc_alloc_size; 439 440 /* RX ADDBA session state */ 441 int ba_status; 442 443 /* RX BA window size */ 444 uint16_t ba_win_size; 445 446 /* TODO: Check the following while adding defragmentation support */ 447 struct dp_rx_reorder_array_elem *array; 448 /* base - single rx reorder element used for non-aggr cases */ 449 struct dp_rx_reorder_array_elem base; 450 451 /* only used for defrag right now */ 452 TAILQ_ENTRY(dp_rx_tid) defrag_waitlist_elem; 453 454 /* Store dst desc for reinjection */ 455 void *dst_ring_desc; 456 struct dp_rx_desc *head_frag_desc; 457 458 /* Sequence and fragments that are being processed currently */ 459 uint32_t curr_seq_num; 460 uint32_t curr_frag_num; 461 462 uint32_t defrag_timeout_ms; 463 uint16_t dialogtoken; 464 uint16_t statuscode; 465 /* user defined ADDBA response status code */ 466 uint16_t userstatuscode; 467 }; 468 469 /* per interrupt context */ 470 struct dp_intr { 471 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 472 associated with this napi context */ 473 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 474 with this interrupt context */ 475 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 476 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 477 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 478 uint8_t reo_status_ring_mask; /* REO command response ring */ 479 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 480 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 481 struct dp_soc *soc; /* Reference to SoC structure , 482 to get DMA ring handles */ 483 qdf_lro_ctx_t lro_ctx; 484 uint8_t dp_intr_id; 485 }; 486 487 #define REO_DESC_FREELIST_SIZE 64 488 #define REO_DESC_FREE_DEFER_MS 1000 489 struct reo_desc_list_node { 490 qdf_list_node_t node; 491 unsigned long free_ts; 492 struct dp_rx_tid rx_tid; 493 }; 494 495 /* SoC level data path statistics */ 496 struct dp_soc_stats { 497 struct { 498 uint32_t added; 499 uint32_t deleted; 500 uint32_t aged_out; 501 } ast; 502 503 /* SOC level TX stats */ 504 struct { 505 /* packets dropped on tx because of no peer */ 506 struct cdp_pkt_info tx_invalid_peer; 507 /* descriptors in each tcl ring */ 508 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 509 /* Descriptors in use at soc */ 510 uint32_t desc_in_use; 511 /* tqm_release_reason == FW removed */ 512 uint32_t dropped_fw_removed; 513 514 } tx; 515 516 /* SOC level RX stats */ 517 struct { 518 /* Rx errors */ 519 /* Total Packets in Rx Error ring */ 520 uint32_t err_ring_pkts; 521 /* No of Fragments */ 522 uint32_t rx_frags; 523 struct { 524 /* Invalid RBM error count */ 525 uint32_t invalid_rbm; 526 /* Invalid VDEV Error count */ 527 uint32_t invalid_vdev; 528 /* Invalid PDEV error count */ 529 uint32_t invalid_pdev; 530 /* Invalid PEER Error count */ 531 struct cdp_pkt_info rx_invalid_peer; 532 /* HAL ring access Fail error count */ 533 uint32_t hal_ring_access_fail; 534 /* RX DMA error count */ 535 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 536 /* REO Error count */ 537 uint32_t reo_error[HAL_REO_ERR_MAX]; 538 /* HAL REO ERR Count */ 539 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 540 } err; 541 542 /* packet count per core - per ring */ 543 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 544 } rx; 545 }; 546 547 #define DP_MAC_ADDR_LEN 6 548 union dp_align_mac_addr { 549 uint8_t raw[DP_MAC_ADDR_LEN]; 550 struct { 551 uint16_t bytes_ab; 552 uint16_t bytes_cd; 553 uint16_t bytes_ef; 554 } align2; 555 struct { 556 uint32_t bytes_abcd; 557 uint16_t bytes_ef; 558 } align4; 559 struct { 560 uint16_t bytes_ab; 561 uint32_t bytes_cdef; 562 } align4_2; 563 }; 564 565 /* 566 * dp_ast_entry 567 * 568 * @ast_idx: Hardware AST Index 569 * @mac_addr: MAC Address for this AST entry 570 * @peer: Next Hop peer (for non-WDS nodes, this will be point to 571 * associated peer with this MAC address) 572 * @next_hop: Set to 1 if this is for a WDS node 573 * @is_active: flag to indicate active data traffic on this node 574 * (used for aging out/expiry) 575 * @ase_list_elem: node in peer AST list 576 * @is_bss: flag to indicate if entry corresponds to bss peer 577 * @pdev_id: pdev ID 578 * @vdev_id: vdev ID 579 * @type: flag to indicate type of the entry(static/WDS/MEC) 580 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 581 */ 582 struct dp_ast_entry { 583 uint16_t ast_idx; 584 /* MAC address */ 585 union dp_align_mac_addr mac_addr; 586 struct dp_peer *peer; 587 bool next_hop; 588 bool is_active; 589 bool is_bss; 590 uint8_t pdev_id; 591 uint8_t vdev_id; 592 enum cdp_txrx_ast_entry_type type; 593 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 594 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 595 }; 596 597 /* SOC level htt stats */ 598 struct htt_t2h_stats { 599 /* lock to protect htt_stats_msg update */ 600 qdf_spinlock_t lock; 601 602 /* work queue to process htt stats */ 603 qdf_work_t work; 604 605 /* T2H Ext stats message queue */ 606 qdf_nbuf_queue_t msg; 607 608 /* number of completed stats in htt_stats_msg */ 609 uint32_t num_stats; 610 }; 611 612 /* SOC level structure for data path */ 613 struct dp_soc { 614 /* Common base structure - Should be the first member */ 615 struct cdp_soc_t cdp_soc; 616 617 /* SoC Obj */ 618 void *ctrl_psoc; 619 620 /* OS device abstraction */ 621 qdf_device_t osdev; 622 623 /* WLAN config context */ 624 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 625 626 /* HTT handle for host-fw interaction */ 627 void *htt_handle; 628 629 /* Commint init done */ 630 qdf_atomic_t cmn_init_done; 631 632 /* Opaque hif handle */ 633 struct hif_opaque_softc *hif_handle; 634 635 /* PDEVs on this SOC */ 636 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 637 638 /* Number of PDEVs */ 639 uint8_t pdev_count; 640 641 /*cce disable*/ 642 bool cce_disable; 643 644 /* Link descriptor memory banks */ 645 struct { 646 void *base_vaddr_unaligned; 647 void *base_vaddr; 648 qdf_dma_addr_t base_paddr_unaligned; 649 qdf_dma_addr_t base_paddr; 650 uint32_t size; 651 } link_desc_banks[MAX_LINK_DESC_BANKS]; 652 653 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 654 struct dp_srng wbm_idle_link_ring; 655 656 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 657 */ 658 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 659 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 660 uint32_t wbm_idle_scatter_buf_size; 661 662 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 663 qdf_spinlock_t flow_pool_array_lock; 664 tx_pause_callback pause_cb; 665 struct dp_txrx_pool_stats pool_stats; 666 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 667 /* Tx SW descriptor pool */ 668 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 669 670 /* Tx MSDU Extension descriptor pool */ 671 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 672 673 /* Tx TSO descriptor pool */ 674 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 675 676 /* Tx TSO Num of segments pool */ 677 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 678 679 /* Tx H/W queues lock */ 680 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 681 682 /* Rx SW descriptor pool for RXDMA buffer */ 683 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 684 685 /* Rx SW descriptor pool for RXDMA monitor buffer */ 686 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 687 688 /* Rx SW descriptor pool for RXDMA status buffer */ 689 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 690 691 /* HAL SOC handle */ 692 void *hal_soc; 693 694 /* DP Interrupts */ 695 struct dp_intr intr_ctx[DP_MAX_INTERRUPT_CONTEXTS]; 696 697 /* REO destination rings */ 698 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 699 700 /* Number of REO destination rings */ 701 uint8_t num_reo_dest_rings; 702 703 /* REO exception ring - See if should combine this with reo_dest_ring */ 704 struct dp_srng reo_exception_ring; 705 706 /* REO reinjection ring */ 707 struct dp_srng reo_reinject_ring; 708 709 /* REO command ring */ 710 struct dp_srng reo_cmd_ring; 711 712 /* REO command status ring */ 713 struct dp_srng reo_status_ring; 714 715 /* WBM Rx release ring */ 716 struct dp_srng rx_rel_ring; 717 718 /* Number of TCL data rings */ 719 uint8_t num_tcl_data_rings; 720 721 /* TCL data ring */ 722 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 723 724 /* TCL command ring */ 725 struct dp_srng tcl_cmd_ring; 726 727 /* TCL command status ring */ 728 struct dp_srng tcl_status_ring; 729 730 /* WBM Tx completion rings */ 731 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 732 733 /* Common WBM link descriptor release ring (SW to WBM) */ 734 struct dp_srng wbm_desc_rel_ring; 735 736 /* Tx ring map for interrupt processing */ 737 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 738 739 /* Rx ring map for interrupt processing */ 740 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 741 742 /* peer ID to peer object map (array of pointers to peer objects) */ 743 struct dp_peer **peer_id_to_obj_map; 744 745 struct { 746 unsigned mask; 747 unsigned idx_bits; 748 TAILQ_HEAD(, dp_peer) * bins; 749 } peer_hash; 750 751 /* rx defrag state – TBD: do we need this per radio? */ 752 struct { 753 struct { 754 TAILQ_HEAD(, dp_rx_tid) waitlist; 755 uint32_t timeout_ms; 756 } defrag; 757 struct { 758 int defrag_timeout_check; 759 int dup_check; 760 } flags; 761 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 762 qdf_spinlock_t reo_cmd_lock; 763 } rx; 764 765 /* optional rx processing function */ 766 void (*rx_opt_proc)( 767 struct dp_vdev *vdev, 768 struct dp_peer *peer, 769 unsigned tid, 770 qdf_nbuf_t msdu_list); 771 772 /* pool addr for mcast enhance buff */ 773 struct { 774 int size; 775 uint32_t paddr; 776 uint32_t *vaddr; 777 struct dp_tx_me_buf_t *freelist; 778 int buf_in_use; 779 qdf_dma_mem_context(memctx); 780 } me_buf; 781 782 /** 783 * peer ref mutex: 784 * 1. Protect peer object lookups until the returned peer object's 785 * reference count is incremented. 786 * 2. Provide mutex when accessing peer object lookup structures. 787 */ 788 DP_MUTEX_TYPE peer_ref_mutex; 789 790 /* maximum value for peer_id */ 791 int max_peers; 792 793 /* SoC level data path statistics */ 794 struct dp_soc_stats stats; 795 796 /* Enable processing of Tx completion status words */ 797 bool process_tx_status; 798 bool process_rx_status; 799 struct dp_ast_entry *ast_table[WLAN_UMAC_PSOC_MAX_PEERS * 2]; 800 struct { 801 unsigned mask; 802 unsigned idx_bits; 803 TAILQ_HEAD(, dp_ast_entry) * bins; 804 } ast_hash; 805 806 qdf_spinlock_t ast_lock; 807 qdf_timer_t wds_aging_timer; 808 809 /*interrupt timer*/ 810 qdf_timer_t mon_reap_timer; 811 uint8_t reap_timer_init; 812 qdf_timer_t int_timer; 813 uint8_t intr_mode; 814 815 qdf_list_t reo_desc_freelist; 816 qdf_spinlock_t reo_desc_freelist_lock; 817 818 #ifdef QCA_SUPPORT_SON 819 /* The timer to check station's inactivity status */ 820 os_timer_t pdev_bs_inact_timer; 821 /* The current inactivity count reload value 822 based on overload condition */ 823 u_int16_t pdev_bs_inact_reload; 824 825 /* The inactivity timer value when not overloaded */ 826 u_int16_t pdev_bs_inact_normal; 827 828 /* The inactivity timer value when overloaded */ 829 u_int16_t pdev_bs_inact_overload; 830 831 /* The inactivity timer check interval */ 832 u_int16_t pdev_bs_inact_interval; 833 /* Inactivity timer */ 834 #endif /* QCA_SUPPORT_SON */ 835 836 /* htt stats */ 837 struct htt_t2h_stats htt_stats; 838 839 void *external_txrx_handle; /* External data path handle */ 840 #ifdef IPA_OFFLOAD 841 /* IPA uC datapath offload Wlan Tx resources */ 842 struct { 843 /* Resource info to be passed to IPA */ 844 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 845 void *ipa_tcl_ring_base_vaddr; 846 uint32_t ipa_tcl_ring_size; 847 qdf_dma_addr_t ipa_tcl_hp_paddr; 848 uint32_t alloc_tx_buf_cnt; 849 850 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 851 void *ipa_wbm_ring_base_vaddr; 852 uint32_t ipa_wbm_ring_size; 853 qdf_dma_addr_t ipa_wbm_tp_paddr; 854 855 /* TX buffers populated into the WBM ring */ 856 void **tx_buf_pool_vaddr_unaligned; 857 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 858 } ipa_uc_tx_rsc; 859 860 /* IPA uC datapath offload Wlan Rx resources */ 861 struct { 862 /* Resource info to be passed to IPA */ 863 qdf_dma_addr_t ipa_reo_ring_base_paddr; 864 void *ipa_reo_ring_base_vaddr; 865 uint32_t ipa_reo_ring_size; 866 qdf_dma_addr_t ipa_reo_tp_paddr; 867 868 /* Resource info to be passed to firmware and IPA */ 869 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 870 void *ipa_rx_refill_buf_ring_base_vaddr; 871 uint32_t ipa_rx_refill_buf_ring_size; 872 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 873 } ipa_uc_rx_rsc; 874 #endif 875 }; 876 877 #ifdef IPA_OFFLOAD 878 /** 879 * dp_ipa_resources - Resources needed for IPA 880 */ 881 struct dp_ipa_resources { 882 qdf_dma_addr_t tx_ring_base_paddr; 883 uint32_t tx_ring_size; 884 uint32_t tx_num_alloc_buffer; 885 886 qdf_dma_addr_t tx_comp_ring_base_paddr; 887 uint32_t tx_comp_ring_size; 888 889 qdf_dma_addr_t rx_rdy_ring_base_paddr; 890 uint32_t rx_rdy_ring_size; 891 892 qdf_dma_addr_t rx_refill_ring_base_paddr; 893 uint32_t rx_refill_ring_size; 894 895 /* IPA UC doorbell registers paddr */ 896 qdf_dma_addr_t tx_comp_doorbell_paddr; 897 uint32_t *tx_comp_doorbell_vaddr; 898 qdf_dma_addr_t rx_ready_doorbell_paddr; 899 }; 900 #endif 901 902 #define MAX_RX_MAC_RINGS 2 903 /* Same as NAC_MAX_CLENT */ 904 #define DP_NAC_MAX_CLIENT 24 905 906 /* 907 * Macros to setup link descriptor cookies - for link descriptors, we just 908 * need first 3 bits to store bank ID. The remaining bytes will be used set a 909 * unique ID, which will be useful in debugging 910 */ 911 #define LINK_DESC_BANK_ID_MASK 0x7 912 #define LINK_DESC_ID_SHIFT 3 913 #define LINK_DESC_ID_START 0x8000 914 915 #define LINK_DESC_COOKIE(_desc_id, _bank_id) \ 916 ((((_desc_id) + LINK_DESC_ID_START) << LINK_DESC_ID_SHIFT) | (_bank_id)) 917 918 #define LINK_DESC_COOKIE_BANK_ID(_cookie) \ 919 ((_cookie) & LINK_DESC_BANK_ID_MASK) 920 921 /* same as ieee80211_nac_param */ 922 enum dp_nac_param_cmd { 923 /* IEEE80211_NAC_PARAM_ADD */ 924 DP_NAC_PARAM_ADD = 1, 925 /* IEEE80211_NAC_PARAM_DEL */ 926 DP_NAC_PARAM_DEL, 927 /* IEEE80211_NAC_PARAM_LIST */ 928 DP_NAC_PARAM_LIST, 929 }; 930 931 /** 932 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 933 * @neighbour_peers_macaddr: neighbour peer's mac address 934 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 935 */ 936 struct dp_neighbour_peer { 937 /* MAC address of neighbour's peer */ 938 union dp_align_mac_addr neighbour_peers_macaddr; 939 /* node in the list of neighbour's peer */ 940 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 941 }; 942 943 /** 944 * struct ppdu_info - PPDU Status info descriptor 945 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 946 * @max_ppdu_id - wrap around for ppdu id 947 * @last_tlv_cnt - Keep track for missing ppdu tlvs 948 * @last_user - last ppdu processed for user 949 * @is_ampdu - set if Ampdu aggregate 950 * @nbuf - ppdu descriptor payload 951 * @ppdu_desc - ppdu descriptor 952 * @ppdu_info_list_elem - linked list of ppdu tlvs 953 */ 954 struct ppdu_info { 955 uint32_t ppdu_id; 956 uint32_t max_ppdu_id; 957 uint16_t tlv_bitmap; 958 uint16_t last_tlv_cnt; 959 uint16_t last_user:8, 960 is_ampdu:1; 961 qdf_nbuf_t nbuf; 962 struct cdp_tx_completion_ppdu *ppdu_desc; 963 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 964 }; 965 966 /* PDEV level structure for data path */ 967 struct dp_pdev { 968 /* PDEV handle from OSIF layer TBD: see if we really need osif_pdev */ 969 void *osif_pdev; 970 971 /* PDEV Id */ 972 int pdev_id; 973 974 /* TXRX SOC handle */ 975 struct dp_soc *soc; 976 977 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 978 struct dp_srng rx_refill_buf_ring; 979 980 /* Second ring used to replenish rx buffers */ 981 struct dp_srng rx_refill_buf_ring2; 982 983 /* Empty ring used by firmware to post rx buffers to the MAC */ 984 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 985 986 /* wlan_cfg pdev ctxt*/ 987 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 988 989 /* RXDMA monitor buffer replenish ring */ 990 struct dp_srng rxdma_mon_buf_ring[NUM_RXDMA_RINGS_PER_PDEV]; 991 992 /* RXDMA monitor destination ring */ 993 struct dp_srng rxdma_mon_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 994 995 /* RXDMA monitor status ring. TBD: Check format of this ring */ 996 struct dp_srng rxdma_mon_status_ring[NUM_RXDMA_RINGS_PER_PDEV]; 997 998 struct dp_srng rxdma_mon_desc_ring[NUM_RXDMA_RINGS_PER_PDEV]; 999 1000 /* RXDMA error destination ring */ 1001 struct dp_srng rxdma_err_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1002 1003 /* Link descriptor memory banks */ 1004 struct { 1005 void *base_vaddr_unaligned; 1006 void *base_vaddr; 1007 qdf_dma_addr_t base_paddr_unaligned; 1008 qdf_dma_addr_t base_paddr; 1009 uint32_t size; 1010 } link_desc_banks[NUM_RXDMA_RINGS_PER_PDEV][MAX_MON_LINK_DESC_BANKS]; 1011 1012 1013 /** 1014 * TODO: See if we need a ring map here for LMAC rings. 1015 * 1. Monitor rings are currently planning to be processed on receiving 1016 * PPDU end interrupts and hence wont need ring based interrupts. 1017 * 2. Rx buffer rings will be replenished during REO destination 1018 * processing and doesn't require regular interrupt handling - we will 1019 * only handle low water mark interrupts which is not expected 1020 * frequently 1021 */ 1022 1023 /* VDEV list */ 1024 TAILQ_HEAD(, dp_vdev) vdev_list; 1025 1026 /* Number of vdevs this device have */ 1027 uint16_t vdev_count; 1028 1029 /* PDEV transmit lock */ 1030 qdf_spinlock_t tx_lock; 1031 1032 #ifndef REMOVE_PKT_LOG 1033 bool pkt_log_init; 1034 /* Pktlog pdev */ 1035 struct pktlog_dev_t *pl_dev; 1036 #endif /* #ifndef REMOVE_PKT_LOG */ 1037 1038 /* Monitor mode interface and status storage */ 1039 struct dp_vdev *monitor_vdev; 1040 1041 /* monitor mode lock */ 1042 qdf_spinlock_t mon_lock; 1043 1044 /*tx_mutex for me*/ 1045 DP_MUTEX_TYPE tx_mutex; 1046 1047 /* Smart Mesh */ 1048 bool filter_neighbour_peers; 1049 /* smart mesh mutex */ 1050 qdf_spinlock_t neighbour_peer_mutex; 1051 /* Neighnour peer list */ 1052 TAILQ_HEAD(, dp_neighbour_peer) neighbour_peers_list; 1053 /* msdu chain head & tail */ 1054 qdf_nbuf_t invalid_peer_head_msdu; 1055 qdf_nbuf_t invalid_peer_tail_msdu; 1056 1057 /* Band steering */ 1058 /* TBD */ 1059 1060 /* PDEV level data path statistics */ 1061 struct cdp_pdev_stats stats; 1062 1063 /* Global RX decap mode for the device */ 1064 enum htt_pkt_type rx_decap_mode; 1065 1066 /* Enhanced Stats is enabled */ 1067 bool enhanced_stats_en; 1068 1069 /* advance filter mode and type*/ 1070 uint8_t mon_filter_mode; 1071 uint16_t fp_mgmt_filter; 1072 uint16_t fp_ctrl_filter; 1073 uint16_t fp_data_filter; 1074 uint16_t mo_mgmt_filter; 1075 uint16_t mo_ctrl_filter; 1076 uint16_t mo_data_filter; 1077 1078 qdf_atomic_t num_tx_outstanding; 1079 1080 qdf_atomic_t num_tx_exception; 1081 1082 /* MCL specific local peer handle */ 1083 struct { 1084 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 1085 uint8_t freelist; 1086 qdf_spinlock_t lock; 1087 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 1088 } local_peer_ids; 1089 1090 /* dscp_tid_map_*/ 1091 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 1092 1093 struct hal_rx_ppdu_info ppdu_info; 1094 1095 /* operating channel */ 1096 uint8_t operating_channel; 1097 1098 qdf_nbuf_queue_t rx_status_q; 1099 uint32_t mon_ppdu_status; 1100 struct cdp_mon_status rx_mon_recv_status; 1101 1102 /* pool addr for mcast enhance buff */ 1103 struct { 1104 int size; 1105 uint32_t paddr; 1106 char *vaddr; 1107 struct dp_tx_me_buf_t *freelist; 1108 int buf_in_use; 1109 qdf_dma_mem_context(memctx); 1110 } me_buf; 1111 1112 /* Number of VAPs with mcast enhancement enabled */ 1113 qdf_atomic_t mc_num_vap_attached; 1114 1115 qdf_atomic_t stats_cmd_complete; 1116 1117 #ifdef IPA_OFFLOAD 1118 ipa_uc_op_cb_type ipa_uc_op_cb; 1119 void *usr_ctxt; 1120 struct dp_ipa_resources ipa_resource; 1121 #endif 1122 1123 /* TBD */ 1124 1125 /* map this pdev to a particular Reo Destination ring */ 1126 enum cdp_host_reo_dest_ring reo_dest; 1127 1128 #ifndef REMOVE_PKT_LOG 1129 /* Packet log mode */ 1130 uint8_t rx_pktlog_mode; 1131 #endif 1132 1133 /* WDI event handlers */ 1134 struct wdi_event_subscribe_t **wdi_event_list; 1135 1136 /* ppdu_id of last received HTT TX stats */ 1137 uint32_t last_ppdu_id; 1138 struct { 1139 uint8_t last_user; 1140 qdf_nbuf_t buf; 1141 } tx_ppdu_info; 1142 1143 bool tx_sniffer_enable; 1144 /* mirror copy mode */ 1145 bool mcopy_mode; 1146 1147 struct { 1148 uint16_t tx_ppdu_id; 1149 uint16_t tx_peer_id; 1150 uint16_t rx_ppdu_id; 1151 } m_copy_id; 1152 1153 /* To check if PPDU Tx stats are enabled for Pktlog */ 1154 bool pktlog_ppdu_stats; 1155 1156 void *dp_txrx_handle; /* Advanced data path handle */ 1157 1158 #ifdef ATH_SUPPORT_NAC_RSSI 1159 bool nac_rssi_filtering; 1160 #endif 1161 /* list of ppdu tlvs */ 1162 TAILQ_HEAD(, ppdu_info) ppdu_info_list; 1163 uint32_t tlv_count; 1164 uint32_t list_depth; 1165 }; 1166 1167 struct dp_peer; 1168 1169 /* VDEV structure for data path state */ 1170 struct dp_vdev { 1171 /* OS device abstraction */ 1172 qdf_device_t osdev; 1173 /* physical device that is the parent of this virtual device */ 1174 struct dp_pdev *pdev; 1175 1176 /* Handle to the OS shim SW's virtual device */ 1177 ol_osif_vdev_handle osif_vdev; 1178 1179 /* vdev_id - ID used to specify a particular vdev to the target */ 1180 uint8_t vdev_id; 1181 1182 /* MAC address */ 1183 union dp_align_mac_addr mac_addr; 1184 1185 /* node in the pdev's list of vdevs */ 1186 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 1187 1188 /* dp_peer list */ 1189 TAILQ_HEAD(, dp_peer) peer_list; 1190 1191 /* callback to hand rx frames to the OS shim */ 1192 ol_txrx_rx_fp osif_rx; 1193 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 1194 ol_txrx_get_key_fp osif_get_key; 1195 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 1196 1197 #ifdef notyet 1198 /* callback to check if the msdu is an WAI (WAPI) frame */ 1199 ol_rx_check_wai_fp osif_check_wai; 1200 #endif 1201 1202 /* proxy arp function */ 1203 ol_txrx_proxy_arp_fp osif_proxy_arp; 1204 1205 /* callback to hand rx monitor 802.11 MPDU to the OS shim */ 1206 ol_txrx_rx_mon_fp osif_rx_mon; 1207 1208 ol_txrx_mcast_me_fp me_convert; 1209 /* deferred vdev deletion state */ 1210 struct { 1211 /* VDEV delete pending */ 1212 int pending; 1213 /* 1214 * callback and a context argument to provide a 1215 * notification for when the vdev is deleted. 1216 */ 1217 ol_txrx_vdev_delete_cb callback; 1218 void *context; 1219 } delete; 1220 1221 /* tx data delivery notification callback function */ 1222 struct { 1223 ol_txrx_data_tx_cb func; 1224 void *ctxt; 1225 } tx_non_std_data_callback; 1226 1227 1228 /* safe mode control to bypass the encrypt and decipher process*/ 1229 uint32_t safemode; 1230 1231 /* rx filter related */ 1232 uint32_t drop_unenc; 1233 #ifdef notyet 1234 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 1235 uint32_t filters_num; 1236 #endif 1237 /* TDLS Link status */ 1238 bool tdls_link_connected; 1239 bool is_tdls_frame; 1240 1241 1242 /* VDEV operating mode */ 1243 enum wlan_op_mode opmode; 1244 1245 /* Tx encapsulation type for this VAP */ 1246 enum htt_cmn_pkt_type tx_encap_type; 1247 /* Rx Decapsulation type for this VAP */ 1248 enum htt_cmn_pkt_type rx_decap_type; 1249 1250 /* BSS peer */ 1251 struct dp_peer *vap_bss_peer; 1252 1253 /* WDS enabled */ 1254 bool wds_enabled; 1255 1256 /* WDS Aging timer period */ 1257 uint32_t wds_aging_timer_val; 1258 1259 /* NAWDS enabled */ 1260 bool nawds_enabled; 1261 1262 /* Default HTT meta data for this VDEV */ 1263 /* TBD: check alignment constraints */ 1264 uint16_t htt_tcl_metadata; 1265 1266 /* Mesh mode vdev */ 1267 uint32_t mesh_vdev; 1268 1269 /* Mesh mode rx filter setting */ 1270 uint32_t mesh_rx_filter; 1271 1272 /* DSCP-TID mapping table ID */ 1273 uint8_t dscp_tid_map_id; 1274 1275 /* Multicast enhancement enabled */ 1276 uint8_t mcast_enhancement_en; 1277 1278 /* per vdev rx nbuf queue */ 1279 qdf_nbuf_queue_t rxq; 1280 1281 uint8_t tx_ring_id; 1282 struct dp_tx_desc_pool_s *tx_desc; 1283 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 1284 1285 /* VDEV Stats */ 1286 struct cdp_vdev_stats stats; 1287 bool lro_enable; 1288 1289 /* Is this a proxySTA VAP */ 1290 bool proxysta_vdev; 1291 /* Is isolation mode enabled */ 1292 bool isolation_vdev; 1293 1294 /* Address search flags to be configured in HAL descriptor */ 1295 uint8_t hal_desc_addr_search_flags; 1296 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1297 struct dp_tx_desc_pool_s *pool; 1298 #endif 1299 /* AP BRIDGE enabled */ 1300 uint32_t ap_bridge_enabled; 1301 1302 enum cdp_sec_type sec_type; 1303 1304 #ifdef ATH_SUPPORT_NAC_RSSI 1305 bool cdp_nac_rssi_enabled; 1306 struct { 1307 uint8_t bssid_mac[6]; 1308 uint8_t client_mac[6]; 1309 uint8_t chan_num; 1310 uint8_t client_rssi_valid; 1311 uint8_t client_rssi; 1312 uint8_t vdev_id; 1313 } cdp_nac_rssi; 1314 #endif 1315 }; 1316 1317 1318 enum { 1319 dp_sec_mcast = 0, 1320 dp_sec_ucast 1321 }; 1322 1323 #ifdef WDS_VENDOR_EXTENSION 1324 typedef struct { 1325 uint8_t wds_tx_mcast_4addr:1, 1326 wds_tx_ucast_4addr:1, 1327 wds_rx_filter:1, /* enforce rx filter */ 1328 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 1329 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 1330 1331 } dp_ecm_policy; 1332 #endif 1333 1334 /* Peer structure for data path state */ 1335 struct dp_peer { 1336 /* VDEV to which this peer is associated */ 1337 struct dp_vdev *vdev; 1338 1339 struct dp_ast_entry *self_ast_entry; 1340 1341 qdf_atomic_t ref_cnt; 1342 1343 /* TODO: See if multiple peer IDs are required in wifi3.0 */ 1344 /* peer ID(s) for this peer */ 1345 uint16_t peer_ids[MAX_NUM_PEER_ID_PER_PEER]; 1346 1347 union dp_align_mac_addr mac_addr; 1348 1349 /* node in the vdev's list of peers */ 1350 TAILQ_ENTRY(dp_peer) peer_list_elem; 1351 /* node in the hash table bin's list of peers */ 1352 TAILQ_ENTRY(dp_peer) hash_list_elem; 1353 1354 /* TID structures */ 1355 struct dp_rx_tid rx_tid[DP_MAX_TIDS]; 1356 1357 /* TBD: No transmit TID state required? */ 1358 1359 struct { 1360 enum htt_sec_type sec_type; 1361 u_int32_t michael_key[2]; /* relevant for TKIP */ 1362 } security[2]; /* 0 -> multicast, 1 -> unicast */ 1363 1364 /* 1365 * rx proc function: this either is a copy of pdev's rx_opt_proc for 1366 * regular rx processing, or has been redirected to a /dev/null discard 1367 * function when peer deletion is in progress. 1368 */ 1369 void (*rx_opt_proc)(struct dp_vdev *vdev, struct dp_peer *peer, 1370 unsigned tid, qdf_nbuf_t msdu_list); 1371 1372 /* set when node is authorized */ 1373 uint8_t authorize:1; 1374 1375 u_int8_t nac; 1376 1377 /* Band steering: Set when node is inactive */ 1378 uint8_t peer_bs_inact_flag:1; 1379 u_int16_t peer_bs_inact; /* inactivity mark count */ 1380 1381 /* NAWDS Flag and Bss Peer bit */ 1382 uint8_t nawds_enabled:1, 1383 bss_peer:1, 1384 wapi:1, 1385 wds_enabled:1; 1386 1387 /* MCL specific peer local id */ 1388 uint16_t local_id; 1389 enum ol_txrx_peer_state state; 1390 qdf_spinlock_t peer_info_lock; 1391 1392 qdf_time_t last_assoc_rcvd; 1393 qdf_time_t last_disassoc_rcvd; 1394 qdf_time_t last_deauth_rcvd; 1395 /* Peer Stats */ 1396 struct cdp_peer_stats stats; 1397 1398 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 1399 /* TBD */ 1400 1401 #ifdef WDS_VENDOR_EXTENSION 1402 dp_ecm_policy wds_ecm; 1403 #endif 1404 bool delete_in_progress; 1405 }; 1406 1407 #ifdef CONFIG_WIN 1408 /* 1409 * dp_invalid_peer_msg 1410 * @nbuf: data buffer 1411 * @wh: 802.11 header 1412 * @vdev_id: id of vdev 1413 */ 1414 struct dp_invalid_peer_msg { 1415 qdf_nbuf_t nbuf; 1416 struct ieee80211_frame *wh; 1417 uint8_t vdev_id; 1418 }; 1419 #endif 1420 1421 /* 1422 * dp_tx_me_buf_t: ME buffer 1423 * next: pointer to next buffer 1424 * data: Destination Mac address 1425 */ 1426 struct dp_tx_me_buf_t { 1427 /* Note: ME buf pool initialization logic expects next pointer to 1428 * be the first element. Dont add anything before next */ 1429 struct dp_tx_me_buf_t *next; 1430 uint8_t data[DP_MAC_ADDR_LEN]; 1431 }; 1432 1433 #endif /* _DP_TYPES_H_ */ 1434